Relevant bibliographies by topics / Programmable RF transmitter

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  1. Journal articles
  2. Dissertations / Theses
  3. Conference papers

Academic literature on the topic 'Programmable RF transmitter'

Author: Grafiati
Published: 25 May 2024

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Journal articles on the topic "Programmable RF transmitter"

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Tang, Wankai, Jun Yan Dai, Mingzheng Chen, et al. "Programmable metasurface‐based RF chain‐free 8PSK wireless transmitter." Electronics Letters 55, no. 7 (2019): 417–20. http://dx.doi.org/10.1049/el.2019.0400.

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Xu, Qin, Christopher Glielmi, Lei Zhou, Kisueng Choi, and Xiaoping Hu. "An inexpensive and programmable RF transmitter setup for two-coil CASL." Concepts in Magnetic Resonance Part B: Magnetic Resonance Engineering 33B, no. 4 (2008): 228–35. http://dx.doi.org/10.1002/cmr.b.20127.

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VOTIS, CONSTANTINOS I., PANOS KOSTARAKIS, and LEONIDAS P. IVRISSIMTZIS. "DESIGN AND MEASUREMENTS OF A MULTIPLE-OUTPUT TRANSMITTER FOR MIMO APPLICATIONS." Journal of Circuits, Systems and Computers 20, no. 03 (2011): 515–29. http://dx.doi.org/10.1142/s0218126611007426.

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The design of a multiple-output transmitter for digital beamforming (DBF), Multiple-Input Multiple-Output (MIMO) and channel sounder applications, based on Direct Digital Synthesis (DDS) system is presented and investigated in terms of antenna array performance. DDS generates independently modulated signals on specific carrier frequencies and is employed as the first stage in the proposed implementation, furnishing output signal of configurable amplitude, phase and frequency. The resulting phase progression, amplitude and beamforming accuracy of a beam steering array are further investigated, showing that the proposed architecture can provide a steering beam with high accuracy. Experimental results of system performance indicate that this architecture can drive efficiently and accurately an antenna array with independent modulated RF signals, with programmable frequency, initial phase, and magnitude.
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Ott, A. T., C. J. Eisner, M. D. Blech, and T. F. Eibert. "Reconfigurable ultra-wideband transmitter for generation of arbitrary impulse shapes and modulation schemes." Advances in Radio Science 10 (September 18, 2012): 57–62. http://dx.doi.org/10.5194/ars-10-57-2012.

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Abstract. In this paper a reconfigurable ultra-wideband (UWB) impulse radio (IR) transmitter is presented. The IR signal is synthesized at an intermediate frequency (IF) by employing a multi-Nyquist digital-to-analog converter (DAC) with 12 bit resolution and an update rate of 2.3 GHz. Digital generation of signals in a field programmable gate array (FPGA) guarantees very high flexibility of the reconfigurable design. For upconversion to the radio frequency (RF) band, a first order bandpass (BP) sampling concept and an alternative conventional concept with mixer stages, have been realized. The system enables to generate signals with arbitrary modulation schemes and techniques at an external host personal computer (PC) employing MATLAB. Different measurements using a digitizing oscilloscope have been conducted to demonstrate the performance of the transmitter.
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Davidson, Kyle, and Joey Bray. "Understanding Digital Radio Frequency Memory Performance in Countermeasure Design." Applied Sciences 10, no. 12 (2020): 4123. http://dx.doi.org/10.3390/app10124123.

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This paper describes the design, implementation, and testing of a novel multi-function software defined Radio Frequency (RF) system designed for small airborne drone applications. The system was created using an inexpensive Field Programmable Gate Array (FPGA) to combine a coherent linear frequency modulated radar transmitter and receiver, with a Digital Radio Frequency Memory (DRFM) jammer for use with a common RF aperture in simultaneous operation. The system was implemented on a Xilinx Kintex-7 FPGA with a wideband analogue-to-digital/ digital-to-analogue (ADC/DAC) converter mezzanine board and tested using hardware-in-the-loop mode to validate its performance. This is the first known account of an integrated multifunction electronic attack and radar system on a single chip, capable of performing a simultaneous, not time shared, operation.
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Hoang, Nguyen Huy, Tran Van Nghia, and Le Van Ky. "IMPLEMENTATION OF FPGA-BASED DVB-T2 TRANSMITTER FOR A SECOND GENERATION DIGITAL TERRESTRIAL TELEVISION BROADCASTING SYSTEM." SYNCHROINFO JOURNAL 7, no. 1 (2021): 30–32. http://dx.doi.org/10.36724/2664-066x-2021-7-1-30-32.

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Nowadays, with strong development of Science and Technology, integrated circuits continue to dominate not only in the field of digital information. Over the last several years, Technological television industry has taken huge strides and powerful transformation to meet with government’s policy about digitization of television all over the country in period 2015 – 2020. Stemming from the practical needs of “localization of products” and mastering of technological design of DVB-T2 transmitter (Digital Video Broadcasting – Terrestrial for Second generation), the authors have made an effort to research in algorithm, designed and tested in Field Programmable Gate Array (FPGA) technology. DVB-T2 is mainly aimed to replace the current standard DVB-T. The main motivation of DVB-T2 is to provide broadcasters with more advanced and efficient alternative to DVB-T standards. In DVB-T2 transmitter system, digital audio, video, and other data are compressed into a single signal to be transmitted on a single RF channel, using orthogonal frequency-division multiplexing (OFDM) with concatenated channel coding and interleaving. The higher offered bit rate makes it a suited system for carrying HDTV signals on the terrestrial TV channel. The next generation broadcasting systems should be designed to make full use of spectral resources while providing reliable transmissions in order to enable services like multichannel HDTV (High Definition Television) and innovative data casting services. The efficient usage of the radio spectrum can be achieved by the introduction of Single Frequency Networks (SFN). Digital transmitter DVB-T2 implemented on FPGA using a software Xilinx System Generator for DSP tool and Xilinx ISE Design Suite 14.7. System Generator for DSP is in conjunction on environment MATLAB-Simulink that is capable of simulating the proposed hardware structures that is synthesized and implemented by the programmable elements in Field-programmable Gate Arrays. In this project, adaptative MPEG-TS bitrate converter is designed to allows to increasing or reducing the MPEG TS rate by adding or filtering NULL packets. The entire digital transmitter DVB-T2 is integrated in one chip Xilinx FPGA Kintex-7 XC7K325T-1FFG676. Experimental design on development Kit NetFPGA-1G-CML of Digilent Corporation is performed at design department of technology center of Vietnamese Communications Television Development JSC. Authors are continuing to improve products, put into practical applications to replace the digital terrestrial television broadcasting stations that are being used in Vietnam. The article named “Implementation of FPGA-based DVB-T2 transmitter for a second generation digital terrestrial television broadcasting system” presents the research results, design methods, test results to compare, evaluate the accuracy of algorithm implementation. The results open up new directions for technological television in Vietnam.
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Korošak, Žiga, Nejc Suhadolnik, and Anton Pleteršek. "Design of Multi Standard Near Field Communication Outphasing Transmitter with Modulation Wave Shaping." Electronics 10, no. 2 (2021): 188. http://dx.doi.org/10.3390/electronics10020188.

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The aim of this work is to tackle the problem of modulation wave shaping in the field of near field communication (NFC) radio frequency identification (RFID). For this purpose, a high-efficiency transmitter circuit was developed to comply with the strict requirements of the newest EMVCo and NFC Forum specifications for pulse shapes. The proposed circuit uses an outphasing modulator that is based on a digital-to-time converter (DTC). The DTC based outphasing modulator supports amplitude shift keying (ASK) modulation, operates at four times the 13.56 MHz carrier frequency and is made fully differential in order to remove the parasitic phase modulation components. The accompanying transmitter logic includes lookup tables with programmable modulation pulse wave shapes. The modulator solution uses a 64-cell tapped current controlled fully differential delay locked loop (DLL), which produces a 360° delay at 54.24 MHz, and a glitch-free multiplexor to select the individual taps. The outphased output from the modulator is mixed to create an RF pulse width modulated (PWM) output, which drives the antenna. Additionally, this implementation is fully compatible with D-class amplifiers enabling high efficiency. A test circuit of the proposed differential multi-standard reader’s transmitter was simulated in 40 nm CMOS technology. Stricter pulse shape requirements were easily satisfied, while achieving an output linearity of 0.2 bits and maximum power consumption under 7.5 mW.
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Bangalore Lokanatha, Sujaya, and Sompura Basavaraju Bhanu Prashanth. "Design and performance analysis of human body communication digital transceiver for wireless body area network applications." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 3 (2022): 2206. http://dx.doi.org/10.11591/ijece.v12i3.pp2206-2213.

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Wireless body area network (WBAN) is a prominent technology for resolving health-care concerns and providing high-speed continuous monitoring and real-time help. Human body communication (HBC) is an IEEE 802.15.6 physical layer standard for short-range communications that is not reliant on radio frequency (RF). Most WBAN applications can benefit from the HBC's low-latency and low-power architectural features. In this manuscript, an efficient digital HBC transceiver (TR) hardware architecture is designed as per IEEE 802.15.6 standard to overcome the drawbacks of the RF-wireless communication standards like signal leakage, on body antenna and power consumption. The design is created using a frequency selective digital transmission scheme for transmitter and receiver modules. The design resources are analyzed using different field programmable gate array (FPGA) families. The HBC TR utilizes <1% slices, consumes 101 mW power, and provides a throughput of 24.31 Mbps on Artix-7 FPGA with a latency of 10.5 clock cycles. In addition, the less than 10-4bit error rate of HBC is achieved with a 9.52 Mbps data rate. The proposed work is compared with existing architectures with significant improvement in performance parameters like chip area, power, and data rate.
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Blech, M. D., A. T. Ott, P. Neumeier, M. Möller, and T. F. Eibert. "A reconfigurable software defined ultra-wideband impulse radio transceiver." Advances in Radio Science 8 (September 30, 2010): 67–73. http://dx.doi.org/10.5194/ars-8-67-2010.

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Abstract. An ultra-wideband (UWB) software defined radio (SDR) implementation is presented. The developed impulse radio (IR) transceiver employs first order bandpass (BP) sampling at a conversion frequency which is four times the channel bandwidth. The subsampling architecture directly provides the RF signal avoiding any non-ideal mixer stages and reduces the requirements of digital signal processing implemented in a field programmable gate array (FPGA). The transmitter consists basically of a multi-Nyquist digital to analog converter (DAC), whereas the implemented matched filter (MF) receiver prototype employs a standard digitizing oscilloscope. This design can be adaptively reconfigured in terms of modulation, data rate, and channel equalization. The reconfigurable design is used for an extensive performance analysis of the quadrature phase shift keying (QPSK) modulation scheme investigating the influence of different antennas, amplifiers, narrowband interferers as well as different equalizer lengths. Even for distances up to 7 m in a multipath environment robust communication was achieved.
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Prasanna, Talapala Lakshmi, Nalluri Siddaiah, Boppana Murali Krishna, and Maheswara Rao Valluri. "Implementation of the advanced encryption standard algorithm on an FPGA for image processing through the universal asynchronous receiver-transmitter protocol." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 6 (2022): 6114. http://dx.doi.org/10.11591/ijece.v12i6.pp6114-6122.

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<span lang="EN-US">Communication among end users can be based either on wired or wireless technology. Cryptography plays a vital role in ensuring data exchange is secure among end users. Data can be encrypted and decrypted using symmetric or asymmetric key cryptographic techniques to provide confidentiality. In wireless technology, images are exchanged through low-cost wireless peripheral devices, such as radio frequency identification device (RFID), nRF, and ZigBee, that can interface with field programmable gate array (FPGA) among the end users. One of the issues is that data exchange through wireless devices does not offer confidentiality, and subsequently, data can be lost. In this paper, we propose a design and implementation of AES-128 cipher algorithm on an FPGA board for image processing through the <a name="_Hlk107307233"></a>universal asynchronous receiver transmitter (UART) protocol. In this process, the advanced encryption standard (AES) algorithm is used to encrypt and decrypt the image, while the transmitter and receiver designs are implemented on two Xilinx BASYS-3 circuits connected with a ZigBee RF module. The encrypted image uses less memory, such as LUTs (141), and also consumes less chip power (0.0291 w), I/O (0.003), block RAM (0.001 w), data, and logic to provide much higher efficiency than wired communication technology. We also observe that images can be exchanged through the UART protocol with different baud rates in run time.</span>
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Dissertations / Theses on the topic "Programmable RF transmitter"

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Eshra, Islam. "Un FIRDAC programmable pour émetteurs RF re-configurable." Electronic Thesis or Diss., Sorbonne université, 2020. http://www.theses.fr/2020SORUS461.

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Le convertisseur numérique-analogique à réponse impulsionnelle finie (FIRDAC) proposé est programmable avec un ordre entièrement reconfigurable et des coefficients capables de fournir un ordre jusqu'à 62 et un rapport entre le coefficient maximum et minimum de 159. Cela a permis une large gamme de facteurs d'atténuation pouvant atteindre 100dB et une large gamme de bandes de transition normalisées (&gt;0.0156). Le filtre FIRDAC a été conçu et implémenté en technologie CMOS 65 nm avec une surface active totale de 0,867 mm2. Au niveau du circuit, le FIRDAC peut atteindre une fréquence d'échantillonnage de 2,56 GHz pour une consommation en puissance moyenne de 9mW. Pour une entrée sinusoïdale, le filtre FIRDAC atteint un rapport signal sur bruit (SNR) jusqu'à 67,3 dB et une dynamique (SFDR) de 72 dBc. Les performances du filtre FIRDAC ont été testées dans des émetteurs QPSK, 16-QAM et 64-QAM avec OFDM et avec différentes largeurs de bande. Les simulations montrent un EVM (Error Vector Magnitude) de 2,66%, 1,9% et 2,29% respectivement. Une partie de ce travail concerne la conception du Front-End d’un émetteur RF programmable. Le Front-End RF est composé d'un mélangeur RF, d'un amplificateur de pré-puissance et d'un filtre LC réglable. Le Front-End RF complet a un gain programmable total de 23 dB avec un pas de 1,53 dB et capable de fonctionner sur une plage de 1,5 GHz à 5 GHz. La puissance RF de sortie maximale est de -11 dBm avec une consommation électrique de 23 mW. Les résultats montrent une dynamique (SFDR) maximum de -61,95 dBc pour deux tonalités à une fréquence porteuse de 4 GHz, tandis que pour un signal OFDM 16-QAM, l'EVM obtenu était de 4,76 %<br>The first part of this work relates to the design and implementation of a programmable Finite Impulse Response Digital to Analog Converter (FIRDAC). The programmability is in the filter's order (N-1) and its coefficients. The proposed FIRDAC is capable of providing an order up to 62 and a ratio between maximum to minimum coefficient up to 159. This allowed the filter to provide up to 100dB of attenuation and a wide range of normalized transition-band (&gt;0.0156). The FIRDAC filter has been designed and implemented in 65nm CMOS with total active area 0.867mm2. The FIRDAC can operate up to 2.56 GHz of sampling frequency at an average power consumption of 9mW. For a single tone input, the FIRDAC filter managed to provide an SNR up to 67.3dB and a SFDR of 72dBc. The FIRDAC filter was tested with different modulation techniques: OFDM, 16-QAM OFDM and 64-QAM OFDM having different channel Bandwidth. The circuit achieved an Error Vector Magnitude (EVM) of 2.66%, 1.9% and 2.29% respectively, complying with the LTE and the 802.11ac standards. The second part of this work relates to the design of a programmable RF front-end circuit. The RF front-end is composed of an analog RF mixer, a programmable Pre-Power Amplifier (PPA) and a tunable LC tank. The whole RF front-end introduced a total programmable gain of 23dB with a gain step of 1.53dB operating in the 1.5GHz - 5GHz frequency range. The maximum output RF power is -11dBm with a power consumption of 23mW. Simulation result showed a maximum SFDR of -61.95dBc for two tones at a carrier frequency of 4GHz. While for a 16-QAM OFDM signal, the obtained EVM was 4.76%
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Conference papers on the topic "Programmable RF transmitter"

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Nan, Hao, and Amin Arbabian. "A Programmable RF Transmitter for Wideband Thermoacoustic Spectroscopic Imaging." In 2018 IEEE/MTT-S International Microwave Symposium - IMS 2018. IEEE, 2018. http://dx.doi.org/10.1109/mwsym.2018.8439554.

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Rosolowski, D. W., and W. Wojtasiak. "Programmable RF Transmitter for Testing of the Transmission Paths in Point-MultiPoint Radiocommunication Systems." In EUROCON 2007. International Conference on "Computer as a Tool". IEEE, 2007. http://dx.doi.org/10.1109/eurcon.2007.4400479.

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Roverato, Enrico, Marko Kosunen, Koen Cornelissens, et al. "13.4 All-digital RF transmitter in 28nm CMOS with programmable RX-band noise shaping." In 2017 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2017. http://dx.doi.org/10.1109/isscc.2017.7870341.

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Lalau-Keraly, Christopher, George Daniel, Joseph Lee, and David Schwartz. "Peel-and-Stick Sensors Powered by Directed RF Energy." In ASME 2017 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems collocated with the ASME 2017 Conference on Information Storage and Processing Systems. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/ipack2017-74150.

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PARC, a Xerox Company, is developing a low-cost system of peel-and-stick wireless sensors that will enable widespread building environment sensor deployment with the potential to deliver up to 30% energy savings. The system is embodied by a set of RF hubs that provide power to automatically located sensor nodes, and relay data wirelessly to the building management system (BMS). The sensor nodes are flexible electronic labels powered by rectified RF energy transmitted by an RF hub and can contain multiple printed and conventional sensors. The system design overcomes limitations in wireless sensors related to power delivery, lifetime, and cost by eliminating batteries and photovoltaic devices. Sensor localization is performed automatically by the inclusion of a programmable multidirectional antenna array in the RF hub. Comparison of signal strengths while the RF beam is swept allows for sensor localization, reducing installation effort and enabling automatic recommissioning of sensors that have been relocated, overcoming a significant challenge in building operations. PARC has already demonstrated wireless power and temperature data transmission up to a distance of 20m with less than one minute between measurements, using power levels well within the FCC regulation limits in the 902–928 MHz ISM band. The sensor’s RF energy harvesting antenna achieves high performance with dimensions below 5cm × 9cm.
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Shim, Sunbo, Bonhoon Koo, and Songcheol Hong. "A highly-linear CMOS RF programmable-gain driver amplifier with a digital-step differential attenuator for RF transmitters." In 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC). IEEE, 2013. http://dx.doi.org/10.1109/rfic.2013.6569629.

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