Relevant bibliographies by topics / Programmable networking hardware

Academic literature on the topic 'Programmable networking hardware'

Author: Grafiati
Published: 10 December 2022
Last updated: 28 January 2023

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Journal articles on the topic "Programmable networking hardware"

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Nagarjuna Reddy, Tella, and K. Annapurani Panaiyappan. "Intrusion Detection on Software Defined Networking." International Journal of Engineering & Technology 7, no. 3.12 (July 20, 2018): 330. http://dx.doi.org/10.14419/ijet.v7i3.12.16052.

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Software Defined Networking and programmability on network have established themselves as current trends in IT by bringing autonomous operation with dynamic flow to network. Networks must be programmable, and it must be aware of the application in order to operate autonomously. Networks need to evolve to catch up with the current trends without losing their current status and operation, reliability, robustness, or security, and without distorting current investments. SDN is a transpiring network architecture where network control plane is distinguished from data plane and by that the network is directly programmable. This control, was initially bound in every network devices, enabled in the network to be abstracted for applications and services. Security is a major challenge for organizational and campus networks. The future of Internet depends on virtualization which is to provide numerous networks hosted the same physical hardware. This proposal takes a great advantage of the programmability provided by SDN to utilize Intrusion Detection System.
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Jepsen, Theo, Alberto Lerner, Fernando Pedone, Robert Soulé, and Philippe Cudré-Mauroux. "In-network support for transaction triaging." Proceedings of the VLDB Endowment 14, no. 9 (May 2021): 1626–39. http://dx.doi.org/10.14778/3461535.3461551.

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We introduce Transaction Triaging, a set of techniques that manipulate streams of transaction requests and responses while they travel to and from a database server. Compared to normal transaction streams, the triaged ones execute faster once they reach the database. The triaging algorithms do not interfere with the transaction execution nor require adherence to any particular concurrency control method, making them easy to port across database systems. Transaction Triaging leverages recent programmable networking hardware that can perform computations on in-flight data. We evaluate our techniques on an in-memory database system using an actual programmable hardware network switch. Our experimental results show that triaging brings enough performance gains to compensate for almost all networking overheads. In high-overhead network stacks such as UDP/IP, we see throughput improvements from 2.05X to 7.95X. In an RDMA stack, the gains range from 1.08X to 1.90X without introducing significant latency.
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Jaziri, Ibtihel, Lotfi Charaabi, and Khaled Jelassi. "Remote web-based control laboratories using embedded Linux and field-programmable gate array." Proceedings of the Institution of Mechanical Engineers, Part I: Journal of Systems and Control Engineering 232, no. 9 (May 28, 2018): 1146–54. http://dx.doi.org/10.1177/0959651818776542.

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In this article, the authors present a new approach based on the hardware and software architecture using embedded Linux and field-programmable gate array for implementation of remote laboratories. It combines a set of software and hardware resources in the interest of offering a multidisciplinary low-cost open platform for engineering education. Thus, the proposed approach allows students to develop low-cost and easily programmable prototypes of electrical systems control, robotics, and other embedded devices that feature Internet connectivity, Input/output, networking, and operating systems. In the proposed work, the authors present a codesign solution with flexible hardware devices, providing characteristics of multipurpose use with many experimental devices, and fully configurable graphical user interface. The physical setup and communication principles of hardware architecture are based on two types of devices: the Beaglebone running embedded Linux operating system and the field-programmable logic gate array. The graphical user interface is designed as a web page based on HTML and PHP programming languages; this allows the teachers/students to control the system easily, parameterize, and observe the behavior of the controller/system remotely.
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Fernández, Carolina, Sergio Giménez, Eduard Grasa, and Steve Bunch. "A P4-Enabled RINA Interior Router for Software-Defined Data Centers." Computers 9, no. 3 (September 2, 2020): 70. http://dx.doi.org/10.3390/computers9030070.

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The lack of high-performance RINA (Recursive InterNetwork Architecture) implementations to date makes it hard to experiment with RINA as an underlay networking fabric solution for different types of networks, and to assess RINA’s benefits in practice on scenarios with high traffic loads. High-performance router implementations typically require dedicated hardware support, such as FPGAs (Field Programmable Gate Arrays) or specialized ASICs (Application Specific Integrated Circuit). With the advance of hardware programmability in recent years, new possibilities unfold to prototype novel networking technologies. In particular, the use of the P4 programming language for programmable ASICs holds great promise for developing a RINA router. This paper details the design and part of the implementation of the first P4-based RINA interior router, which reuses the layer management components of the IRATI Linux-based RINA implementation and implements the data-transfer components using a P4 program. We also describe the configuration and testing of our initial deployment scenarios, using ancillary open-source tools such as the P4 reference test software switch (BMv2) or the P4Runtime API.
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Reinehr Gobatto, Leonardo, Pablo Rodrigues, Mateus Saquetti Pereira de Carvalho Tirone, Weverton Luis da Costa Cordeiro, and José Rodrigo Furlanetto Azambuja. "Programmable Data Planes meets In-Network Computing: A Review of the State of the Art and Prospective Directions." Journal of Integrated Circuits and Systems 16, no. 2 (August 17, 2021): 1–8. http://dx.doi.org/10.29292/jics.v16i2.497.

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Improving network traffic in networks is one of the concerns between networking researchers and network operators since the architecture of modern networks still faces challenges to process large data traffic without the cost of consuming a significant amount of resources not related to computing specifically. On the other hand, network programmability has enabled the development of new applications and network services, from software-defined networking to domain-specific languages created to program network devices and specify their behavior. The development of programmable hardware and hardware accelerators like FPGAs, GPUs, and CPUs help this new paradigm go one step further. Use the artifact of programmability of these devices to solve problems, such as improve the processing of data traffic is the key of in-network computing. It offers the opportunity to execute programs typically running on end-hosts within programmable network devices already incorporated on the network, thus being capable of provides a reduction on the in-network processing load and requires no extra cost, since operations can be concluded using a fewer amount of devices of the network and no extra device are needed. In this paper, we survey in-network computing, as well as we suggest classifying related works to in-network computing according to the hardware accelerator used. Also, we discuss challenges and research directions.
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Jipping, Michael J., Agata Bugaj, Liliyana Mihalkova, and Donald E. Porter. "Using Java to teach networking concepts with a programmable network sniffer." ACM SIGCSE Bulletin 35, no. 1 (January 11, 2003): 120–24. http://dx.doi.org/10.1145/792548.611948.

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Tsai, Pang Wei, Hou Yi Chou, Mon Yen Luo, and Chu Sing Yang. "Design a Flexible Software Development Environment on NetFPGA Platform." Applied Mechanics and Materials 411-414 (September 2013): 1665–69. http://dx.doi.org/10.4028/www.scientific.net/amm.411-414.1665.

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Among numerous embedded platforms, NetFPGA provides developers with a freely programmable FPGA component to design custom functionalities in networking. However, most hardware projects are developed based on reference designs without embedded operating system. For hybrid developments on multi-layers, there will be some difficulties to apply. On the other hand, due to the limited resources on embedded platform, both performance and flexibility need to be concerned on implementation. And for networking processing, it is quite difficult to adjust control parameters without software environment. Therefore, this paper proposes an integrated architecture using PowerPC processor on NetFPGA and embedded Linux operating system on NetFPGA platform. This not only provides developers with an environment for software execution which added more flexibility, but also enhanced the system to provide more applied possibilities on development.
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LY, SUNG, and ABBAS BIGDELI. "EXTENDABLE AND DYNAMICALLY RECONFIGURABLE MULTI-PROTOCOL FIREWALL." International Journal of Software Engineering and Knowledge Engineering 15, no. 02 (April 2005): 363–71. http://dx.doi.org/10.1142/s0218194005001926.

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Security issues within a networking environment are critical, as attacks or intrusions can come from many different sources. Firewalls are an effective tool used for intrusion detection and provide protection against attacks on a system or network. In the past, protection barriers for a local network have been provided using software solutions. Emerging multi-gigabit networking technology and the high uptake of gigabit Ethernet has rendered these solutions inefficient as it cannot cope with the high data rate. In this paper, a new approach using reconfigurable hardware such as Field Programmable Gate Arrays is proposed to provide the flexibility and performance required for a gigabit firewall. The solution is extendable, has low cost and is capable of scanning multiple protocols. The design approach will allow it to be easily ported over to another family of chips with no or minor modification.
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Huang, LinYun, Young-Pil Lee, Yong-Seon Moon, and Young-Chul Bae. "Noble Implementation of Motor Driver with All Programmable SoC for Humanoid Robot or Industrial Device." International Journal of Humanoid Robotics 14, no. 04 (November 16, 2017): 1750028. http://dx.doi.org/10.1142/s0219843617500281.

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Currently, as the requirements for simple implementations in the motor control technologies increase, System-on-Chip (SoC) device such as Zynq All Programmable SoC was devised to meet those requirements. Because this CPU and FPGA can be assembled into one SoC device, we can consolidate motor-control functions and additional processing tasks into a single SoC device. The control algorithms, networking and other tasks, are off-loaded to the programmable logic that can include multiple control cores and multiple control system. This SoC system with a single chip can allow the hardware design with a single chip, hence, we can implement to control the motor to be simpler, more reliable, and less expensive. In this paper, in order to implement motor controller, we apply latest All Programmable SoC technologies for humanoid robot or industrial device that is integrated with FPGA technologies and embedded processor technologies. We also propose the structure of motor controller that decentralizes the function of motor driver from previous typical motor driver into FPGA and level of embedded processor by using All Programmable SoC for humanoid robot or industrial device. We verify the possibilities of applying the novel implemented motor controller in Zynq EPP (Extensible Processing Platform) which is one kind of All Programmable SoC made by Xilinx. To do this, we perform velocity control and position control with digital PI controller on the BLDC motor.
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Kang, Liyi, Xiao Chen, and Jun Chen. "Design and Implementation of Enhanced Programmable Data Plane Supporting ICN Mobility." Electronics 11, no. 16 (August 12, 2022): 2524. http://dx.doi.org/10.3390/electronics11162524.

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Information-centric networking (ICN) separates the identifier and locator of network entities, providing a natural advantage in supporting mobility. To gain the advantage of ICN to support mobility, an urgent challenge is the problem of practical implementation with performance optimization. Software-defined networking (SDN) can be regarded as infrastructure to implement ICN mobility. However, it is difficult for the centralized SDN controller to quickly process mobile signaling. Therefore, this paper proposes enhanced programmable data plane supporting ICN mobility. By offloading mobility-related control plane functions from the controller to the data plane, the data plane can locally process mobile signaling without interacting with the controller. We propose an offloading mechanism for control plane functions, based on a rule table, where the controller authorizes the data plane to process the mobile signaling by loading the programmable rule table to data plane’s control element, and the control element intercepts the mobile signaling, matches the predefined rule table, and executes a series of application logic actions. In addition, we propose an improved SmartSplit algorithm to manage the rule table and speed up packets matching the rule table. Based on Intel’s Data Plane Development Kit (DPDK), we implement the enhanced programmable data plane. Our experimental results prove that the proposed enhanced programmable data plane has a stronger ability to process mobile signaling and reduce latency.
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Dissertations / Theses on the topic "Programmable networking hardware"

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Lalevée, André. "Towards highly flexible hardware architectures for high-speed data processing : a 100 Gbps network case study." Thesis, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire, 2017. http://www.theses.fr/2017IMTA0054/document.

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L’augmentation de la taille des réseaux actuels ainsi que de la diversité des applications qui les utilisent font que les architectures de calcul traditionnelles deviennent limitées. En effet, les architectures purement logicielles ne permettent pas de tenir les débits en jeu, tandis que celles purement matérielles n’offrent pas assez de flexibilité pour répondre à la diversité des applications. Ainsi, l’utilisation de solutions de type matériel programmable, en particulier les Field Programmable Gate Arrays (FPGAs), a été envisagée. En effet, ces architectures sont souvent considérées comme un bon compromis entre performances et flexibilité, notamment grâce à la technique de Reconfiguration Dynamique Partielle (RDP), qui permet de modifier le comportement d’une partie du circuit pendant l’exécution. Cependant, cette technique peut présenter des inconvénients lorsqu’elle est utilisée de manière intensive, en particulier au niveau du stockage des fichiers de configuration, appelés bitstreams. Pour palier ce problème, il est possible d’utiliser la relocation de bitstreams, permettant de réduire le nombre de fichiers de configuration. Cependant cette technique est fastidieuse et exige des connaissances pointues dans les FPGAs. Un flot de conception entièrement automatisé a donc été développé dans le but de simplifier son utilisation.Pour permettre une flexibilité sur l’enchaînement des traitements effectués, une architecture de communication flexible supportant des hauts débits est également nécessaire. Ainsi, l’étude de Network-on-Chips dédiés aux circuits reconfigurables et au traitements réseaux à haut débit.Enfin, un cas d’étude a été mené pour valider notre approche
The increase in both size and diversity of applications regarding modern networks is making traditional computing architectures limited. Indeed, purely software architectures can not sustain typical throughputs, while purely hardware ones severely lack the flexibility needed to adapt to the diversity of applications. Thus, the investigation of programmable hardware, such as Field Programmable Gate Arrays (FPGAs), has been done. These architectures are indeed usually considered as a good tradeoff between performance and flexibility, mainly thanks to the Dynamic Partial Reconfiguration (DPR), which allows to reconfigure a part of the design during run-time.However, this technique can have several drawbacks, especially regarding the storing of the configuration files, called bitstreams. To solve this issue, bitstream relocation can be deployed, which allows to decrease the number of configuration files required. However, this technique is long, error-prone, and requires specific knowledge inFPGAs. A fully automated design flow has been developped to ease the use of this technique. In order to provide flexibility regarding the sequence of treatments to be done on our architecture, a flexible and high-throughput communication structure is required. Thus, a Network-on-Chips study and characterization has been done accordingly to network processing and bitstream relocation properties. Finally, a case study has been developed in order to validate our approach
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Book chapters on the topic "Programmable networking hardware"

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Sheybani, Ehsan. "Universal Software Radio Peripheral/GNU Radio-Based Implementation of a Software-Defined Radio Communication System." In Strategic Innovations and Interdisciplinary Perspectives in Telecommunications and Networking, 227–40. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-8188-8.ch012.

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Challenges involved in space communications across wireless channels call for new approaches to radio systems. Due to the growing need for frequency change in modern wireless systems, an adaptive radio system has the highest demand. Software-defined radios (SDR) offer this type of adaptivity as well as compatibility with other standard platforms such as USRP/GNU radio. Despite limitations of this approach due to hardware components, viable modeling and simulation as well as deployable systems are possible using this platform. This chapter presents a detailed implementation procedure for a USRP/GNU radio-based SDR communication system that can be used for practical experiments as well as an academic lab in this field. In this experiment the USRP has been configured to receive signal from a local radio station using the BasicRX model daughterboard. The programmable USRP executes Python block code implemented in the GNU Radio Companion (GRC) on Ubuntu OS.
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Hagos, Desta Haileselassie. "Software-Defined Networking for Scalable Cloud-Based Services to Improve System Performance of Hadoop-Based Big Data Applications." In Web Services, 1460–84. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-7501-6.ch076.

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The rapid growth of Cloud Computing has brought with it major new challenges in the automated manageability, dynamic network reconfiguration, provisioning, scalability and flexibility of virtual networks. OpenFlow-enabled Software-Defined Networking (SDN) alleviates these key challenges through the abstraction of lower level functionality that removes the complexities of the underlying hardware by separating the data and control planes. SDN has an efficient, dynamic, automated network management, higher availability and application provisioning through programmable interfaces which are very critical for flexible and scalable cloud-based services. In this study, the author explores broadly useful open technologies and methodologies for applying an OpenFlow-enabled SDN to scalable cloud-based services and a variety of diverse applications. The approach in this paper introduces new research challenges in the design and implementation of advanced techniques for bringing an SDN-enabled components and big data applications into a cloud environment in a dynamic setting. Some of these challenges become pressing concerns to cloud providers when managing virtual networks and data centers, while others complicate the development and deployment of cloud-hosted applications from the perspective of developers and end users. However, the growing demand for manageable, scalable and flexible clouds necessitates that effective solutions to these challenges be found. Hence, through real-world research validation use cases, this paper aims at exploring useful mechanisms for the role and potential of an OpenFlow-enabled SDN and its direct benefit for scalable cloud-based services. Finally, it demonstrates the impact of an OpenFlow-enabled SDN that fully embraces the opportunities and challenges of cloud infrastructures to improve the system performance of Hadoop-based big data applications by utilizing the network control capabilities of an OpenFlow to solve network congestion.
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Conference papers on the topic "Programmable networking hardware"

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Brebner, Gordon. "Programmable Hardware in Software Defined Networking." In Optical Fiber Communication Conference. Washington, D.C.: OSA, 2015. http://dx.doi.org/10.1364/ofc.2015.m3h.3.

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Harkous, Hasanin, Michael Jarschel, Mu He, Rastin Priest, and Wolfgang Kellerer. "Towards Understanding the Performance of P4 Programmable Hardware." In 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS). IEEE, 2019. http://dx.doi.org/10.1109/ancs.2019.8901881.

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Wong, Michael D., Aatish Kishan Varma, and Anirudh Sivaraman. "Testing compilers for programmable switches through switch hardware simulation." In CoNEXT '20: The 16th International Conference on emerging Networking EXperiments and Technologies. New York, NY, USA: ACM, 2020. http://dx.doi.org/10.1145/3386367.3431309.

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Khan, Asif, and Nirav Dave. "Enabling Hardware Exploration in Software-Defined Networking: A Flexible, Portable OpenFlow Switch." In 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM). IEEE, 2013. http://dx.doi.org/10.1109/fccm.2013.15.

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Kundel, Ralf, Fridolin Siegmund, and Boris Koldehofe. "How to measure the speed of light with programmable data plane hardware?" In 2019 ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS). IEEE, 2019. http://dx.doi.org/10.1109/ancs.2019.8901871.

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Tavares, Kairo, and Tiago Coelho Ferreto. "DDoS on Sketch: Spoofed DDoS attack defense with programmable data plans using sketches in SDN." In XXXVII Simpósio Brasileiro de Redes de Computadores e Sistemas Distribuídos. Sociedade Brasileira de Computação - SBC, 2019. http://dx.doi.org/10.5753/sbrc.2019.7404.

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Distributed Denial of Service (DDoS) attacks continues to be a major issue in todays Internet. Over the last few years, we have observed a dramatic escalation in the number, scale, and diversity of these attacks. Among the various types, spoofed TCP SYN Flood is one of the most common forms of volumetric DDoS attacks. Several works explored the flexible management control provided by the new network paradigm called Defined Networking Software (SDN) to produce a flexible and powerful defense system. Among them, data plane based solutions combined with recent flexibility of programmable switches aims to leverage hardware speed and defend against Spoofed Flooding attacks. Usually, they implement anti-spoofing mechanisms that rely on performing client authentication on the data plane using techniques such as TCP Proxy, TCP Reset, and Safe Reset. However, these mechanisms have several limitations. First, due to the required interaction to authenticate the client, they penalize all clients connection time even without an ongoing attack. Second, they use a limited version of TCP cookies to detect a valid client ACK or RST, and finally, they are vulnerable to a buffer saturation attack due to limited data plan resources that stores the whitelist of authenticated users. In this work, we propose the use of sketch-based solutions to improve the data plane Safe Reset anti-spoofing defense mechanism. We implemented our solution in P4, a high-level language for programmable data planes, and evaluate our solution against a data plan. Safe Reset technique on an emulated environment using Mininet.
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Lechler, Armin, and Alexander Verl. "Software Defined Manufacturing Extends Cloud-Based Control." In ASME 2017 12th International Manufacturing Science and Engineering Conference collocated with the JSME/ASME 2017 6th International Conference on Materials and Processing. American Society of Mechanical Engineers, 2017. http://dx.doi.org/10.1115/msec2017-2656.

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Nowadays, the key goal in manufacturing is being very efficient within changing markets and under turbulent conditions. Therefore, production plants with their machines logistics and all the other involved components have to be adaptable to changing conditions. For this reason, reconfigurable manufacturing systems are needed, which allow a fast adaption to new requirements of the product to be manufactured. Today, reconfiguration in manufacturing is mostly limited due to missing reconfigurability of the control software in combination with the underlying hardware. The coupling is that strong that in manufacturing control software is always bound to special hardware. Until now, flexibility is only possible by changing application or part programs that are interpreted by a fixed control kernel. The adaption of any core functionality is impossible, and any other changes require high manual effort for redesigning software systems and parametrizing their functionalities. For better adaptability in manufacturing this coupling has to be dissolved. Other disciplines and industries have similar requirements like the information and communication technology (ICT). In the area of ICT, there are more and more concepts of Software Defined Anything (SDX) like Software Defined Networking (SDN) or Software Defined Radio (SDR). Flexible, adaptive and really reconfigurable manufacturing should be improved by a new concept of Software Defined Manufacturing (SDM). SDM allows freely defined functionalities within the physical limitations of the mechanical and electrical components of a machine. But current manufacturing equipment with its control architecture does not offer the technical basis for such a concept. Existing concepts of cloud-based control architectures show indeed a virtualization of the control algorithms. Due to the fact that the software is running remotely, the software is decoupled from its hardware. However, the local control algorithms with hard real-time requirements still have a very strong coupling with the hardware. The local control software could not be defined freely according to the requirements of the product to be manufactured. In this paper, a new control architecture for manufacturing that combines cloud-based control as a service (CaaS) and Software Defined Manufacturing is presented. As a result, an architecture of an operating system for manufacturing equipment is shown, which is freely programmable. This paper deals with Software Defined Manufacturing for local control software, communication and cloud-based control systems. SDM allows defining the behavior of the entire manufacturing process based on design description of a product to be manufactured. In addition, methods are described, which allow the automatic configuration and optimization of such an architecture by using simulation technics and collected process data.
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