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Journal articles on the topic 'Programmable logic integrated circuits'

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Published: 30 May 2022
Last updated: 31 May 2022

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1

Brukštus, Tautvydas. "ANALYSIS AND IMPLEMENTATION OF CRYPTOGRAPHIC HASH FUNCTIONS IN PROGRAMMABLE LOGIC DEVICES / KRIPTOGRAFINIŲ MAIŠOS FUNKCIJŲ ĮGYVENDINIMO PROGRAMUOJAMOSIOS LOGIKOS LUSTUOSE TYRIMAS." Mokslas – Lietuvos ateitis 8, no. 3 (June 29, 2016): 321–26. http://dx.doi.org/10.3846/mla.2016.927.

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In this day’s world, more and more focused on data protection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryptographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryptographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less efficiency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be investigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integrated circuit made using different dimension technology. Choosing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Research show the calculation speed and stability of different programmable logic circuits. Vis daugiau dėmesio skiriama duomenų apsaugai – duomenų apsaugai skirta net atskira kriptografijos mokslo šaka. Taip pat yra svarbi slaptažodžių sauga, kurioje naudojamos kriptografinės maišos funkcijos. Darbe parinkta įgyvendinimui ir ištirta šiuo metu populiari bei saugi SHA-2 kriptografinė maišos funkcija. Ji naudojama kriptografinėse valiutose. SHA-2 kriptografinės funkcijos analizės metu nepavyko rasti teorinių spragų ar kolizijos atvejų. Tyrimams pasirinkti Altera programuojamos logikos integriniai grandynai, kurie efektyvumu nusileidžia tik specializuotiems integriniams grandynams. Skaičiavimo sparta ir stabilumas buvo tiriama trijuose programuojamos logikos integrinuose grandynuose, priklausančiuose tai pačiai šeimai ir pagamintais skirtingų kartų technologijomis – naudojant 65 nm, 60 nm ir 28 nm KMOP technologijas. Tirtų grandynų kodiniai žymenys EP3C16, EP4CE115 ir 5CSEMA5F31.
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2

Grekov, Artem Vladimirovich, and Vadim Borisovich Uspalenko. "PERSPECTIVE PROGRAMMABLE LOGIC INTEGRATED CIRCUITS FPGA FROM ALTERA." V mire nauchnykh otkrytiy, no. 6.1 (November 22, 2014): 518. http://dx.doi.org/10.12731/wsd-2014-6.1-13.

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3

Sou, Antony, Sungjune Jung, Enrico Gili, Vincenzo Pecunia, Jerome Joimel, Guillaume Fichet, and Henning Sirringhaus. "Programmable logic circuits for functional integrated smart plastic systems." Organic Electronics 15, no. 11 (November 2014): 3111–19. http://dx.doi.org/10.1016/j.orgel.2014.08.032.

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4

Shipulin, S. N., and S. N. Shilyaev. "Use of programmable integrated logic circuits in measurement engineering." Measurement Techniques 37, no. 2 (February 1994): 136–38. http://dx.doi.org/10.1007/bf00979200.

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5

Pashukov, A. V. "RESEARCH OF PECULIARITIES OF ERROR DETECTION ON THE OUTPUTS OF PROGRAMMABLE LOGIC INTEGRATED CIRCUITS WITH FUNCTIONAL CONTROL BASED ON MODULAR CODES WITH SUMMATION." Automation on Transport 7, no. 3 (September 2021): 477–95. http://dx.doi.org/10.20295/2412-9186-2021-7-3-477-495.

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The article provides examples of the use of programmable logic integrated circuits in various industries. Possible faults in FPGA blocks and their difference from faults in programmable logic arrays are described. Particular attention is paid to the failures of the LUT element. Features of the organization of technical diagnostics systems operating in the operating mode of the objects of diagnostics for combinational logic devices, implemented on the basis of programmable logic integrated circuits are described. Using the example of modular summation codes, it is shown that the known approaches to organizing such systems for devices implemented on a valve basis can be directly applied to devices of the type under consideration. Since malfunctions in the form of errors are recorded, and not the malfunctions themselves, the approaches to the organization of diagnostic systems are universal. It also provides a comparative characteristic of modular sum codes depending on the code module. A code has been proposed that will detect all faults in the example under study.
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6

Пирогов, А. А., Ю. А. Пирогова, С. А. Гвозденко, Д. В. Шардаков, and Б. И. Жилин. "DEVELOPMENT OF RECONFIGURABLE DEVICES BASED ON PROGRAMMABLE LOGIC INTEGRATED CIRCUITS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, no. 6 (January 10, 2021): 90–97. http://dx.doi.org/10.36622/vstu.2020.16.6.013.

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Цифровая фильтрация распознаваемых сигналов является непременной процедурой при обнаружении и распознавании сообщений. Под фильтрацией понимают любое преобразование сигналов, при котором во входной последовательности обрабатываемых данных целенаправленно изменяются определенные соотношения между различными параметрами сигналов. Системы, избирательно меняющие форму сигналов, устраняющие или уменьшающие помехи, извлекающие из сигналов определенную информацию и т.п., называют фильтрами. Соответственно, фильтры с любым целевым назначением являются частным случаем систем преобразования сигналов. Программируемые логические интегральные схемы (ПЛИС) представляют собой конфигурируемые интегральные схемы, логика работы которых определяется посредством их программирования. Применение ПЛИС для задач цифровой обработки сигналов позволяет получать устройства, способные менять конфигурацию, подстраиваться под определенную задачу за счет их гибко изменяемой, программируемой структуры. При разработке сложных устройств могут применяться в качестве компонентов для проектирования готовые блоки - IP-ядра или сложно-функциональные блоки (СФ-блоки). Использование программных СФ-блоков позволяет наиболее эффективно задействовать их в конечной структуре, в значительной степени сократить затраты на проектирование. Цель работы состоит в построении RTL модели СФ-блока цифровой обработки сигналов, его верификации как на логическом уровне, так и физическом Digital filtering of recognized signals is an indispensable procedure for the detection and recognition of messages. Filtering is understood as any transformation of signals in which certain relationships between different signal parameters are purposefully changed in the input sequence of the processed data. Systems that selectively change the shape of signals, eliminate or reduce interference, extract certain information from the signals, and so on, are called filters. Accordingly, filters with any purpose are a special case of signal conversion systems. Programmable logic integrated circuits (FPGAs) are configurable integrated circuits whose logic is defined through programming. The use of FPGAs for digital signal processing tasks makes it possible to obtain devices capable of changing the configuration, adapting to a specific task due to their flexibly changeable, programmable structure. When developing complex devices, ready-made blocks - IP-cores or complex-functional blocks (SF blocks) - can be used as components for design. The use of software SF-blocks allows them to be used most effectively in the final structure, to a significant extent to reduce design costs. The purpose of the work is to build an RTL model of the SF-block for digital signal processing, its verification both at the logical and physical levels
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7

Lashin, A. V., and A. V. Kozyrev. "Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits." Power Technology and Engineering 49, no. 3 (September 2015): 216–18. http://dx.doi.org/10.1007/s10749-015-0602-6.

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8

Trost, Andrej, Andrej Zemva, and Matjaz Verderber. "Prototyping Hardware and Software Environment for Teaching Digital Circuit Design." International Journal of Electrical Engineering & Education 38, no. 4 (October 2001): 368–78. http://dx.doi.org/10.7227/ijeee.38.4.9.

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In the paper, we present our latest achievements and experience in undergraduate teaching of digital circuits, integrated circuits and embedded systems by exploiting our prototyping hardware and software environment. The hardware environment is based on Field Programmable Gate Array (FPGA) modules that provide sufficient flexibility and support a broad scope of digital design applications. In addition, the designed software environment supports user-friendly hardware verification of the logic circuits implemented on the hardware system. We describe some typical applications and student projects implemented on the programmable prototyping system.
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9

Melnyk, Oleksandr, and Viktoriia Kozarevych. "SIMULATION OF PROGRAMMABLE SINGLE-ELECTRON NANOCIRCUITS." Bulletin of the National Technical University "KhPI". Series: Mathematical modeling in engineering and technologies, no. 1 (March 5, 2021): 64–68. http://dx.doi.org/10.20998/2222-0631.2020.01.05.

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The speed and specializations of large-scale integrated circuits always contradict their versatility, which expands their range and causes the rise in price of electronic devices. It is possible to eliminate the contradictions between universality and specialization by developing programmable nanoelectronic devices, the algorithms of which are changed at the request of computer hardware developers, i.e. by creating arithmetic circuits with programmable characteristics. The development of issues of theory and practice of the majority principle is now an urgent problem, since the nanoelectronic execution of computer systems with programmable structures will significantly reduce their cost and significantly simplify the design stage of automated systems. Today there is an important problem of developing principles for building reliable computer equipment. The use of mathematical and circuit modeling along with computer-aided design systems (CAD) can significantly increase the reliability of the designed devices. The authors prove the advantages of creating programmable nanodevices to overcome the physical limitations of micro-rominiatization. This continuity contributes to the accelerated introduction of mathematical modeling based on programmable nanoelectronics devices. The simulation and computer-aided design of reliable programmable nanoelectronic devices based on the technology of quantum automata is described. While constructing single-electron nanocircuits of combinational and sequential types the theory of majority logic is used. The order of construction and programming of various types of arithmetic-logic units is analyzed.
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10

Tyurin, S. F., and O. A. Gromov. "A residual basis search algorithm of fault-tolerant programmable logic integrated circuits." Russian Electrical Engineering 84, no. 11 (November 2013): 647–51. http://dx.doi.org/10.3103/s1068371213110163.

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11

Irmansyah, Muhammad. "MULTIPLEKSER BERBASIS PROGRAMMABLE LOGIC DEVICE (PLD)." Elektron : Jurnal Ilmiah 1, no. 2 (December 18, 2009): 13–18. http://dx.doi.org/10.30630/eji.1.2.16.

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In middle 1990, electronics industry had the evolution of personal Computer, telephone cellular and high speed data communication equipment. To follow this development, electronics companies have designed and produce new product. One of these innovations is Programmable Logic Devices (PLD) technology. It is a technology to change function of IC digital logic using programming. Many of Programmable Logic Device (PLD) can be used to programming logic using single chip of integrated circuit (IC). Programmable Logic Devices (PLD) technology is applied using IC PAL 22V10 to design multiplexer 4 input 1 output and 2 selector.
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12

Vasil’ev, A. E., G. S. Vasil’yanov, D. F. Cabezas Tapia, A. E. Pereverzev, and Nguyen Boi Hue. "Hardware Implementation of High-Performance Fuzzy Computations Based on Programmable Logic Integrated Circuits." Journal of Communications Technology and Electronics 62, no. 12 (December 2017): 1414–26. http://dx.doi.org/10.1134/s1064226917110183.

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13

Lyubchinova, V. V. "AUTOMATION OF THE DESIGN OF A DEVICE BASED ON PROGRAMMABLE LOGIC INTEGRATED CIRCUITS." YOUNG RUSSIA HIGH TECHNOLOGY – INTO INDUSTRY, no. 1 (2021): 035–38. http://dx.doi.org/10.25206/2310-4597-2021-1-35-38.

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В статье рассмотрена возможность автоматизации проектирования устройства на ПЛИС. Такие устройства применяются во многих сферах радиоэлектронной промышленности. Полученный алгоритм позволит сократить временные затраты на проектирование приемо-передающих устройств.
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14

Irmansyah, Muhammad. "GERBANG LOGIKA BERBASIS PROGRAMMABLE LOGIC DEVICE (PLD)." Elektron : Jurnal Ilmiah 1, no. 1 (September 10, 2009): 75–81. http://dx.doi.org/10.30630/eji.1.1.12.

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In middle 1990, electronics industry had evolution in personal Computer, telephone cellular and high speed data communication equipment. To follow this development, electronics companies have designed and produce new product. One of these innovations is Programmable Logic Devices (PLD) technology. It is a technology to change function of IC digital logic using programming. Many of Programmable Logic Device (PLD) can be used to programming logic using single chip of integrated circuit (IC). Programmable Logic Devices (PLD) technology is applied using IC PAL 22V10 to design basic logic gate AND, OR, NOT and combinational logic gate NAND and NOR.
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15

Kostikova, E. V., S. A. Seliverstov, Ya A. Seliverstov, and Sh S. Fahmi. "Measuring the Speed of Data Exchange in Memory Cards Using Programmable Logic Integrated Circuits." Measurement Techniques 62, no. 1 (April 2019): 23–30. http://dx.doi.org/10.1007/s11018-019-01580-7.

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16

Shtanenko, Serhii, Yurii Samokhvalov, Olexandr Iohov, and Victor Maliuk. "Microprocessor systems based on programmable logic devices as an object of diagnostics." Advanced Information Systems 6, no. 1 (April 6, 2022): 81–87. http://dx.doi.org/10.20998/2522-9052.2022.1.14.

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The subject of research in the article is the methods of testing digital devices implemented on programmable logic devices (PLDs). The aim of the research is to substantiate the approach to diagnosing microprocessor systems based on PLD, which is a further development of the self-diagnostics method. The following tasks are solved in the article: the analysis of existing methods for testing digital devices is conducted, their advantages and disadvantages are disclosed; analyzed the existing approaches to the diagnosis of microprocessor systems, which are based on integrated circuits with a programmable structure; an approach to diagnosing microprocessor systems based on PLDs is proposed, which is based on the principle of interaction between processors by introducing a service processor into a multiprocessor system. The following results have been obtained: it has been proved that the implementation of the proposed models of interaction between processors in a multiprocessor system will provide the service processor with diagnostic information about the technical state of the system. It is noted that the availability of diagnostic information about the technical condition of the microprocessor system is the basis for making a decision to restore the system by reprogramming the PLD. Conclusions: the problem of diagnosing microprocessor systems in the PLD basis is considered. The analysis of existing methods for testing integrated circuits with a programmable structure has been conducted, their advantages and disadvantages have been noted. It is proposed to use the built-in service processor as a diagnostic device, the main function of which is to collect diagnostic information and make a decision on the reconfiguration of the microprocessor system in order to quickly restore its functioning automatically.
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Yudachev, S. S., S. S. ,. Sitnikov, N. A. ,. Gordienko, and P. A. Monakhov. "Operation description and creating an analog VGA output on the debugging board when making programs for CNC machines." Glavnyj mekhanik (Chief Mechanic), no. 2 (January 18, 2022): 88–99. http://dx.doi.org/10.33920/pro-2-2202-01.

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The priority task of the development of mechanical engineering is complex mechanization and automation of technological processes of mechanical processing. This problem can be solved by the introduction of machine tools and machine complexes with numerical control. CNC equipment combines the flexibility of universal and high performance of special automatic equipment, which significantly changes the nature of production and makes it mobile, meeting the requirements for continuous improvement and updating of mechanical engineering products. However, such equipment is quite complex, and its acquisition is associated with large financial costs, therefore, the problem of efficient use of CNC machines is a priority for most mechanical engineering enterprises and is inextricably linked with the need to create various programs. The article presents a theoretical analysis of the VGA interface, as well as a practical implementation of this interface, written in the Verilog programming language, on the Terasic DE10-Lite debugging board, with the MAX10 10M50DAF484C7G programmable logic integrated circuit and other peripheral modules. The practical significance of the work is familiarizing with programmable logic integrated circuits of the Intel FPGA family, obtaining basic knowledge in working with the Quartus Lite computer-aided design system (CAD), and learning the basics of programming programmable logic integrated circuits in the Verilog language. In the course of the work, the algorithm for writing code in the Verilog programming language for implementing the VGA interface on the DE10-Lite debugging board was described in detail. The software and mathematical excerpts used in the work are publicly available on the Internet, which allows anyone to carry out similar work and make sure that the written codes and the obtained conclusions are correct. This work can be used not only for writing programs for machine tools, but also for teaching students in the field of developing electronic devices in terms of their algorithmization and for organizing laboratory work, as well as for creating and designing real devices both in production and within a higher educational institution, for example, for developing laboratory work using specialized CAD. Familiarization and study of this programming language are conducted within the walls of one of the leading engineering universities of the Russian Federation, the Bauman Moscow State Technical University.
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MANULIAK, I., S. MELNYCHUK, S. VASCHYSHAK, and S. RUDAK. "IMPLEMENTATION OF THE SLIDING MEDIAN METHOD ON FPGA FOR SENSOR SIGNALS PRE-PROCESSING." HERALD OF KHMELNYTSKYI NATIONAL UNIVERSITY 295, no. 2 (May 2021): 35–39. http://dx.doi.org/10.31891/2307-5732-2021-295-2-35-39.

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The use of modern hardware platforms in the development of computer system components, including digital signal processing, allows to describe circuit solutions using specialized languages such as AlteraHDL, VHDL, Verilog, etc. One of the options for using the resources of programmable logic integrated circuits is to create digital components of signal pre-processing, in particular in information and measurement channels. The application of this approach is due to the presence of various distortions that lead to information and accuracy loss. Another problem is the need to preserve the information performance of such information and measurement channels. It is common to use analog implementations of signal pre-processing methods, in particular different types filters. In this case, the implementation of pre-processing methods at the hardware level will provide the appropriate processing speed at insignificant hardware costs. The paper proposes the implementation of the algorithm for processing information and measurement signals using the sliding median method, implemented on a programmable logic integrated circuit. Based on the simulation in a numerical experiment, the efficiency of using such a method is shown in a relatively simple implementation scheme on the FPGA platform. In fact, the pyramidal scheme of conditional constructions provides a simple description of the logical scheme by means of the Altera HDL language, and also allows to reduce the number of comparison operations. The proposed algorithm does not require complex hardware resources, which allows you to effectively involve typical circuit solutions.
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19

Irmansyah, Muhammad. "PENGIMPLEMENTASIAN TEKNOLOGI PROGRAMMABLE LOGIC DEVICE (PLD) SEBAGAI BINER CODE DECIMAL (BCD) UNTUK SCANNING KEYPAD." Elektron : Jurnal Ilmiah 5, no. 1 (August 22, 2018): 9–18. http://dx.doi.org/10.30630/eji.5.1.38.

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Industrial of electronics developed in many fields in the middle of 1990s. Base on this situation, the manufacturer produce the product by increased the function, display, low cost, low power consumption and small size. This kind of product must be supported by complex system, small number of integrated circuit and tiny printed circuit board (PCB). Many integrated technologies such as submicron semiconductor, PCB technology, and the using of PCB surface maximal. The market situation push the producer used modern technology in design and testing for example Programmable Logic Device (PLD). It is the integrated circuit using digital logic which can be changed this function by programming and can be used to industrial application. Programmable Logic Device (PLD) technology can be used to many logical programming by using only one IC. The application of this technology can be found in IC 22V10 with 24 pins. This IC can be applied to replace the function of IC 74299 as encoder decimal to biner to scanning keypad.
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20

Vasil’ev, A. E., T. Yu Ivanova, T. D. F. Cabezas, and Ya D. Sadin. "Design of function-oriented microcontrollers on equipment of programmable logic integrated circuits for embedded systems." Automatic Control and Computer Sciences 49, no. 6 (November 2015): 404–11. http://dx.doi.org/10.3103/s0146411615060103.

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21

Sotnik, О., S. Marchenko, V. Litvinenko, and О. Syanov. "RADIO COMMUNICATION CHANNEL WITH FREQUENCY MODULATED SIGNAL BASED ON PROGRAMMABLE LOGICAL INTEGRATED CIRCUIT." Collection of scholarly papers of Dniprovsk State Technical University (Technical Sciences) 1, no. 38 (September 8, 2021): 75–83. http://dx.doi.org/10.31319/2519-2884.38.2021.9.

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This paper presents the results of an experimental study of a radio communication channel (RF) with a frequency-modulated signal based on a programmable logic integrated circuit (FPGA). The work highlights the features of hardware and software implementation of algorithms for the synthesis of frequency-modulated signal and demodulation of this signal using FPGA in real time. The software part is made in the development environment of ISE WebPack 14.7 in Verilog language with the ability to visualize the results of GTKWave. Hardware implementation is performed on the basis of FPGA (Spartan-6) using a debug board from Alinx AX309. The experimental study consists of two stages of the study of the FM oscillator modulator and the synchronous FM oscillator demodulator. In the course of research, the amplitude spectral characteristics of the signals (amplitude spectra) were obtained: at the output of the modulator and demodulator of the frequency-modulated signal, which have good agreement with the simulation results. The quality of the hardware synchronous demodulation of the FM signal based on the phase tuning system was confirmed by the result of the obtained spectrum of the restored information signal, in which the ratio between the first harmonic and the second is 51.87 dBm. When obtaining the results of experimental studies of the RH system, it was found necessary to take into account the peculiarities of the arithmetic of integers, which make errors in the hardware implementation of DSP algorithms. Thus, the use of programmable logic integrated circuits at the present stage of development of telecommunications and radio engineering opens wide opportunities for the construction of high-speed digital RH systems with parallel signal processing in real time.
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Semka, E. V., A. B. Buslaev, V. V. Ovcharov, A. A. Pirogov, and S. A. Gvozdenko. "Software driver for working with different types of SPI interfaces." Issues of radio electronics 49, no. 9 (October 28, 2020): 38–45. http://dx.doi.org/10.21778/2218-5453-2020-9-38-45.

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Field-Programmable Gate Arrays (FPGAs) are configurable integrated circuits whose logic is defined through programming. The use of FPGAs makes it possible to obtain devices capable of changing the configuration, adapting to a specific task due to their flexibly changeable, programmable structure. When developing complex devices, ready-made IP-cores can be used as components for design. The use of software IP-cores allows them to be used most effectively in the final structure, to a significant extent to reduce design costs. A software driver has been developed for working with different types of SPI interfaces (Serial Peripheral Interface), which implements switching the input-output line when transmitting data through a FPGA.
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Bogdanov, D. R., and O. V. Darintsev. "Multiprocessor systems based on FPGA for receiving and processing data from the position sensors of the manipulator elements with controlled bending." Proceedings of the Mavlyutov Institute of Mechanics 11, no. 1 (2016): 100–106. http://dx.doi.org/10.21662/uim2016.1.015.

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Key moments of technique of reception and processing of information from the MEMS position sensors in the information system of the manipulator built on the basis units with controlled bend is discussed in detail. The differences in the procedure for construction of multiprocessor information systems based on the new programmable logic integrated circuits large capacity which provide the use of soft-core processors is presented too. The results of qualitative comparison of the solutions obtained by use state machine circuits and schemes based on soft-processors is shown. As an example, consider the structure developed multiprocessor information system and variants of its hardware and structural implementation.
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Kostikova, E. V., S. A. Seliverstov, Ya A. Seliverstov, and Sh S. Fahmi. "Correction to: “Measuring the Speed of Data Exchange in Memory Cards Using Programmable Logic Integrated Circuits”." Measurement Techniques 62, no. 11 (February 2020): 1008. http://dx.doi.org/10.1007/s11018-020-01726-y.

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Choi, Seungdo, Geonhu Lee, and Jongmin Kim. "Cellular Computational Logic Using Toehold Switches." International Journal of Molecular Sciences 23, no. 8 (April 12, 2022): 4265. http://dx.doi.org/10.3390/ijms23084265.

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The development of computational logic that carries programmable and predictable features is one of the key requirements for next-generation synthetic biological devices. Despite considerable progress, the construction of synthetic biological arithmetic logic units presents numerous challenges. In this paper, utilizing the unique advantages of RNA molecules in building complex logic circuits in the cellular environment, we demonstrate the RNA-only bitwise logical operation of XOR gates and basic arithmetic operations, including a half adder, a half subtractor, and a Feynman gate, in Escherichia coli. Specifically, de-novo-designed riboregulators, known as toehold switches, were concatenated to enhance the functionality of an OR gate, and a previously utilized antisense RNA strategy was further optimized to construct orthogonal NIMPLY gates. These optimized synthetic logic gates were able to be seamlessly integrated to achieve final arithmetic operations on small molecule inputs in cells. Toehold-switch-based ribocomputing devices may provide a fundamental basis for synthetic RNA-based arithmetic logic units or higher-order systems in cells.
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Hassan, S., D. Chack, and L. Pavesi. "High extinction ratio thermo-optic based reconfigurable optical logic gates for programmable PICs." AIP Advances 12, no. 5 (May 1, 2022): 055304. http://dx.doi.org/10.1063/5.0086185.

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In this paper, a new scheme is proposed to realize reconfigurable and multifunction optical logic gates (XOR, XNOR, NAND, and OR) using a Mach–Zehnder interferometer with a tunable thermo-optic phase shifter (TOPS). The reconfigurable optical logic gates are realized by tuning the phase of an optical signal using TOPS without changing the physical device structure. The logical input “0” or “1” is considered corresponding to the phase of the optical signal at TOPS. The logical output of the proposed device depends on the light intensity at output ports. The device is designed on silicon on insulator (SOI) platform and the simulation result shows that the on–off extinction ratio is greater than 37 dB at 1550 nm and >25 dB for the C-band. Moreover, it has a low insertion loss of 0.09 dB at a wavelength of 1550 nm and <0.8 dB for the C-band window. The proposed optical logic gates can be a promising logical device for programmable photonic integrated circuits.
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Vyngra, A. V., A. S. Sobolev, and S. G. Chernyi. "Automated control system for electric drives with integration of programmable relays and active filters." Transactions of the Krylov State Research Centre S-I, no. 2 (December 21, 2021): 53–59. http://dx.doi.org/10.24937/2542-2324-2021-2-s-i-53-59.

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This paper discusses relevant challenges in upgrade of control systems and reviews possible applications of new programmable relays OVEN PR10 for non-stop Ethernet data transmission. It also discusses integration of active power filters in feeding circuits of electric drives with upgraded automatic control systems. The study analyses the applications of active filters and suggests a testing system that consists of electric compressor drives and automated multi-channel control system with integrated active filters. The tests performed under this study have shown that automatic systems work more efficiently if they are fed by high-quality loading current from their electric drives and are governed by OVEN PLC110 programmable logic controllers. This paper also describes a case study: laboratory experiment on integrating active power filter for interharmonic current components with multi-channel drive control system based on cutting-edge programmable relay OVEN PR103. The results of this study could be useful for the upgrade of Russian fishing fleet, as well as for design and development of innovative ships.
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Solov’ev, V. V., and A. A. Posrednikova. "The hierarchical method of synthesis of large-capacity comparators with the use of programmable logic integrated circuits." Journal of Communications Technology and Electronics 54, no. 3 (March 2009): 338–46. http://dx.doi.org/10.1134/s1064226909030139.

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Ward, Tyler, Neil Grabham, Chris Freeman, Yang Wei, Ann-Marie Hughes, Conor Power, John Tudor, and Kai Yang. "Multichannel Biphasic Muscle Stimulation System for Post Stroke Rehabilitation." Electronics 9, no. 7 (July 17, 2020): 1156. http://dx.doi.org/10.3390/electronics9071156.

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We present biphasic stimulator electronics developed for a wearable functional electrical stimulation system. The reported stimulator electronics consist of a twenty four channel biphasic stimulator. The stimulator circuitry is physically smaller per channel and offers a greater degree of control over stimulation parameters than existing functional electrical stimulator systems. The design achieves this by using, off the shelf multichannel high voltage switch integrated circuits combined with discrete current limiting and dc blocking circuitry for the frontend, and field programmable gate array based logic to manage pulse timing. The system has been tested on both healthy adults and those with reduced upper limb function following a stroke. Initial testing on healthy users has shown the stimulator can reliably generate specific target gestures such as palm opening or pointing with an average accuracy of better than 4 degrees across all gestures. Tests on stroke survivors produced some movement but this was limited by the mechanical movement available in those users’ hands.
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Poudel, Bikash, Arslan Munir, Joonho Kong, and Muazzam A. Khan. "Design and Validation of Low-Power Secure and Dependable Elliptic Curve Cryptosystem." Journal of Low Power Electronics and Applications 11, no. 4 (November 12, 2021): 43. http://dx.doi.org/10.3390/jlpea11040043.

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The elliptic curve cryptosystem (ECC) has been proven to be vulnerable to non-invasive side-channel analysis attacks, such as timing, power, visible light, electromagnetic emanation, and acoustic analysis attacks. In ECC, the scalar multiplication component is considered to be highly susceptible to side-channel attacks (SCAs) because it consumes the most power and leaks the most information. In this work, we design a robust asynchronous circuit for scalar multiplication that is resistant to state-of-the-art timing, power, and fault analysis attacks. We leverage the genetic algorithm with multi-objective fitness function to generate a standard Boolean logic-based combinational circuit for scalar multiplication. We transform this circuit into a multi-threshold dual-spacer dual-rail delay-insensitive logic (MTD3L) circuit. We then design point-addition and point-doubling circuits using the same procedure. Finally, we integrate these components together into a complete secure and dependable ECC processor. We design and validate the ECC processor using Xilinx ISE 14.7 and implement it in a Xilinx Kintex-7 field-programmable gate array (FPGA).
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Jaafar, Anuar, Norhayati Soin, Sharifah F. Wan Muhamad Hatta, Sani Irwan Salim, and Zahriladha Zakaria. "Multipoint Detection Technique with the Best Clock Signal Closed-Loop Feedback to Prolong FPGA Performance." Applied Sciences 11, no. 14 (July 12, 2021): 6417. http://dx.doi.org/10.3390/app11146417.

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The degradation effect of a field-programmable gate array becomes a significant issue due to the high density of logic circuits inside the field-programmable gate array. The degradation effect occurs because of the rapid technology scaling process of the field-programmable gate array while sustaining its performance. One parameter that causes the degradation effect is the delay occurrence caused by the hot carrier injection and negative bias temperature instability. As such, this research proposed a multipoint detection technique that detects the delay occurrence caused by the hot carrier injection and negative bias temperature instability degradation effects. The multipoint detection technique also assisted in signaling the aging effect on the field-programmable gate array caused by the delay occurrence. The multipoint detection technique was also integrated with a method to optimize the performance of the field-programmable gate array via an automatic clock correction scheme, which could provide the best clock signal for prolonging the field-programmable gate array performance that degraded due to the degradation effect. The delay degradation effect ranged from 0° to 360° phase shifts that happened in the field-programmable gate array as an input feeder into the multipoint detection technique. With the ability to provide closed-loop feedback, the proposed multipoint detection technique offered the best clock signal to prolong the field-programmable gate array performance. The results obtained using the multipoint detection technique could detect the remaining lifetime of the field-programmable gate array and propose the best possible signal to prolong the field-programmable gate array’s performance. The validation showed that the multipoint detection technique could prolong the performance of the degraded field-programmable gate array by 13.89%. With the improvement shown using the multipoint detection technique, it was shown that compensating for the degradation effect of the field-programmable gate array with the best clock signal prolonged the performances.
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Пирогов, А. А., Ю. А. Пирогова, С. А. Гвозденко, Д. В. Шардаков, and Э. В. Сёмка. "DEVELOPMENT OF A PROCEDURE FOR DESIGNING DIGITAL AUTOMATES WITH MEMORY ON FPGA." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, no. 6 (January 10, 2021): 61–68. http://dx.doi.org/10.36622/vstu.2020.16.6.009.

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Программируемые логические интегральные схемы (ПЛИС) - это настраиваемые интегральные схемы, логика которых определяется программированием. ПЛИС производятся полностью в готовом виде, т.е. относятся к стандартной продукции, что сопровождается известными преимуществами - массовым производством и снижением затрат. Благодаря регулярной структуре ПЛИС реализованы с уровнем интеграции, близким к максимально эффективному. Использование ПЛИС позволяет получить устройства, которые могут менять конфигурацию, подстраиваясь под конкретную задачу, благодаря своей гибко изменяемой, программируемой структуре. При разработке сложных устройств в качестве компонентов для проектирования могут использоваться готовые блоки: IP-ядра или сложно-функциональные блоки (СФ-блоки). Применение программных СФ-блоков позволяет максимально эффективно использовать их в итоговом проекте, таким образом во многом снижаются затраты на проектирование. Цель работы - изучение методики описания триггеров на языке VHDL, применения встроенного схемного редактора Active HDL для формирования структур различных цифровых автоматов и верификации моделей на логическом уровне. В данном исследовании рассмотрены схемы генераторов псевдослучайных последовательностей, которые находят применение в задачах криптографии, где свойства программируемой структуры ПЛИС достаточно актуальны Programmable logic integrated circuits (FPGAs) are custom integrated circuits whose logic is defined by programming. FPGAs are manufactured completely off-the-shelf, i.e. belong to standard products, which is accompanied by well-known advantages - mass production and cost reduction. Due to the regular structure, FPGAs are implemented with a level of integration close to the most efficient one. The use of FPGAs makes it possible to obtain devices that can change configuration, adjusting to a specific task, thanks to their flexible, programmable structure. When developing complex devices, ready-made blocks - IP-cores or complex-functional blocks (SF blocks) - can be used as components for design. The use of software SF blocks allows you to use them as efficiently as possible in the final project, largely reducing design costs. The purpose of the work is to study the technique of describing triggers in the VHDL language, using the built-in Active HDL schematic editor to form the structures of various digital automata and verifying models at the logical level. In this study, we considered schemes of pseudo-random sequence generators, which are used in cryptography problems, where the properties of the programmable FPGA structure are quite relevant
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33

Zhang, Zi Sheng, Peng Bo Ge, Xiao Dong Shi, Bo Feng Liu, and Zhi Qiang Liu. "The Control System of High Voltage Electrostatic Precipitator Based on FPGA." Advanced Materials Research 823 (October 2013): 528–31. http://dx.doi.org/10.4028/www.scientific.net/amr.823.528.

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It is urgent to study a new control system for improving the efficiency of electrostatic precipitator. The System-on-a-Programmable-Chip (SOPC) development board, which belongs to the series of Cyclone of Altera Company, is used as the development platform. Analog Digital (AD) conversion module, voltage control module and overall control module of the electrostatic precipitator are designed and the simulation waveform of the system is analyzed, based on the programmable logic device EP1C12Q240C6 and Very-High-Speed Integrated Circuit Hardware Description Language (VHDL) programming language. The results show that: by using Field Programmable Gate Array (FPGA) as the control, transformation of AD is accurate and fast and high voltage power supply is stable, which leads to a certain value for generalization.
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34

Gozali, M. Syafei. "Komunikasi Sistem Pembaca 2D Dengan Mesin Laser Marking Berbasis PLC." Journal of Applied Electrical Engineering 2, no. 1 (December 31, 2018): 22–27. http://dx.doi.org/10.30871/jaee.v2i1.1079.

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Currently size of Integrated Circuits (IC) become smaller while it needs more information on its label. Therefore 2D data matrix is use to replace standard character for the identification. To improve laser mark machine capabilities to be able to read 2D data matrix, a 2D reader system is required to integrate with existing laser mark machine. This study aims to develop 2D reader system that can read 2D data matrix and communicates with laser mark machine automatically. Communication between 2D reader system and laser mark machine was done through Programmable Logic Control (PLC) inside the machine using serial (RS-232) by utilizes available data memories inside the PLC. The experimental result indicates the 2D reader system able to communicate with laser mark machine and it can differentiate readable and unreadable 2D data matrix. Unreadable 2D Code was caused by different process on the tested material. The readable 2D Code through Chemical Deflash – Water Jet (CD-WJ) process while the unreadable 2D Code run without CD-WJ.
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35

Levin, Ilya. "Matrix Model of Logical Simulator Within Spreadsheet." International Journal of Electrical Engineering & Education 30, no. 3 (July 1993): 216–23. http://dx.doi.org/10.1177/002072099303000304.

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Matrix model of logical simulator within spreadsheet This paper examines the use of spreadsheets for simulation of logical control units. A matrix model is proposed for this aim. The use of this model is appropriate both for teaching and learning of simulation of a specific type of integrated circuit — Programmable Logic Arrays — and also for any type of control unit representable in the form of a logical function system.
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36

Mailsamy, M., V. Rukkumani, and K. Srinivasan. "Low Power Adiabetic Logic System for Biomedical Applications." Journal of Medical Imaging and Health Informatics 11, no. 12 (December 1, 2021): 3123–32. http://dx.doi.org/10.1166/jmihi.2021.3910.

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There have been significant advances in sensors and device structures in the medical industry, particularly in implanted medical devices. Increasingly complex electronic circuitry may now be implanted in the human body thanks to compact, high-energy batteries and hermetic packaging. These gadgets must adhere to strict power consumption guidelines due to the battery recharging schedule. Designing energy-efficient circuits and systems becomes increasingly important as a result of this fact. Adiabatic circuits provide a hopeful alternative for traditional circuitry in case of low energy design. Because of power-clock phases synchronization complexity, designing and functionally verifying presenting 4-phase adiabatic circuitry takes longer. Accordingly, multiple clock generators are used typically and can reveal enhanced consumption of energy in the network of clock distribution. Furthermore, they are not suitable for designing in high-speed because of their clock skew management and high complexity issues. In this paper, TMEL (True multi-phase energy recovering logic), the first energyrecovering/adiabatic logic family is presented for biomedical applications, which functions using the scheme multiple-phase sinusoidal clocking. Moreover, a system of SCAL, a source-coupled variation with TMEL having enhanced energy efficiency and supply voltage scalability, is introduced. A novel true multi-phase Approach and Source-coupled adiabatic logic for energy effective communication system is proposed. The adiabatic logic is employed for both write and read side operation. The CMOS inverter is integrated with TMEL cascades, which in turn reduces leakage loss. In SCAL, the optimal performance at any operating circumstance is attained byan adjustable current source in each gate. SCAL, and TMEL, are capable of outperforming existing adiabatic logic families concerning operating speed and energy efficiency. The performance analysis was carried and simulated through 45 nm CMOS inverter in terms of leakage power, delay, and power consumption. In particular, for the clock rates that range from 10 MHz to 200 MHz, the proposed SCAL was more energy-efficient and less dissipative on comparing their pipelined or purely combinational CMOS counterparts. In biomedical equipment, the system may be included into the low-power design since it is energy efficient and very robust. Improvements in VLSI technology, such as increased dynamic range, low-voltage EEPROMs (electrically eraseable programmable ROMs), and specific sensor techniques, are also expected to contribute to advancements in implanted medical devices in the near future.
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Al Rabea, Adnan I., Mahmud S. Alkoffash, Feras Almatarneh, and Basim Alhadidi. "The Methods of Synthesis of Multilevel Circuits of Compositional Micro Program Control Units." Applied Mechanics and Materials 110-116 (October 2011): 5429–36. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5429.

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On the basis of theoretical and experimental researches the new structures and formal methods of compositional micro program control units design are proposed. It is shown that optimization of hardware in the unit of microinstructions’ addressing can be achieved by application of the methods of multilevel implementation of automata with “hardware” logic, that need adaptation to the peculiarities of compositional micro program control units. It is proposed to use the methods of the logic conditions’ encoding, the codes of the states, the codes of the operational linear chains and their classes, and also the addresses of microinstructions. The new structures and methods of design were developed for all known structures of compositional micro program control units. The proposed methods permit to decrease the amount of programmable logic devices in the automaton of addressing’s circuit from 12% to 42% in comparison with known methods of design. The analytical estimations of hardware amount as the function of characteristics of initial flow-chart have been made up. These methods permit to expand the class of synthesizable control units. The conducted researches permit to find an area of the effective application of proposed methods of design. The purpose of work is minimization of number of the large-scale integrated circuit in circuit of automatons of addressing of CMCU due to application of methods of a structural reduction. The analysis of methods of realization of algorithms of control, element basis, methods of a structural reduction, methods of synthesis and optimization of compositional micro program control units are executed, the primary goals of researches are formulated.. (Abstract)
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38

Zhang, Pengyun, and Henan Guo. "Ultra-high Speed and Dual-Channel Data Acquisition Card with 1GSPS Based on PXI Bus." Modern Electronic Technology 2, no. 1 (January 16, 2018): 22. http://dx.doi.org/10.26549/met.v2i1.753.

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This paper discusses the chief techniques and design principles of an ultra-high speed and dual-channel data acquisition card based on PXI bus, using FPGA (Field Programmable Gate Array) as logic controller cell. The instrument consists of pre-process circuit, A/D converter, SDRAM (Synchronous Dynamic random access memory), and control circuit integrated in FPGA. It can achieve allowing up to 1000MHz real-time sampling rate. The test result indicates that the system works normally and the system design is successful.
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Chu, Kai-Chun, Kuo-Chi Chang, Hsiao-Chuan Wang, Yuh-Chung Lin, and Tsui-Lien Hsu. "Field-Programmable Gate Array-Based Hardware Design of Optical Fiber Transducer Integrated Platform." Journal of Nanoelectronics and Optoelectronics 15, no. 5 (May 1, 2020): 663–71. http://dx.doi.org/10.1166/jno.2020.2835.

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This study focuses on the hardware architecture of a Raman scattering distributed optical fiber transducer platform, the principles of Raman scattering are analyzed, and the output 2 analog electrical signals are converted to digital signals at a 16-bit sampling rate by an Analog-to-Digital Converter (ADC). The system is implemented based on the FPGA. The integrated circuit is responsible for controlling the data acquisition process. The differential amplifier circuit, FPGA peripheral circuit, and CPU subsystem circuit, which takes ARM as the core, are separately designed. The composition of software includes a DDR2 (Double Data Rate 2) driver and central control logic. In this study, the optical fiber transducer platform has been tested. The CPU DDR2 is read/written by the test program respectively. According to the results, the program passes the read/write test. The NAND FLASH is tested. The results show that this program returns all operations successfully. The timing tests of the DDR2 interface and data latching are conducted. The results show that the read/write operations ensure that the clock and data curves are aligned. Therefore, the optical fiber transducer integrated platform designed in this study is effective.
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40

Zapletina, M. A., D. V. Zhukov, and S. V. Gavrilov. "Boolean Satisfiability Methods for Modern Computer-Aided Design Problems in Microelectronics." Proceedings of Universities. ELECTRONICS 25, no. 6 (December 2020): 525–38. http://dx.doi.org/10.24151/1561-5405-2020-25-6-525-538.

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Currently, the methods based on a Boolean satisfiability (SAT) problem are one of the efficient approaches to solving the problem of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, the SAT methods demonstrate the results exceeding the classic routing algorithms by the operation speed and the quality of obtained results. In the paper, the analysis of the modern practice of using the SAT methods in the CAD systems for VLSI has been performed. The examples of modern SAT approaches to the problems of the formal equivalence checking of digital circuits descriptions within the technological mapping framework and to the routing problem as a part of the FPGA design flow have been considered. The algorithm of the detailed routing of the FPGA switching blocks using the satisfiability problem has been developed and presented. The results of its work have been demonstrated on the example of the programmable logic block of the domestic made integrated circuit 5400TP094. The block has the island architecture, where the configurable logic blocks and switching blocks form a regularly repeated layout template. The properties of the chosen classic architecture permit to expand the region of presented algorithm to the entire class of island style FPGA. The algorithm has been tested on the project benchmarks ISCAS-85, ISCAS-89 and LGSynth-89. The comparison of the developed SAT-based algorithm with the well-known routing algorithm Pathfinder by criteria of the elapsed time and the achieved portion of routed nets in the switching blocks is presented. It has been determined that the considered Boolean satisfiability methods for the routing problem are capable to prove the circuit unroutability, unlike the algorithm Pathfinder which results can only implicitly indicate it. The paper demonstrates that the application of more efficient SAT solver significantly accelerates work of the suggested detailed routing algorithm.
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41

Tokunaga, Yusuke, Toshihide Hakukawa, and Takahiro Inoue. "Algorithm and Design of an Intelligent Digital Integrated Circuit for a Watermelon Harvesting Robot." Journal of Robotics and Mechatronics 11, no. 3 (June 20, 1999): 173–82. http://dx.doi.org/10.20965/jrm.1999.p0173.

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We propose an algorithm and design of an intelligent digital integrated circuit for recognition of circular patterns in a binary image based on template matching using a modified matching degree. The proposed system consists of a preprocessor #1 (noise reduction, coarsening, and edge detection), a preprocessor #2 (noise filtering and location parameter detection), and a circular pattern recognition block. The proposed system is implementable onto field programmable gate arrays (FPGAs) and forming part of the vision system for a watermelon harvesting robot. Functional verification, logic synthesis, and implementation are detailed for the FPGA circular pattern recognition block.
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42

Kopysov, A. N., A. Yu Shaimov, and A. Yu Belousov. "Ways to Reduce FPGA Power Supply by Software Methods." Intellekt. Sist. Proizv. 19, no. 4 (2021): 88–97. http://dx.doi.org/10.22213/2410-9304-2021-4-88-97.

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The paper is devoted to solving the problem of reducing the power consumption of programmable logic integrated circuits (hereinafter FPGAs) by software methods. The solution of this issue is especially relevant for various types of radio engineering systems, which include autonomous and portable stations. At the beginning of the paper, the theoretical foundations of FPGA consumption are given: types of consumption (static and dynamic) and influencing parameters (switching logic, the physical foundations of the integrated circuit and other internal resources). The work is explained and methodological guidelines are given for the specialized built-in PowerAnalyzer utility of the Quartus II software development environment, the main indicators with which the utility works are explained: toggle rate (switching frequency) and static probability (the probability of finding a signal in a stable state "0" or "1"). The following is a Pipelinning method for eliminating the racing effect (the effect in which signals passing through an element/crystal reach the destination point with different time delays). The essence of the method is that a register is set at the output of the element that creates the delay. The register stores the value at the input at the CLK clock frequency, so random switching of the previous circuit element will be ignored. This eliminates the effect of racing and reduces the dynamic consumption of the circuit. At the end of the paper, the results of reducing energy consumption using the above methods are presented. The greatest gain is observed when minimizing consumption, when a large number of logic elements on the FPGA chip are involved, as well as when high-frequency operation occurs. This is due to the fact that when using the methods of switching off the clock frequency, we get rid of a large number of switches between the states of logic elements (the higher the frequency, the more such state switches per unit of time). If the number of occupied elements is more than 50%, we get a reduction in power consumption of more than 5%, and if the number of occupied elements is 75%, then we get a gain of about 14%.
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43

Zhang, Ai Rong. "The Integration on Electrical Control Systems Based on Optimized Method." Advanced Materials Research 490-495 (March 2012): 2604–8. http://dx.doi.org/10.4028/www.scientific.net/amr.490-495.2604.

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Very large scale integration (VLSI) applications have improved control implementation performance. Indeed, an application specific integrated circuit (ASIC) solution can exploit efficiently specificities of the control algorithms that fixed hardware architecture cannot do. For example, parallel calculation cannot be included in a software solution based on sequential processing. In addition, ASIC can reduce wire and electromagnetic field interference by a fully system on a chip (SoC) integration. However, there are still two main drawbacks to an integrated circuit solution: design complexity and reuse difficulty. This is true even with programmable logic device (PLD) solutions. Conception aid developer (CAD) combined with hardware description languages (HDL) and VLSI design methodology have accelerated conception and reuse. Nevertheless, the main problem of integrated circuit design is to define the hardware architecture; this is particularly true for heterogeneous algorithm structures such as electrical controls.
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Akbatı, Onur, Hatice Didem Üzgün, and Sirin Akkaya. "Hardware-in-the-loop simulation and implementation of a fuzzy logic controller with FPGA: case study of a magnetic levitation system." Transactions of the Institute of Measurement and Control 41, no. 8 (December 13, 2018): 2150–59. http://dx.doi.org/10.1177/0142331218813425.

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This paper presents the design and implementation of a fuzzy logic controller using Very High Speed Integrated Circuit Hardware Description Language (VHDL) on a field programmable gate array (FPGA). First, a Sugeno-type fuzzy logic controller with five triangular and trapezoidal membership functions for two inputs and with nine singleton membership functions for one output is examined. The proposed structure is tested with second- and third-order system model using FPGA-in-the-loop simulation via a MATLAB/Simulink environment. Then, for different kinds of fuzzy logic controllers, a new look-up table (LUT) and interpolation-based controller implementation is proposed to eliminate the computational complexity of the primarily designed structure. As a case study, a magnetic levitation system is controlled with an adaptive neuro-fuzzy inference system (ANFIS) trained fuzzy logic controller, then it is simulated and implemented using a LUT-based controller. Finally, we provide a comparison of results.
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45

Das, Apangshu, and Sambhu Nath Pradhan. "Thermal-aware Output Polarity Selection Based on And-Inverter Graph Manipulation." Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) 12, no. 1 (January 10, 2019): 30–39. http://dx.doi.org/10.2174/2352096511666180320120016.

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Background: Output polarity of the sub-function is generally considered to reduce the area and power of a circuit at the two-level realization. Along with area and power, the power-density is also one of the significant parameter which needs to be consider, because power-density directly converges to circuit temperature. More than 50% of the modern day integrated circuits are damaged due to excessive overheating. Methods: This work demonstrates the impact of efficient power density based logic synthesis (in the form of suitable polarity selection of sub-function of Programmable Logic Arrays (PLAs) for its multilevel realization) for the reduction of temperature. Two-level PLA optimization using output polarity selection is considered first and compared with other existing techniques and then And-Invert Graphs (AIG) based multi-level realization has been considered to overcome the redundant solution generated in two-level synthesis. AIG nodes and associated power dissipation can be reduced by rewriting, refactoring and balancing technique. Reduction of nodes leads to the reduction of the area but on the contrary increases power and power density of the circuit. A meta-heuristic search approach i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II) is proposed to select the suitable output polarity of PLA sub-functions for its optimal realization. Results: Best power density based solution saves up to 8.29% power density compared to ‘espresso – dopo’ based solutions. Around 9.57% saving in area and 9.67% saving in power (switching activity) are obtained with respect to ‘espresso’ based solution using NSGA-II. Conclusion: Suitable output polarity realized circuit is converted into multi-level AIG structure and synthesized to overcome the redundant solution at the two-level circuit. It is observed that with the increase in power density, the temperature of a particular circuit is also increases.
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46

Varghese, Mini P., A. Manjunatha, and T. V. Snehaprabha. "Method for improving ripple reduction during phase shedding in multiphase buck converters for SCADA systems." Indonesian Journal of Electrical Engineering and Computer Science 24, no. 1 (October 1, 2021): 29. http://dx.doi.org/10.11591/ijeecs.v24.i1.pp29-36.

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In the current digital environment, central processing unit (CPUs), field programmable gate array (FPGAs), application-specific integrated circuit (ASICs), as well as peripherals, are growing progressively complex. On motherboards in many areas of computing, from laptops and tablets to servers and Ethernet switches, multiphase phase buck regulators are seen to be more common nowadays, because of the higher power requirements. This study describes a four-stage buck converter with a phase shedding scheme that can be used to power processors in programmable logic controller (PLCs). The proposed power supply is designed to generate a regulated voltage with minimal ripple. Because of the suggested phase shedding method, this power supply also offers better light load efficiency. For this objective, a multiphase system with phase shedding is modeled in MATLAB SIMULINK, and the findings are validated.
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Jiménez, Jaime, Leire Muguira, Unai Bidarte, Alejandro Largacha, and Jesús Lázaro. "Specific Electronic Platform to Test the Influence of Hypervisors on the Performance of Embedded Systems." Technologies 10, no. 3 (May 24, 2022): 65. http://dx.doi.org/10.3390/technologies10030065.

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Some complex digital circuits must host various operating systems in a single electronic platform to make real-time and not-real-time tasks compatible or assign different priorities to current applications. For this purpose, some hardware–software techniques—called virtualization—must be integrated to run the operating systems independently, as isolated in different processors: virtual machines. These are monitored and managed by a software tool named hypervisor, which is in charge of allowing each operating system to take control of the hardware resources. Therefore, the hypervisor determines the effectiveness of the system when reacting to events. To measure, estimate or compare the performance of different ways to configure the virtualization, our research team has designed and implemented a specific testbench: an electronic system, based on a complex System on Chip with a processing system and programmable logic, to configure the hardware–software partition and show merit figures, to evaluate the performance of the different options, a field that has received insufficient attention so far. In this way, the fabric of the Field Programmable Gate Array (FPGA) can be exploited for measurements and instrumentation. The platform has been validated with two hypervisors, Xen and Jailhouse, in a multiprocessor System-on-Chip, by executing real-time operating systems and application programs in different contexts.
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48

Wasnik, Pratyush, Asawari Kamble, Ritvik Remje, Adinath Uparkar, and Priyanka Sharma. "Protection of Induction Motor Using PLC." International Journal for Research in Applied Science and Engineering Technology 10, no. 4 (April 30, 2022): 3273–77. http://dx.doi.org/10.22214/ijraset.2022.42071.

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Abstract: Protection of an induction motor (IM) against possible problems, such as over voltage, over current, overload, over temperature, and under-voltage, occurring during its operation is very important, because it is used intensively in industry as an actuator. IMs can be protected using some components, such as timers, contactors, voltage, and current relays. This method is known as the classical method that is very basic and involves mechanical dynamic parts. Computer and programmable integrated circuit (PIC) based protection methods have eliminated most of the mechanical components. However, the computer-based protection method requires an analog to digital conversion (ADC) card, and the PIC-based protection method does not visualize the electrical parametersmeasured. In this study, for IMs, a new protection method based on a programmable logic controller (PLC) has been introduced. In this method, all contactors, timers, relays, and the conversion card are eliminated. Moreover, the voltages, the currents, the speed, and the temperature values of the motor, and the problems occurring in the system, are monitored and warning indicators are shown using colored LED’s. Experimental results show that the PLC-based protection method costs less, provides higher accuracy as well as a safe and visual environment compared with the classical, the computer, and the PIC-based protection systems. Keywords: programmable logic controller, induction motor, motor protection, ladder diagram, protection system
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49

Belghadr, Armin, and Ali Jahanian. "Three-Dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area." Journal of Circuits, Systems and Computers 26, no. 10 (March 8, 2017): 1750154. http://dx.doi.org/10.1142/s0218126617501547.

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By scaling the semiconductor industry to nano-scale era, design and prototyping cost of cell-based Application-Specific Integrated Circuits (ASICs) becomes more expensive and it makes Field Programmable Gate Arrays (FPGAs) more popular among designers. However, there is a gap between FPGAs and ASICs in terms of timing, dynamic power consumption and logic density. Three-dimensional integration, particularly in the full monolithic process, has been considered as a promising solution to reduce the performance gap of ASICs and FPGAs. In this paper, two new architectures for the monolithically integrated 3D-FPGAs are introduced. In order to exploit the great potentials of the suggested architectures, a new three-dimensional FPGA placement algorithm is proposed thereafter. The proposed placement algorithm, named JABE, is the first of its kind that enables designers to take advantages of the large number of vertical interconnections in the monolithically stacked 3D-FPGAs. Our experiments show a 24% timing improvement for the new architectures and CAD algorithms compared with the conventional TSV-based 3D-FPGAs and design flows. In addition, improvements in terms of the total wirelength and area footprint are reported for the proposed placement algorithms and new architectures.
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50

Wu, Bin, Ji Tao Ma, and Ping Wu. "Implement an Indoor Low Frequency Noise Reduction System Based on FXLMS Algorithm." Applied Mechanics and Materials 667 (October 2014): 440–47. http://dx.doi.org/10.4028/www.scientific.net/amm.667.440.

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In order to solve the hazards of indoor low-frequency noise on the human body, the low-frequency noise reduction system is designed for a confined space by using the active control theory, and the process of adaptive noise elimination is achieved through the FX-LMS algorithm. The system hardware is integrated with the sound sensor, the complex programmable logic devices, the digital to analog converter and micro control unit to build the core circuit. Furthermore, the processing software of noise reduction is implemented by the FXLMS. Through the system test, the result shows that the noise reduction system can effectively reduce the low frequency noise intensity in the confined space.
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