Dissertations / Theses on the topic 'Programmable logic integrated circuits'
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Hadjinicolaou, M. G. "Synthesis of programmable logic arrays." Thesis, Brunel University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.371168.
Full textDavis, Justin S. "An FPGA-based digital logic core for ATE support and embedded test applications." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15639.
Full textMoon, Gyo Sik. "An Algorithm for the PLA Equivalence Problem." Thesis, University of North Texas, 1995. https://digital.library.unt.edu/ark:/67531/metadc278922/.
Full textTan, Chong Guan. "Another approach to PLA folding." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66054.
Full textВоргуль, О. В., І. В. Свид, О. В. Зубков, and В. В. Семенець. "Teaching microcontrollers and FPGAs in Quarantine from Coronavirus: Challenges and Prospects." Thesis, MC&FPGA, 2020. https://mcfpga.nure.ua/conf/2020-mcfpga/10-35598-mcfpga-2020-005.
Full textChadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.
Full textDraier, Benny. "Test vector generation and compaction for easily testable PLAs." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63970.
Full textWan, Wei. "A New Approach to the Decomposition of Incompletely Specified Functions Based on Graph Coloring and Local Transformation and Its Application to FPGA Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4698.
Full textPerez, Segovia Tomás. "Paola : un système d'optimisation topologique de PLA." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316330.
Full textNguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.
Full textDandache, Abbas. "Conception de PLA CMOS." Phd thesis, Grenoble 2 : ANRT, 1986. http://catalogue.bnf.fr/ark:/12148/cb37596962j.
Full textWilliams, Ryan Daniel. "Photonic integrated circuits for optical logic applications." Thesis, Massachusetts Institute of Technology, 2007. http://hdl.handle.net/1721.1/42025.
Full textThis electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.
Includes bibliographical references.
The optical logic unit cell is the photonic analog to transistor-transistor logic in electronic devices. Active devices such as InP-based semiconductor optical amplifiers (SOA) emitting at 1550 nm are vertically integrated with passive waveguides using the asymmetric twin waveguide technique and the SOAs are placed in a Mach-Zehnder interferometer (MZI) configuration. By sending in high-intensity pulses, the gain characteristics, phase-shifting, and refractive indices of the SOA can be altered, creating constructive or deconstructive interference at the MZI output. Boolean logic and wavelength conversion can be achieved using this technique, building blocks for optical switching and signal regeneration. The fabrication of these devices is complex and the fabrication of two generations of devices is described in this thesis, including optimization of the mask design, photolithography, etching, and backside processing techniques. Testing and characterization of the active and passive components is also reported, confirming gain and emission at 1550 nm for the SOAs, as well as verifying evanescent coupling between the active and passive waveguides. In addition to the vertical integration of photonic waveguides, Esaki tunnel junctions are investigated for vertical electronic integration. Quantum dot formation and growth via molecular beam epitaxy is investigated for emission at the technologically important wavelength of 1310 nm. The effect of indium incorporation on tunnel junctions is investigated. The tunnel junctions are used to epitaxially link multiple quantum dot active regions in series and lasers are designed, fabricated, and tested.
by Ryan Daniel Williams.
Ph.D.
Belhadj, Mohamed Hichem. "Spécification et synthèse de systèmes à controle intensif." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0084.
Full textBen, Dhia Arwa. "Durcissement de circuits logiques reconfigurables." Thesis, Paris, ENST, 2014. http://www.theses.fr/2014ENST0068/document.
Full textAs feature sizes scale down to nano-design level, electronic devices have become smaller, more performant, less power-onsuming, but also less reliable. Indeed, reliability has arisen as a serious challenge in nowadays’ microelectronics industry and as an important design criterion, along with area, performance and power consumption. For instance, physical defects due to imperfections in the manufacturing process have been observed more frequently, impacting the yield. Besides, nanometric circuits have become more vulnerable during their lifetime to ionizing radiation which causes transient faults. Both manufacturing defects and transient faults contribute to decreasing reliability of integrated circuits. When moving to a new technology node, Field Programmable Gate Arrays (FPGAs) are the first coming into the market, thanks to their low development and Non-Recurring Engineering (NRE) costs and their flexibility to be used for any application. FPGAs have especially attractive characteristics for space and avionic applications, where reconfigurability, high performance and low-power consumption can be fruitfully used to develop innovative systems. However, missions take place in a harsh environment, rich in radiation, which can induce soft errors within electronic devices. This shows the importance of FPGA reliability as a design criterion in safety and critical applications. Most of commercial FPGAs have a mesh architecture and their logic blocks are gathered into clusters. Therefore, this thesis deals with the fault tolerance of basic blocks (clusters and switch boxes) in a mesh of clusters FPGA. These blocks are mainly made up of multiplexers. In order to improve their reliability, it is imperative to be able to assess it first, then select the proper hardening approach according to the available budget. So, this is the main outline in which this thesis is conceived. Its goals are twofold: (a) analyze the fault tolerance of the basic blocks in a mesh of clusters FPGA, and point out the most vulnerable components (b) propose hardening schemes at different granularity levels, depending on the hardening budget. As far as the first goal is concerned, a methodology to evaluate the reliability of the cluster is proposed. This methodology uses an existent analytical method for reliability computation of combinational circuits. The same method is employed to identify the worthiest components to be hardened. Regarding the second goal, hardening techniques are proposed at both multiplexer and transistor levels. At multiplexer level, two hardening solutions are presented. The first solution resorts to spacial redundancy and concerns the logic block structure. A novel Configurable Logic Block (CLB) architecture baptized Butterfly is introduced. It is compared with other hardened CLB architectures in terms of reliability and cost penalties. The second hardening solution is a redundanceless scheme. It is based on a “smart” synthesis that consists in seeking the most reliable design in a given founder library, instead of directly using a redundant solution. Then, at transistor level, new single-ended and dual-rail multiplexer architectures are proposed. They are compared to different other transistor structures, according to suitable design metrics
Baskaya, Ismail Faik. "Physical design automation for large scale field programmable analog arrays." Diss., Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31810.
Full textCommittee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.
Le, Pelleter Tugdual. "Méthode de discrétisation adaptée à une logique événementielle pour l'utra-faible consommation : application à la reconnaissance de signaux physiologiques." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT043/document.
Full textOur everyday life is highly dependent on mobile embedded systems. In order to make them suitable to differentapplications, they have underwent size reduction and lifetime extension. However, these improvementsare currently limited by the possibilities of the integrated circuits technologies. In order to push back theboundaries, it is necessary to reconsider the whole digital signal processing chain from scratch to sustain thepower consumption reduction in this kind of system. This work develops on the first hand a strategy thatsmartly uses the level-crossing sampling scheme and on the other combines this sampling method with eventlogicto highly reduce the power consumption in mobile embedded systems. A discretisation method adaptedto the recognition of physiological patterns application is described. A first event-logic (asynchronous) prototypeimplemented on FPGA proved the potential benefits that an adapted sampling scheme could offersto reduce activity compared to a uniform sampling scheme. Electrical simulations performed on a secondprototype, also designed in asynchronous logic, with CMOS AMS 0.35 μm technology, validated a high gainin power consumption
Sandireddy, Raja Kiran Kumar Reddy Agrawal Vishwani D. "Hierarchical fault collapsing for logic circuits." Auburn, Ala., 2005. http://repo.lib.auburn.edu/EtdRoot/2005/SPRING/Electrical_and_Computer_Engineering/Thesis/SANDIREDDY_RAJA-KIRAN-KUMAR_48.pdf.
Full textOsseiran, Adam. "Définition, étude et conception d'un microprocesseur autotestable spécifique : cobra." Grenoble INPG, 1986. http://tel.archives-ouvertes.fr/tel-00320884.
Full textYourst, Matt T. "Peptidal processor enhanced with programmable translation and integrated dynamic acceleration logic /." Diss., Online access via UMI:, 2005.
Find full text"This dissertation is a compound document (contains both a paper copy and a CD as part of the dissertation)"--ProQuest abstract document view. Includes bibliographical references.
Young, Fung Yu. "Algorithms for the design of VLSI floorplans and logic modules /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Full textLiu, Tai-hung. "Logic synthesis for high-performance digital circuits /." Digital version accessible at:, 1999. http://wwwlib.umi.com/cr/utexas/main.
Full textDhingra, Inderpreet Singh. "Formalising an integrated circuit design style in higher order logic." Thesis, University of Cambridge, 1988. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.278296.
Full textBertrand, François. "Conception descendante appliquée aux microprocesseurs VLSI." Phd thesis, Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316026.
Full textModi, Manish Harsukh. "Susceptibility evaluation of combational logic in VLSI circuits." Thesis, Virginia Tech, 1990. http://hdl.handle.net/10919/42221.
Full textMaster of Science
Degnan, Brian Paul. "Temperature robust programmable subthreshold circuits through a balanced force approach." Diss., Georgia Institute of Technology, 2013. http://hdl.handle.net/1853/47548.
Full textSunki, Supriya. "Performance optimization in three-dimensional programmable logic arrays (PLAs)." [Tampa, Fla.] : University of South Florida, 2005. http://purl.fcla.edu/fcla/etd/SFE0001255.
Full textKim, Dongho. "Power estimation for combinational logic and low power design /." Full text (PDF) from UMI/Dissertation Abstracts International, 2001. http://wwwlib.umi.com/cr/utexas/fullcit?p3008367.
Full textYee, Gin Sun. "Dynamic logic design and synthesis using clock-delayed domino /." Thesis, Connect to this title online; UW restricted, 1999. http://hdl.handle.net/1773/6039.
Full textHan, Yi. "A high-performance CMOS programmable logic core for system-on-chip applications /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/5948.
Full textLee, Hoon S. "A CAD tool for current-mode multiple-valued CMOS circuits." Thesis, Monterey, California. Naval Postgraduate School, 1988. http://hdl.handle.net/10945/22935.
Full textThe contribution of this thesis is the development of a CAD (computer aided design) tool for current mode multiple-valued logic (MVL) CMOS circuits. It is only the second known MVL CAD tool and the first CAD tool for MVL CMOS. The tool accepts a specification of the function to be realized by the user, produces a minimal or near-minimal realization (if such a realization is possible), and produces a layout of a programmable logic array (PLA) integrated circuit that realizes the given function. The layout is in MAGIC format, suitable for submission to a chip manufacturer. The CAD tool also allows the user to simulate the realized function so that he/she can verify correctness of design. The CAD tool is designed also to be an analysis tool for heuristic minimization algorithms. As part of this thesis, a random function generator and statistics gathering package were developed. In the present tool, two heuristics are provided and the user can choose one or both. In the latter case, the better realization is output to the user. The CAD tool is designed to be flexible, so that future improvements can be made in the heuristic algorithms, as well as the layout generator. Thus, the tool can be used to accommodate new technologies, for example, a voltage mode CMOS PLA rather than the current mode CMOS currently implemented.
http://archive.org/details/cadtoolforcurren00leeh
Lieutenant, Republic of Korea Navy
Holland, Mark. "Automatic creation of product-term-based reconfigurable architectures for system-on-a-chip /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6124.
Full textKucic, Matthew R. "Analog programmable filters using floating-gate arrays." Thesis, Georgia Institute of Technology, 2000. http://hdl.handle.net/1853/13755.
Full textStamoulis, Iakovos. "Computer graphics hardware using ASICs, FPGAs and embedded logic." Thesis, University of Sussex, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313943.
Full textSharma, Akshay. "Place and route techniques for FPGA architecture advancement /." Thesis, Connect to this title online; UW restricted, 2005. http://hdl.handle.net/1773/6108.
Full textChen, Daven 1959. "COMPARISON OF SCIRTSS EFFICIENCY WITH D-ALGORITHM APPLICATION TO ITERATIVE NETWORKS (TEST)." Thesis, The University of Arizona, 1986. http://hdl.handle.net/10150/275572.
Full textChenard, Jean-Samuel. "Hardware-based temporal logic checkers for the debugging of digital integrated circuits." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106282.
Full textLa complexité des circuits intégrés augmente sans cesse et à un tel point que le procéssus de déboggage pose de nombreux problèmes techniques et engendre des retards dans la production. Une approche d'ensemble de conception pour le déboggage (Design-for-Debug) devient donc rapidement une nécessité. Cette thèse propose une approche détaillée de niveau système, intégrant des circuits de surveillance sur puce. L'approche proposée s'appuie sur la réutilisation de déclarations écrites en language de logique temporelle afin de les transformer en circuits digitaux efficaces. Ces derniers seront intégrés à la puce à travers son interface d'image mémoire afin qu'ils puissent servir au processus de déboggage ainsi qu'à une utilisation dans le système lorsque la puce est intégrée dans son environement. Cette thèse présente une série d'ajout au procéssus de transformation d'instructions de logique temporelle de manière à faciliter le procéssus de déboggage. Une méthode qui automatise l'intégration des sorties et du contrôle des circuits de surveillance est présentée ainsi que la manière dont une utilisation de ces circuits peut être accomplie dans le contexte d'un système d'exploitation moderne (Linux). Finalement, une méthode globale d'intégration des circuits de vérification dans le contexte de systèmes basés sur les réseaux-sur-puce est présentée, accompagnée de la chaine d'outils requise pour supporter ce nouveau processus de conception. Cette méthode propose l'utilisation de facteurs de qualité de test, de surveillance et de déboggage (Test, Monitoring and Debug) permettant une meilleure sélection des circuits ainsi qu'une intégration plus efficace au niveau des resources matérielles.
Eckhardt, James P. "An investigation of high-performance logic circuitry in BiCMOS." Diss., Georgia Institute of Technology, 1990. http://hdl.handle.net/1853/15759.
Full textZhao, Weisheng. "Conception, evaluation and development of the non-volatile programmable logic circuits using the Magnetic Tunnel Junction (MTJ)." Paris 11, 2008. http://www.theses.fr/2008PA112051.
Full textOver the past 20 years, programmable logic circuits have grown rapidly, particularly through the advantages presented by their reconfigurability, ease of use and low cost of their development process. However, the inherent volatility of CMOS technology based on charge storage is the source of inconvenient for these circuits, such as: data loss in case of power failure, the long latency to initialize the system at each (re) start-up and increasing high standby power due to the leakage currents. This last point has become a major challenge as the shrinking of transistors down to 90nm or below. In recent years, numerous emerging technologies have been proposed and explored to overcome these problems. Among them, Spintronics technology, is among the most efficient and practical solutions. This thesis focuses on the study, design, simulation and implementation of reconfigurable circuits combining CMOS technology and advanced non-volatile emerging technologies based on Nano Spintronics. The Magnetic Tunnel Junction (MTJ) was particularly studied based on three modes of writing such as Spin Transfer Torque (STT). The hybrid circuits were first designed and simulated electrically. They show great potential in terms of speed, non-volatility and power compared to conventional circuits. They would promise also new computing architectures and some advanced reconfiguration methods. Finally, a prototype was developed to demonstrate the behaviour and performance of these circuits
Twigg, Christopher M. "Floating Gate Based Large-Scale Field-Programmable Analog Arrays for Analog Signal Processing." Diss., Georgia Institute of Technology, 2006. http://hdl.handle.net/1853/11601.
Full textHerbert, J. M. J. "Application of formal methods to digital system design." Thesis, University of Cambridge, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.233985.
Full textBridges, Seth. "Low-power visual pattern classification in analog VLSI /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/6984.
Full textWu, Lifei. "Minimization of Permuted Reed-Muller Trees and Reed-Muller Trees for Cellular Logic Programmable Gate Arrays." PDXScholar, 1993. https://pdxscholar.library.pdx.edu/open_access_etds/4745.
Full textLeeser, Miriam Ellen. "Reasoning about the function and timing of integrated circuits with Prolog and temporal logic." Thesis, University of Cambridge, 1987. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.232797.
Full textRamirez, Ortiz Rolando Carleton University Dissertation Engineering Electronics. "Circuit design rules for mixed static and dynamics CMOS logic circuits." Ottawa, 1999.
Find full textSunwoo, John Stroud Charles E. "Built-In Self-Test of programmable resources in microcontroller based System-on-Chips." Auburn, Ala., 2005. http://repo.lib.auburn.edu/2005%20Fall/Thesis/SUNWOO_JOHN_31.pdf.
Full textAziz, Syed Mahfuzul. "The realisation of high-speed, testable multipliers suitable for synthesis using differential CMOS circuits." Thesis, University of Kent, 1993. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.240166.
Full textVan, Aardt Stefan. "Total ionizing dose and single event upset testing of flash based field programmable gate arrays." Thesis, Nelson Mandela Metropolitan University, 2015. http://hdl.handle.net/10948/12548.
Full textOrr, Marc Stewart. "A Logic Formulation for the QCA Cell Arrangement Problem." PDXScholar, 2010. https://pdxscholar.library.pdx.edu/open_access_etds/438.
Full textSchafer, Ingo. "Orthogonal and Nonorthogonal Expansions for Multi-Level Logic Synthesis for Nearly Linear Functions and their Application to Field Programmable Gate Array Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/1339.
Full textPetre, Csaba. "Sim2spice a tool for compiling simulink designs on FPAA and applications to neuromorphic circuits /." Thesis, Atlanta, Ga. : Georgia Institute of Technology, 2009. http://hdl.handle.net/1853/31820.
Full textCommittee Chair: Paul Hasler; Committee Member: Christopher Rozell; Committee Member: David Anderson. Part of the SMARTech Electronic Thesis and Dissertation Collection.