Relevant bibliographies by topics / Programmable logic integrated circuits

Academic literature on the topic 'Programmable logic integrated circuits'

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Published: 30 May 2022
Last updated: 31 May 2022

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Journal articles on the topic "Programmable logic integrated circuits"

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Brukštus, Tautvydas. "ANALYSIS AND IMPLEMENTATION OF CRYPTOGRAPHIC HASH FUNCTIONS IN PROGRAMMABLE LOGIC DEVICES / KRIPTOGRAFINIŲ MAIŠOS FUNKCIJŲ ĮGYVENDINIMO PROGRAMUOJAMOSIOS LOGIKOS LUSTUOSE TYRIMAS." Mokslas – Lietuvos ateitis 8, no. 3 (June 29, 2016): 321–26. http://dx.doi.org/10.3846/mla.2016.927.

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In this day’s world, more and more focused on data protection. For data protection using cryptographic science. It is also important for the safe storage of passwords for this uses a cryptographic hash function. In this article has been selected the SHA-256 cryptographic hash function to implement and explore, based on fact that it is now a popular and safe. SHA-256 cryptographic function did not find any theoretical gaps or conflict situations. Also SHA-256 cryptographic hash function used cryptographic currencies. Currently cryptographic currency is popular and their value is high. For the measurements have been chosen programmable logic integrated circuits as they less efficiency then ASIC. We chose Altera Corporation produced prog-rammable logic integrated circuits. Counting speed will be investigated by three programmable logic integrated circuit. We will use programmable logic integrated circuits belong to the same family, but different generations. Each programmable logic integrated circuit made using different dimension technology. Choosing these programmable logic integrated circuits: EP3C16, EP4CE115 and 5CSEMA5F31. To compare calculations perfor-mances parameters are provided in the tables and graphs. Research show the calculation speed and stability of different programmable logic circuits. Vis daugiau dėmesio skiriama duomenų apsaugai – duomenų apsaugai skirta net atskira kriptografijos mokslo šaka. Taip pat yra svarbi slaptažodžių sauga, kurioje naudojamos kriptografinės maišos funkcijos. Darbe parinkta įgyvendinimui ir ištirta šiuo metu populiari bei saugi SHA-2 kriptografinė maišos funkcija. Ji naudojama kriptografinėse valiutose. SHA-2 kriptografinės funkcijos analizės metu nepavyko rasti teorinių spragų ar kolizijos atvejų. Tyrimams pasirinkti Altera programuojamos logikos integriniai grandynai, kurie efektyvumu nusileidžia tik specializuotiems integriniams grandynams. Skaičiavimo sparta ir stabilumas buvo tiriama trijuose programuojamos logikos integrinuose grandynuose, priklausančiuose tai pačiai šeimai ir pagamintais skirtingų kartų technologijomis – naudojant 65 nm, 60 nm ir 28 nm KMOP technologijas. Tirtų grandynų kodiniai žymenys EP3C16, EP4CE115 ir 5CSEMA5F31.
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Grekov, Artem Vladimirovich, and Vadim Borisovich Uspalenko. "PERSPECTIVE PROGRAMMABLE LOGIC INTEGRATED CIRCUITS FPGA FROM ALTERA." V mire nauchnykh otkrytiy, no. 6.1 (November 22, 2014): 518. http://dx.doi.org/10.12731/wsd-2014-6.1-13.

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Sou, Antony, Sungjune Jung, Enrico Gili, Vincenzo Pecunia, Jerome Joimel, Guillaume Fichet, and Henning Sirringhaus. "Programmable logic circuits for functional integrated smart plastic systems." Organic Electronics 15, no. 11 (November 2014): 3111–19. http://dx.doi.org/10.1016/j.orgel.2014.08.032.

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Shipulin, S. N., and S. N. Shilyaev. "Use of programmable integrated logic circuits in measurement engineering." Measurement Techniques 37, no. 2 (February 1994): 136–38. http://dx.doi.org/10.1007/bf00979200.

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Pashukov, A. V. "RESEARCH OF PECULIARITIES OF ERROR DETECTION ON THE OUTPUTS OF PROGRAMMABLE LOGIC INTEGRATED CIRCUITS WITH FUNCTIONAL CONTROL BASED ON MODULAR CODES WITH SUMMATION." Automation on Transport 7, no. 3 (September 2021): 477–95. http://dx.doi.org/10.20295/2412-9186-2021-7-3-477-495.

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The article provides examples of the use of programmable logic integrated circuits in various industries. Possible faults in FPGA blocks and their difference from faults in programmable logic arrays are described. Particular attention is paid to the failures of the LUT element. Features of the organization of technical diagnostics systems operating in the operating mode of the objects of diagnostics for combinational logic devices, implemented on the basis of programmable logic integrated circuits are described. Using the example of modular summation codes, it is shown that the known approaches to organizing such systems for devices implemented on a valve basis can be directly applied to devices of the type under consideration. Since malfunctions in the form of errors are recorded, and not the malfunctions themselves, the approaches to the organization of diagnostic systems are universal. It also provides a comparative characteristic of modular sum codes depending on the code module. A code has been proposed that will detect all faults in the example under study.
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Пирогов, А. А., Ю. А. Пирогова, С. А. Гвозденко, Д. В. Шардаков, and Б. И. Жилин. "DEVELOPMENT OF RECONFIGURABLE DEVICES BASED ON PROGRAMMABLE LOGIC INTEGRATED CIRCUITS." ВЕСТНИК ВОРОНЕЖСКОГО ГОСУДАРСТВЕННОГО ТЕХНИЧЕСКОГО УНИВЕРСИТЕТА, no. 6 (January 10, 2021): 90–97. http://dx.doi.org/10.36622/vstu.2020.16.6.013.

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Цифровая фильтрация распознаваемых сигналов является непременной процедурой при обнаружении и распознавании сообщений. Под фильтрацией понимают любое преобразование сигналов, при котором во входной последовательности обрабатываемых данных целенаправленно изменяются определенные соотношения между различными параметрами сигналов. Системы, избирательно меняющие форму сигналов, устраняющие или уменьшающие помехи, извлекающие из сигналов определенную информацию и т.п., называют фильтрами. Соответственно, фильтры с любым целевым назначением являются частным случаем систем преобразования сигналов. Программируемые логические интегральные схемы (ПЛИС) представляют собой конфигурируемые интегральные схемы, логика работы которых определяется посредством их программирования. Применение ПЛИС для задач цифровой обработки сигналов позволяет получать устройства, способные менять конфигурацию, подстраиваться под определенную задачу за счет их гибко изменяемой, программируемой структуры. При разработке сложных устройств могут применяться в качестве компонентов для проектирования готовые блоки - IP-ядра или сложно-функциональные блоки (СФ-блоки). Использование программных СФ-блоков позволяет наиболее эффективно задействовать их в конечной структуре, в значительной степени сократить затраты на проектирование. Цель работы состоит в построении RTL модели СФ-блока цифровой обработки сигналов, его верификации как на логическом уровне, так и физическом Digital filtering of recognized signals is an indispensable procedure for the detection and recognition of messages. Filtering is understood as any transformation of signals in which certain relationships between different signal parameters are purposefully changed in the input sequence of the processed data. Systems that selectively change the shape of signals, eliminate or reduce interference, extract certain information from the signals, and so on, are called filters. Accordingly, filters with any purpose are a special case of signal conversion systems. Programmable logic integrated circuits (FPGAs) are configurable integrated circuits whose logic is defined through programming. The use of FPGAs for digital signal processing tasks makes it possible to obtain devices capable of changing the configuration, adapting to a specific task due to their flexibly changeable, programmable structure. When developing complex devices, ready-made blocks - IP-cores or complex-functional blocks (SF blocks) - can be used as components for design. The use of software SF-blocks allows them to be used most effectively in the final structure, to a significant extent to reduce design costs. The purpose of the work is to build an RTL model of the SF-block for digital signal processing, its verification both at the logical and physical levels
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Lashin, A. V., and A. V. Kozyrev. "Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits." Power Technology and Engineering 49, no. 3 (September 2015): 216–18. http://dx.doi.org/10.1007/s10749-015-0602-6.

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Trost, Andrej, Andrej Zemva, and Matjaz Verderber. "Prototyping Hardware and Software Environment for Teaching Digital Circuit Design." International Journal of Electrical Engineering & Education 38, no. 4 (October 2001): 368–78. http://dx.doi.org/10.7227/ijeee.38.4.9.

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In the paper, we present our latest achievements and experience in undergraduate teaching of digital circuits, integrated circuits and embedded systems by exploiting our prototyping hardware and software environment. The hardware environment is based on Field Programmable Gate Array (FPGA) modules that provide sufficient flexibility and support a broad scope of digital design applications. In addition, the designed software environment supports user-friendly hardware verification of the logic circuits implemented on the hardware system. We describe some typical applications and student projects implemented on the programmable prototyping system.
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Melnyk, Oleksandr, and Viktoriia Kozarevych. "SIMULATION OF PROGRAMMABLE SINGLE-ELECTRON NANOCIRCUITS." Bulletin of the National Technical University "KhPI". Series: Mathematical modeling in engineering and technologies, no. 1 (March 5, 2021): 64–68. http://dx.doi.org/10.20998/2222-0631.2020.01.05.

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The speed and specializations of large-scale integrated circuits always contradict their versatility, which expands their range and causes the rise in price of electronic devices. It is possible to eliminate the contradictions between universality and specialization by developing programmable nanoelectronic devices, the algorithms of which are changed at the request of computer hardware developers, i.e. by creating arithmetic circuits with programmable characteristics. The development of issues of theory and practice of the majority principle is now an urgent problem, since the nanoelectronic execution of computer systems with programmable structures will significantly reduce their cost and significantly simplify the design stage of automated systems. Today there is an important problem of developing principles for building reliable computer equipment. The use of mathematical and circuit modeling along with computer-aided design systems (CAD) can significantly increase the reliability of the designed devices. The authors prove the advantages of creating programmable nanodevices to overcome the physical limitations of micro-rominiatization. This continuity contributes to the accelerated introduction of mathematical modeling based on programmable nanoelectronics devices. The simulation and computer-aided design of reliable programmable nanoelectronic devices based on the technology of quantum automata is described. While constructing single-electron nanocircuits of combinational and sequential types the theory of majority logic is used. The order of construction and programming of various types of arithmetic-logic units is analyzed.
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Tyurin, S. F., and O. A. Gromov. "A residual basis search algorithm of fault-tolerant programmable logic integrated circuits." Russian Electrical Engineering 84, no. 11 (November 2013): 647–51. http://dx.doi.org/10.3103/s1068371213110163.

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Dissertations / Theses on the topic "Programmable logic integrated circuits"

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Hadjinicolaou, M. G. "Synthesis of programmable logic arrays." Thesis, Brunel University, 1986. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.371168.

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Davis, Justin S. "An FPGA-based digital logic core for ATE support and embedded test applications." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/15639.

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Moon, Gyo Sik. "An Algorithm for the PLA Equivalence Problem." Thesis, University of North Texas, 1995. https://digital.library.unt.edu/ark:/67531/metadc278922/.

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The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunately, BDD requires too much time and space to represent moderately large circuits for equivalence testing. We design and implement a new algorithm called the Cover-Merge Algorithm for the equivalence problem based on a divide-and-conquer strategy using the concept of cover and a derivational method. We prove that the algorithm is sound and complete. Because of the NP-completeness of the problem, we emphasize simplifications to reduce the search space or to avoid redundant computations. Simplification techniques are incorporated into the algorithm as an essential part to speed up the the derivation process. Two different sets of heuristics are developed for two opposite goals: one for the proof of equivalence and the other for its disproof. Experiments on a large scale of data have shown that big speed-ups can be achieved by prioritizing the heuristics and by choosing the most favorable one at each iteration of the Algorithm. Results are compared with those for BDD on standard benchmark problems as well as on random PLAs to perform an unbiased way of testing algorithms. It has been shown that the Cover-Merge Algorithm outperforms BDD in nearly all problem instances in terms of time and space. The algorithm has demonstrated fairly stabilized and practical performances especially for big PLAs under a wide range of conditions, while BDD shows poor performance because of its memory greedy representation scheme without adequate simplification.
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Tan, Chong Guan. "Another approach to PLA folding." Thesis, McGill University, 1985. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=66054.

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Воргуль, О. В., І. В. Свид, О. В. Зубков, and В. В. Семенець. "Teaching microcontrollers and FPGAs in Quarantine from Coronavirus: Challenges and Prospects." Thesis, MC&FPGA, 2020. https://mcfpga.nure.ua/conf/2020-mcfpga/10-35598-mcfpga-2020-005.

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Modern equipment is becoming more and more complex and education establishment must keep up with it and offer its contribution to the overall progress. The goal of this work is to find the way how to survive on self-isolation and teach microcontrollers and FPGAs. What challenges need to be overcome and what prospects may open up.
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Chadha, Vishal. "Design and Implementation of a Second Generation Logic Cluster for Multi-Technology Field Programmable Gate Arrays." University of Cincinnati / OhioLINK, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1126539992.

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Draier, Benny. "Test vector generation and compaction for easily testable PLAs." Thesis, McGill University, 1988. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=63970.

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Wan, Wei. "A New Approach to the Decomposition of Incompletely Specified Functions Based on Graph Coloring and Local Transformation and Its Application to FPGA Mapping." PDXScholar, 1992. https://pdxscholar.library.pdx.edu/open_access_etds/4698.

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The thesis presents a new approach to the decomposition of incompletely specified functions and its application to FPGA (Field Programmable Gate Array) mapping. Five methods: Variable Partitioning, Graph Coloring, Bond Set Encoding, CLB Reusing and Local Transformation are developed in order to efficiently perform decomposition and FPGA (Lookup-Table based FPGA) mapping. 1) Variable Partitioning is a high quality hemistic method used to find the "best" partitions, avoiding the very time consuming testing of all possible decomposition charts, which is impractical when there are many input variables in the input function. 2) Graph Coloring is another high quality heuristic\ used to perform the quasi-optimum don't care assignment, making the program possible to accept incompletely specified function and perform a quasi-optimum assignment to the unspecified part of the function. 3) Bond Set Encoding algorithm is used to simplify the decomposed blocks during the process of decomposition. 4) CLB Reusing algorithm is used to reduce the number of CLBs used in the final mapped circuit. 5) Local Transformation concept is introduced to transform nondecomposable functions into decomposable ones, thus making it possible to apply decomposition method to FPGA mapping. All the above developed methods are incorporated into a program named TRADE, which performs global optimization over the input functions. While most of the existing methods recursively perform local optimization over some kinds of network-like graphs, and few of them can handle incompletely specified functions. Cube calculus is used in the TRADE program, the operations are global and very fast. A short description of the TRADE program and the evaluation of the results are provided at the_ end of the thesis. For many benchmarks the TRADE program gives better results than any program published in the literature.
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Perez, Segovia Tomás. "Paola : un système d'optimisation topologique de PLA." Grenoble INPG, 1985. http://tel.archives-ouvertes.fr/tel-00316330.

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Lors de la conception des circuits intégrés VLSI, les Réseaux Logiques Programmables (P. L. A. ) permettent le dessin automatique des masques à partir d'une description logique. La surface occupée par ces PLAs peut, dans certains cas, s'avérer prohibitive; d'où l'intérêt des méthodes d'optimisation topologique de ceux-ci. Après avoir défini les différentes représentations possibles des PLAs, on présente l'état en ce qui concerne l'optimisation topologique des PLAs. La méthode des «Lignes Brisées» est ensuite détaillée en insistant sur les heuristiques choisies ainsi que sur les interactions qui existent entre l'étape d'optimisation et l'étape de tracé des connexions internes. On termine par une présentation globale du système PAOLA d'optimisation topologique et dessin de PLAs
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Nguyen, Loc Bao. "Logic design using programmable logic devices." PDXScholar, 1988. https://pdxscholar.library.pdx.edu/open_access_etds/4103.

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The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems. This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits. The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good. The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent. One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.
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Books on the topic "Programmable logic integrated circuits"

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F, Whapshott G., ed. Programmable logic: PLDs and FPGAs. New York: McGraw-Hill, 1997.

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Kelly, David. Parallel test pattern generation for programmable logic devices. Dublin: University College Dublin, 1995.

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Lemieux, Guy. Design of interconnection networks for programmable logic. Boston, MA: Kluwer Academic, 2003.

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David, Lewis, ed. Design of interconnection networks for programmable logic. Boston: Kluwer Academic Publishers, 2004.

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Baranov, S. I. T͡S︡ifrovye ustroĭstva na programmiruemykh BIS s matrichnoĭ strukturoĭ. Moskva: Radio i svi͡a︡zʹ, 1986.

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Bostock, Geoff. FPGAs and programmable LSI: A designer's handbook / Geoff Bostock. Oxford: Butterworth-Heinemann, 1996.

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Digital fundamentals: Experiments and concepts with CPLDs. Clifton Park, NY: Thomson/Delmar Learning, 2004.

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Plaks, Toomas P. Piecewise regular arrays: Application-specific computations. Australia: Gordon and Breach Science, 1999.

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Nikhil, Rishiyur S. BSV by example: The next-generation language for electronic system design. [Framingham, MA]: Bluespec, 2010.

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Bolton, W. Programmable logic controllers. 4th ed. Amsterdam: Elsevier, 2007.

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Book chapters on the topic "Programmable logic integrated circuits"

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Seals, R. C., and G. F. Whapshott. "Introduction to integrated circuits." In Programmable Logic: PLDs and FPGAs, 1–35. London: Macmillan Education UK, 1997. http://dx.doi.org/10.1007/978-1-349-14003-9_1.

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LaMeres, Brock J. "Programmable Logic." In Introduction to Logic Circuits & Logic Design with Verilog, 383–96. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-13605-5_11.

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LaMeres, Brock J. "Programmable Logic." In Introduction to Logic Circuits & Logic Design with VHDL, 393–406. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-12489-2_11.

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LaMeres, Brock J. "Programmable Logic." In Introduction to Logic Circuits & Logic Design with Verilog, 359–72. Cham: Springer International Publishing, 2017. http://dx.doi.org/10.1007/978-3-319-53883-9_11.

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LaMeres, Brock J. "Programmable Logic." In Introduction to Logic Circuits & Logic Design with VHDL, 371–84. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-34195-8_11.

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Keller, Eric. "Building Asynchronous Circuits with JBits." In Field-Programmable Logic and Applications, 628–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_68.

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Sachdev, Manoj. "Testing Defects in Programmable Logic Circuits." In Defect Oriented Testing for CMOS Analog and Digital Circuits, 205–41. Boston, MA: Springer US, 1999. http://dx.doi.org/10.1007/978-1-4757-4926-7_6.

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Ferrera, Steve, and Nicholas P. Carter. "Reconfigurable Circuits Using Hybrid Hall Effect Devices." In Field Programmable Logic and Application, 1–10. Berlin, Heidelberg: Springer Berlin Heidelberg, 2003. http://dx.doi.org/10.1007/978-3-540-45234-8_1.

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Wolz, Frank, and Reiner Kolla. "Bubble Partitioning for LUT-Based Sequential Circuits." In Field-Programmable Logic and Applications, 336–45. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-44687-7_35.

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D’Mello, Dean R., and P. Glenn Gulak. "Design Approaches to Field-Programmable Analog Integrated Circuits." In Field-Programmable Analog Arrays, 7–34. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-1-4757-5224-3_1.

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Conference papers on the topic "Programmable logic integrated circuits"

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Gowni, S. P., P. E. Platt, A. L. Hawkins, W. R. Hiltpold, and S. M. Douglass. "A 12 ns, CMOS programmable logic device for combinatorial applications." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56694.

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Samson, G., and L. T. Clark. "A 0.13 μm Low-power Race-free Programmable Logic Array." In Proceedings of the IEEE 2006 Custom Integrated Circuits Conference. IEEE, 2006. http://dx.doi.org/10.1109/cicc.2006.320899.

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Akihiro, Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, and Takeshi Fujino. "Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing." In 2007 IEEE 29th Custom Integrated Circuits Conference. IEEE, 2007. http://dx.doi.org/10.1109/cicc.2007.4405728.

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Rose, J., R. J. Francis, P. Chow, and D. Lewis. "The effect of logic block complexity on area of programmable gate arrays." In 1989 Proceedings of the IEEE Custom Integrated Circuits Conference. IEEE, 1989. http://dx.doi.org/10.1109/cicc.1989.56691.

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Vorobev, Konstantin Sergeevich, and Ruslan Sergeevich Slobodin. "Overview of the functionality of network processors based on programmable logic integrated circuits." In X International Research-to-practice conference. TSNS Interaktiv Plus, 2017. http://dx.doi.org/10.21661/r-118809.

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Chang, Augustine. "The Giga Hz 1 Mb mask programmable ROM chip with SBD array, logic gate, and SRAM cores." In 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, 2010. http://dx.doi.org/10.1109/icsict.2010.5667814.

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Kara-Zaitri, Chakib, and Obaida Alsahli. "The Development of a Hardware Oriented Tool for Risk Assessment and Modelling." In ASME 2000 International Mechanical Engineering Congress and Exposition. American Society of Mechanical Engineers, 2000. http://dx.doi.org/10.1115/imece2000-1020.

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Abstract This paper describes the development of a “hardware-oriented” tool capable of handling the qualitative analysis of Integrated FMEA and FTA i.e. Failure Modes and Effects Tree Analysis (FMETA). The Boolean reduction required for the determination of MCSs is inherently dealt with the hardware system. The work carried takes advantage of the significant development made in Application Specific Integrated Circuits (ASICs). The new idea here is that a hardware design can, in fact, mimic the failure logic of a given system and can therefore encapsulate the underlying FMETA knowledge base. In this research, an algorithm based on the new idea has been successfully implemented on a Programmable Logic Device (PLD) using simulation software. The prototype system developed is a small unit consisting of a chip containing the “wired-in” failure knowledge base, in terms of FMETA, and a simple input / output device for interrogation purposes. The intrinsic PLD simulation algorithm is shown to successfully model the relationships existing between repeated failure causes, modes and effects and generate the list of associated MCSs in a truly integrated FMEA/FTA context.
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Jingyao, Huang, Yang Jing, and Peter Floyd Salinas. "Successfully Look Up Table Distribution RAM Control Circuitry Fault Isolation with Different Test Methodologies and Conflict Results Analysis by Using Virtual IO and Integrated Logic Analyzer Debug Tools." In ISTFA 2018. ASM International, 2018. http://dx.doi.org/10.31399/asm.cp.istfa2018p0467.

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Abstract This electrical fault isolation based on Xilinx 28nm all programmable device in a Distribution RAM (LUTRAM) functional block. The Look-Up-Table (LUT) was the major component to achieve the programmable chip versus the ASIC chip. In the device architecture, one 6-inputs-LUT (LUT6) memory can be configured as a 64bits distribution RAM (LUTRAM64) or two 32bits distribution RAMs (LUTRAM32). The Vivado design and debug tool brought up two powerful Intellectual Property (IP) Cores: Virtual Input/Output (VIO) and Integrated Logic Analyzer (ILA). This debug tool used Block RAM (BRAM) and fabric routing resources to store the full test results and achieved package level probe-less. [1] It can probe LUTRAM block input, output and Build-In Self-Test (BIST) interconnects. However the limitation was that the inner primitive functional block LUTRAM like memory cells, decoders, mode switchers, write/read controllers and so on were not able to probe. In this case study, the defect was not conventional failure inside the LUTRAM memory cell or stuck on Address/Data_in inputs. Moreover the test behavior with LUTRAM64 mode had conflicting results, which made the fault isolation even more challenge to narrow down from complex LUTRAM control circuitry to transistor level. Therefore different pattern test methodologies, pattern commonality analysis and hypothesis verification were wisely compiled together. In the end, the defect was successfully localized at the fault Isolation circuitry. It was fully matching with the failing mode and proving the fault isolation was correct. The physical defect analysis shown multiple layers metal fusing. The defect shorted the internal control output with the GND signal, which forced LUTRAM to setup as an invalid mode.
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Bogaerts, Wim, Xiangfeng Chen, Mi Wang, Iman Zand, Hong Deng, Lukas Van Iseghem, Antonio Ribeiro, Alejandro Diaz Tormo, and Umar Khan. "Programmable Silicon Photonic Integrated Circuits." In 2020 IEEE Photonics Conference (IPC). IEEE, 2020. http://dx.doi.org/10.1109/ipc47351.2020.9252475.

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Pathak, Vider, Douglass, Arreola, and Mehta. "A 50mhz Cmos Programmable Logic Device." In 1988 IEEE International Solid-State Circuits Conference. IEEE, 1988. http://dx.doi.org/10.1109/isscc.1988.663671.

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