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Journal articles on the topic 'Programmable finite impulse response'

Author: Grafiati

Published: 25 May 2024

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1

Poornima, Y., and M. Kamalanathan. "Design of Low Power Vedic Multiplier Based Reconfigurable Fir Filter for DSP Applications." International Journal of Advance Research and Innovation 7, no. 2 (2019): 57–60. http://dx.doi.org/10.51976/ijari.721908.

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Recent advances in mobile computing and multimedia applications demand high - performance and low - power VLSI digital signal processing (DSP) systems. One of the most widely used operations in DSP is finite - impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high - performance applications. One of the most widely used operations in DSP is finite - impulse response (FIR) filtering. In the existing method FIR filter is designed using array multiplier, which is having higher delay and power dissipation. The proposed method presents a programmable digital finite impulse response (FIR) filter for high performance applications. The FIR filter performs the weighted summations of input sequences and is widely used in video convolution functions, signal preconditioning, and various communication applications. Recently, due to the high - performance requirement and increasing complexity of DSP and multimedia communication application. In this work, , FIR filter multipliers are extensively characterized with power simulations, providing a methodology for the perturbation of the coefficients of baseline filters at the algorithm level to trade-off reduced power consumption for filter quality. The proposed optimization technique does not require any hardware overhead and it enables the possibility of scaling the power consumption of the filter at runtime.

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2

Aparna, A., and T. Vigneswaran. "DESIGN OF HIGH PERFORMANCE MULTIPLIERLESS LINEAR PHASE FINITE IMPULSE RESPONSE FILTERS." Asian Journal of Pharmaceutical and Clinical Research 10, no. 13 (April 1, 2017): 66. http://dx.doi.org/10.22159/ajpcr.2017.v10s1.19564.

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This research work proposes the finite impulse response (FIR) filters design using distributed arithmetic architecture optimized for field programmable gate array. To implement computationally efficient, low power, high-speed FIR filter a two-dimensional fully pipelined structure is used. The FIR filter is dynamically reconfigured to realize low pass and high pass filter by changing the filter coefficients. The FIR filter is most fundamental components in digital signal processing for high-speed application. The aim of this research work is to design multiplier-less FIR filter for the requirements of low power and high speed various embedded applications.

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3

Zhang, Zhenyu, Yanan Li, and Bassam Nima. "Digital Finite Impulse Response Equalizer for Nonlinear Frequency Response Compensation in Wireless Communication." Electronics 12, no. 9 (April 26, 2023): 2010. http://dx.doi.org/10.3390/electronics12092010.

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Signal distortion can occur when the gain or attenuation of a component changes non-linearly with frequency, which is referred to as nonlinear frequency response. Common communications components such as filters, amplifiers, and mixers can lead to nonlinear frequency responses, which can cause errors in transmitting and receiving. This article outlines the design and demonstration of a static and dynamic finite impulse response (FIR) digital equalizer circuit. Using predistortion topology with a coupled feedback loop, the adaptive Least-Mean Square (LMS) algorithm was implemented. The FIR filter was simulated in MATLAB and Vivado and then implemented onto an Eclypse Z7 Field Programmable Gate Array (FPGA) evaluation board. Simulations showed that the custom RTL module gave the same frequency response that was produced in MATLAB calculations. The filter was able to dynamically equalize the frequency responses of different nonlinear boards that were used as the devices under test (DUT). Measurements showed that the equalizer was able to compensate for system distortion from 0.2 to 0.8 Nyquist frequency. The phase response remained relatively linear across the band of interest, with a group delay flatness less than 10 ns.

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4

Vandenbussche, Jean‐Jacques, Peter Lee, and Joan Peuteman. "Multiplicative finite impulse response filters: implementations and applications using field programmable gate arrays." IET Signal Processing 9, no. 5 (July 2015): 449–56. http://dx.doi.org/10.1049/iet-spr.2014.0143.

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5

Mohanraj, R., and R. Vimala. "ECG Signal Denoising with Field-Programmable Gate Array Implementation of Fast Digital Finite Impulse Response and Infinite Impulse Response Filters." Journal of Medical Imaging and Health Informatics 10, no. 1 (January 1, 2020): 81–85. http://dx.doi.org/10.1166/jmihi.2020.2842.

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6

Długosz, Rafał, and Krzysztof Iniewski. "Programmable Switched Capacitor Finite Impulse Response Filter with Circular Memory Implemented in CMOS 0.18 μm Technology." Journal of Signal Processing Systems 56, no. 2-3 (June 10, 2008): 295–306. http://dx.doi.org/10.1007/s11265-008-0233-3.

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7

., Akriti. "The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW." International Journal for Research in Applied Science and Engineering Technology 12, no. 3 (March 31, 2024): 17–20. http://dx.doi.org/10.22214/ijraset.2024.58572.

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Abstract: This research investigates challenges in employing the Distributed Arithmetic (DA) algorithm for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). Focusing on coefficient representation, it explores precision trade-offs via fixed-point arithmetic and quantization. Memory optimization strategies, such as efficient storage within FPGA resources, are analysed to reduce memory requirements. Enhancing computational speed involves optimizing lookup table access and architectural modifications. Efficient management of FPGA resources and trade-offs between latency, throughput, and resource usage are also explored. Algorithmic refinements specific to DA-based FIR filters are studied to enhance resource utilization and computational efficiency. Overall, this work offers insights and solutions spanning algorithm design, memory utilization, lookup table speed, and FPGA architecture for more efficient DA-based FIR filter implementations on FPGAs.

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8

Kumari, Puja, Rajeev Gupta, and Abhijit Chandra. "Design and Implementation of a Power Efficient Pulse-shaping Finite Impulse Response Filter on a Field Programmable Gate Array Chip." International Journal of Image, Graphics and Signal Processing 4, no. 4 (May 15, 2012): 1–10. http://dx.doi.org/10.5815/ijigsp.2012.04.01.

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9

Jain, Ekta H., and Chandu N. Bhoyar. "Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result." Journal of Advance Research in Electrical & Electronics Engineering (ISSN: 2208-2395) 2, no. 2 (February 28, 2015): 10–17. http://dx.doi.org/10.53555/nneee.v2i2.231.

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Recent years there has been a increasing trend to implement digital signal processing functions in Field Programmable Gate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functions such as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present a method for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) and Distributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements are used. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

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10

WANG, WEI, M. N. S. SWAMY, and M. O. AHMAD. "NOVEL DESIGN AND FPGA IMPLEMENTATION OF DA-RNS FIR FILTERS." Journal of Circuits, Systems and Computers 13, no. 06 (December 2004): 1233–49. http://dx.doi.org/10.1142/s0218126604001970.

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Field programmable gate array (FPGA)-based digital signal processing has been widely used in multimedia applications. By combining distributed arithmetic (DA) and residue number system (RNS) in such designs, efficient area, speed and power efficiency can be achieved. In this paper, we propose novel techniques for the design and FPGA implementation of DA-RNS finite impulse response (FIR) filters. By introducing a novel low-cost moduli set and its selection method, efficient modulo arithmetic units inside the subfilters are designed. Then, a new residue-to-binary conversion algorithm, a so-called modified DA Chinese remainder theorem, is derived to reduce the modulo operations and provide an efficient residue-to-binary converter suitable to FPGA implementation. Based on these proposed techniques, a seventh-order DA-RNS FIR filter is designed, implemented and tested by using Xilinx FPGA tools. The implementation results show that the proposed filter design consumes only 77% of the power that the existing filter12,13 requires, while maintaining the same speed (throughput).

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11

Dwivedi, Atul Kumar, Narendra D. Londhe, and Subhojit Ghosh. "Low power 2D finite impulse response filter design using modified artificial bee colony algorithm with experimental validation using field-programmable gate array." IET Science, Measurement & Technology 10, no. 6 (September 1, 2016): 671–78. http://dx.doi.org/10.1049/iet-smt.2016.0069.

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12

Šlenderis, Arūnas, and Gintautas Daunys. "IMAGE FILTERING WITH FIELD PROGRAMMABLE GATE ARRAY / VAIZDŲ FILTRAVIMAS LAUKU PROGRAMUOJAMA LOGINE MATRICA." Mokslas - Lietuvos ateitis 5, no. 2 (May 24, 2013): 70–73. http://dx.doi.org/10.3846/mla.2013.11.

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The research examined the use of field programmable gate arrays (FPGA) in image filtering. Experimental and theoretical researches were reviewed. Experiments with Cyclone III family FPGA chip with implemented NIOS II soft processor were considered. Image filtering was achieved with symmetrical and asymmetrical finite impulse response filters with convolution kernel. The system, which was implemented with 3×3 symmetrical filter, which was implemented using the hardware description language, uses 59% of logic elements of the chip and 10 multiplication elements. The system with asymmetrical filter uses the same amount of logic elements and 13 multiplication elements. Both filter systems consume approx. 545 mW of power. The system, which is designed for filter implementation in C language, uses 65% of all logical elements and consumes 729 mW of power. Article in Lithuanian. Santrauka Nagrinėjama, kaip vaizdams filtruoti naudojamos lauku programuojamos loginės matricos (LPLM). Apžvelgti eksperimentiniai ir teoriniai darbai. Atlikti bandymai su Cyclone III šeimos LPLM lustu, kuriame buvo įdiegtas įkeliamasis NIOS II procesorius. Vaizdai filtruoti su simetriniu ir nesimetriniu ribotos impulsinės reakcijos filtrais, naudojant sąsūkos branduolį. Sistema, kuri buvo įdiegta kartu su 3×3 simetriniu filtru, naudojant aparatinės įrangos aprašymo kalbą, naudoja 59 % lusto loginių elementų ir 10 dauginimo elementų. Ši sistema su nesimetriniu filtru naudoja tiek pat loginių elementų ir 13 dauginimo elementų. Abiejų filtrų sistemų naudojama galia yra panaši – apie 545 mW. Sistemos su įkeliamuoju procesoriumi naudojamų loginių elementų dalis siekia 65 %, naudojama galia – 729 mW.

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13

Astik, Noopur. "Dynamic Partial Reconfiguration with FIR Filter Application." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 3 (November 1, 2015): 201. http://dx.doi.org/10.11591/ijres.v4.i3.pp201-208.

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Dynamic partial reconfiguration has evolved as a very prominent state of art for efficient area utilization of <em>Field Programmable Gate Array</em> (FPGA) as well as significant reduction in its overall power consumption when properly used to lessen the idle logic on FPGA. It provides desired results even as the computational complexity increases in the field of Digital Signal Processing. This paper explains Dynamic Partial Reconfiguration (DPR) with an example of Finite Impulse response (FIR) filter of order 10. Initially RTL coding for Direct Form FIR structure is written in Verilog in fixed point format for low pass and high pass filter modules using ISE Design suite. Functioning of the both the modules is verified individually through hardware co-simulation on ZYBO (Zynq Board) from Digilent using Black Box from System Generator. Finally dynamic partial reconfigurable FIR filter with low pass and high pass as reconfigurable modules is implemented on ZYBO using PlanAhead tool. Final comparison of resource utilization with and without DPR is presented

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14

Patel, Vandana, and Ankit Shah. "Denoising electrocardiogram signals using multiband filter and its implementation on FPGA." Serbian Journal of Electrical Engineering 19, no. 2 (2022): 115–28. http://dx.doi.org/10.2298/sjee2202115p.

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The electrocardiogram (ECG) signal carries vital information related to cardiac activities. While measuring ECG using electrodes, the signal is contaminated with powerline interference (PLI) from harmonics, baseline wandering (BW), motion artefacts (MA) and high frequency (HF) noise. The extraction of the ECG signal, without the loss of useful information from the noisy environment, is required. Therefore, the selection and implementation of an efficient filter design is proposed. The Finite Impulse Response (FIR)-based multiband needs separate digital filters, such as Lowpass, Highpass, and Bandstop Filter in cascade. The coefficients of the FIR multiband filter are optimised using a least squares optimisation method and realised in a direct form symmetrical structure. The capability of the proposed filter is evaluated on a Physionet ECG ID database, having records of inherent noisy ECG signals. The performance is also verified by measuring the power spectrum of the noisy and filtered ECG waveform. Also, the feasibility of the proposed multiband filter is investigated on Xilinx ISE and the design is implemented on a field programmable gate array (FPGA) platform. A low order simple multiband filter structure is designed and implemented on the reconfigurable FPGA device.

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15

Monica, Kommalapati, Dereddy Anuradha, Syed Rasheed, and Barnala Shereesha. "VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder." International Journal of Intelligent Engineering and Systems 14, no. 1 (February 28, 2021): 22–31. http://dx.doi.org/10.22266/ijies2021.0228.03.

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Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

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16

Meitei, Huirem Bharat, and Manoj Kumar. "Implementation of a secure wireless communication system using true random number generator for internet of things." Indonesian Journal of Electrical Engineering and Computer Science 30, no. 2 (May 1, 2023): 982. http://dx.doi.org/10.11591/ijeecs.v30.i2.pp982-992.

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This paper describes the design and implementation of an internet of thing (IoT)-based application that uses a true random number generator (TRNG) with an all digital phase locked loop (ADPLL) for secure wireless communication. Field programmable gate array (FPGA) boards were used on the transmitter and receiver sides and were interfaced with Esp8266 chips to wirelessly send and receive encrypted sensor data. The MQ-2 gas sensor and tracking sensor were connected to the FPGA board on the transmitter side, where data from the sensors was encrypted using the exclusive-OR (XOR) function and the TRNG architecture. The system can be controlled by users through a web browser served by the ThingSpeak cloud. The Artix-7 FPGA device is used to implement the proposed wireless communication system, for which design and synthesis were done using the Xilinx Vivado 2015.2 tool. The proposed system uses a low amount of power and is suitable for a standalone, highly secure TRNG-based IoT application. The National Institute of Standard and Testing (NIST SP 800-22) test showed that ADPLL with finite impulse response (FIR) filter-based TRNGs are better for encrypting IoT devices for secure wireless communication.

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17

Mirzaei, Shahnam, Ryan Kastner, and Anup Hosangadi. "Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs." International Journal of Reconfigurable Computing 2010 (2010): 1–17. http://dx.doi.org/10.1155/2010/697625.

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We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes routing delay using prelayout wire length estimation techniques to improve the final placed and routed design. The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks. For placement, there is a saving up to 20% in number of routing channels. This results in lower congestion and up to 8% reduction in average wirelength.

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Ezilarasan, M. R., J. Britto Pari, and Man-Fai Leung. "Reconfigurable Architecture for Noise Cancellation in Acoustic Environment Using Single Multiply Accumulate Adaline Filter." Electronics 12, no. 4 (February 6, 2023): 810. http://dx.doi.org/10.3390/electronics12040810.

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The creation of multiple applications with a higher level of complexity has been made possible by the usage of artificial neural networks (ANNs). In this research, an efficient flexible finite impulse response (FIR) filter structure called ADALINE (adaptive linear element) that makes use of a MAC (multiply accumulate) core is proposed. The least mean square (LMS) and recursive least square (RLS) algorithms are the most often used methods for maximizing filter coefficients. Despite outperforming the LMS, the RLS approach has not been favored for real-time applications due to its higher design arithmetic complexity. To achieve less computation, the fundamental filter has utilized an LMS-based tapping delay line filter, which is practically a workable option for an adaptive filtering algorithm. To discover the undiscovered system, the adjustable coefficient filters have been developed in the suggested work utilizing an optimal LMS approach. The 10-tap filter being considered here has been analyzed and synthesized utilizing field programmable gate array (FPGA) devices and programming in hardware description language. In terms of how well the resources were used, the placement and postrouting design performed well. If the implemented filter architecture is compared with the existing filter architecture, it reveals a 25% decrease in resources from the existing one and an increase in clock frequency of roughly 20%.

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19

Santoni, Francesco, Alessio De Angelis, Antonio Moschitta, and Paolo Carbone. "Digital Impedance Emulator for Battery Measurement System Calibration." Sensors 21, no. 21 (November 6, 2021): 7377. http://dx.doi.org/10.3390/s21217377.

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Meaningful information on the internal state of a battery can be derived by measuring its impedance. Accordingly, battery management systems based on electrochemical impedance spectroscopy are now recognized as a feasible solutions for online battery control and diagnostic. Since the impedance of a battery is always changing along with its state of charge and aging effects, it is important to have a stable impedance reference in order to calibrate and test a battery management system. In this work we propose a programmable impedance emulator that in principle could be used for the calibration of any battery management system based on electrochemical impedance spectroscopy. A digital finite-impulse-response filter is implemented, whose frequency response is programmed so as to reproduce exactly the impedance of a real battery in the frequency domain. The whole design process of the filter is presented in detail. An analytical expression for the impedance of real battery in the frequency domain is derived from an equivalent circuit model. The model is validated both through numerical simulations and experimental tests. In particular, the filter is implemented on a low-cost microcontroller unit, and the emulated impedance is measured by means of a custom-made electrochemical impedance spectroscopy measuring system, and verified by using standard commercial bench instruments. Results on this prototype show the feasibility of using the proposed emulator as a fully controllable and low-cost reference for calibrating battery impedance measurement systems.

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20

Ruano, Óscar, Francisco García-Herrero, Luis Alberto Aranda, Alfonso Sánchez-Macián, Laura Rodriguez, and Juan Antonio Maestro. "Fault Injection Emulation for Systems in FPGAs: Tools, Techniques and Methodology, a Tutorial." Sensors 21, no. 4 (February 17, 2021): 1392. http://dx.doi.org/10.3390/s21041392.

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Communication systems that work in jeopardized environments such as space are affected by soft errors that can cause malfunctions in the behavior of the circuits such as, for example, single event upsets (SEUs) or multiple bit upsets (MBUs). In order to avoid this erroneous functioning, this kind of systems are usually protected using redundant logic such as triple modular redundancy (TMR) or error correction codes (ECCs). After the implementation of the protected modules, the communication modules must be tested to assess the achieved reliability. These tests could be driven into accelerator facilities through ionization processes or they can be performed using fault injection tools based on software simulation such as the SEUs simulation tool (SST), or based on field-programmable gate array (FPGA) emulation like the one described in this work. In this paper, a tutorial for the setup of a fault injection emulation platform based on the Xilinx soft error mitigation (SEM) intellectual property (IP) controller is depicted step by step, showing a complete cycle. To illustrate this procedure, an online repository with a complete project and a step-by-step guide is provided, using as device under test a classical communication component such as a finite impulse response (FIR) filter. Finally, the integration of the automatic configuration memory error-injection (ACME) tool to speed up the fault injection process is explained in detail at the end of the paper.

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Han, Mangi, and Youngmin Kim. "Efficient Implementation of Multichannel FM and T-DMB Repeater in FPGA with Automatic Gain Controller." Electronics 8, no. 5 (April 29, 2019): 482. http://dx.doi.org/10.3390/electronics8050482.

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In this study, we implemented a high-performance multichannel repeater, both for FM and T-Digital Multimedia Broadcasting (DMB) signals using a Field Programmable Gate Array (FPGA). In a system for providing services using wireless communication, a radio-shaded area is inevitably generated due to various obstacles. Thus, an electronic device that receives weak or low-level signals and retransmits them at a higher level is crucial. In addition, parallel implementation of digital filters and gain controllers is necessary for a multichannel repeater. When power level is too low or too high, the repeater is required to compensate the power level and ensure a stable signal. However, analog- and software-based repeaters are expensive and they are difficult to install. They also cannot effectively process multichannel in parallel. The proposed system exploits various digital signal-processing algorithms, which include modulation, demodulation, Cascaded Integrator Comb (CIC) filters, Finite Impulse Response (FIR) filters, Interpolated Second Ordered Polynomials (ISOP) filters, and Automatic Gain Controllers (AGCs). The newly proposed AGC is more efficient than others in terms of computation amount and throughput. The designed digital circuit was implemented by using Verilog HDL, and tested using a Xilinx Kintex 7 device. As a result, the proposed repeater can simultaneously handle 40 FM channels and 6 DMB channels in parallel. Output power level is also always maintained by the AGC.

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Mohan Kumar, B. N., and H. G. Rangaraju. "Performance analysis of Low energy and highspeed DA-RNS based FIR filter design for SDR Applications on FPGA." International Journal of Circuits, Systems and Signal Processing 15 (July 22, 2021): 700–712. http://dx.doi.org/10.46300/9106.2021.15.78.

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For different applications, the Finite Impulse Response (FIR) filter is widely used in digital signal processing (DSP) applications. We exhibit a significant Residue Number System (RNS)-based FIR filter design for Software Defined Radio (SDR) filtration in this article. Including its underlying concurrency and information clustering process, the RNS provides important statistics over FIR application in specific. According to several residue computing and reverse translation, expanded bit size results in a significant performance trade-off, conversely. Through RNS replication, accompanied by conditional delay optimized reverse processing to minimize the FIR filter trade-off features with filter duration optimized Residue Number System arithmetic is proposed in this study, which involves distributed arithmetic-based residue processing. To execute the task of reverse translation and to store pre-computational properties, the suggested Residue Number System architecture makes use of built-in RAM blocks found in field-programmable gate array (FPGA) devices. The proposed FIR filter with core optimized RNS has the benefit of lowering processing latency delay while rising performance torque. Followed by FPGA hardware synthesis for different input word sizes and FIR lengths verification by the efficiency of the FIR filter core, fetal audio signal detection is performed first. The test results reveal that over the optimization procedure RNS method, a compromise in traditional RNS FIR over filter size is narrowed, as well as a substantial decrease in sophistication.

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P. S., Manjunath, Revanna C. R., Kusuma M. S., Ponduri Sivaprasad, and Uppala Ramakrishna. "Design and Performance Analysis of RNS-Based Reconfigurable FIR Filter for Noise Removal in Speech Signals Applications." WSEAS TRANSACTIONS ON SYSTEMS AND CONTROL 18 (June 16, 2023): 154–65. http://dx.doi.org/10.37394/23203.2023.18.16.

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In DSP solutions, the Residual Number System with Two's Complement systems is the most commonly utilized system for building low-power and high-throughput programmable Finite Impulse Response filters. It would be done by creating FIR filters in the Residual Number organization and 2's Enhance scheme by comparing the results to the current assert. The RNS based on FIR filter architecture reduces power consumption while allowing the device to operate at 150 MHz without increasing its size significantly. In case of memory and latency reduction, the implementations of the Residual Number System and 2's Complement System must be able to obtain and decode signals with fewer physical servers for every clock signal. The principal idea of this proposed model is to provide data bits with larger sizes for RNS-based multiplier and delayed wavelet LMS (DWLMS) that operates at speed high with premised reconfigurable FIR via forward and reverse conversions that don't produce as much power output and size as reflective thinking. The Application Specific Integrated Circuit will be designed and integrated for 32 nm technology. The proposed design addresses the four essential parameter optimization, such as power, area, and timing, using the Residual Number System, which is superior to Two's Complement System. According to the findings, there is a 13 percent reduction in power, a 21 % enhancement in area, and a 13 % enhance in throughput.

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24

Figuli, Shalina Percy Delicia, and Jürgen Becker. "An Efficient High-Throughput Generic QAM Transmitter with Scalable Spiral FIR Filter." Journal of Circuits, Systems and Computers 28, no. 01 (October 15, 2018): 1950015. http://dx.doi.org/10.1142/s0218126619500154.

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The need for efficient Finite Impulse Response (FIR) filters in high-speed applications such as telecommunications targets Field Programmable Gate Arrays (FPGAs) as an effective and flexible platform for digital implementation. Although FIR filter offers many advantages, its convolution nature poises a challenge in parallelization due to data dependency and computational complexity. To resolve this, we propose a novel FPGA-based reconfigurable filter architecture, which processes several data samples in parallel and breaks down data interdependency in a spiral fashion. Experimental results show a throughput of 7.2[Formula: see text]GSPS with an operating frequency of only 450[Formula: see text]MHz for a filter length of 11 with 16 parallel inputs. With parallelization of 4, it is 4.44 times faster than the state-of-the-art solution for a filter length of 16 and a promising 1.04[Formula: see text]GSPS throughput is achieved for a higher order of length 61. Incorporated into a generic Quadrature Amplitude Modulation (QAM) transmitter fitted with Forward Error Correction technique, a maximum throughput of 23[Formula: see text]Gb/s is achieved by the system for processing 16 input samples in parallel. In comparison to the state-of-the-art mixed domain approach, a threefold performance gain, while utilizing comparatively less Look-up Tables (LUTs), registers and DSP48 slices with an average gain factor of 43.3[Formula: see text], 4.7[Formula: see text] and 3.9[Formula: see text], respectively, is accomplished.

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Jameil, Ahmed K., Yassir A. Ahmed, and Saad Albawi. "Efficient FIR Filter Architecture using FPGA." Recent Advances in Computer Science and Communications 13, no. 1 (March 13, 2020): 91–98. http://dx.doi.org/10.2174/2213275912666190603115506.

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Background: Advance communication systems require new techniques for FIR filters with resource efficiency in terms of high performance and low power consumption. Lowcomplexity architectures are required by FIR filters for implementation in field programmable gate Arrays (FPGA). In addition, FIR filters in multistandard wireless communication systems must have low complexity and be reconfigurable. The coefficient multipliers of FIR filters are complicated. Objective: The implementation and application of high tap FIR filters by a partial product reduce this complexity. Thus, this article proposes a novel digital finite impulse response (FIR) filter architecture with FPGA. Method: The proposed technique FIR filter is based on a new architecture method and implemented using the Quartus II design suite manufactured by Altera. Also, the proposed architecture is coded in Verilog HDL and the code developed from the proposed architecture has been simulated using Modelsim. This efficient FIR filter architecture is based on the shift and add method. Efficient circuit techniques are used to further improve power and performance. In addition, the proposed architecture achieves better hardware requirements as multipliers are reduced. A 10-tap FIR filter is implemented on the proposed architecture. Results: The design’s example demonstrates a 25% reduction in resource usage compared to existing reconfigurable architectures with FPGA synthesis. In addition, the speed of the proposed architecture is 37% faster than the best performance of existing methods. Conclusion: The proposed architecture offers low power and improved speed with the lowcomplexity design that gives the best architecture FIR filter for both reconfigurable and fixed applications.

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Alhelal, Dheyaa, and Miad Faezipour. "Denoising and Beat Detection of ECG Signal by Using FPGA." International Journal of High Speed Electronics and Systems 26, no. 03 (June 27, 2017): 1740016. http://dx.doi.org/10.1142/s012915641740016x.

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This paper introduces an efficient digital system design using hardware concepts to filter the Electrocardiogram (ECG) signal and to detect QRS complex (beats). The system implementation has been done using a Field Programmable Gate Array (FPGA) in two phases. In the first phase, Finite Impule Response (FIR) filters are designed for preprocessing and denoising the ECG signal. The filtered signal is then used as the input of the second phase to detect and classify the ECG beats. The entire system has been implemented on ALTERA DE II FPGA by desinging synthesizable finite state machines. The design has been tested on ECG waves from the MIT-BIH Arrhythmia database by windowing the signal and applying adaptive signal and noise theresholds in each window of processing. The hardware system has achieved an overall accuracy of 98% in the beat detection phase, while providing the detected beats and the classification of irregular heat-beat rates in real-time. The synthesized hardware of the ECG denoising and beat detection system yields reasonable hardware resources, making the system attractive to be eventually fabricated as a stand alone hardware system or integrated/embedded within a portable electronic device for monitoring patients’ conditions on a daily basis conveinently.

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Murthy, C. Srinivasa, and K. Sridevi. "Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications." Circuit World 47, no. 3 (June 8, 2021): 252–61. http://dx.doi.org/10.1108/cw-11-2020-0332.

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Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

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Kim, K., and B. Shafai. "Finite impulse response estimator (FIRE)." IEEE Transactions on Signal Processing 43, no. 9 (1995): 2186–89. http://dx.doi.org/10.1109/78.414818.

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Nounou, Mohamed N. "Multiscale finite impulse response modeling." Engineering Applications of Artificial Intelligence 19, no. 3 (April 2006): 289–304. http://dx.doi.org/10.1016/j.engappai.2005.09.007.

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Kwon, Bo-Kyu, and Sang-Il Kim. "Adaptive Finite Impulse Response Filter." Transactions of the Korean Society of Mechanical Engineers - A 47, no. 4 (April 30, 2023): 303–11. http://dx.doi.org/10.3795/ksme-a.2023.47.4.303.

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31

Hillenbrand, James, and Robert A. Houde. "Comments on Finite Impulse Response Filters." Journal of Speech, Language, and Hearing Research 40, no. 2 (April 1997): 408–9. http://dx.doi.org/10.1044/jslhr.4002.408.

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32

Silveira, Paulo E. X., G. S. Pati, and Kelvin H. Wagner. "Optical finite impulse response neural networks." Applied Optics 41, no. 20 (July 10, 2002): 4162. http://dx.doi.org/10.1364/ao.41.004162.

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Mooney, Jon W. "Psychoacoustic limitations of discrete infinite impulse response and finite impulse response auralizations." Journal of the Acoustical Society of America 129, no. 4 (April 2011): 2390. http://dx.doi.org/10.1121/1.3587764.

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Li, Junfeng, Jian Zhang, Shuichi Sakamoto, Yoiti Suzuki, and Yonghong Yan. "An efficient finite-impulse-response filter model of head-related impulse response." Journal of the Acoustical Society of America 133, no. 5 (May 2013): 3515. http://dx.doi.org/10.1121/1.4806294.

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35

Skripniks, D., S. Sarkovskis, A. Yershov, and E. Grab. "Impulse response approximation of digital finite impulse response filter with delay line units." Automatic Control and Computer Sciences 51, no. 4 (July 2017): 279–84. http://dx.doi.org/10.3103/s0146411617040071.

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Bottegal, Giulio, Farhad Farokhi, and Iman Shames. "Preserving Privacy of Finite Impulse Response Systems." IEEE Control Systems Letters 1, no. 1 (July 2017): 128–33. http://dx.doi.org/10.1109/lcsys.2017.2709621.

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37

Zikic, A. M. "Finite impulse response adaptive self-tuning algorithm." Electronics Letters 32, no. 25 (1996): 2312. http://dx.doi.org/10.1049/el:19961560.

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38

Vollmerhausen, Richard. "Design of finite impulse response deconvolution filters." Applied Optics 49, no. 30 (October 15, 2010): 5814. http://dx.doi.org/10.1364/ao.49.005814.

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Zhou, Ying, Guangjie Zeng, Feihong Yu, and H. S. Kwok. "Study on optical finite impulse response filter." Optical Engineering 42, no. 8 (2003): 2318. http://dx.doi.org/10.1117/1.1586289.

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40

Rajatheva, N., and E. Shwedyk. "Distance properties of finite-impulse response channels." IEEE Transactions on Communications 48, no. 9 (2000): 1429–31. http://dx.doi.org/10.1109/26.870003.

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41

Kirk Bailey, J. "Process identification using finite impulse response models." Journal of Process Control 5, no. 2 (April 1995): 77–84. http://dx.doi.org/10.1016/0959-1524(95)90343-d.

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42

Fursov, V. A., and S. A. Bibikov. "Finite Impulse Response Filter with Square-Exponential Frequency Response." Pattern Recognition and Image Analysis 29, no. 2 (April 2019): 284–95. http://dx.doi.org/10.1134/s1054661819020081.

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43

Mohapatra, Badri Narayan, and Rashmita Kumari Mohapatra. "Performance Analysis on Frequency Response of Finite Impulse Response Filter." Procedia Computer Science 79 (2016): 729–36. http://dx.doi.org/10.1016/j.procs.2016.03.096.

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44

Gawthrop, Peter J., and Liuping Wang. "INFINITE-IMPULSE AND FINITE-IMPULSE RESPONSE FILTERS FOR CONTINUOUS-TIME PARAMETER ESTIMATION." IFAC Proceedings Volumes 35, no. 1 (2002): 121–26. http://dx.doi.org/10.3182/20020721-6-es-1901.01006.

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Stojanovic, Vidosav, and Sinisa Minic. "Finite impulse response digital filters with integer multipliers." Serbian Journal of Electrical Engineering 1, no. 1 (2003): 131–41. http://dx.doi.org/10.2298/sjee0301131s.

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In this paper, a family of non-recursive digital filters will be described in which all multipliers are small integers. It is shown that this practical advantage is only available if some rather severe restrictions on the locations of z-plane poles and zeros are accepted. These restrictions have the further advantage that all filters of the family display pure linear-phase characteristics, imposing a pure transmission delay on all frequency components of an input signal.

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46

Berggren, M., S. Caiazza, M. Chera, and J. List. "Kinematic edge detection using finite impulse response filters." Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment 1010 (September 2021): 165555. http://dx.doi.org/10.1016/j.nima.2021.165555.

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47

Melinda, Melinda, Syahrial, Yunidar, Al Bahri, and Muhammad Irhamsyah. "Finite Impulse Response Filter for Electroencephalogram Waves Detection." Green Intelligent Systems and Applications 2, no. 1 (April 7, 2022): 7–19. http://dx.doi.org/10.53623/gisa.v2i1.65.

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Electroencephalographic data signals consist of electrical signal activity with several characteristics, such as non-periodic patterns and small voltage amplitudes that can mix with noise making it difficult to recognize. This study uses several types of EEG wave signals, namely Delta, Alpha, Beta, and Gamma. The method we use in this study is the application of an impulse response filter to replace the noise obtained before and after the FIR filter is applied. In addition, we also analyzed the quality of several types of electroencephalographic signal waves by looking at the addition of the signal to noise ratio value. In the end, the results we get after applying the filter, the noise that occurs in some types of waves shows better results.

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48

Guilar, N. J., F. Lau, P. J. Hurst, and S. H. Lewis. "A Passive Switched-Capacitor Finite-Impulse-Response Equalizer." IEEE Journal of Solid-State Circuits 42, no. 2 (February 2007): 400–409. http://dx.doi.org/10.1109/jssc.2006.889378.

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Levantino, S., M. Milani, C. Samori, and A. L. Lacaita. "Fast-Switching Analog PLL With Finite-Impulse Response." IEEE Transactions on Circuits and Systems I: Regular Papers 51, no. 9 (September 2004): 1697–701. http://dx.doi.org/10.1109/tcsi.2004.834519.

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50

Wilkinson, Robert H. "High-fidelity low-pass finite-impulse-response filters." Journal of Guidance, Control, and Dynamics 12, no. 3 (May 1989): 412–20. http://dx.doi.org/10.2514/3.20423.

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