Dissertations / Theses on the topic 'Programmable controllers Design and construction'

The use of embedded Internet systems is growing rapidly in the manufacturing sector. These systems allow the monitoring and controlling of plant machinery and manufactured items from a remote location via a standard Web interface. In a manufacturing environment, it is inevitable that long running processes will require support for dynamic reconfiguration because, for example, machines may fail, services may be moved or withdrawn and user requirements may change. In such an environment it is essential that the operation and architecture of such processes can be modified to reflect such changes. This research project will present methods and ideas for establishing a reconfigurable remote system by using standard 8-bit microcontrollers and reconfigurable hardware. It will allow a manufacturing process to be modified and changed within minutes without even having to be physically present at the location where the process is running.

Water scarcity for agriculture is one of the most important challenges to improve food security worldwide. In this thesis we study the potential to develop a low-cost controller for a small scale brackish desalination plant that consists of proven water treatment technologies, reverse osmosis, cation exchange, and nanofiltration to treat groundwater into two final products: drinking water and irrigation water. The plant is powered by a combination of wind and solar power systems. The low-cost controller uses Arduino Mega, and Arduino DUE, which consist of ATmega2560 and Atmel SAM3X8E ARM Cortex-M3 CPU microcontrollers. These are widely used systems characterized for good performance and low cost. However, Arduino also requires drivers and interfaces to allow the control and monitoring of sensors and actuators. The thesis explains the process, as well as the hardware and software implemented.

Thesis (MTech (Electrical Engineering))--Cape Peninsula University of Technology, 2014.
The application of digital control techniques has become dominant in power electronics owing to several advantages they present, when compared to analogue solutions. Their development is based on the use of microprocessors and microcontrollers, such as Application Specific Integrated Circuit (ASIC), Digital signal processors (DSP), Field Programmable Gate Arrays (FPGA), or a combination of these devices. This thesis presents an investigation of a soft-core based FPGA control system as a solution for power electronic applications. The aim was the development and implementation of a conversion controller, which purpose is to supply control inputs in the form of digital Pulse Width Modulation (PWM) signals, to a number of power electronic applications, such as single half and full bridge DC-DC converters, three phase and multicell inverters. The PWM control technique is achieved via their power semiconductor switching devices. These PWM control signals are necessary for the high frequency conversion of an analog input voltage (AC, DC or unregulated) to an analog output voltage of another level (AC or DC). This was intended to be achieved by exploiting and combining the advantages that FPGA and embedded processors provide such as high reconfigurability and multipurpose ability. This controller’s digital outputs, namely PWM switching signals, can be directly delivered to an analog signal amplification circuit to create an adequate voltage level before being processed by the converters’ switches.

Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2002.
Includes bibliographical references (leaves 111-112). Also available in electronic version. Access restricted to campus users.

Thesis (Ed. D.)--Illinois State University, 1989.
Title from title page screen, viewed November 1, 2005. Dissertation Committee: Dent M. Rhodes (chair), Franzie L. Loepp, Walter D. Pierce, Henry L. Thomas. Includes bibliographical references (leaves 248-260) and abstract. Also available in print.

This thesis project presents the T-Sticks, a new family of digital musical instruments (DMIs). Most DMIs are either entirely unique interfaces, or exist as design iterations in which each incarnation is intended to improve on the last. The T-Sticks are instead intended to form a complementary group or consort which may be performed ensemble and also performed individually in solo pieces or works for mixed instrumentation. Each of the T-Sticks is based on the same general structure and sensing platform, but each also differs from its siblings in size, weight, timbre and register.
This document explores some of the issues challenging and motivating the field of DMI design and performance, and describes the motivations behind the T-Stick project in this context. Several existing DMIs are examined for similarities to the T-Stick and compared in terms of design intention, implementation, and usage. The hardware and software designed and built for this project is presented, along with insights gained through collaboration with performers and composers in the context of McGill University's Digital Orchestra project. The performers in question have collectively practiced and performed with the T-Stick for hundreds of hours in the lab, practice room, and on the concert stage. The consort of T-Sticks will be featured as an ensemble in a piece to be performed during the 2008 MusiMarch festival in Montreal.

The Programmable Logic Devices, PLO, have caused a major impact in logic design of digital systems in this decade. For instance, a twenty pin PLO device can replace from three hundreds to six hundreds Transistor Transistor Logic gates, which people have designed with since the 60s. Therefore, by using PLD devices, designers can squeeze more features, reduce chip counts, reduce power consumption, and enhance the reliability of the digital systems. This thesis covers the most important aspects of logic design using PLD devices. They are Logic Minimization and State Assignment. In addition, the thesis also covers a seldomly used but very useful design style, Self-Synchronized Circuits. The thesis introduces a new method to minimize Two-Level Boolean Functions using Graph Coloring Algorithms and the result is very encouraging. The raw speed of the coloring algorithms is as fast as the Espresso, the industry standard minimizer from Berkeley, and the solution is equally good. The thesis also introduces a rule-based state assignment method which gives equal or better solutions than STASH (an Intel Automatic CAD tool) by as much as twenty percent. One of the problems with Self-Synchronized circuits is that it takes many extra components to implement the circuit. The thesis shows how it can be designed using PLD devices and also suggests the idea of a Clock Chip to reduce the chip count to make the design style more attractive.

A microcomputer-based process controller has been developed to produce porous membrane material. The production process is based on stretching the material in a constant temperature solvent bath. This thesis describes the hardware and software designed to direct and monitor the process. A VIC 20 is used as the process-controlling microcomputer. The system features two dedicated motor controllers and two channels for controlling temperature. The motor controllers determine the material feed rate and rate of stretch. The temperature controllers keep the system at a selectable constant temperature. An interactive assembly language program directs the entire process and monitors the controlled variables. A complete description of the interface and temperature control circuitry is given. The software used to direct the process is also discussed and presented.
Master of Science

Thesis (MTech (Electrical Engineering))--Peninsula Technikon, 2002
This research outlines the development and design of an infrared radiation heating profile controller. The study includes both the theoretical aspects of the design process as well as giving an overview of the practical facets involved. The controller was subjected to comparative testing with a proportional control model, in order to observe its performance and validate its effectiveness. A need exists for these types of controllers and proved to be the motivation to embark on this investigation. Controllers of this nature that are commercially available either lacks the functionality of this unit or are too expensive to implement for research purposes. This unit was designed with cost effectiveness in mind but still meet the standards required of an industrial style controller. To this end the construction was completed using low cost and affordable electronic components. Heating profiles are necessary and useful tools for the proper processing of a host of materials. The controller developed in this research is able to within a fair degree of accuracy track a heating profile. The results confirm that this programmable control model to be a benefit and a valuable tool in temperature regulation. This means that intensive studies into the effects of infrared radiation on materials are now feasible. Research of this nature could possibly expand the application of infrared as a heating mechanism. Although tests were conducted on this controller, they are not meant to serve as an exhaustive analysis. The conclusions of these examinations do reveal the benefit of such a controller. More rigorous investigation is suggested as a subject for further study.

Thesis (Ph.D)--Electrical and Computer Engineering, Georgia Institute of Technology, 2010.
Committee Chair: David V Anderson; Committee Co-Chair: Sung Kyu Lim; Committee Member: Aaron Lanterman; Committee Member: Abhijit Chatterjee; Committee Member: Daniel Foty; Committee Member: Paul Hasler. Part of the SMARTech Electronic Thesis and Dissertation Collection.

Most existing computers today are built upon a subset of the arithmetic system which is based upon the foundation of set theory. All formal systems can be expressed in terms of arithmetic and logic on current arithmetic computers through an appropriate model, then work with the model using software manipulation. However, severe speed degradation is the price one must pay for using a software-based approach, making several high-level formal systems impractical. To improve the speed at which computers can implement these high-level systems, one must either design special hardware, implementing specific operations much like math and image processing coprocessors, or execute operations upon multiple processors in a parallel fashion. Due to the increase in developing applications for the manipulation of logic functions, an interest in the logic machine has arisen. Many applications such as logic optimization, simulation, pattern recognition and image processing can be better implemented with a logic machine. This thesis proposes the design, hardware realization, and testing of the iterative logic unit (ILU) of the Cube Calculus Machine II (CCM2). The CCM2 is a general purpose computer with an architecture that emphasizes a data path designed to execute operations of cube calculus, a popular algebraic model used in the minimization of Boolean functions. The ILU is an iterative logic array of cells (ITs) using internal distributed control, enabling the execution of basic cube operations, while the Control Unit (CU) handles global signals from the host computer. The ILU of the CCM2 has been realized in hardware using Xilinx Logic Cell Arrays (LCAs). FPGAs offer the logic density and versatility of gate arrays, with the off-the shelf availability and time-to-market advantages of standard user-programmable devices. These devices can be reconfigured, allowing multiple revisions and future design generations to accommodate the same device, thus saving design and production costs, an ideal solution to the resource and financial problems plaguing the University environment.

Thesis (Ph. D.)--Electrical and Computer Engineering, Georgia Institute of Technology, 2005. Directed by David Anderson.
Prvulovic, Milos, Committee Member ; Citrin, David, Committee Member ; Lanterman, Aaron, Committee Member ; Yalamanchili, Sudhakar, Committee Member ; Hasler, Paul, Committee Member ; Anderson, David, Committee Chair. Includes bibliographical references.

This research presents a solution to the problem of tuning a PID controller for a nonlinear system. Many systems in industrial applications use a PID controller to control a plant or the process. Conventional PID controllers work in linear systems but are less effective when the plant or the process is nonlinear because PID controllers cannot adapt the gain parameters as needed. In this research we design a Nonlinear PID (NPID) controller using a fuzzy logic system based on the Mamdani type Fuzzy Inference System to control three different DC motor systems. This fuzzy system is responsible for adapting the gain parameters of a conventional PID controller. This fuzzy system's rule base was heuristically evolved using an Evolutionary Algorithm (Differential Evolution). Our results show that a NPID controller can restore a moderately or a heavily under-damped DC motor system under consideration to a desired behavior (slightly under-damped).

The Programmable Logic Array (PLA) has been widely used in the design of VLSI circuits and systems because of its regularity, flexibility, and simplicity. The equivalence problem is typically to verify that the final description of a circuit is functionally equivalent to its initial description. Verifying the functional equivalence of two descriptions is equivalent to proving their logical equivalence. This problem of pure logic is essential to circuit design. The most widely used technique to solve the problem is based on Binary Decision Diagram or BDD, proposed by Bryant in 1986. Unfortunately, BDD requires too much time and space to represent moderately large circuits for equivalence testing. We design and implement a new algorithm called the Cover-Merge Algorithm for the equivalence problem based on a divide-and-conquer strategy using the concept of cover and a derivational method. We prove that the algorithm is sound and complete. Because of the NP-completeness of the problem, we emphasize simplifications to reduce the search space or to avoid redundant computations. Simplification techniques are incorporated into the algorithm as an essential part to speed up the the derivation process. Two different sets of heuristics are developed for two opposite goals: one for the proof of equivalence and the other for its disproof. Experiments on a large scale of data have shown that big speed-ups can be achieved by prioritizing the heuristics and by choosing the most favorable one at each iteration of the Algorithm. Results are compared with those for BDD on standard benchmark problems as well as on random PLAs to perform an unbiased way of testing algorithms. It has been shown that the Cover-Merge Algorithm outperforms BDD in nearly all problem instances in terms of time and space. The algorithm has demonstrated fairly stabilized and practical performances especially for big PLAs under a wide range of conditions, while BDD shows poor performance because of its memory greedy representation scheme without adequate simplification.

The thesis presents a new approach to the decomposition of incompletely specified functions and its application to FPGA (Field Programmable Gate Array) mapping. Five methods: Variable Partitioning, Graph Coloring, Bond Set Encoding, CLB Reusing and Local Transformation are developed in order to efficiently perform decomposition and FPGA (Lookup-Table based FPGA) mapping. 1) Variable Partitioning is a high quality hemistic method used to find the "best" partitions, avoiding the very time consuming testing of all possible decomposition charts, which is impractical when there are many input variables in the input function. 2) Graph Coloring is another high quality heuristic\ used to perform the quasi-optimum don't care assignment, making the program possible to accept incompletely specified function and perform a quasi-optimum assignment to the unspecified part of the function. 3) Bond Set Encoding algorithm is used to simplify the decomposed blocks during the process of decomposition. 4) CLB Reusing algorithm is used to reduce the number of CLBs used in the final mapped circuit. 5) Local Transformation concept is introduced to transform nondecomposable functions into decomposable ones, thus making it possible to apply decomposition method to FPGA mapping. All the above developed methods are incorporated into a program named TRADE, which performs global optimization over the input functions. While most of the existing methods recursively perform local optimization over some kinds of network-like graphs, and few of them can handle incompletely specified functions. Cube calculus is used in the TRADE program, the operations are global and very fast. A short description of the TRADE program and the evaluation of the results are provided at the_ end of the thesis. For many benchmarks the TRADE program gives better results than any program published in the literature.

Thesis (D. Tech. (Engineering: Electrical)) -- Central University of technology, Free State, 2012
This thesis describes a method for the automatic generation of appli- cation speci_c processors. The thesis was organized into three sepa- rate but interrelated studies, which together provide: a justi_cation for the method used, a theory that supports the method, and a soft- ware application that realizes the method. The _rst study looked at how modern day microprocessors utilize their hardware resources and it proposed a metric, called core density, for measuring the utilization rate. The core density is a function of the microprocessor's instruction set and the application scheduled to run on that microprocessor. This study concluded that modern day microprocessors use their resources very ine_ciently and proposed the use of subset processors to exe- cute the same applications more e_ciently. The second study sought to provide a theoretical framework for the use of subset processors by developing a generic formal model of computer architecture. To demonstrate the model's versatility, it was used to describe a number of computer architecture components and entire computing systems. The third study describes the development of a set of software tools that enable the automatic generation of application speci_c proces- sors. The FiT toolkit automatically generates a unique Hardware Description Language (HDL) description of a processor based on an application binary _le and a parameterizable template of a generic mi- croprocessor. Area-optimized and performance-optimized custom soft processors were generated using the FiT toolkit and the utilization of the hardware resources by the custom soft processors was character- ized. The FiT toolkit was combined with an ANSI C compiler and a third-party tool for programming _eld-programmable gate arrays (FPGAs) to create an unconstrained C-to-silicon compiler.

Dans la méthode de conception sûre et descendante CAPRI applicable aux circuits intégrés VLSI, on analyse les spécifications initiales à la définition de l'architecture du circuit. La méthode proposée est une méthode par affinements successifs de spécifications dans laquelle on distingue: 1) le choix des algorithmes; 2) le choix du chemin de données associé aux blocs fonctionnels; 3) le choix de la structure de la partie contrôle. Application de la démarche descendante au microordinateur 80 C48 d'INTEL en technologie CMOS

In real-time control systems, the value of a control decision depends not only on the correctness of the decision but also on the time when that decision is available. Recent work in real-time decision making has used machine learning techniques to automatically construct reactive controllers, that is, controllers with little or no internal state and low time complexity pathways between sensors and effectors. This paper presents research on 1) how a problem representation affects the trade-offs between space and performance, and 2) off -line versus on-line approaches for collecting training examples when using machine learning techniques to construct reactive controllers. Empirical results show that for a partially observable problem both the inclusion of history information in the problem representation and the use of on-line rather than off -line learning can improve the performance of the reactive controller.
Graduation date: 1994

M. Tech. Electrical Engineering.
Discusses how to develop the kinematic and dynamic model and the controller for the 2-DOf motion platform used in an augmented reality environment for wheelchair driving. This comes as a motivation to help to train disabled and elderly people to drive wheelchairs.. With accurate inverse dynamic model, it is possible to achieve high performance control algorithms of robots and direct dynamic model is required for their simulation. The other part of this research was to model and control the roller for the feedback of the wheelchair wheels.

碩士
國防大學理工學院
電子工程碩士班
106
In recent years, people began to pay attention to environmental issues, hybrid vehicles have become the focus of research themes. However, most of the researches only discuss the optimal power distribution while vehicles driving on a general road, that the road slope is 0 degree, but ignoring the traffic conditions or slope load. In view of the fact that the vehicle may face the slope path when driving, this paper aims to develop a small hybrid vehicle system and design an optimal power strategy in particular against the slope resistance that has not been discussed yet. In additions, in response to the real traffic situation in Taiwan, we chose to use a commonly used motorcycle engine as the main research object, and planned a parallel-type platform of the hybrid electric vehicle (HEV) to benefit the hardware testing of the system. In term of our hybrid system, we not only integrated the continuously variable transmission (CVT) of the Scooter and the hub motor of the electric motorcycle, but also additionally set up the magnetic powder brake to provide the attached braking torque as the source of vehicle load to assist in exploring the characteristics of the system when the vehicle is driving on the abrupt slope. Besides, in view of the inevitable slope disturbances of the vehicle, this study applied the high-efficiency operation performance of the hybrid CVT and the low-speed but high-efficiency torque output of the electric motor to help develop the strategies of the power splitting mechanism for kinetic energy control. Afterward the power splitting mechanism of the system platform could timely switch the power source to supply the vehicle for climbing power. In addition, this design could overcome the high fuel consumption caused by the slope road, and also avoid the unnecessary load and wear produced from the unused power source when operator only uses the other single power source. Finally, this study also discussed the optimal timing for planning and switching the hybrid mode. Therefore, the design in this study can avoid vehicles hesitations frequently caused by the improper power matching, and then reduce the damage probability of the system components. Moreover, it can improve the quality and comfort of the vehicle driving.

Thesis (M.Sc.)--York University, 2006. Graduate Programme in Computer Science.
Typescript. Includes bibliographical references (leaves 128-137). Also available on the Internet. MODE OF ACCESS via web browser by entering the following URL: http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&res_dat=xri:pqdiss&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&rft_dat=xri:pqdiss:MR29550

Zhou Lin.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2004.
Includes bibliographical references (leaves 50-53).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Aims and Contribution --- p.3
Chapter 1.3 --- Thesis Overview --- p.4
Chapter 2 --- Field-Programmable Gate Array and Routing Algorithm in VPR --- p.6
Chapter 2.1 --- Commercially Available FPGAs --- p.6
Chapter 2.2 --- FPGA Logic Block Architecture --- p.7
Chapter 2.2.1 --- Logic Block Functionality vs. FPGA Area-Efficiency --- p.7
Chapter 2.2.2 --- Logic Block Functionality vs. FPGA Delay-Performance --- p.7
Chapter 2.2.3 --- Lookup Table-Based FPGAs --- p.8
Chapter 2.3 --- FPGA Routing Architecture --- p.8
Chapter 2.4 --- Design Parameters of FPGA Routing Architecture --- p.10
Chapter 2.5 --- CAD for FPGAs --- p.10
Chapter 2.5.1 --- Synthesis and Logic Block Packing --- p.11
Chapter 2.5.2 --- Placement --- p.11
Chapter 2.5.3 --- Routing --- p.12
Chapter 2.5.4 --- Delay Modelling --- p.13
Chapter 2.5.5 --- Timing Analysis --- p.13
Chapter 2.6 --- FPGA Programming Technologies --- p.13
Chapter 2.7 --- Routing Algorithm in VPR --- p.14
Chapter 2.7.1 --- Pathfinder Negotiated Congestion Algorithm --- p.14
Chapter 2.7.2 --- Routing Algorithm Used by VPR --- p.16
Chapter 3 --- Connection-Switch Box Design --- p.17
Chapter 3.1 --- Introduction --- p.17
Chapter 3.2 --- Connection-Switch Box Design Algorithm --- p.19
Chapter 3.2.1 --- Connection between Logic Pins and Tracks --- p.20
Chapter 3.2.2 --- Connection between Pad Pins and Tracks --- p.25
Chapter 3.3 --- Switch Number Comparisons --- p.26
Chapter 3.4 --- Experimental Results --- p.29
Chapter 3.5 --- Summary --- p.32
Chapter 4 --- Optimal MST-Based Graph Algorithm on FPGA Segmenta- tion Design --- p.37
Chapter 4.1 --- Introduction --- p.37
Chapter 4.2 --- MST-Based Graph Algorithm on FPGA Channel Segmentation Design --- p.39
Chapter 4.2.1 --- Net Merging Problem of Row-Based FPGAs --- p.41
Chapter 4.2.2 --- Extended Net Merging Problem of Symmetrical Array FPGAs --- p.44
Chapter 4.3 --- Experimental Results --- p.46
Chapter 4.4 --- Summary --- p.46
Chapter 5 --- Conclusions --- p.48
Bibliography --- p.50

M.Ing.
This thesis describes a full design project of a processor based sophisticated measurement instrument - the datalogger. It covers the theoretical approach to the design project followed with hardware and software design. Many nonstandard solutions in hardware and software parts are used to approach a target, and they are fully described. The world that surrounds us today is full of products based on science and technology knowledge. These products are part of everyday life. The development of science and technology is very much depend upon a parallel development of measurement techniques and instruments. Measurement and the technology of measurement called instrumentation, serves not only science but all branches of engineering, medicine and almost every sphere of human life. Measuring instruments are used in the monitoring and control of processes and operations, too. Most specialised instruments, such as the datalogger, are used in experimental, research and develop science and engineering work. This thesis is organised into six chapters. The dataloger position in the measurement instruments tree is shown in the first chapter. The electronics design philosophy follows in the next chapter. It covers the most common problems found when the new design project starts. The global design strategy with brief description of all steps follows. The second chapter contains the datalogger project history, the reasons for going into the project, and the requests of the new device, too. At the end of this chapter the basic work principle of the datalogger is described to allow an easily following applied solutions. The third chapter covers all datalogger design specialities that make the datalogger design different from the design of other measurement instruments. It starts with remote sensors problems and problems commonly connected to the input stage of similar systems. The second half of this chapter analyses the instrument precision and error sources. There are several different methods that precision can be increased. Two methods applied here, reducing measurement range and oversampling with noise, are briefly described. The forth chapter interpretates the design of the processor board. It starts with a general microcontroller overview, describing the reasons for selecting the Hitachi microcontroller H8/532. The most important microcontroller characteristics are shown, too. The second part of this chapter contains the organisation, connections and contents of other electronics blocks in the processor board. At the end of this chapter the processor board schematic and full characteristics are given. The datalogger's hardware is described in the fifth chapter. The basic work principles of the various hardware parts are given in the beginning. The hardware is broken down and described in the following way: power electronics, digital control, signal processing part, and interface cards. All parts are covered with detailed descriptions of design circuit and the following calculation. The last chapter shows the software for the datalogger. It starts with the mathematical calculation principle developed and used in the datalogger. The customer part which follows covers software and hardware part relation between user and datalogger. One of the datalogger's software speciality is organisation of RAM space which allows high software flexibility of the datalogger as a measurement instrument. At the end the full datalogger program organisation is given on a global level.

Chau, Chun Pong.
"August 2010."
Thesis (M.Phil.)--Chinese University of Hong Kong, 2010.
Includes bibliographical references (leaves 67-71).
Abstracts in English and Chinese.
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Objectives --- p.4
Chapter 1.3 --- Contribution --- p.4
Chapter 1.4 --- Thesis Organization --- p.5
Chapter 2 --- Background and Review --- p.6
Chapter 2.1 --- Introduction --- p.6
Chapter 2.2 --- Logic Cell Style and Mask Programmability --- p.6
Chapter 2.3 --- CAD Tools Compatibility --- p.8
Chapter 2.4 --- Summary --- p.9
Chapter 3 --- Architectural Design --- p.11
Chapter 3.1 --- Overview --- p.11
Chapter 3.2 --- Programmable Layers --- p.12
Chapter 3.3 --- Combinational Logics --- p.12
Chapter 3.4 --- Sequential Logics --- p.19
Chapter 3.5 --- Inter-cell Connections --- p.21
Chapter 3.6 --- Hard Macros --- p.22
Chapter 3.7 --- Summary --- p.22
Chapter 4 --- Design Flow --- p.23
Chapter 4.1 --- Overview --- p.23
Chapter 4.2 --- Library Creation --- p.24
Chapter 4.3 --- Synthesis --- p.30
Chapter 4.4 --- Placement and Routing --- p.30
Chapter 4.5 --- Static Timing Analysis --- p.34
Chapter 4.6 --- Summary --- p.35
Chapter 5 --- Experimental Results --- p.36
Chapter 5.1 --- Benchmark Circuits Description --- p.36
Chapter 5.2 --- Experiment Settings --- p.37
Chapter 5.3 --- Ratio of Dedicated Elements --- p.42
Chapter 5.4 --- Delay and Area Comparison --- p.49
Chapter 5.5 --- Distributed Memories --- p.53
Chapter 5.6 --- Summary --- p.54
Chapter 6 --- Prototypes and Applications --- p.55
Chapter 6.1 --- Overview --- p.55
Chapter 6.2 --- First Prototype --- p.55
Chapter 6.3 --- Second Prototype --- p.63
Chapter 7 --- Conclusion --- p.65
Chapter 7.1 --- Future Work --- p.66
Chapter 7.2 --- Concluding Remark --- p.67

by Lo Wing-yee.
Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.
Includes bibliographical references (leaves vii-ix).
ABSTRACT --- p.i
LIST OF TABLES --- p.iv
LIST OF FIGURES --- p.v
Chapter 1. --- INTRODUCTION --- p.1
Chapter 1.1 --- Traditional Design Prototyping --- p.1
Chapter 1.2 --- In-Circuit Rapid Prototyping System --- p.2
Chapter 1.3 --- A Summary of Prototyping Systems Available --- p.5
Chapter 1.4 --- Universal Prototyping Board (UPB) --- p.6
Chapter 2. --- HARDWARE DESIGNS --- p.9
Chapter 2.1 --- Bus Interconnection --- p.9
Chapter 2.1.1 --- Fixed buses --- p.9
Chapter 2.1.2 --- Programmable buses --- p.12
Chapter 2.2 --- Architectural Features --- p.15
Chapter 2.2.1 --- Field programmable gate array --- p.15
Chapter 2.2.2 --- Microprocessor --- p.15
Chapter 2.2.3 --- Memory --- p.16
Chapter 2.2.4 --- Buffers --- p.18
Chapter 3. --- SOFTWARE TOOLS --- p.20
Chapter 3.1 --- Critical Path Analysis --- p.20
Chapter 3.1.1 --- Algorithm of critical path analysis --- p.21
Chapter 3.1.2 --- Computation time --- p.21
Chapter 3.2 --- Circuit Partitioning --- p.23
Chapter 3.2.1 --- Partitioning algorithm --- p.24
Chapter 3.2.2 --- Effects of partitioning --- p.36
Chapter 3.2.3 --- Partitioning parameters --- p.38
Chapter 3.2.4 --- Pseudo-code of partitioner --- p.39
Chapter 3.3 --- IO Assignments --- p.40
Chapter 3.3.1 --- Connect 4 FPGAs --- p.40
Chapter 3.3.2 --- Connect 3 FPGAs --- p.42
Chapter 3.3.3 --- Connect 2 FPGAs --- p.44
Chapter 3.3.4 --- System IO (Connect 1 FPGA) --- p.47
Chapter 3.4 --- Other Tools --- p.48
Chapter 4. --- STRUCTURE ANALYSIS --- p.49
Chapter 5. --- RESULTS --- p.52
Chapter 6. --- FUTURE DIRECTION --- p.73
Chapter 6.1 --- Other Possible Configurations --- p.73
Chapter 6.2 --- Programmable Interconnection --- p.73
Chapter 6.3 --- Expandability of UPB --- p.74
Chapter 7. --- CONCLUSION --- p.75
BIBLIOGRAPHY --- p.vii
APPENDICES --- p.x

隨著半導體生產工藝的特徵尺寸日益縮小，工藝變化引起的良率損失亦日益顯著。在現場可編程門陣列平臺，一些優化設計方法根據芯片的特定的工藝變化特徵來優化設計以提高時序良率。然而，目前缺乏一種實際的工藝變化特徵提取方法以支持上述優化設計方法。為了滿足這一需求，在文論文的第一部份，我們提出利用環形振盪器來提取商用現場可編程門陣列芯片的工藝變化特徵。該方法可以提取到邏輯單元級別的時序特徵，并進而推測出互聯電路的時序特徵。為了證明該方法的有效性我們在現場可編程門陣列芯片上任意放置兩個結構完全相同的環形振盪器于不同的位置。我們分別通過直接測量和通過分析特徵提取的數據得到兩振盪器的時序差異。對比結果顯示通過分析特徵提取數據，推算結果和實際測量結果僅平均相差10% 以內。我們在Xilinx 公司的Spartan-3e 芯片上實現了該方法，別且在其他Xilinx 的芯片上同樣適用。
在本論文的第二部份，我們提出一種利用現場可編程門陣列架構對稱性的方法來系統化的改變設計道路。通過對一個初始設計電路的旋轉和翻轉，我們可以得到八種時序性能相同的候選設計。在隨機工藝變化的存在下，八種候選設計的任何一個都有同樣的可能性被選為針對某一特定芯片的最優設計。如果大批芯片的單一個體都可以確定最優設計，整體性能將大幅度改善。另外，我們提出交換關鍵路徑上的相鄰邏輯單元來進一步提高時序性能通過對二十個測試電路的仿真實驗，我們發現統計時序性能得到了大幅度改善。相比于其他改善時序性能的方法，該方法從設計時間的角度來看更有效率。
雖然工藝變換常被認為一種有害的寄生效應，但是它提供了一些應用前景。物理費克隆方程的提出啟發研究人員把芯片的工藝變化的唯一性轉化為芯片的數字身份。在本論文的第三部份，我們提出利用環形振盪器陣列來測量工藝變化，并通過比較振盪器的相對速度來計算芯片數字身份。然而，芯片身份的穩定性是一個普遍的問題，尤其是在考慮到工作環境(如溫度、這墨)改變的情況下。為了解決這一間包我們提出結合使用可配置的環形振盪器以及重新初始化的方法來提高穩定性。改方法同樣在Xilinx 的Spartan-3e 芯片上實現。實驗結果表明該方法大幅度提高了在工作環境變化下芯片身份的穩定性。
As semiconductor manufacturing continues towards reduced feature size, yield loss induced by process variation becomes increasingly significant. On the platform of field programmable field array (FPGA), several works proposed to improve timing yield by optimizing design implementation based on chip-specific variation distribution, which are generally defined as variation aware design (VAD) methods. However, there is a lack of practical variation characterization method to facilitate the invented VAD methods. To fulfill this demand, in the first part of this thesis, we proposed to characterize delay variation by measuring the loop delay of ring oscillator (RO) on commercial FPGAs. By comparing the difference of loop delays for ROs with slightly different structures, the logic element (LE) delay can be explicitly characterized. The delays of interconnect circuits can be further derived with existing LE delay information and additional measurements. To evaluate the effectiveness of the proposed variation characterization, two ROs with identical structure are arbitrarily placed at different locations on an FPGA chip. The difference of the loop delays between two ROs can be both directly measured and estimated by characterization results. Taking measurement results as references, the error rate of estimation by characterization results is less than 10% on average. The proposed characterization method is implemented on Xilinx Spartan-3e FPGA chips. Without loss of generality, the proposed method can be also adopted on other Xilinx FPGA devices.
In the second part of this thesis, we proposed to systematically manipulates FPGA post-layout circuits by using FPGA architectural symmetry. Eight timing equivalent “candidate configurations“ can be obtained by rotating and flipping an initial configuration. In presence of random process variation, any of them has equal opportunity to be selected as the optimal implementation for a specific FPGA chip. If each individual from a large number of FPGAs is applied with the optimal among all candidate configurations, the overall timing performance is evidently improved compared to applying a single configuration to those FPGAs. Furthermore, the technique of LE swapping makes faster one of two neighboring LEs occupied by critical paths, which guarantees an incremental timing performance improvement based on any optimized design. Twenty MCNC benchmark circuitsare placed and routed by VPR [12]. Statistical timing performance is obtained by Monte-Carlo simulation with FPGA process variation model. The experimental results demonstrate evident timing yield improvement. Compared to previous VAD works, the proposed method saves the effort of variation characterization and design time.
Although process variation is always stated as a side-effect, it still offers some opportunities for variation-based applications. The invention of physically unclonable function (PUF) enlightens the researchers to translate physical uniqueness to digital identification. In the third part of this thesis, a compact chip identification (ID) circuit on FPGA is presented. An array of ring oscillators is used to measure the process variation. The chip ID is calculated based on their relative speeds. The repeatability of chip ID generation is a common challenge for all kinds of implementations, particularly when variations in operating conditions such as supply voltage and temperature are taken into account. To address this issue, configurable ring oscillators together with an orthogonal (re-)initialization scheme is used to improve reliability. The implementation of the proposed design is tested on nine Xilinx Spartan-3e FPGA chips. The experimental results show that the new method significantly enhances reliability of ID generation and tolerance to environmental changes.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Detailed summary in vernacular field only.
Yu, Haile.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2012.
Includes bibliographical references (leaves 125-137).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.
Abstract --- p.ii
Acknowledgement --- p.vi
Publication List --- p.viii
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Introduction to Process Variation --- p.1
Chapter 1.2 --- Variation Compensation --- p.3
Chapter 1.2.1 --- Post-silicon Tuning --- p.3
Chapter 1.2.2 --- Variation-Aware Design (VAD) --- p.5
Chapter 1.3 --- Background and Prior Art --- p.6
Chapter 1.3.1 --- Variation Characterization --- p.6
Chapter 1.3.2 --- Variation Compensation --- p.8
Chapter 1.3.3 --- Chip Identification --- p.11
Chapter 1.4 --- Motivations --- p.17
Chapter 1.4.1 --- Variation Characterization --- p.17
Chapter 1.4.2 --- Timing Yield Improvement by Architectural Symmetry --- p.18
Chapter 1.4.3 --- Chip Identification --- p.18
Chapter 1.5 --- Key Contributions --- p.19
Chapter 1.5.1 --- Variation Characterization --- p.19
Chapter 1.5.2 --- Timing Yield Improvement by Architectural Symmetry --- p.20
Chapter 1.5.3 --- Chip Identification --- p.20
Chapter 1.6 --- Thesis Outline --- p.22
Chapter 2 --- Variation Characterization for FPGA --- p.24
Chapter 2.1 --- Introduction --- p.25
Chapter 2.2 --- Characterization Primitives --- p.27
Chapter 2.3 --- Methodology --- p.28
Chapter 2.3.1 --- LE Characterization --- p.30
Chapter 2.3.2 --- LUT Full Characterization --- p.33
Chapter 2.3.3 --- Interconnect Characterization --- p.36
Chapter 2.4 --- Implementation --- p.39
Chapter 2.5 --- Experimental Results --- p.41
Chapter 2.5.1 --- Scaling Factor --- p.41
Chapter 2.5.2 --- Characterization Results --- p.42
Chapter 2.5.3 --- Verification --- p.47
Chapter 2.6 --- Conclusion and Discussion --- p.49
Chapter 2.6.1 --- Discussion --- p.50
Chapter 3 --- Timing Yield Improvement for FPGA --- p.51
Chapter 3.1 --- Introduction --- p.52
Chapter 3.2 --- Variation Model --- p.52
Chapter 3.2.1 --- Random Variation --- p.53
Chapter 3.2.2 --- Spatial Correlation --- p.54
Chapter 3.3 --- Theoretical Analysis --- p.55
Chapter 3.3.1 --- 1-out-of-N Redundancy Method --- p.55
Chapter 3.3.2 --- Configuration-Level Redundancy vs. Fine-Grained Adjustment --- p.57
Chapter 3.3.3 --- Coverage Rate of Fine-Grained Adjustment --- p.61
Chapter 3.4 --- Architecture --- p.62
Chapter 3.4.1 --- Modification for Configuration Rotation and Flip --- p.62
Chapter 3.4.2 --- Modification for Fine-grained Adjustment --- p.65
Chapter 3.5 --- Flow of Methodology --- p.66
Chapter 3.6 --- Experimental Results --- p.68
Chapter 3.7 --- Cost-Efficiency Comparison --- p.74
Chapter 3.8 --- Conclusions --- p.76
Chapter 4 --- Chip Identification Circuit for FPGA --- p.78
Chapter 4.1 --- Introduction --- p.79
Chapter 4.2 --- Design --- p.80
Chapter 4.2.1 --- Measurement Circuits --- p.80
Chapter 4.2.2 --- “Cell“ Composition and One-bit Generation --- p.82
Chapter 4.3 --- Results --- p.85
Chapter 4.3.1 --- Distribution of R[subscript i] --- p.86
Chapter 4.3.2 --- Effect of P,T,N --- p.87
Chapter 4.3.3 --- Distribution of 1’s and 0’s --- p.88
Chapter 4.3.4 --- Hamming Distance --- p.89
Chapter 4.3.5 --- Execution Time --- p.89
Chapter 4.3.6 --- Variation with Temperature --- p.90
Chapter 4.4 --- Conclusions --- p.93
Chapter 5 --- Enhanced Chip Identification Circuit for FPGA --- p.96
Chapter 5.1 --- Introduction --- p.96
Chapter 5.2 --- Sources of Instability --- p.97
Chapter 5.3 --- Implementation --- p.98
Chapter 5.3.1 --- Overlapped Cell Composition --- p.98
Chapter 5.3.2 --- Configurable RO --- p.99
Chapter 5.3.3 --- Configuration Initialization --- p.101
Chapter 5.3.4 --- Flow of Chip ID Generation --- p.107
Chapter 5.4 --- Results --- p.109
Chapter 5.4.1 --- Summary of Hardware Resource Consumption --- p.109
Chapter 5.4.2 --- Statistical Analysis --- p.109
Chapter 5.4.3 --- Environmental Influences --- p.117
Chapter 5.5 --- Conclusion --- p.119
Chapter 6 --- Conclusion --- p.120
Chapter 6.1 --- Future Work --- p.122
Chapter 6.1.1 --- Variation Characterization for FPGA --- p.122
Chapter 6.1.2 --- Timing Yield Improvement for FPGA --- p.123
Chapter 6.1.3 --- Chip Identification Circuit for FPGA --- p.124
Bibliography --- p.137

Cheung Chak Chung.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (leaves 101-114).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgments --- p.iii
Vita --- p.v
Table of Contents --- p.vi
List of Figures --- p.x
List of Tables --- p.xiv
Chapter 1 --- Introduction --- p.1
Chapter 1.1 --- Motivation --- p.1
Chapter 1.2 --- Aims and Contribution --- p.4
Chapter 1.3 --- Thesis Overview --- p.5
Chapter 2 --- VLSI Design Cycle --- p.6
Chapter 2.1 --- Logic Synthesis --- p.7
Chapter 2.1.1 --- Logic Minimization --- p.8
Chapter 2.1.2 --- Technology Mapping --- p.8
Chapter 2.1.3 --- Testability --- p.8
Chapter 2.2 --- Physical Design Synthesis --- p.8
Chapter 2.2.1 --- Partitioning --- p.9
Chapter 2.2.2 --- Floorplanning & Placement --- p.10
Chapter 2.2.3 --- Routing --- p.11
Chapter 2.2.4 --- "Compaction, Extraction & Verification" --- p.12
Chapter 2.2.5 --- Physical Design of FPGAs --- p.12
Chapter 3 --- Alternative Wiring --- p.13
Chapter 3.1 --- Introduction --- p.13
Chapter 3.2 --- Notation and Definitions --- p.15
Chapter 3.3 --- Application of Rewiring --- p.17
Chapter 3.3.1 --- Logic Optimization --- p.17
Chapter 3.3.2 --- Timing Optimization --- p.17
Chapter 3.3.3 --- Circuit Partitioning and Routing --- p.18
Chapter 3.4 --- Logic Optimization Analysis --- p.19
Chapter 3.4.1 --- Global Flow Optimization --- p.19
Chapter 3.4.2 --- OBDD Representation --- p.20
Chapter 3.4.3 --- Automatic Test Pattern Generation (ATPG) --- p.22
Chapter 3.4.4 --- Graph Based Alternative Wiring (GBAW) --- p.23
Chapter 3.5 --- Augmented GBAW --- p.26
Chapter 3.6 --- Logic Optimization by using GBAW --- p.28
Chapter 3.7 --- Conclusions --- p.31
Chapter 4 --- Multi-way Partitioning using Rewiring Techniques --- p.33
Chapter 4.1 --- Introduction --- p.33
Chapter 4.2 --- Circuit Partitioning Algorithm Analysis --- p.38
Chapter 4.2.1 --- The Kernighan-Lin (KL) Algorithm --- p.39
Chapter 4.2.2 --- The Fiduccia-Mattheyses (FM) Algorithm --- p.42
Chapter 4.2.3 --- Geometric Representation Algorithm --- p.46
Chapter 4.2.4 --- The Multi-level Partitioning Algorithm --- p.49
Chapter 4.2.5 --- Hypergraph METIS - hMETIS --- p.51
Chapter 4.3 --- The GBAW Partitioning Algorithm --- p.53
Chapter 4.4 --- Experimental Results --- p.56
Chapter 4.5 --- Conclusions --- p.58
Chapter 5 --- Optimum FPGA Switch-Box Designs - HUSB --- p.62
Chapter 5.1 --- Introduction --- p.62
Chapter 5.2 --- Background and Definitions --- p.65
Chapter 5.2.1 --- Routing Architectures --- p.65
Chapter 5.2.2 --- Global Routing --- p.67
Chapter 5.2.3 --- Detailed Routing --- p.67
Chapter 5.3 --- FPGA Router Comparison --- p.69
Chapter 5.3.1 --- CGE --- p.69
Chapter 5.3.2 --- SEGA --- p.70
Chapter 5.3.3 --- TRACER --- p.71
Chapter 5.3.4 --- VPR --- p.72
Chapter 5.4 --- Switch Box Design --- p.73
Chapter 5.4.1 --- Disjoint type switch box (XC4000-type) --- p.73
Chapter 5.4.2 --- Anti-symmetric switch box --- p.74
Chapter 5.4.3 --- Universal Switch box --- p.74
Chapter 5.4.4 --- Switch box Analysis --- p.75
Chapter 5.5 --- Terminology --- p.77
Chapter 5.6 --- "Hyper-universal (4, W)-design analysis" --- p.82
Chapter 5.6.1 --- "H3 is an optimum (4, 3)-design" --- p.84
Chapter 5.6.2 --- "H4 is an optimum (4,4)-design" --- p.88
Chapter 5.6.3 --- "Hi is a hyper-universal (4, i)-design for i = 5,6,7" --- p.90
Chapter 5.7 --- Experimental Results --- p.92
Chapter 5.8 --- Conclusions --- p.95
Chapter 6 --- Conclusions --- p.99
Chapter 6.1 --- Thesis Summary --- p.99
Chapter 6.2 --- Future work --- p.100
Chapter 6.2.1 --- Alternative Wiring --- p.100
Chapter 6.2.2 --- Partitioning Quality --- p.100
Chapter 6.2.3 --- Routing Devices Studies --- p.100
Bibliography --- p.101
Chapter A --- 5xpl - Berkeley Logic Interchange Format (BLIF) --- p.115
Chapter B --- Proof of some 2-local patterns --- p.122
Chapter C --- Illustrations of FM algorithm --- p.124
Chapter D --- HUSB Structures --- p.127
Chapter E --- Primitive minimal 4-way global routing Structures --- p.132

With advancements in CMOS technology, high speed analog circuits that were traditionally implemented with discrete circuit components can now be made monolithically. Antialiasing filters for video signals as well as signal conditioning filters in high speed communication channels are examples of applications where high frequency integrated circuits are now feasible. Transconductance-Capacitor or Gm-C filters are well suited to these applications as they operate in the continuous-time domain and are able to overcome the high-frequency and noise limitations imposed by clocked filter topologies. This thesis covers the design of a programmable fourth-order Chebychev filter with a 50MHz passband using the transconductance-C technique. A previously proposed transconductor based upon a CMOS inverter is used to implement the filter. Since this transconductor has no internal nodes, it can achieve extremely high bandwidths. However, it requires a variable power source for programming. Thus, a wide-band, on-chip, variable-BiCMOS power supply is presented as the method for setting the transconductance. Practical design issues are addressed as well as many methods for compensating non-idealities. Simulations of the filter as well as some parametric measurement of the filter structures are presented.
Graduation date: 1994

The thesis presents the development of force controller to maintain desired normal forces during a very stiff contact operation conducted in a Computer Numerical Control (CNC) machine. Force controller approach described in this thesis requires the accurate knowledge of the nominal tool path a priori. Obtaining the nominal tool path accurately is carried out by a vision based profile tracking system presented in this thesis. Both the force control and visual profile tracking systems require the development of an active control system to respond to force and vision signals. To facilitate the active control, a two-stage approach has been taken. The first stage is to bring the CNC machine under real-time control of an external computer. The second stage is the design of the active axis controller. This is achieved by adding sensor feedback loops to the external axis controller. The purpose of the active vision based profile tracking system is to automatically generate the tool path accurately. Emphasis is on combining low resolution vision with visual control of the precision CNC machine to attain the accuracy required for metal spinning. Combination of visual profile tracking and an edge detection method that gives sub-pixel accuracy were used to obtain the required tool path. A curvature detection algorithm was developed to identify segments of the tool path by assuming that the tool path consists of circular and straight line segments. The developed active force controller operates in a dynamic setup and is used to maintain tool forces at desired levels. The complete control system operates in a manner similar to reaction compensation and the force controller can be viewed as an integrating on-off controller with minimum integral wind-up effect. As a result, a direct dependency of the control efforts on error signals has been eliminated. In addition, the force controller brings in artificial damping that ensures the stability of the control system. To demonstrate the effect of the force controller, spun component qualities were assessed.

Tang Wai Chung.
Thesis (M.Phil.)--Chinese University of Hong Kong, 2005.
Includes bibliographical references (leaves 40-41).
Abstracts in English and Chinese.
Abstract --- p.i
Acknowledgement --- p.iii
Chapter 1 --- Introduction --- p.1
Chapter 2 --- Rewiring Algorithms --- p.3
Chapter 2.1 --- REWIRE --- p.5
Chapter 2.2 --- RAMFIRE --- p.7
Chapter 2.3 --- GBAW --- p.8
Chapter 3 --- FPGA Technology Mapping --- p.11
Chapter 3.1 --- Problem Definition --- p.13
Chapter 3.2 --- Network-flow-based Algorithms for FPGA Technology Mapping --- p.16
Chapter 3.2.1 --- FlowMap --- p.16
Chapter 3.2.2 --- FlowSYN --- p.21
Chapter 3.2.3 --- CutMap --- p.22
Chapter 4 --- LUT Minimization by Rewiring --- p.24
Chapter 4.1 --- Greedy Decision Heuristic for LUT Minimization --- p.27
Chapter 4.2 --- Experimental Result --- p.28
Chapter 5 --- Conclusion --- p.38
Bibliography --- p.40

Leong Monk Ping.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2001.
Includes bibliographical references (p. 255-278).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Mode of access: World Wide Web.
Abstracts in English and Chinese.

The Brushless Doubly-Fed Machine (BDFM) has recently become an important research topic in the field of variable-speed AC drives. In recent studies, the BDFM has shown significant potential for improving the reliability and performance of AC drive systems, as well as reducing total system cost. While the BDFM offers several advantages over existing AC drives in steady-state operation, it suffers from dynamic instabilities and slow response times, and a feedback control system is necessary. The mathematics of the BDFM are much more complicated than those of a singly-fed machine, and thus traditional control methods can't be applied. In this thesis, a control method known as "Direct Torque Control" has been adapted from that of a singly-fed induction machine and successfully applied to the BDFM. The thesis begins by discussing the background of the BDFM, its open-loop operating characteristics, and some of the control considerations. The reduced-order system differential equations are introduced, and it is noted that they are coupled and nonlinear. Furthermore, all state variables are time-varying (but periodic), even in steady-state operation. In the controller development, it is found that a linear relationship exists between the desired torque/flux-level change and the d-q voltages to be applied to the control winding of the machine via the power-electronic converter. This linear relationship, together with a one-step-ahead predictor to compensate for computational delay, is successfully used to control the speed and efficiency of the machine, for a wide range of speeds and load torques. Numerous open- vs. closed-loop simulations are compared and summarized, and it is found that the performance of the BDFM is greatly improved in the closed-loop, with faster response and reduced oscillation. Further simulations investigating the robustness of the controller are summarized, and it is found that the controller is reasonably insensitive to errors in most of the the static machine parameters. Hardware implementation is briefly discussed but is not complete; laboratory results are not yet available but should be soon. Future controller considerations are then discussed; included among the recommendations are an on-line parameter estimator for use in adaptive control, and a controller for generator applications of the BDFM.
Graduation date: 1993

The loads on the electrical systems of automobiles are projected to increase significantly in the near future. This will result in a requirement for improved efficiency over the present-day car alternators. An alternative scheme proposed at Oregon State University employs a Brushless Doubly-Fed Machine (BDFM) as an alternator. This thesis begins with a study and characterization of the existing car alternator system. The configuration of the proposed scheme is discussed. In the proposed configuration, the power winding of the machine generates the bulk of the power and the control winding provides the excitation. The power winding feeds a power rectifier, which in turn charges the battery in an automobile. The control winding is supplied through an inverter. Issues related to inverter and rectifier design are discussed. A 3-phase pulse width modulated inverter and a bridge rectifier were developed and tested for performance. A PSPICE simulation model for the rectifier was developed and results are compared with laboratory tests. A Voltage Regulator Circuit (VRC) and an Efficiency Maximizer Unit (EMU) for the system are designed and developed. A prototype alternator system is tested and the principle of efficiency maximization is verified. Finally. the comparative performance of the the existing and the proposed system is discussed and some recommendations for further improvements in the prototype system are made.
Graduation date: 1992

Field Programmable Gate Array (FPGA) has a dominating market in digital system prototyping and reconfigurable computing. To make a flexible and efficient FPGA chip both the hardware architecture and the design tool should be further engineered. An innovative architecture always requires excellent development of EDA tools to fully explore the intrinsic merits of the hardware.
FPGA Technology Mapping is an important design automation problem which affects placement and routing dramatically. Depth-optimal technology mapping algorithms were proposed and produced quality mapping solution for delay minimization. However such algorithms have not yet considered to further reduce area consumption using the powerful logic transformation techniques.
On hardware side, we present a study on the effect of direct and fast routing hard-wires in FPGA routing architecture. Based on the routing pattern analyzed from real routing data, we proposed a so-called shortcut -based routing to handle short and localized routing requirements. Experimental results show that the shortcuts are well utilized and it allows a better average wirelength usage in the whole routing architecture.
On software side, we propose a versatile approach to combine logic transformation and technology mapping. In addition to a level-reduction scheme, we also present a method of reducing the number of LUTs used while keeping the depth optimality. Our approach is based on a greedy but effective heuristic to choose good alternative wires for transformation. Large number of experiments were conducted to analyze the effectiveness of the system. Our results show that our approach can effectively reduce at least 5% (up to 25%) of the area over initial mapping by various state-of-the-art FPGA technology mappers. Furthermore, we found that the delay performance can be improved by 5% when the area is reduced by our system.
Tang, Wai Chung.
Adviser: David Yu-Liang Wu.
Source: Dissertation Abstracts International, Volume: 70-06, Section: B, page: 3704.
Thesis (Ph.D.)--Chinese University of Hong Kong, 2008.
Includes bibliographical references (leaves 70-74).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. [Ann Arbor, MI] : ProQuest Information and Learning, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstracts in English and Chinese.
School code: 1307.

In this thesis, a digital-PID-control single-inductor triple-output (SITO) DC-DC converter is realized in AMS 0.35mum CMOS technology. The size of the chip is about 1600 mum x 1700 mum. To improve load current and reduce cross regulation, a Pre-Sub-Period inductor-current regulation is proposed. Based on the maximum duty cycle limiter, an adaptive inductor current adjustment is realized when the duty cycle of the digital PWM signal is larger than the set maximum duty cycle. By an optimized phase control sequence, the S&H stages of the feedback switching and ADC are controlled to on/off with a minimized delay time. Moreover, the control sequence can virtually remove the setting time.
Multiple voltage supplies are necessary to satisfy the different voltage supply requirements of the different on-chip blocks to reduce power consumption in modem electronic devices, such as the modem embedded systems, the portable devices, personal computing devices and wireless communications and imaging systems. For example, WiMAX transmitter includes different sub-blocks: Baseband processor, IQ modulator and power amplifier. Different blocks should operate with the different power supply voltages to satisfy the different requirements.
Single-input multiple-output DC-DC converter is presented to provide the different voltage supplies and reduce the cost on the elements such as the inductor on PCB and save PCB area. Meanwhile, to remove cross regulation and improve load driving capability, the DC-DC converter should operate in the pseudo-continuous mode/discontinuous mode (P-CCM/DCM). However, in the previous designs, the DC current in the inductor is fixed. When the load becomes heavy enough, cross regulation will significantly affect across the different sub-converters.
Jia, Jingbin.
"December 2009."
Adviser: KaNang Leung Alex.
Source: Dissertation Abstracts International, Volume: 72-01, Section: B, page: .
Thesis (Ph.D.)--Chinese University of Hong Kong, 2010.
Includes bibliographical references (leaves 121-124).
Electronic reproduction. Hong Kong : Chinese University of Hong Kong, [2012] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Electronic reproduction. Ann Arbor, MI : ProQuest Information and Learning Company, [200-] System requirements: Adobe Acrobat Reader. Available via World Wide Web.
Abstract also in Chinese.