Academic literature on the topic 'Processor Architectures'
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'Processor Architectures.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Journal articles on the topic "Processor Architectures"
Page, Ian. "Reconfigurable processor architectures." Microprocessors and Microsystems 20, no. 3 (May 1996): 185–96. http://dx.doi.org/10.1016/0141-9331(95)01076-9.
Full textByrd, G. T., and M. A. Holliday. "Multithreaded processor architectures." IEEE Spectrum 32, no. 8 (1995): 38–46. http://dx.doi.org/10.1109/6.402166.
Full textYantır, Hasan Erdem, Wenzhe Guo, Ahmed M. Eltawil, Fadi J. Kurdahi, and Khaled Nabil Salama. "An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor." Micromachines 10, no. 8 (July 31, 2019): 509. http://dx.doi.org/10.3390/mi10080509.
Full textKorolija, Nenad, and Kent Milfeld. "Towards hybrid supercomputing architectures." Journal of Computer and Forensic Sciences 1, no. 1 (2022): 47–54. http://dx.doi.org/10.5937/1-42710.
Full textTabak, Daniel. "Microelectronics: Processor architectures I." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 563. http://dx.doi.org/10.1016/0165-6074(88)90111-1.
Full textTabak, Daniel. "Microelectronics: Processor architectures II." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 693. http://dx.doi.org/10.1016/0165-6074(88)90131-7.
Full textRao, Wenjing, Alex Orailoglu, and Ramesh Karri. "Towards Nanoelectronics Processor Architectures." Journal of Electronic Testing 23, no. 2-3 (March 20, 2007): 235–54. http://dx.doi.org/10.1007/s10836-006-0555-7.
Full textGöhringer, Diana, Thomas Perschke, Michael Hübner, and Jürgen Becker. "A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/395018.
Full textBezzubtsev, Stanislav O., Vyacheslav V. Vasin, Dmitry Yu Volkanov, Shynar R. Zhailauova, Vladislav A. Miroshnik, Yuliya A. Skobtsova, and Ruslan L. Smeliansky. "An Approach to the Construction of a Network Processing Unit." Modeling and Analysis of Information Systems 26, no. 1 (March 15, 2019): 39–62. http://dx.doi.org/10.18255/1818-1015-2019-1-39-62.
Full textKATZ, RANDY H., and JOHN L. HENNESSY. "HIGH PERFORMANCE MICROPROCESSOR ARCHITECTURES." International Journal of High Speed Electronics and Systems 01, no. 01 (March 1990): 1–17. http://dx.doi.org/10.1142/s0129156490000022.
Full textDissertations / Theses on the topic "Processor Architectures"
Sherwood, Timothy. "Application-tuned processor architectures /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3090450.
Full textKilleen, Timothy F. "Improving processor utilization in multiple context processor architectures." Ohio : Ohio University, 1997. http://www.ohiolink.edu/etd/view.cgi?ohiou1174618393.
Full textTune, Eric. "Critical-path aware processor architectures /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2004. http://wwwlib.umi.com/cr/ucsd/fullcit?p3153686.
Full textCommissariat, Hormazd P. "Performance Modeling of Single Processor and Multi-Processor Computer Architectures." Thesis, Virginia Tech, 1995. http://hdl.handle.net/10919/31377.
Full textMaster of Science
Al-Khayatt, Samir S. "Functional partitioning of multi-processor architectures." Thesis, Loughborough University, 1990. https://dspace.lboro.ac.uk/2134/32337.
Full textSeng, John. "Optimizing processor architectures for power-efficiency /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3091334.
Full textShnidman, Nathan R. (Nathan Robert). "Multipass communication systems for tiled processor architectures." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36137.
Full textIncludes bibliographical references (p. 191-202).
Multipass communication systems utilize multiple sets of parallel baseband receiver functions to balance communication data rates and available computation capabilities. This is achieved by spatially pipelining baseband functions across parallel resources to perform multiple processing passes on the same set of received values, thus allowing the system to simultaneously convey multiple sequences of data using a single wireless link. The use of multiple passes mitigates the effects of data rate on receiver processing bottlenecks, making the use of general-purpose processing elements for high data rate communication functions viable. The flexibility of general-purpose processing, in turn, allows the receiver composition to trade-off resource usage and required processing rate. For instance, a communication system could be distributed across 2 passes using 2x the overall area, but reducing the data rate for each pass and the resultant overall required processing rate, and hence clock speed, by 1/2. Lowering the clock speed can also be leveraged to reduce power through voltage scaling and/or the use of higher Vt devices. The characteristics of general-purpose parallel processors for communications processing are explored, as well as the applicability of specific parallel designs to communications processing.
(Cont.) In particular, an in depth look is taken of the Raw processor's tiled architecture as a general-purpose parallel processor particularly well suited to portable communications processing. An example of a multipass system, based on the 802.11a baseband, implemented on the Raw processor along with the accompanying hardware implementation is presented as both a proof-of-concept, as well as a means to explore some of the advantages and trade-offs of such a system. A bit-error rate study is presented which shows this multipass system to be within a small fraction of dB of the performance of an equivalent data rate single pass system, thus demonstrating the viability of the multipass algorithm. In addition, the capability of tiled processors to maximize processing capabilities at the system block level, as well as the system architectural level, is shown. Parallel implementations of two processing intensive functions: the FFT and the Viterbi decoder are shown. A parallelized assembly language FFT utilizing 16 tiles is shown to have a 1,000x improvement , and a parallelized 48-tile assembly language Viterbi decoder is shown to have a 10, 000x improvement over corresponding serial C implementations.
by Nathan Robert Shnidman.
Ph.D.
Trilla, Rodríguez David. "Non-functional considerations of time-randomized processor architectures." Doctoral thesis, Universitat Politècnica de Catalunya, 2020. http://hdl.handle.net/10803/670903.
Full textLos Sistemas Críticos Empotrados de Tiempo Real (SCETR) son el subconjunto de sistemas empotrados con requerimientos temporales cuyo mal funcionamiento puede poner en peligro vidas humanas o material valioso. Para obtener evidencias de su correcta operación, los SCETR son diseñados, implementados y desplegados en conformidad con los estándares de fiabilidad y las regulaciones de certificación. Para lograrlo, los SCETR deben seguir estrictos procesos de Validación y Verificación (VyV) de sus propiedades funcionales y no funcionales. Una de las propiedades no funcionales más importantes es la temporalidad, cuya verificación se basa en derivar los tiempos de ejecución en el peor caso de las tareas y generar una planificación de éstas para asegurar el correcto comportamiento temporal del sistema. Sin embargo, el uso de hardware y software de mayor complejidad para poder satisfacer las crecientes demandas de rendimiento en los SCETR provoca un incremento sustancial de los costes de la VyV. En el caso de la VyV temporal, métodos estadísticos como el Análisis Temporal Probabilístico Basado en Mediciones (ATPBM) ayudan a reducir el coste de la VyV en el hardware y software complejo de los SCETR. Para lograrlo, se emplea el uso de la randomización temporal a nivel de hardware. En este sentido, los Procesadores Temporalmente Randomizados (PTR) logran contener los costes de VyV mediante la destrucción de comportamientos patológicos sistemáticos y habilitando el uso de las técnicas de ATPBM. En este contexto, esta tesis demuestra que los diseños hardware y software que incorporan randomización no solo consiguen exitosamente solucionar parte del problema de análisis temporal, sino que también son útiles para analizar otras métricas no funcionales clave en los SCETR cómo la durabilidad, la seguridad y la energía. En términos de durabilidad, esta tesis demuestra que los PTR son de manera natural resilientes ante efectos de envejecimiento del hardware, efectos de inestabilidad en la alimentación y aumentamos esas propiedades proponiendo mejoras a su diseño. Además, los PTR mitigan las amenazas de seguridad e intrusiones mediante la destrucción de la asociación determinista entre el mapeo de memoria y su tiempo de acceso y desarrollamos una metodología en concordancia para una operabilidad segura en automóviles. Finalmente, para la temática energética, introducimos una taxonomía para guiar a los futuros retos en la derivación de estimaciones para consumo energético en el peor caso y marcamos los primeros pasos para usar una metodología tipo ATPBM en estimaciones energéticas bajo los efectos de variaciones de proceso. Siguiendo en la temática energética, esta tesis también muestra como los PTR de manera natural rompen y exponen patrones patológicos de consumo energético y ayudan a cuantificar y validar picos instantáneos de demanda energética. En resumen, esta tesis abre el camino en el uso de los PTR en los SCETR para atacar sus retos emergentes en las temáticas de durabilidad, seguridad y consumo energético.
Rebello, Vinod. "On the distribution of control in asynchronous processor architectures." Thesis, University of Edinburgh, 1997. http://hdl.handle.net/1842/507.
Full textPetters, Stefan M. E. "Worst case execution time estimation for advanced processor architectures." [S.l. : s.n.], 2002. http://deposit.ddb.de/cgi-bin/dokserv?idn=965404110.
Full textBooks on the topic "Processor Architectures"
Fountain, T. J. Processor arrays: Architectures and applications. London: Academic Press, 1987.
Find full text1965-, Lapsley Phil, ed. DSP processor fundamentals: Architectures and features. New York: IEEE Press, 1997.
Find full textEndecott, Philip Brian. Processor architectures for power efficiency and asynchronous implementation. Manchester: University of Manchester, 1993.
Find full textUnited States. National Aeronautics and Space Administration., ed. Periodic application of concurrent error detection in processor array architectures. [Urbana, IL]: Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, College of Engineering, University of Illinois at Urbana-Champaign, 1993.
Find full textJohnson, Sally C. Evaluation of fault-tolerant parallel-processor architectures over long space missions. Hampton, Va: Langley Research Center, 1989.
Find full textFarooq, Umer. Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization. New York, NY: Springer New York, 2012.
Find full textZatt, Bruno. 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures. New York, NY: Springer New York, 2013.
Find full textUnited States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.
Find full textUnited States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.
Find full textUnited States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.
Find full textBook chapters on the topic "Processor Architectures"
Rochange, Christine, Sascha Uhrig, and Pascal Sainrat. "Current Processor Architectures." In Time-Predictable Architectures, 37–67. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2014. http://dx.doi.org/10.1002/9781118790229.ch3.
Full textSingh, Nikhilesh, Vinod Ganesan, and Chester Rebeiro. "Secure Processor Architectures." In Handbook of Computer Architecture, 1–29. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-15-6401-7_10-1.
Full textSzefer, Jakub. "Secure Processor Architectures." In Principles of Secure Processor Architecture Design, 25–42. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-031-01760-5_3.
Full textMurti, KCS. "Embedded Processor Architectures." In Transactions on Computer Systems and Networks, 341–89. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3293-8_12.
Full textFricke, Florian, Safdar Mahmood, Javier Hoffmann, Muhammad Ali, Keyvan Shahin, Michael Hübner, and Diana Göhringer. "Domain Adaptive Processor Architectures." In Technologien für die intelligente Automation, 315–30. Berlin, Heidelberg: Springer Berlin Heidelberg, 2020. http://dx.doi.org/10.1007/978-3-662-59895-5_23.
Full textRao, W., A. Orailoglu, and R. Karri. "Towards Nanoelectronics Processor Architectures." In Emerging Nanotechnologies, 339–72. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-74747-7_13.
Full textFurht, Borko. "Processor Architectures for Multimedia." In Multimedia Technologies and Applications for the 21st Century, 3–28. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-0-585-28767-6_1.
Full textPirsch, P., A. Freimann, C. Klar, and J. P. Wittenburg. "Processor Architectures for Multimedia Applications." In Embedded Processor Design Challenges, 188–206. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45874-3_11.
Full textSrini, Vason P. "Crossbar-Multi-Processor Architecture." In Cache and Interconnect Architectures in Multiprocessors, 223–43. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_12.
Full textHelmbold, David, and Ernst Mayr. "Two processor scheduling is in NC." In VLSI Algorithms and Architectures, 12–25. Berlin, Heidelberg: Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/3-540-16766-8_2.
Full textConference papers on the topic "Processor Architectures"
Boehme, Johann F., D. Timmermann, H. Hahn, and Bedrich J. Hosticka. "CORDIC processor architectures." In San Diego, '91, San Diego, CA, edited by Franklin T. Luk. SPIE, 1991. http://dx.doi.org/10.1117/12.49829.
Full textPetrov, P., and A. Orailoglu. "Customizable embedded processor architectures." In Proceedings. Euromicro Symposium on Digital System Design. IEEE, 2003. http://dx.doi.org/10.1109/dsd.2003.1231986.
Full textRao, Wenjing, Alex Orailoglu, and Ramesh Karri. "Fault tolerant nanoelectronic processor architectures." In the 2005 conference. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1120725.1120857.
Full textNarayanan, P. J. "Processor autonomy on SIMD architectures." In the 7th international conference. New York, New York, USA: ACM Press, 1993. http://dx.doi.org/10.1145/165939.165963.
Full textKatz. "High performance VLSI processor architectures." In 1993 Symposium on VLSI Circuits. IEEE, 1989. http://dx.doi.org/10.1109/vlsic.1989.1037461.
Full textOstler, Chris, Karam S. Chatha, and Goran Konjevod. "Approximation Algorithm for Process Mapping on Network Processor Architectures." In 2007 Asia and South Pacific Design Automation Conference. IEEE, 2007. http://dx.doi.org/10.1109/aspdac.2007.358048.
Full textJing, He, Li Tianyue, and Xu Xinyu. "Architectures for 3780 point FFT processor." In 2011 4th International Congress on Image and Signal Processing (CISP). IEEE, 2011. http://dx.doi.org/10.1109/cisp.2011.6100733.
Full textHazmi, Ibrahim H., Fan Zhou, Fayez Gebali, and Turki F. Al-Somani. "Review of Elliptic Curve Processor architectures." In 2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM). IEEE, 2015. http://dx.doi.org/10.1109/pacrim.2015.7334833.
Full textCavallaro, Joseph R., and Franklin T. Luk. "Architectures For A Cordic SVD Processor." In 30th Annual Technical Symposium, edited by William J. Miceli. SPIE, 1986. http://dx.doi.org/10.1117/12.976245.
Full textYi, Kyueun, and Jean-luc Gaudiot. "Features of Future Network Processor Architectures." In IEEE John Vincent Atanasoff 2006 International Symposium on Modern Computing (JVA'06). IEEE, 2006. http://dx.doi.org/10.1109/jva.2006.19.
Full textReports on the topic "Processor Architectures"
Van Houten, Jonathan Roger, Jason P. Jarosz, Benjamin James Welch, Daniel E. Gallegos, and Mark Walter Learn. Soft-core processor study for node-based architectures. Office of Scientific and Technical Information (OSTI), September 2008. http://dx.doi.org/10.2172/942207.
Full textPenedo, Maria H. PSEE Architecture Report. Architectures and Models for Next Generation Process-based Software Engineering Environments. Fort Belvoir, VA: Defense Technical Information Center, February 1995. http://dx.doi.org/10.21236/ada291268.
Full textTRW SYSTEMS GROUP REDONDO BEACH CA. PSEE Architecture Report. PSEE Architecture Report Attachment - Section 11. Architectures and Models for Next Generation Process-Based Software Engineering Environments. Fort Belvoir, VA: Defense Technical Information Center, February 1995. http://dx.doi.org/10.21236/ada293112.
Full textBequillard, A. L., D. O. Carhoun, and W. L. Eastman. Advanced Architectures for Digital Signal Processors. Fort Belvoir, VA: Defense Technical Information Center, October 1985. http://dx.doi.org/10.21236/ada166921.
Full textAgarwal, Anant, Beng-Hong Lim, David Kranz, and John Kubiatowicz. APRIL: A Processor Architecture for Multiprocessing. Fort Belvoir, VA: Defense Technical Information Center, June 1991. http://dx.doi.org/10.21236/ada237476.
Full textShetty, Prasad, Rupali Gupte, Dipti Bhaindarkar, and Vastavikta Bhagat. Educational Ecosystem of Architecture in India: A Review. Indian Institute for Human Settlements, 2023. http://dx.doi.org/10.24943/tesf2207.2024.
Full textBryson, W. Packaging of the S-1 advanced architecture processor. Office of Scientific and Technical Information (OSTI), October 1988. http://dx.doi.org/10.2172/6999343.
Full textCardinal, Douglas J. Architecture as a Living Process. Inter-American Development Bank, July 1997. http://dx.doi.org/10.18235/0007925.
Full textSinha, Velu. Architecture of MRMS Simulation: Distributing Processes,. Fort Belvoir, VA: Defense Technical Information Center, January 1987. http://dx.doi.org/10.21236/ada189697.
Full textAndrews, Michael, and David James. SBNR (Signed Binary Number Representations) Digital Signal Processor Architecture. Fort Belvoir, VA: Defense Technical Information Center, May 1987. http://dx.doi.org/10.21236/ada184603.
Full text