Relevant bibliographies by topics / Processor Architectures

Academic literature on the topic 'Processor Architectures'

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Published: 4 June 2021
Last updated: 1 August 2024

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Journal articles on the topic "Processor Architectures"

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Page, Ian. "Reconfigurable processor architectures." Microprocessors and Microsystems 20, no. 3 (May 1996): 185–96. http://dx.doi.org/10.1016/0141-9331(95)01076-9.

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Byrd, G. T., and M. A. Holliday. "Multithreaded processor architectures." IEEE Spectrum 32, no. 8 (1995): 38–46. http://dx.doi.org/10.1109/6.402166.

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Yantır, Hasan Erdem, Wenzhe Guo, Ahmed M. Eltawil, Fadi J. Kurdahi, and Khaled Nabil Salama. "An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor." Micromachines 10, no. 8 (July 31, 2019): 509. http://dx.doi.org/10.3390/mi10080509.

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Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.
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Korolija, Nenad, and Kent Milfeld. "Towards hybrid supercomputing architectures." Journal of Computer and Forensic Sciences 1, no. 1 (2022): 47–54. http://dx.doi.org/10.5937/1-42710.

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In light of recent work on combining control-flow and dataflow architectures on the same chip die, a new architecture based on an asymmetric multicore processor is proposed. The control-flow architectures are described as a most commonly used computer architecture today. Both multicore and manycore architectures are explained, as they are based on the same principles. A dataflow computing model assumes that data input flows through hardware as either a software or hardware dataflow implementation. In software dataflow, processors based on the control-flow paradigm process tasks based on their availability from the same queue (if there are any). In hardware dataflow architectures, the hardware is configured for a particular algorithm, and data input is streamed into the hardware, and the output is streamed back to the multicore processor for further processing. Hardware dataflow architectures are usually implemented with FPGAs. Hybrid architectures employ asymmetric multicore and manycore computer architectures that are based on the control-flow and hardware dataflow architecture, all combined on the same chip die. Advantages include faster processing time, lower power consumption (and heating), and less space needed for the hardware.
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Tabak, Daniel. "Microelectronics: Processor architectures I." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 563. http://dx.doi.org/10.1016/0165-6074(88)90111-1.

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Tabak, Daniel. "Microelectronics: Processor architectures II." Microprocessing and Microprogramming 24, no. 1-5 (August 1988): 693. http://dx.doi.org/10.1016/0165-6074(88)90131-7.

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Rao, Wenjing, Alex Orailoglu, and Ramesh Karri. "Towards Nanoelectronics Processor Architectures." Journal of Electronic Testing 23, no. 2-3 (March 20, 2007): 235–54. http://dx.doi.org/10.1007/s10836-006-0555-7.

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Göhringer, Diana, Thomas Perschke, Michael Hübner, and Jürgen Becker. "A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip." International Journal of Reconfigurable Computing 2009 (2009): 1–11. http://dx.doi.org/10.1155/2009/395018.

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Runtime adaptivity of hardware in processor architectures is a novel trend, which is under investigation in a variety of research labs all over the world. The runtime exchange of modules, implemented on a reconfigurable hardware, affects the instruction flow (e.g., in reconfigurable instruction set processors) or the data flow, which has a strong impact on the performance of an application. Furthermore, the choice of a certain processor architecture related to the class of target applications is a crucial point in application development. A simple example is the domain of high-performance computing applications found in meteorology or high-energy physics, where vector processors are the optimal choice. A classification scheme for computer systems was provided in 1966 by Flynn where single/multiple data and instruction streams were combined to four types of architectures. This classification is now used as a foundation for an extended classification scheme including runtime adaptivity as further degree of freedom for processor architecture design. The developed scheme is validated by a multiprocessor system implemented on reconfigurable hardware as well as by a classification of existing static and reconfigurable processor systems.
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Bezzubtsev, Stanislav O., Vyacheslav V. Vasin, Dmitry Yu Volkanov, Shynar R. Zhailauova, Vladislav A. Miroshnik, Yuliya A. Skobtsova, and Ruslan L. Smeliansky. "An Approach to the Construction of a Network Processing Unit." Modeling and Analysis of Information Systems 26, no. 1 (March 15, 2019): 39–62. http://dx.doi.org/10.18255/1818-1015-2019-1-39-62.

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The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.
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KATZ, RANDY H., and JOHN L. HENNESSY. "HIGH PERFORMANCE MICROPROCESSOR ARCHITECTURES." International Journal of High Speed Electronics and Systems 01, no. 01 (March 1990): 1–17. http://dx.doi.org/10.1142/s0129156490000022.

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Single chip processor performance has improved dramatically since the inception of the four-bit microprocessor in 1971. This is due in part to technological advances, (i.e., faster devices and greater device density), but also because of the adoption of architectural approaches well suited to the opportunities and limitations of VLSI. The most appropriate are those that effectively reduce off-chip memory accesses and admit to a regular pipelined implementation. The over-riding goal of pipelining is to achieve “single cycle execution”, i.e., instructions appear to execute in a single processor cycle. Today’s RISC processors are close to realizing this goal, and the next generation will reduce the cycles per instruction even further. In this paper, we will review the design issues and the proposed architectures for high performance VLSI processors.
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Dissertations / Theses on the topic "Processor Architectures"

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Sherwood, Timothy. "Application-tuned processor architectures /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3090450.

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Killeen, Timothy F. "Improving processor utilization in multiple context processor architectures." Ohio : Ohio University, 1997. http://www.ohiolink.edu/etd/view.cgi?ohiou1174618393.

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Tune, Eric. "Critical-path aware processor architectures /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2004. http://wwwlib.umi.com/cr/ucsd/fullcit?p3153686.

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Commissariat, Hormazd P. "Performance Modeling of Single Processor and Multi-Processor Computer Architectures." Thesis, Virginia Tech, 1995. http://hdl.handle.net/10919/31377.

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Determining the optimum computer architecture configuration for a specific application or a generic algorithm is a difficult task. The complexity involved in today's computer architectures and systems makes it more difficult and expensive to easily and economically implement and test full functional prototypes of computer architectures. High level VHDL performance modeling of architectures is an efficient way to rapidly prototype and evaluate computer architectures. Determining the architecture configuration is fixed, one would like to know the tolerance and expected performance of individual/critical components and also what would be the best way to map the software tasks onto the processor(s). Trade-offs and engineering compromises can be analyzed and the effects of certain component failures and communication bottle-necks can be studied. A part of the research work done for the RASSP (Rapid Prototyping of Application Specific Signal Processors) project funded by Department of Defense contracts is documented in this thesis. The architectures modeled include a single-processor, single-global-bus system; a four processor, single-global-bus system; a four processor, multiple-local-bus, single-global-bus system; and finally, a four processor multiple-local-bus system interconnected by a crossbar interconnection switch. The hardware models used are mostly legacy/inherited models from an earlier project and they were upgraded, modified and customized to suit the current research needs and requirements. The software tasks that are run on the processors are pieces of the signal and image processing algorithm run on the Synthetic Aperture Radar (SAR). The communication between components/devices is achieved in the form of tokens which are record structures. The output is a trace file which tracks the passage of the tokens through various components of the architecture. The output trace file is post-processed to obtain activity plots and latency plots for individual components of the architecture.
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Al-Khayatt, Samir S. "Functional partitioning of multi-processor architectures." Thesis, Loughborough University, 1990. https://dspace.lboro.ac.uk/2134/32337.

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Many real-time computations such as process control and robotic applications may be naturally distributed in a functional manner. One way of ensuring good performance, reliability and security of operation is to map or distribute such tasks onto a distributed, multi-processor system. The time-critical task is thus functionally partitioned into a set of cooperating sub-tasks. These sub-tasks run concurrently and asynchronously on different nodes (stations) of the system. The software design and support of such a functional distribution of sub-tasks (processes) depends on the degree of interaction of these processes among the different nodes.
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Seng, John. "Optimizing processor architectures for power-efficiency /." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2003. http://wwwlib.umi.com/cr/ucsd/fullcit?p3091334.

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Shnidman, Nathan R. (Nathan Robert). "Multipass communication systems for tiled processor architectures." Thesis, Massachusetts Institute of Technology, 2006. http://hdl.handle.net/1721.1/36137.

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Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2006.
Includes bibliographical references (p. 191-202).
Multipass communication systems utilize multiple sets of parallel baseband receiver functions to balance communication data rates and available computation capabilities. This is achieved by spatially pipelining baseband functions across parallel resources to perform multiple processing passes on the same set of received values, thus allowing the system to simultaneously convey multiple sequences of data using a single wireless link. The use of multiple passes mitigates the effects of data rate on receiver processing bottlenecks, making the use of general-purpose processing elements for high data rate communication functions viable. The flexibility of general-purpose processing, in turn, allows the receiver composition to trade-off resource usage and required processing rate. For instance, a communication system could be distributed across 2 passes using 2x the overall area, but reducing the data rate for each pass and the resultant overall required processing rate, and hence clock speed, by 1/2. Lowering the clock speed can also be leveraged to reduce power through voltage scaling and/or the use of higher Vt devices. The characteristics of general-purpose parallel processors for communications processing are explored, as well as the applicability of specific parallel designs to communications processing.
(Cont.) In particular, an in depth look is taken of the Raw processor's tiled architecture as a general-purpose parallel processor particularly well suited to portable communications processing. An example of a multipass system, based on the 802.11a baseband, implemented on the Raw processor along with the accompanying hardware implementation is presented as both a proof-of-concept, as well as a means to explore some of the advantages and trade-offs of such a system. A bit-error rate study is presented which shows this multipass system to be within a small fraction of dB of the performance of an equivalent data rate single pass system, thus demonstrating the viability of the multipass algorithm. In addition, the capability of tiled processors to maximize processing capabilities at the system block level, as well as the system architectural level, is shown. Parallel implementations of two processing intensive functions: the FFT and the Viterbi decoder are shown. A parallelized assembly language FFT utilizing 16 tiles is shown to have a 1,000x improvement , and a parallelized 48-tile assembly language Viterbi decoder is shown to have a 10, 000x improvement over corresponding serial C implementations.
by Nathan Robert Shnidman.
Ph.D.
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Trilla, Rodríguez David. "Non-functional considerations of time-randomized processor architectures." Doctoral thesis, Universitat Politècnica de Catalunya, 2020. http://hdl.handle.net/10803/670903.

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Critical Real-Time Embedded Systems (CRTES) are the subset of embedded systems with timing constraints whose miss behavior can endanger human lives or expensive equipment. To provide evidence of correctness, CRTES are designed, implemented and deployed in adherence to safety standards and certification regulations. To that end, CRTES follow strict Validation & Verification (V&V) procedures of their functional and non-functional properties. One of the most important non-functional properties is timing, which builds on computing the worst-case execution time of tasks and a schedule of tasks so that the overall system timing behavior is correct. However, the use of more complex hardware and software to satisfy CRTES unprecedented performance requirements, heavily increase the cost of V&V. For timing V&V, statistical techniques, like Measurement-Based Probabilistic Timing Analysis (MBPTA) help to address the complexity of hardware and software in CRTES. To that end, they benefit from randomization of temporal behavior at the hardware level. In this line, Time-Randomized Processors (TRP) contain timing V&V costs by breaking systematic pathological behaviors and enabling MBPTA applicability. In the context of TRP, this thesis shows that hardware and software designs incorporating randomization can not only successfully tackle the existing timing analysis problem, but also provide helpful properties to other emerging non-functional metrics key in CRTES like reliability, security and energy. For reliability, we show that TRP are naturally resilient against hardware aging effects and voltage noise and we add up to such resilience by improving its design. Also, TRP hinders security threats and intrusions by breaking and mangling the deterministic association between memory mapping and access time and we develop a framework for secure automotive operation. Finally for energy, we introduce a taxonomy to guide the future challenges for worst-case energy estimation and make the first steps towards the use of MBPTA-like methodology to address worst-case energy estimation under the presence of process variation. Moreover this thesis also shows that together with the application of MBPTA-like methodology, TRP also naturally expose and break pathological energy consumption patterns and help in validating and accounting instantaneous peak power demands. In summary, this thesis pioneers several aspects of the use of TRP to address the emerging challenges that CRTES face in the reliability, security and energy domains.
Los Sistemas Críticos Empotrados de Tiempo Real (SCETR) son el subconjunto de sistemas empotrados con requerimientos temporales cuyo mal funcionamiento puede poner en peligro vidas humanas o material valioso. Para obtener evidencias de su correcta operación, los SCETR son diseñados, implementados y desplegados en conformidad con los estándares de fiabilidad y las regulaciones de certificación. Para lograrlo, los SCETR deben seguir estrictos procesos de Validación y Verificación (VyV) de sus propiedades funcionales y no funcionales. Una de las propiedades no funcionales más importantes es la temporalidad, cuya verificación se basa en derivar los tiempos de ejecución en el peor caso de las tareas y generar una planificación de éstas para asegurar el correcto comportamiento temporal del sistema. Sin embargo, el uso de hardware y software de mayor complejidad para poder satisfacer las crecientes demandas de rendimiento en los SCETR provoca un incremento sustancial de los costes de la VyV. En el caso de la VyV temporal, métodos estadísticos como el Análisis Temporal Probabilístico Basado en Mediciones (ATPBM) ayudan a reducir el coste de la VyV en el hardware y software complejo de los SCETR. Para lograrlo, se emplea el uso de la randomización temporal a nivel de hardware. En este sentido, los Procesadores Temporalmente Randomizados (PTR) logran contener los costes de VyV mediante la destrucción de comportamientos patológicos sistemáticos y habilitando el uso de las técnicas de ATPBM. En este contexto, esta tesis demuestra que los diseños hardware y software que incorporan randomización no solo consiguen exitosamente solucionar parte del problema de análisis temporal, sino que también son útiles para analizar otras métricas no funcionales clave en los SCETR cómo la durabilidad, la seguridad y la energía. En términos de durabilidad, esta tesis demuestra que los PTR son de manera natural resilientes ante efectos de envejecimiento del hardware, efectos de inestabilidad en la alimentación y aumentamos esas propiedades proponiendo mejoras a su diseño. Además, los PTR mitigan las amenazas de seguridad e intrusiones mediante la destrucción de la asociación determinista entre el mapeo de memoria y su tiempo de acceso y desarrollamos una metodología en concordancia para una operabilidad segura en automóviles. Finalmente, para la temática energética, introducimos una taxonomía para guiar a los futuros retos en la derivación de estimaciones para consumo energético en el peor caso y marcamos los primeros pasos para usar una metodología tipo ATPBM en estimaciones energéticas bajo los efectos de variaciones de proceso. Siguiendo en la temática energética, esta tesis también muestra como los PTR de manera natural rompen y exponen patrones patológicos de consumo energético y ayudan a cuantificar y validar picos instantáneos de demanda energética. En resumen, esta tesis abre el camino en el uso de los PTR en los SCETR para atacar sus retos emergentes en las temáticas de durabilidad, seguridad y consumo energético.
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Rebello, Vinod. "On the distribution of control in asynchronous processor architectures." Thesis, University of Edinburgh, 1997. http://hdl.handle.net/1842/507.

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The effective performance of computer systems is to a large measure determined by the synergy between the processor architecture, the instruction set and the compiler. In the past, the sequencing of information within processor architectures has normally been synchronous: controlled centrally by a clock. However, this global signal could possibly limit the future gains in performance that can potentially be achieved through improvements in implementation technology. This thesis investigates the effects of relaxing this strict synchrony by distributing control within processor architectures through the use of a novel asynchronous design model known as a micronet. The impact of asynchronous control on the performance of a RISC-style processor is explored at different levels. Firstly, improvements in the performance of individual instructions by exploiting actual run-time behaviours are demonstrated. Secondly, it is shown that micronets are able to exploit further (both spatial and temporal) instructionlevel parallelism (ILP) efficiently through the distribution of control to datapath resources. Finally, exposing fine-grain concurrency within a datapath can only be of benefit to a computer system if it can easily be exploited by the compiler. Although compilers for micronet-based asynchronous processors may be considered to be more complex than their synchronous counterparts, it is shown that the variable execution time of an instruction does not adversely affect the compiler's ability to schedule code efficiently. In conclusion, the modelling of a processor's datapath as a micronet permits the exploitation of both finegrain ILP and actual run-time delays, thus leading to the efficient utilisation of functional units and in turn resulting in an improvement in overall system performance.
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Petters, Stefan M. E. "Worst case execution time estimation for advanced processor architectures." [S.l. : s.n.], 2002. http://deposit.ddb.de/cgi-bin/dokserv?idn=965404110.

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Books on the topic "Processor Architectures"

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Fountain, T. J. Processor arrays: Architectures and applications. London: Academic Press, 1987.

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1965-, Lapsley Phil, ed. DSP processor fundamentals: Architectures and features. New York: IEEE Press, 1997.

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Endecott, Philip Brian. Processor architectures for power efficiency and asynchronous implementation. Manchester: University of Manchester, 1993.

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United States. National Aeronautics and Space Administration., ed. Periodic application of concurrent error detection in processor array architectures. [Urbana, IL]: Center for Reliable and High-Performance Computing, Coordinated Science Laboratory, College of Engineering, University of Illinois at Urbana-Champaign, 1993.

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Johnson, Sally C. Evaluation of fault-tolerant parallel-processor architectures over long space missions. Hampton, Va: Langley Research Center, 1989.

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Farooq, Umer. Tree-based Heterogeneous FPGA Architectures: Application Specific Exploration and Optimization. New York, NY: Springer New York, 2012.

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Zatt, Bruno. 3D Video Coding for Embedded Devices: Energy Efficient Algorithms and Architectures. New York, NY: Springer New York, 2013.

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United States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.

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United States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.

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United States. National Aeronautics and Space Administration., ed. Processor-In-Memory (PIM) based architectures for petaflops potential massively parallel processing: Final report, NASA grant NAG 5-2998. [Washington, DC: National Aeronautics and Space Administration, 1996.

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Book chapters on the topic "Processor Architectures"

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Rochange, Christine, Sascha Uhrig, and Pascal Sainrat. "Current Processor Architectures." In Time-Predictable Architectures, 37–67. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2014. http://dx.doi.org/10.1002/9781118790229.ch3.

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Singh, Nikhilesh, Vinod Ganesan, and Chester Rebeiro. "Secure Processor Architectures." In Handbook of Computer Architecture, 1–29. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-15-6401-7_10-1.

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Szefer, Jakub. "Secure Processor Architectures." In Principles of Secure Processor Architecture Design, 25–42. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-031-01760-5_3.

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Murti, KCS. "Embedded Processor Architectures." In Transactions on Computer Systems and Networks, 341–89. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-16-3293-8_12.

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Fricke, Florian, Safdar Mahmood, Javier Hoffmann, Muhammad Ali, Keyvan Shahin, Michael Hübner, and Diana Göhringer. "Domain Adaptive Processor Architectures." In Technologien für die intelligente Automation, 315–30. Berlin, Heidelberg: Springer Berlin Heidelberg, 2020. http://dx.doi.org/10.1007/978-3-662-59895-5_23.

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Rao, W., A. Orailoglu, and R. Karri. "Towards Nanoelectronics Processor Architectures." In Emerging Nanotechnologies, 339–72. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-74747-7_13.

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Furht, Borko. "Processor Architectures for Multimedia." In Multimedia Technologies and Applications for the 21st Century, 3–28. Boston, MA: Springer US, 1998. http://dx.doi.org/10.1007/978-0-585-28767-6_1.

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Pirsch, P., A. Freimann, C. Klar, and J. P. Wittenburg. "Processor Architectures for Multimedia Applications." In Embedded Processor Design Challenges, 188–206. Berlin, Heidelberg: Springer Berlin Heidelberg, 2002. http://dx.doi.org/10.1007/3-540-45874-3_11.

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Srini, Vason P. "Crossbar-Multi-Processor Architecture." In Cache and Interconnect Architectures in Multiprocessors, 223–43. Boston, MA: Springer US, 1990. http://dx.doi.org/10.1007/978-1-4613-1537-7_12.

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Helmbold, David, and Ernst Mayr. "Two processor scheduling is in NC." In VLSI Algorithms and Architectures, 12–25. Berlin, Heidelberg: Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/3-540-16766-8_2.

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Conference papers on the topic "Processor Architectures"

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Boehme, Johann F., D. Timmermann, H. Hahn, and Bedrich J. Hosticka. "CORDIC processor architectures." In San Diego, '91, San Diego, CA, edited by Franklin T. Luk. SPIE, 1991. http://dx.doi.org/10.1117/12.49829.

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Petrov, P., and A. Orailoglu. "Customizable embedded processor architectures." In Proceedings. Euromicro Symposium on Digital System Design. IEEE, 2003. http://dx.doi.org/10.1109/dsd.2003.1231986.

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Rao, Wenjing, Alex Orailoglu, and Ramesh Karri. "Fault tolerant nanoelectronic processor architectures." In the 2005 conference. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1120725.1120857.

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Narayanan, P. J. "Processor autonomy on SIMD architectures." In the 7th international conference. New York, New York, USA: ACM Press, 1993. http://dx.doi.org/10.1145/165939.165963.

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Katz. "High performance VLSI processor architectures." In 1993 Symposium on VLSI Circuits. IEEE, 1989. http://dx.doi.org/10.1109/vlsic.1989.1037461.

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Ostler, Chris, Karam S. Chatha, and Goran Konjevod. "Approximation Algorithm for Process Mapping on Network Processor Architectures." In 2007 Asia and South Pacific Design Automation Conference. IEEE, 2007. http://dx.doi.org/10.1109/aspdac.2007.358048.

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Jing, He, Li Tianyue, and Xu Xinyu. "Architectures for 3780 point FFT processor." In 2011 4th International Congress on Image and Signal Processing (CISP). IEEE, 2011. http://dx.doi.org/10.1109/cisp.2011.6100733.

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Hazmi, Ibrahim H., Fan Zhou, Fayez Gebali, and Turki F. Al-Somani. "Review of Elliptic Curve Processor architectures." In 2015 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM). IEEE, 2015. http://dx.doi.org/10.1109/pacrim.2015.7334833.

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Cavallaro, Joseph R., and Franklin T. Luk. "Architectures For A Cordic SVD Processor." In 30th Annual Technical Symposium, edited by William J. Miceli. SPIE, 1986. http://dx.doi.org/10.1117/12.976245.

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Yi, Kyueun, and Jean-luc Gaudiot. "Features of Future Network Processor Architectures." In IEEE John Vincent Atanasoff 2006 International Symposium on Modern Computing (JVA'06). IEEE, 2006. http://dx.doi.org/10.1109/jva.2006.19.

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Reports on the topic "Processor Architectures"

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Van Houten, Jonathan Roger, Jason P. Jarosz, Benjamin James Welch, Daniel E. Gallegos, and Mark Walter Learn. Soft-core processor study for node-based architectures. Office of Scientific and Technical Information (OSTI), September 2008. http://dx.doi.org/10.2172/942207.

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Penedo, Maria H. PSEE Architecture Report. Architectures and Models for Next Generation Process-based Software Engineering Environments. Fort Belvoir, VA: Defense Technical Information Center, February 1995. http://dx.doi.org/10.21236/ada291268.

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TRW SYSTEMS GROUP REDONDO BEACH CA. PSEE Architecture Report. PSEE Architecture Report Attachment - Section 11. Architectures and Models for Next Generation Process-Based Software Engineering Environments. Fort Belvoir, VA: Defense Technical Information Center, February 1995. http://dx.doi.org/10.21236/ada293112.

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Bequillard, A. L., D. O. Carhoun, and W. L. Eastman. Advanced Architectures for Digital Signal Processors. Fort Belvoir, VA: Defense Technical Information Center, October 1985. http://dx.doi.org/10.21236/ada166921.

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Agarwal, Anant, Beng-Hong Lim, David Kranz, and John Kubiatowicz. APRIL: A Processor Architecture for Multiprocessing. Fort Belvoir, VA: Defense Technical Information Center, June 1991. http://dx.doi.org/10.21236/ada237476.

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Shetty, Prasad, Rupali Gupte, Dipti Bhaindarkar, and Vastavikta Bhagat. Educational Ecosystem of Architecture in India: A Review. Indian Institute for Human Settlements, 2023. http://dx.doi.org/10.24943/tesf2207.2024.

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Abstract:
"Formally trained architects in India participate in building habitation for less than 10 per cent of the population. Most architecture created through the involvement of architects produces segregation and discrimination towards certain classes, castes and genders. This study is concerned with the role of formal architectural education in addressing the habitation question and issues of spatial justice. Towards this, a review of the educational ecosystem for architecture has been undertaken. This ecosystem includes institutions, universities, regulatory bodies, journals, events, awards and offices. The study also briefly looks at cases of habitation making for the remaining 90 per cent who do not get served by trained architects. From our review, it is apparent that this ecosystem is structurally, institutionally and pedagogically insufficient to produce a relevant spatial culture, spatial justice or cultural sustainability. While it is structurally located within a political economy where education is a money-making enterprise, it is institutionally geared to reduce academia to educational organisations and pedagogically oriented to prepare students for a building industry of a certain kind. Yet, despite the odds, architectural institutions have been innovating and striving to create relevance. Their efforts will remain key for the overhaul of the ecosystem and they will have to steer the process of change."
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Bryson, W. Packaging of the S-1 advanced architecture processor. Office of Scientific and Technical Information (OSTI), October 1988. http://dx.doi.org/10.2172/6999343.

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Cardinal, Douglas J. Architecture as a Living Process. Inter-American Development Bank, July 1997. http://dx.doi.org/10.18235/0007925.

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Sinha, Velu. Architecture of MRMS Simulation: Distributing Processes,. Fort Belvoir, VA: Defense Technical Information Center, January 1987. http://dx.doi.org/10.21236/ada189697.

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Andrews, Michael, and David James. SBNR (Signed Binary Number Representations) Digital Signal Processor Architecture. Fort Belvoir, VA: Defense Technical Information Center, May 1987. http://dx.doi.org/10.21236/ada184603.

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