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Academic literature on the topic 'Prefetching'

Author: Grafiati

Published: 4 June 2021

Last updated: 15 June 2025

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Journal articles on the topic "Prefetching"

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Yee, Yee Soe. "A Taxonomy of Data Prefetching Mechanisms." International Journal of Trend in Scientific Research and Development 3, no. 6 (2019): 1122–27. https://doi.org/10.5281/zenodo.3589409.

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Data prefetching has been considered an effective way to cross the performance gap between processor and memory and to mask data access latency caused by cache misses. Data prefetching prefers data closer to a processor before it is actually needed with hardware and or software support. Many prefetching techniques have been proposed in the few years to reduce data access latency by taking advantage of multi core architectures. In this paper, a taxonomy that classifies various design concerns has been proposed in developing a prefetching strategy. The various prefetching strategies and issues that have to be considered in designing a prefetching strategy for multi core processors. Yee Yee Soe "A Taxonomy of Data Prefetching Mechanisms" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-3 | Issue-6 , October 2019, URL: https://www.ijtsrd.com/papers/ijtsrd29339.pdf

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Gu, Ji, and Hui Guo. "Reducing Power and Energy Overhead in Instruction Prefetching for Embedded Processor Systems." International Journal of Handheld Computing Research 2, no. 4 (2011): 42–58. http://dx.doi.org/10.4018/jhcr.2011100103.

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Instruction prefetching is an effective way to improve performance of the pipelined processors. However, existing instruction prefetching schemes increase performance with a significant energy sacrifice, making them unsuitable for embedded and ubiquitous systems where high performance and low energy consumption are all demanded. This paper proposes reducing energy overhead in instruction prefetching by using a simple hardware/software design and an efficient prefetching operation scheme. Two approaches are investigated: Decoded Loop Instruction Cache based Prefetching (DLICP) that is most effective for loop intensive applications, and the enhanced DLICP with the popular existing Next Line Prefetching (NLP) for applications of a moderate number of loops. The experimental results show that both DLICP and the enhanced DLICP deliver improved performance at a much reduced energy overhead.

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Jiang, Yong, Shu Wu Zhang, and Jie Liu. "Optimized Prefetching Scheme to Support VCR-Like Operations in P2P VoD Applications with Guided Seeks." Applied Mechanics and Materials 719-720 (January 2015): 756–66. http://dx.doi.org/10.4028/www.scientific.net/amm.719-720.756.

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In Peer-to-Peer (P2P) Video-on-Demand (VoD) streaming systems, supporting free VCR operations is challenging. Prefetching is a good way to improve user experience of VCR interactivity. But most existing P2P VoD prefetching schemes are proposed aimed at those popular videos with large amount of log data, without considering the situation that the videos are unpopular or the popular videos are in their initial phase of release. In this situation, these schemes cannot support user VCR interactivity very well. To address this issue, we propose a new optimized prefetching scheme, called Hybrid Anchor Scheme (HAS), in which fixed anchors and dynamic anchors are merged together. The dynamic anchors are generated based on association rule and segments popularity. Through combining the way of sequential prefetching according to weight of segments and the way of several rounds prefetching, we implement HAS effectively. Extensive simulations validate the proposed prefetching scheme provide shorter seeking latency compared to other prefetching schemes.

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Chen, Yong, Huaiyu Zhu, Philip C. Roth, Hui Jin, and Xian-He Sun. "Global-aware and multi-order context-based prefetching for high-performance processors." International Journal of High Performance Computing Applications 25, no. 4 (2011): 355–70. http://dx.doi.org/10.1177/1094342010394386.

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Data prefetching is widely used in high-end computing systems to accelerate data accesses and to bridge the increasing performance gap between processor and memory. Context-based prefetching has become a primary focus of study in recent years due to its general applicability. However, current context-based prefetchers only adopt the context analysis of a single order, which suffers from low prefetching coverage and thus limits the overall prefetching effectiveness. Also, existing approaches usually consider the context of the address stream from a single instruction but not the context of the address stream from all instructions, which further limits the context-based prefetching effectiveness. In this study, we propose a new context-based prefetcher called the Global-aware and Multi-order Context-based (GMC) prefetcher. The GMC prefetcher uses multi-order, local and global context analysis to increase prefetching coverage while maintaining prefetching accuracy. In extensive simulation testing of the SPEC-CPU2006 benchmarks with an enhanced CMP$im simulator, the proposed GMC prefetcher was shown to outperform existing prefetchers and to reduce the data-access latency effectively. The average Instructions Per Cycle (IPC) improvement of SPEC CINT2006 and CFP2006 benchmarks with GMC prefetching was over 55% and 44% respectively.

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Liu, Shuxin. "Exploring Optimal Prefetching Sizes in RaLMSpec to Enhance Retrieval-Augmented Generation Efficiency." Highlights in Science, Engineering and Technology 138 (May 11, 2025): 24–31. https://doi.org/10.54097/hhff9g78.

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Retrieval-augmented generation (RAG) frameworks like RaLMSpec enhance language model performance by integrating external knowledge. A key method to accelerate RaLMSpec efficiency is the prefetching, which determines the number of documents to retrieve in advance to balance retrieval speed and cache utilization. This study introduces and tests both static and dynamic prefetching strategies to optimize performance in RaLMSpec. Static prefetching uses fixed sizes, while dynamic prefetching adjusts based on real-time factors including task complexity, cache hit rates, and retrieval latency. Experiments across multiple datasets, retrievers, and language models demonstrate that dynamic prefetching significantly reduces latency by 18% on average, outperforming static strategies. Dynamic prefetching adapts to varying task demands, providing better balance between retrieval and caching efficiency. Among static strategies, a prefetch size of 64 offers the best trade-off between latency reduction and cache utilization. The results highlight that dynamic prefetching is optimal for environments with fluctuating task complexity, while static prefetching with a size of 64 is effective for predictable tasks. This study provides valuable insights for improving RAG system efficiency and suggests future directions, including machine learning-based adaptations and hardware optimizations.

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Chen, Yunliang, Fangyuan Li, Bo Du, Junqing Fan, and Ze Deng. "A Quantitative Analysis on Semantic Relations of Data Blocks in Storage Systems." Journal of Circuits, Systems and Computers 24, no. 08 (2015): 1550118. http://dx.doi.org/10.1142/s0218126615501182.

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In a big data era, there are and will be more demands and higher requirements for data organization and management in the storage system. Previous studies on semantic relations of blocks have set an essential theoretical basis in storage systems. Revealing semantic relationship of blocks has great scientific values and indicates a promising prospect in the application. However, only qualitative description of block correlations has been obtained by traditional ways, and few researches have been done on unifying and quantizing the blocks semantic relationships. In this paper, an uniform design-aided gene expression programming (UGEP) method has been proposed to address this issue. After analyzing historical access streams, a quantitative description system on semantic relationship of blocks is established. The semantic relationship of blocks can also be used in prefetching in storage system, which means the next access block can be calculated by the prefetching model. Simulation tests in four real system traces indicate that compared with sequential prefetching and no prefetching model, the quantitative semantic relationships model based on UGEP can highly improve the performance of the storage system. The experimental results show that in Cello-92 cases, compared with no prefetching method and sequential prefetching method, prefetching based on UGEP can reduce average I/O response time by 23.7% and 17.9%, and hit ratio is also increased by 16% and 8% as well.

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Callahan, David, Ken Kennedy, and Allan Porterfield. "Software prefetching." ACM SIGPLAN Notices 26, no. 4 (1991): 40–52. http://dx.doi.org/10.1145/106973.106979.

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Callahan, David, Ken Kennedy, and Allan Porterfield. "Software prefetching." ACM SIGOPS Operating Systems Review 25, Special Issue (1991): 40–52. http://dx.doi.org/10.1145/106974.106979.

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Callahan, David, Ken Kennedy, and Allan Porterfield. "Software prefetching." ACM SIGARCH Computer Architecture News 19, no. 2 (1991): 40–52. http://dx.doi.org/10.1145/106975.106979.

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Gschwind, Michael K., and Thomas J. Pietsch. "Vector prefetching." ACM SIGARCH Computer Architecture News 23, no. 5 (1995): 1–7. http://dx.doi.org/10.1145/218328.218329.

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Dissertations / Theses on the topic "Prefetching"

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Lee, Vivian Tin-Wai. "User directed prefetching." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/MQ57760.pdf.

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Lee, Vivian Tin-Wai 1972 Carleton University Dissertation Computer Science. "User directed prefetching." Ottawa.:, 2000.

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Kimbrel, Tracy. "Parallel prefetching and caching /." Thesis, Connect to this title online; UW restricted, 1997. http://hdl.handle.net/1773/6943.

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FIGUEROA, AMPARITO ALEXANDRA MORALES. "PREFETCHING CONTENT IN MULTIMEDIA PRESENTATIONS." PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO, 2014. http://www.maxwell.vrac.puc-rio.br/Busca_etds.php?strSecao=resultado&nrSeq=24285@1.

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PONTIFÍCIA UNIVERSIDADE CATÓLICA DO RIO DE JANEIRO<br>COORDENAÇÃO DE APERFEIÇOAMENTO DO PESSOAL DE ENSINO SUPERIOR<br>PROGRAMA DE EXCELENCIA ACADEMICA<br>Quando entregamos e apresentamos aplicações multimídia por meio de uma rede de comunicação, a latência de exibição pode representar um fator central e crítico que afeta a qualidade da apresentação multimídia. Na entrega de uma apresentação multimídia de boa qualidade o sincronismo é prevalecido, consequentemente, os conteúdos são exibidos de forma contínua, conforme as especificações do autor da aplicação. Nesta tese, um plano de pré-busca de conteúdos multimídia é proposto com o intuito de reduzir a latência de exibição e garantir o sincronismo entre os objetos de mídia que fazem parte da apresentação multimídia. O mecanismo proposto considera as aplicações multimídia desenvolvidas na linguagem declarativa NCL e utiliza a vantagem do sincronismo estar baseado em eventos, na determinação da ordem adequada de recuperação dos diferentes objetos de mídia e no cálculo dos seus tempos de início de recuperação. Aspectos importantes a serem considerados em um ambiente de pré-busca são levantados e os diferentes algoritmos que compõem o plano de pré-busca são desenvolvidos.<br>When delivering and presenting multimedia applications through a communication network, the presentation lag could be a major and critical factor affecting the multimedia presentation quality. In a good quality presentation the synchronism is always preserved, hence all the contents are presented in a continue way according to the authoring specifications. In this dissertation, a multimedia content prefetching plan is proposed in order to minimize the presentation lag and guarantee the synchronism between the media objects, which constitute the multimedia application. The proposed mechanism regards the multimedia applications developed using the NCL declarative language and it uses the events based synchronism advantage to determinate the ideal retrieval order of the media objects and to calculate their start retrieval times. Furthermore, important issues to be considered in a prefetch ambient are raised and the different algorithms that belong to the prefetching plan are developed.

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Charmchi, Niloofar. "Compressed cache layout aware prefetching." Thesis, Rennes 1, 2020. http://www.theses.fr/2020REN1S017.

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Le fossé de vitesse entre le processeur et la mémoire dégrade la performance. La compression de cache et le préchargement matériel sont deux techniques qui pourraient éviter ce goulet d'étranglement en diminuant les échecs du dernier niveau de cache. Pourtant, la compression et le préchargement ont des interactions positives, car le préchargement bénéficie d'une capacité de cache plus élevée et la compression augmente la taille effective du cache. Cette étude propose Compressed cache Layout Aware Prefetching (CLAP) pour exploiter les schémas de cache sectoriels compressés, comme SCC ou YACC, pour créer une synergie entre les caches compressés et le préchargement. L'idée de cette approche est de précharger des blocs contigus qui peuvent être compressés et co-alloués ensemble avec le bloc demandé sur un défaut de cache. Les blocs préchargés qui partagent le stockage avec les blocs existants n'ont pas besoin d'expulser une entrée existante valide; par conséquent, CLAP évite la pollution de cache. Afin de choisir les blocs co-allouables à précharger, nous proposons un prédicteur de compression. Sur nos évaluations expérimentales, CLAP réduit le nombre de défauts de cache de 9% et améliore les performances de 3% en moyenne, par rapport à un cache compressé. De plus, afin d'obtenir plus d'améliorations, nous unifions CLAP et d'autres politiques de préchargement et introduisons deux CLAP adaptatifs qui sélectionnent le meilleur politique de préchargement selon l'application<br>The speed gap between CPU and memory is impairing performance. Cache compression and hardware prefetching are two techniques that could confront this bottleneck by decreasing last level cache misses. However, compression and prefetching have positive interactions, as prefetching benefits from higher cache capacity and compression increases the effective cache size. This study proposes Compressed cache Layout Aware Prefetching (CLAP) to leverage the recently proposed sector-based compressed cache layouts, such as SCC or YACC, to create a synergy between compressed caches and prefetching. The idea of this approach is to prefetch contiguous blocks that can be compressed and co-allocated together with the requested block on a miss access. Prefetched blocks that share storage with existing blocks do not need to evict a valid existing entry; therefore, CLAP avoids cache pollution. In order to decide the co-allocatable blocks to prefetch, we propose a compression predictor. Based on our experimental evaluations, CLAP reduces the number of cache misses by 9% and improves performance by 3% on average, comparing to a compressed cache. Furthermore, in order to get more improvements, we unify CLAP and other prefetchers and introduce two adaptive CLAPs which select the best prefetcher based on the application

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Sharma, Mayank. "PERFORMANCE EVALUATION OF AN ENHANCED POPULARITY-BASED WEB PREFETCHING TECHNIQUE." University of Akron / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=akron1164053047.

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Touma, Rizkallah. "Computer-language based data prefetching techniques." Doctoral thesis, Universitat Politècnica de Catalunya, 2019. http://hdl.handle.net/10803/665207.

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Data prefetching has long been used as a technique to improve access times to persistent data. It is based on retrieving data records from persistent storage to main memory before the records are needed. Data prefetching has been applied to a wide variety of persistent storage systems, from file systems to Relational Database Management Systems and NoSQL databases, with the aim of reducing access times to the data maintained by the system and thus improve the execution times of the applications using this data. However, most existing solutions to data prefetching have been based on information that can be retrieved from the storage system itself, whether in the form of heuristics based on the data schema or data access patterns detected by monitoring access to the system. There are multiple disadvantages of these approaches in terms of the rigidity of the heuristics they use, the accuracy of the predictions they make and / or the time they need to make these predictions, a process often performed while the applications are accessing the data and causing considerable overhead. In light of the above, this thesis proposes two novel approaches to data prefetching based on predictions made by analyzing the instructions and statements of the computer languages used to access persistent data. The proposed approaches take into consideration how the data is accessed by the higher-level applications, make accurate predictions and are performed without causing any additional overhead. The first of the proposed approaches aims at analyzing instructions of applications written in object-oriented languages in order to prefetch data from Persistent Object Stores. The approach is based on static code analysis that is done prior to the application execution and hence does not add any overhead. It also includes various strategies to deal with cases that require runtime information unavailable prior to the execution of the application. We integrate this analysis approach into an existing Persistent Object Store and run a series of extensive experiments to measure the improvement obtained by prefetching the objects predicted by the approach. The second approach analyzes statements and historic logs of the declarative query language SPARQL in order to prefetch data from RDF Triplestores. The approach measures two types of similarity between SPARQL queries in order to detect recurring query patterns in the historic logs. Afterwards, it uses the detected patterns to predict subsequent queries and launch them before they are requested to prefetch the data needed by them. Our evaluation of the proposed approach shows that it high-accuracy prediction and can achieve a high cache hit rate when caching the results of the predicted queries.<br>Precargar datos ha sido una de las técnicas más comunes para mejorar los tiempos de acceso a datos persistentes. Esta técnica se basa en predecir los registros de datos que se van a acceder en el futuro y cargarlos del almacenimiento persistente a la memoria con antelación a su uso. Precargar datos ha sido aplicado en multitud de sistemas de almacenimiento persistente, desde sistemas de ficheros a bases de datos relacionales y NoSQL, con el objetivo de reducir los tiempos de acceso a los datos y por lo tanto mejorar los tiempos de ejecución de las aplicaciones que usan estos datos. Sin embargo, la mayoría de los enfoques existentes utilizan predicciones basadas en información que se encuentra dentro del mismo sistema de almacenimiento, ya sea en forma de heurísticas basadas en el esquema de los datos o patrones de acceso a los datos generados mediante la monitorización del acceso al sistema. Estos enfoques presentan varias desventajas en cuanto a la rigidez de las heurísticas usadas, la precisión de las predicciones generadas y el tiempo que necesitan para generar estas predicciones, un proceso que se realiza con frecuencia mientras las aplicaciones acceden a los datos y que puede tener efectos negativos en el tiempo de ejecución de estas aplicaciones. En vista de lo anterior, esta tesis presenta dos enfoques novedosos para precargar datos basados en predicciones generadas por el análisis de las instrucciones y sentencias del lenguaje informático usado para acceder a los datos persistentes. Los enfoques propuestos toman en consideración cómo las aplicaciones acceden a los datos, generan predicciones precisas y mejoran el rendimiento de las aplicaciones sin causar ningún efecto negativo. El primer enfoque analiza las instrucciones de applicaciones escritas en lenguajes de programación orientados a objetos con el fin de precargar datos de almacenes de objetos persistentes. El enfoque emplea análisis estático de código hecho antes de la ejecución de las aplicaciones, y por lo tanto no afecta negativamente el rendimiento de las mismas. El enfoque también incluye varias estrategias para tratar casos que requieren información de runtime no disponible antes de ejecutar las aplicaciones. Además, integramos este enfoque en un almacén de objetos persistentes y ejecutamos una serie extensa de experimentos para medir la mejora de rendimiento que se puede obtener utilizando el enfoque. Por otro lado, el segundo enfoque analiza las sentencias y logs del lenguaje declarativo de consultas SPARQL para precargar datos de triplestores de RDF. Este enfoque aplica dos medidas para calcular la similtud entre las consultas del lenguaje SPARQL con el objetivo de detectar patrones recurrentes en los logs históricos. Posteriormente, el enfoque utiliza los patrones detectados para predecir las consultas siguientes y precargar con antelación los datos que necesitan. Nuestra evaluación muestra que este enfoque produce predicciones de alta precisión y puede lograr un alto índice de aciertos cuando los resultados de las consultas predichas se guardan en el caché.

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Grannæs, Marius. "Bandwidth-Aware Prefetching in Chip Multiprocessors." Thesis, Norwegian University of Science and Technology, Department of Computer and Information Science, 2006. http://urn.kb.se/resolve?urn=urn:nbn:no:ntnu:diva-10115.

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<p>Chip Multiprocessors (CMP) are an increasingly popular architecture and increasing numbers of vendors are now offering CMP solutions. The shift to CMP architectures from uniprocessors is driven by the increasing complexity of cores, the processor-memory performance gap, limitations in ILP and increasing power requirements. Prefetching is a successful technique commonly used in high performance processors to hide latency. In a CMP, prefetching offers new opportunities and challenges, as current uniprocessor heuristics will need adaption or redesign to integrate with CMPs. In this thesis, I look at the state of the art in prefetching and CMP architecture. I conduct experiments on how unmodified uniprocessor prefetching heuristics perform in a CMP. In addition, I have proposed a new prefetching scheme based on bandwidth monitoring and prediction through performance counters, suited for embedded CMP systems. This new prefetching scheme has been simulated with SimpleScalar. It offers lower bandwidth usage (up to 47.8 %), while retaining most of the performance gains from prefetching for low accuracy prefetching heuristics.</p>

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Cevikbas, Safak Burak. "Visibility Based Prefetching With Simulated Annealing." Master's thesis, METU, 2008. http://etd.lib.metu.edu.tr/upload/12609324/index.pdf.

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Complex urban scene rendering is not feasible without culling invisible geometry before the rendering actually takes place. Visibility culling can be performed on predefined regions of scene where for each region a potential visible set of scene geometry is computed. Rendering cost is reduced since instead of a bigger set only a single PVS which is associated with the region of the viewer is rendered. However, when the viewer leaves a region and enters one of its neighbors, disposing currently loaded PVS and loading the new PVS causes stalls. Prefetching policies are utilized to overcome stalls by loading PVS of a region before the viewer enters it. This study presents a prefetching method for interactive urban walkthroughs. Regions and transitions among them are represented as a graph where the regions are the nodes and transitions are the edges. Groups of nodes are formed according to statistical data of transitions and used as the prefetching policy. Some heuristics for constructing groups of nodes are developed and Simulated Annealing is utilized for constructing optimized groups based on developed heuristics. The proposed method and underlying application of Simulated Annealing are customized for minimizing average transition cost.

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Palpanas, Themistoklis. "Web prefetching using partial match prediction." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape10/PQDD_0022/MQ40748.pdf.

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Books on the topic "Prefetching"

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Palpanas, Themistoklis. Web prefetching using partial match prediction. University of Toronto, Dept. of Computer Science, 1998.

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Burdorf, Christopher. Prefetching simulation objects in a persistent simulation environment. Rand Corp., 1989.

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Ebiary, Mohamed El. History guided prefetching in a telephone switching application. National Library of Canada, 1994.

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Demke, Angela K. Automatic I/O prefetching for out-of-core applications. National Library of Canada = Bibliothèque nationale du Canada, 1999.

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Chan, Charles Quoc Cuong. Tolerating latency in software distributed shared memory systems through non-binding prefetching. University of Toronto, Dept. of Computer Science, 1998.

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Wenisch, Thomas F., and Babak Falsafi. Primer on Hardware Prefetching. Morgan & Claypool Publishers, 2014.

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Wenisch, Thomas F., and Babak Falsafi. Primer on Hardware Prefetching. Springer International Publishing AG, 2014.

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Wenisch, Thomas F., and Babak Falsafi. Primer on Hardware Prefetching. Morgan & Claypool Publishers, 2014.

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Esfahbod, Behdad. Preload: An adaptive prefetching Daemon. 2006.

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Wong, Gordon. Web prefetching with client clustering. 2004.

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Book chapters on the topic "Prefetching"

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Falsafi, Babak, and Thomas F. Wenisch. "Instruction Prefetching." In A Primer on Hardware Prefetching. Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-031-01743-8_2.

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Ji, Rongju, and Haoqi Ren. "A New Prefetching Unit for Digital Signal Processor." In Proceeding of 2021 International Conference on Wireless Communications, Networking and Applications. Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2456-9_94.

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AbstractIn this paper, a new structure of instruction prefetching unit is proposed. The prefetching is achieved by building the relationship between the branch source and its branch target and the relationship between the branch target and the first branch in its following instruction sequence. With the help of the proposed structure, it is easy to know whether the instruction block of branch target blocks exist in the instruction cache based on the recorded branch information. The two-level depth target prefetching can be performed to eliminate or reduce the instruction cache miss penalty. Experimental results demonstrate that the proposed instruction prefetching scheme can achieve lower cache miss rate and miss penalty than the traditional next-line prefetching technique.

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Wong, Weng-Fai. "Targeted Data Prefetching." In Advances in Computer Systems Architecture. Springer Berlin Heidelberg, 2005. http://dx.doi.org/10.1007/11572961_63.

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Buyuktanir, Tolga, and Mehmet S. Aktas. "Mobile Prefetching and Web Prefetching: A Systematic Literature Review." In Computational Science and Its Applications – ICCSA 2022 Workshops. Springer International Publishing, 2022. http://dx.doi.org/10.1007/978-3-031-10545-6_6.

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Manoharan, Sathiamoorthy, and Chaitanya Reddy Yavasani. "Experiments with Sequential Prefetching." In High-Performance Computing and Networking. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-48228-8_33.

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Kim, See-Mu, and S. Manoharan. "Data Prefetching Using Dual Processors." In The Kluwer International Series in Engineering and Computer Science. Springer US, 2002. http://dx.doi.org/10.1007/978-1-4615-0849-6_15.

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Ramos, Luis M., José Luis Briz, Pablo E. Ibáñez, and Víctor Viñals. "Low-Cost Adaptive Data Prefetching." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2008. http://dx.doi.org/10.1007/978-3-540-85451-7_36.

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Manoharan, S. "Data prefetching for digital alpha." In High-Performance Computing and Networking. Springer Berlin Heidelberg, 1999. http://dx.doi.org/10.1007/bfb0100678.

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Stoutchinin, Artour, José Nelson Amaral, Guang R. Gao, James C. Dehnert, Suneel Jain, and Alban Douillet. "Speculative Prefetching of Induction Pointers." In Lecture Notes in Computer Science. Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/3-540-45306-7_20.

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Pang, Zhengyuan, Lifeng Sun, Zhi Wang, Yuan Xie, and Shiqiang Yang. "Understanding Performance of Edge Prefetching." In MultiMedia Modeling. Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-51811-4_43.

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Conference papers on the topic "Prefetching"

1

Nath, Sumon, Agustin Navarro-Torres, Alberto Ros, and Biswabandan Panda. "Secure Prefetching for Secure Cache Systems." In 2024 57th IEEE/ACM International Symposium on Microarchitecture (MICRO). IEEE, 2024. https://doi.org/10.1109/micro61859.2024.00017.

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Negi, Anurag, Adrià Armejach, Adrián Cristal, Osman S. Unsal, and Per Stenstrom. "Transactional prefetching." In the 21st international conference. ACM Press, 2012. http://dx.doi.org/10.1145/2370816.2370844.

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Callahan, David, Ken Kennedy, and Allan Porterfield. "Software prefetching." In the fourth international conference. ACM Press, 1991. http://dx.doi.org/10.1145/106972.106979.

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Chen, Chao-Chun, Chiang Lee, Chun-Chiang Wang, and Yu-Chi Chung. "Prefetching LDD." In Proceeding of the 2006 international conference. ACM Press, 2006. http://dx.doi.org/10.1145/1143549.1143770.

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Cantin, Jason F., Mikko H. Lipasti, and James E. Smith. "Stealth prefetching." In the 12th international conference. ACM Press, 2006. http://dx.doi.org/10.1145/1168857.1168892.

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Fuchs, Adi, and Ruby B. Lee. "Disruptive prefetching." In SYSTOR 2015: International Conference on Systems and Storage. ACM, 2015. http://dx.doi.org/10.1145/2757667.2757672.

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Jégou, Y., and O. Temam. "Speculative prefetching." In the 7th international conference. ACM Press, 1993. http://dx.doi.org/10.1145/165939.165954.

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Manikantan, R., and R. Govindarajan. "Focused prefetching." In the 22nd annual international conference. ACM Press, 2008. http://dx.doi.org/10.1145/1375527.1375576.

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Pinto, Raquel Gomes, Ricardo Bianchini, and Claudio Luis de Amorim. "Avaliando Técnicas de Prefetching para Software DSMs." In International Symposium on Computer Architecture and High Performance Computing. Sociedade Brasileira de Computação, 1996. http://dx.doi.org/10.5753/sbac-pad.1996.19814.

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Abstract:

Sistemas de memória compartilhada distribuída com coerência de dados mantida por software, denominados software DSMs, oferecem a facilidade de programação do modelo de memória compartilhada com o baixo custo das arquiteturas de memória distribuída. No entanto, são poucas as classes de aplicações que alcançam um bom desempenho nesses sistemas. Um dos maiores problemas com software DSMs é o overhead da busca de dados remotos, que ocorre no caminho crítico da computação. Neste artigo propomos três técnicas de prefetching que antecipam essa busca. Analisamos o impacto das técnicas de prefetching no desempenho de TreadMarks, usando simulações detalhadas de aplicações reais. Nossos experimentos mostram que o uso dessas técnicas reduz a latência de acesso a dados, mas aumenta o tempo de sincronização e a interferência da busca dos dados com a computação nos processadores remotos. Nossos resultados mostram também que a obtenção de ganhos de desempenho através de prefetching depende de um suporte de hardware que diminua a interferência em processadores remotos; duas das aplicações que estudamos obtiveram ganhos de 22-39% com o auxílio desse hardware especializado.

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10

Khuong, Paul. "Prefetching and Searching." In Applicative 2016. ACM Press, 2016. http://dx.doi.org/10.1145/2959689.2960161.

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Reports on the topic "Prefetching"

1

Chen, Shimin, Phillip B. Gibbons, and Todd C. Mowry. Improving Index Performance through Prefetching. Defense Technical Information Center, 2000. http://dx.doi.org/10.21236/ada397030.

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Halvic, Ian William. Improving Capsaicin Sweep Performance Using Memory Prefetching. Office of Scientific and Technical Information (OSTI), 2018. http://dx.doi.org/10.2172/1467295.

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Patterson, R. H., and Garth A. Gibson. A Status Report on Research in Transparent Informed Prefetching. Defense Technical Information Center, 1993. http://dx.doi.org/10.21236/ada265417.

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Mowry, Todd C., and Chi-Keung Luk. Compiler and Hardware Support for Automatic Instruction Prefetching: A Cooperative Approach. Defense Technical Information Center, 1998. http://dx.doi.org/10.21236/ada352369.

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5

Bianchini, Ricardo, and Thomas J. LeBlanc. A Preliminary Evaluation of Cache-Miss-Initiated Prefetching Techniques in Scalable Multiprocessors. Defense Technical Information Center, 1994. http://dx.doi.org/10.21236/ada281502.

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