Academic literature on the topic 'Prefetch techniques'
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Journal articles on the topic "Prefetch techniques"
VERMA, SANTHOSH, and DAVID M. KOPPELMAN. "THE INTERACTION AND RELATIVE EFFECTIVENESS OF HARDWARE AND SOFTWARE DATA PREFETCH." Journal of Circuits, Systems and Computers 21, no. 02 (April 2012): 1240002. http://dx.doi.org/10.1142/s0218126612400026.
Full textAlves, Ricardo, Stefanos Kaxiras, and David Black-Schaffer. "Early Address Prediction." ACM Transactions on Architecture and Code Optimization 18, no. 3 (June 2021): 1–22. http://dx.doi.org/10.1145/3458883.
Full textLiang, Ye. "Big Data Storage Method in Wireless Communication Environment." Advanced Materials Research 756-759 (September 2013): 899–904. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.899.
Full textHariharan, I., and M. Kannan. "Efficient Use of On-Chip Memories and Scheduling Techniques to Eliminate the Reconfiguration Overheads in Reconfigurable Systems." Journal of Circuits, Systems and Computers 28, no. 14 (March 15, 2019): 1950246. http://dx.doi.org/10.1142/s0218126619502463.
Full textLi, Haoyu, Qizhi Chen, Yixin Zhang, Tong Yang, and Bin Cui. "Stingy sketch." Proceedings of the VLDB Endowment 15, no. 7 (March 2022): 1426–38. http://dx.doi.org/10.14778/3523210.3523220.
Full textNATARAJAN, RAGAVENDRA, VINEETH MEKKAT, WEI-CHUNG HSU, and ANTONIA ZHAI. "EFFECTIVENESS OF COMPILER-DIRECTED PREFETCHING ON DATA MINING BENCHMARKS." Journal of Circuits, Systems and Computers 21, no. 02 (April 2012): 1240006. http://dx.doi.org/10.1142/s0218126612400063.
Full textLamela, Adrián, Óscar G. Ossorio, Guillermo Vinuesa, and Benjamín Sahelices. "Off-chip prefetching based on Hidden Markov Model for non-volatile memory architectures." PLOS ONE 16, no. 9 (September 14, 2021): e0257047. http://dx.doi.org/10.1371/journal.pone.0257047.
Full textSasongko, Muhammad Aditya, Milind Chabbi, Mandana Bagheri Marzijarani, and Didem Unat. "ReuseTracker : Fast Yet Accurate Multicore Reuse Distance Analyzer." ACM Transactions on Architecture and Code Optimization 19, no. 1 (March 31, 2022): 1–25. http://dx.doi.org/10.1145/3484199.
Full textLee, Minsuk, Sang Lyul Min, and Chong Sang Kim. "A worst case timing analysis technique for instruction prefetch buffers." Microprocessing and Microprogramming 40, no. 10-12 (December 1994): 681–84. http://dx.doi.org/10.1016/0165-6074(94)90017-5.
Full textShyamala, K., and S. Kalaivani. "Application of Monte Carlo Search for Performance Improvement of Web Page Prediction." International Journal of Engineering & Technology 7, no. 3.4 (June 25, 2018): 133. http://dx.doi.org/10.14419/ijet.v7i3.4.16761.
Full textDissertations / Theses on the topic "Prefetch techniques"
Chang, Nelson Yen-Chung, and 張彥中. "Cache Prefetch Techniques and Bus Bridge Design in SOC." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/01054116522540066658.
Full text國立交通大學
電子工程系
90
Cache prefetching has long been known in reducing cache miss rate, and in hiding memory access latencies seen by the processor in a processor-based system. This provides a chance to implement a smaller cache with prefetch mechanism to achieve same miss rate with larger cache without prefetching, hence reducing the cache hardware cost. Though reducing the miss rate improves the performance of a cache, the extra prefetch memory requests increases the overall system bus traffics. The increased bus traffic sometimes diminishes the overall performance of a system, even with the reduced miss rate. In an embedded SOC system, there are more devices that access through the shared system bus. Therefore the heavy traffic of the system bus will limit the benefits of applying cache prefetching techniques to an embedded system. Since the hardware prefetching approach takes the advantage of run-time information, and can take the system bus status into consideration, it is more suitable for embedded systems with multiple master devices. In this thesis, we investigate the characteristics of several hardware cache prefetching techniques. Then we proposed a new cache prefetching named reference time stride prefetch (RTSP) scheme incorporating access timing information, and a system bus bridge design with access reordering for the processor to solve the bus congestion problem. The effect of each relevant parameters and how the prefetching affects an embedded system are revealed by running cycle-by-cycle trace-driven simulations of an embedded system model with an ARM7TDMI core and AHB system bus. The simulation result shows that RTSP can reduce 8.8% of average data reference time and more than 90% of data miss rate compared with an unprefetched system.
Jen, Hsung, and 任軒. "Reconfiguration Overhead Reduction Using Prefetch and Merge Techniques in Run-Time Reconfigurable System." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/21085391635759437079.
Full textHuang, Hsuan-Woei, and 黃宣偉. "A Study on Prefetch and Compiler Assistant Techniques for Clustering Multiprocessor System Design and Implementation of Its Simulation and Evaluation Environment." Thesis, 1998. http://ndltd.ncl.edu.tw/handle/20226792088898404435.
Full text國立交通大學
資訊工程學系
86
Recently, shared-memory multiprocessor systems have become one of the design trends in computer system architectures. As the increasingly need of computation, multiprocessor system with more processors on it becomes an unavoidable trend. Thus, clustering multiprocessor system has indeed played an important role due to its high scalability and data locality. We had developed a simulation and evaluation environment for clustering multiprocessor system, which aims at investigating the key design issues of its memory subsystem. Our environment is a program-driven simulator, consisting of a memory reference generator supported by MINT and a memory subsystem simulator that we have designed. The memory subsystem simulator can support several simulation modules, including two- level cache, local bus, inter-cluster cache, cache coherence protocols, and interconnection network. With the aid of this environment, we had studied major design issues of clustering multiprocessor system, including data prefetching and parallel compiler assistant techniques. Based on a great deal of evaluation results, we have found that clustering may have good scalability compared with non-clustering architectures. By the way, the size of cluster node and related issues are also investigated. Moreover, data prefetching techniques boost the performance gain in clustering multiprocessor system, especially with our clus-prefetch and combined-prefetch design. Besides, we also provide some assistant techniques for parallel compiler to improve performance of clustering multiprocessor system in some degree.
Cai, Jie. "Region-based techniques for modeling and enhancing cluster OpenMP performance." Phd thesis, 2011. http://hdl.handle.net/1885/8865.
Full textBook chapters on the topic "Prefetch techniques"
Hong, Maria, Euisun Kang, Sungmin Um, Dongho Kim, and Younghwan Lim. "A Transcode and Prefetch Technique of Multimedia Presentations for Mobile Terminals." In Computational Science and Its Applications – ICCSA 2004, 57–64. Berlin, Heidelberg: Springer Berlin Heidelberg, 2004. http://dx.doi.org/10.1007/978-3-540-24707-4_8.
Full textGupta, Ajay Kumar, and Udai Shanker. "An Efficient Markov Chain Model Development based Prefetching in Location-Based Services." In Privacy and Security Challenges in Location Aware Computing, 109–25. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-7756-1.ch005.
Full textHuang, Shi-Ming, Binshan Lin, and Qun-Shi Deng. "Intelligent Cache Management for Mobile Data Warehouse Systems." In Data Warehousing and Mining, 1539–56. IGI Global, 2008. http://dx.doi.org/10.4018/978-1-59904-951-9.ch088.
Full textMacmaster, Neil. "The Arzew Camp." In War in the Mountains, 402–25. Oxford University Press, 2020. http://dx.doi.org/10.1093/oso/9780198860211.003.0019.
Full textPrakash, Amit. "Imperial Sentinels." In Empire on the Seine, 89–128. Oxford University Press, 2022. http://dx.doi.org/10.1093/oso/9780192898876.003.0005.
Full textFleming, James R. "Joseph Fourier’s Theory of Terrestrial Temperatures." In Historical Perspectives on Climate Change. Oxford University Press, 1998. http://dx.doi.org/10.1093/oso/9780195078701.003.0010.
Full textConference papers on the topic "Prefetch techniques"
Heirman, Wim, Kristof Du Bois, Yves Vandriessche, Stijn Eyerman, and Ibrahim Hur. "Near-side prefetch throttling." In PACT '18: International conference on Parallel Architectures and Compilation Techniques. New York, NY, USA: ACM, 2018. http://dx.doi.org/10.1145/3243176.3243181.
Full textCai, Jie, Peter E. Strazdins, and Alistair P. Rendell. "Region-Based Prefetch Techniques for Software Distributed Shared Memory Systems." In 2010 10th IEEE/ACM International Conference on Cluster, Cloud and Grid Computing. IEEE, 2010. http://dx.doi.org/10.1109/ccgrid.2010.16.
Full textHoltryd, Nadja Ramhoj, Madhavan Manivannan, Per Stenstrom, and Miquel Pericas. "CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling." In 2021 30th International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2021. http://dx.doi.org/10.1109/pact52795.2021.00023.
Full textQu, Wenxin, Xiaoya Fan, Ying Hu, Yong Xia, and Fuyuan Hu. "New Prefetch Technique Design for L2 Cache." In TENCON 2006 - 2006 IEEE Region 10 Conference. IEEE, 2006. http://dx.doi.org/10.1109/tencon.2006.344002.
Full textChoi, Hong Jun, Dong Oh Son, Cheol Hong Kim, and Jong Myron Kim Kim. "A Novel Prefetch Technique for High Performance Embedded System." In 2014 International Conference on IT Convergence and Security (ICITCS). IEEE, 2014. http://dx.doi.org/10.1109/icitcs.2014.7021713.
Full textYuan He, Hiroshi Sasaki, Shinobu Miwa, and Hiroshi Nakamura. "TCPT: thread criticality-driven prefetcher throttling." In 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2013. http://dx.doi.org/10.1109/pact.2013.6618828.
Full textPanda, Biswabandan, and Shankar Balachandran. "TCPT - Thread criticality-driven prefetcher throttling." In 2013 22nd International Conference on Parallel Architectures and Compilation Techniques (PACT). IEEE, 2013. http://dx.doi.org/10.1109/pact.2013.6618835.
Full textCai, Jie, and Peter E. Strazdins. "An Accurate Prefetch Technique for Dynamic Paging Behaviour for Software Distributed Shared Memory." In 2012 41st International Conference on Parallel Processing (ICPP). IEEE, 2012. http://dx.doi.org/10.1109/icpp.2012.16.
Full textIrie, Hidetsugu, Takefumi Miyoshi, Goki Honjo, Kei Hiraki, and Tsutomu Yoshinaga. "CCCPO: Robust Prefetcher Optimization Technique Based on Cache Convection." In 2011 Second International Conference on Networking and Computing (ICNC). IEEE, 2011. http://dx.doi.org/10.1109/icnc.2011.26.
Full textCappelli, Luigi. "Vernacular architecture on archaeological remains. Conservation and enhancement of the “Villa San Limato” in Cellole." In HERITAGE2022 International Conference on Vernacular Heritage: Culture, People and Sustainability. Valencia: Universitat Politècnica de València, 2022. http://dx.doi.org/10.4995/heritage2022.2022.14365.
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