Relevant bibliographies by topics / Pre-silicon evaluation

Academic literature on the topic 'Pre-silicon evaluation'

Author: Grafiati
Published: 1 June 2024

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Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Book chapters
  4. Conference papers

Journal articles on the topic "Pre-silicon evaluation":

1

Radue, C., and E. E. van Dyk. "Pre-deployment evaluation of amorphous silicon photovoltaic modules." Solar Energy Materials and Solar Cells 91, no. 2-3 (January 2007): 129–36. http://dx.doi.org/10.1016/j.solmat.2006.07.007.

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Latukhina, N. V., D. A. Pisarenko, A. V. Volkov, and V. A. Kitaeva. "PHOTOSENSITIVE MATRIX BASED ON POROUS MICROCRYSTALLINE SILICON." Vestnik of Samara University. Natural Science Series 17, no. 5 (June 14, 2017): 115–21. http://dx.doi.org/10.18287/2541-7525-2011-17-5-115-121.

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The article presents the results of experimental researches of optoelectric properties of porous silicon. Layers of porous silicon were formed using electrochemical etching process in water-alcohol solutions of hydrofluoric acid on plates with a pre-established microrelief surface. Evaluation of possibility of using of created structure as the artificial retina component was performed based on the results of the research.
3

Kim, Gyu Hyun, Geun Min Choi, and Young Wook Song. "Evaluation of Wafer Drying Methods for GIGA-LEVEL Device Fabrication." Solid State Phenomena 103-104 (April 2005): 67–70. http://dx.doi.org/10.4028/www.scientific.net/ssp.103-104.67.

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This study deals with drying induced water marks dependency on the last cleaning methods, substrate conditions, and drying pre-step delaying times, which are supposed to become a big issue with down scaling of device geometry. The data show that water marks induced by drying failure increase with increasing contact angle on the various surfaces. They are mainly composed of either silicon oxide only or silicon oxide with organic compounds. The former is removed by a dilute HF and/or hot SC-1 treatment and the latter is removed by organic removal cleaning followed by dilute HF etching.
4

Guilley, Sylvain, Khaled Karray, Thomas Perianin, Ritu-Ranjan Shrivastwa, Youssef Souissi, and Sofiane Takarabt. "Side-Channel Evaluation Methodology on Software." Cryptography 4, no. 4 (September 25, 2020): 27. http://dx.doi.org/10.3390/cryptography4040027.

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Cryptographic implementations need to be robust amidst the widespread use of crypto-libraries and attacks targeting their implementation, such as side-channel attacks (SCA). Many certification schemes, such as Common Criteria and FIPS 140, continue without addressing side-channel flaws. Research works mostly tackle sophisticated attacks with simple use-cases, which is not the reality where end-to-end evaluation is not trivial. In this study we used all due diligence to assess the invulnerability of a given implementation from the shoes of an evaluator. In this work we underline that there are two kinds of SCA: horizontal and vertical. In terms of quotation, measurement and exploitation, horizontal SCA is easier. If traces are constant-time, then vertical attacks become convenient, since there is no need for specific alignment (“value based analysis”). We introduce our new methodology: Vary the key to select sensitive samples, where the values depend upon the key, and subsequently vary the mask to uncover unmasked key-dependent leakage, i.e., the flaws. This can be done in the source code (pre-silicon) for the designer or on the actual traces (post-silicon) for the test-lab. We also propose a methodology for quotations regarding SCA unlike standards that focus on only one aspect (like number of traces) and forgets about other aspects (such as equipment; cf. ISO/IEC 20085-1.
5

Willems, Geert, and Herman Maes. "Evaluation of a Pre-Objective Scan System for the Laser Recrystallization of Silicon on Insulator Material." Japanese Journal of Applied Physics 31, Part 1, No. 8 (August 15, 1992): 2631–39. http://dx.doi.org/10.1143/jjap.31.2631.

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Hossain, Sk Saddam, Soumya Sarkar, Naresh Kr Oraon, and Ashok Ranjan. "Pre-ceramic polymer-derived open/closed cell silicon carbide foam: microstructure, phase evaluation, and thermal properties." Journal of Materials Science 51, no. 21 (July 20, 2016): 9865–78. http://dx.doi.org/10.1007/s10853-016-0220-1.

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Zaman, Muhammad Yousuf, Denis Perrone, Sergio Ferrero, Luciano Scaltrito, and Marco Naretto. "Evaluation of Correct Value of Richardson's Constant by Analyzing the Electrical Behavior of Three Different Diodes at Different Temperatures." Materials Science Forum 711 (January 2012): 174–78. http://dx.doi.org/10.4028/www.scientific.net/msf.711.174.

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Various attempts have been made to evaluate the correct value (A*=146 A/cm2.K2) ofRichardson's constant. In 2005 S. Ferrero et al. published their research in which they performedan analysis of electrical characterizations of twenty Ti/4H-SiC(titanium on silicon carbide) Schottkydiodes with the help of thermionic emission theory and evaluated the value of Richardson's constantto be 17±8 A/cm2.K2; which is very low as compared to the theoretical value of 146 A/cm2.K2.Wehave tried in this paper to evaluate the Richardson's constant's value by nearly same experimental tech-niques followed by S. Ferrero et al. and additionally, have applied Tung's theoretical approach whichdeals with the incorrect value of A* in the perspective of Schottky barrier inhomogeneities caused bythe presence of nanometer size low barrier patches present in the uniform high barrier of the Schottkydiode.We have fabricated two Ti/4H-SiC (titanium on silicon carbide) Schottky diodes with differentareas and oneMo/4H-SiC (molybdenumon silicon carbide) Schottky diode. In this paper we have pre-sented a comparative analysis of forward current-voltage characteristics of all three Schottky diodes.In all three cases we were successful in the evaluation of nearly correct value of Richardson's constant.This work emphasizes the effects of differentmetal-SiC combinations and laboratory environments onthe evaluation of Richardson's constant and the effective area involved in the current transport. As pre-dicted by Tung's model the effective area is seen to be substantially different from the geometric areaof the Schottky diode. Evaluated values of A*, with an error of ±2, come out to be 145.39, 148.33and 148.33 A/cm2.K2for Ti/4H-SiC(large area), Mo/4H-SiC and Ti/4H-SiC(small area) Schottkydiodes, respectively.
8

Radun, V., R. P. von Metzen, T. Stieglitz, V. Bucher, and A. Stett. "Evaluation of adhesion promoters for Parylene C on gold metallization." Current Directions in Biomedical Engineering 1, no. 1 (September 1, 2015): 493–97. http://dx.doi.org/10.1515/cdbme-2015-0118.

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AbstractDelamination of thin film polymeric coatings from metallization layers is a common cause of failure in biomedical implants. To address the problem, different adhesion promotion techniques can be applied which include surface pre-treatment with oxygen and argon plasma and the use of different adhesion promoters. In this paper the applicability of titanium (Ti), silicon oxide (SiOx), diamond-like carbon (DLC), tetramethylsilane (TMS) and aluminium oxide (AlOx) as adhesion promoters is evaluated. A cross cut, peel and scratch test are used to qualify and quantify the adhesion before and after storage in phosphate buffered saline (PBS) for 48 hours at a temperature of 37 °C. Promising results could be achieved by a combination of Ti and DLC as well as by AlOx.
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Shibata, Satoshi, Fumitoshi Kawase, Akihiko Kitada, Takashi Kouzaki, and Akira Kitamura. "Evaluation of Pre-Amorphized Layer Thickness and Interface Quality of High-Dose Shallow Implanted Silicon by Spectroscopic Ellipsometry." IEEE Transactions on Semiconductor Manufacturing 23, no. 4 (November 2010): 545–52. http://dx.doi.org/10.1109/tsm.2010.2072450.

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Galaktionova, L. V., A. M. Korotkova, N. A. Terekhova, N. I. Voskobulova, and S. V. Lebedev. "Evaluation of the use of silicon and iron nanoform for pre-sowing treatment of <i>Pisum sativum</i> seeds." Agrarian science, no. 12 (January 18, 2023): 81–86. http://dx.doi.org/10.32634/0869-8155-2022-365-12-81-86.

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Relevance. Modern plant growing technologies are associated with the use of nanoparticles for pre-sowing seed treatment. The article presents the results of studying the effect of pre-sowing treatment of Pisum sativum seeds with solutions of iron and silicon nanooxides on the germination, viability and yield of plants in the conditions of the Southern Ural. Methods. For pre-sowing treatment of seeds, solutions of nanoparticles of SiO2 and Fe3O4 were used at a concentration of 10–2, 10–3 and 10–4 mg/l, as well as a solution of mixture of two oxides. Cell viability was assessed by the method of Vijayaraghavaraddy, superoxide dismutase activity was determined by Giannopolitis and Ries, catalase, lipid peroxidation and malondialdehyde content – by Heath and Packer, and the fractional composition of proteins in seeds – by Chen. Results. Determination of the germination of P. sativum showed a significant stimulation of seed germination and an increase in catalase activity when seeds were treated with SiO2 in two concentrations (up to 83 % and 146 %), Fe3O4 (up to 111 %) and Fe3O4 + SiO2 (up to 47 %). A decrease in the content of malonic dialdehyde due to the treatment with SiO2 and its mixture with Fe3O4 (up to 40 %) was noted. Against the background of the use of nanoparticles for pre-sowing seed treatment, the composition of the protein complex changed due to an increase in the pool of albumins by 88 % and a decrease in the content of globulins down to 9,8 %.
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Journal articles

Dissertations / Theses on the topic "Pre-silicon evaluation":

1

Yao, Yuan. "Towards Comprehensive Side-channel Resistant Embedded Systems." Diss., Virginia Tech, 2021. http://hdl.handle.net/10919/104662.

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Embedded devices almost involve every part of our lives, such as health condition monitoring, communicating with other people, traveling, financial transactions, etc. Within the embedded devices, our private information is utilized, collected and stored. Cryptography is the security mechanism within the embedded devices for protecting this secret information. However, cryptography algorithms can still be analyzed and attacked by malicious adversaries to steal secret data. There are different categories of attacks towards embedded devices, and the side-channel attack is one of the powerful attacks. Unlike analyzing the vulnerabilities within the cryptography algorithm itself in traditional attacks, the side-channel attack observes the physical effect signals while the cryptography algorithm runs on the device. These physical effects include the power consumption of the devices, timing, electromagnetic radiations, etc., and we call these physical effects that carry secret information side-channel leakage. By statistically analyzing these side-channel leakages, an attacker can reconstruct the secret information. The manifestation of side-channel leakage happens at the hardware level. Therefore, the designer has to ensure that the hardware design of the embedded system is secure against side-channel attacks. However, it is very arduous work. An embedded systems design including a large number of electronic components makes it very difficult to comprehensively capture every side-channel vulnerability, locate the root cause of the side-channel leakage, and efficiently fix the vulnerabilities. In this dissertation, we developed methodologies that can help designers detect and fix side-channel vulnerabilities within the embedded system design at low cost and early design stage.
Doctor of Philosophy
Side-channel leakage, which reveals the secret information from the physical effects of computing secret variables, has become a serious vulnerability in secure hardware and software implementations. In side-channel attacks, adversaries passively exploit variations such as power consumption, timing, and electromagnetic emission during the computation with secret variables to retrieve sensitive information. The side-channel attack poses a practical threat to embedded devices, an embedded device's cryptosystem without adequate protection against side-channel leakage can be easily broken by the side-channel attack. In this dissertation, we investigate methodologies to build up comprehensive side-channel resistant embedded systems. However, this is challenging because of the complexity of the embedded system. First, an embedded system integrates a large number of components. Even if the designer can make sure that each component is protected within the system, the integration of the components will possibly introduce new vulnerabilities. Second, the existing side-channel leakage evaluation of embedded system design happens post-silicon and utilizes the measurement on the prototype of the taped-out chip. This is too late for mitigating the vulnerability in the design. Third, due to the complexity of the embedded system, even though the side-channel leakage is detected, it is very hard to precisely locate the root cause within the design. Existing side-channel attack countermeasures are very costly in terms of design overhead. Without a method that can precisely identify the side-channel leakage source within the design, huge overhead will be introduced by blindly add the side-channel countermeasure to the whole design. To make the challenge even harder, the Power Distribution Network (PDN) where the hardware design locates is also vulnerable to side-channel attacks. It has been continuously demonstrated by researchers that attackers can place malicious circuits on a shared PDN with victim design and open the opportunities for the attackers to inject faults or monitoring power changes of the victim circuit. In this dissertation, we address the challenges mentioned above in designing a side-channel-resistant embedded system. We categorize our contributions into three major aspects—first, we investigating the effects of integration of security components and developing corresponding countermeasures. We analyze the vulnerability in a widely used countermeasure - masking, and identify that the random number transfer procedure is a weak link in the integration which can be bypassed by the attacker. We further propose a lightweight protection scheme to protect function calls from instruction skip fault attacks. Second, we developed a novel analysis methodology for pre-silicon side-channel leakage evaluation and root cause analysis. The methodology we developed enables the designer to detect the side-channel leakage at the early pre-silicon design stage, locate the leakage source in the design precisely to the individual gate and apply highly targeted countermeasure with low overhead. Third, we developed a multipurpose on-chip side-channel and fault monitoring extension - Programmable Ring Oscillator (PRO), to further guarantee the security of PDN. PRO can provide on-chip side-channel resistance, power monitoring, and fault detection capabilities to the secure design. We show that PRO as application-independent integrated primitives can provide side-channel and fault countermeasure to the design at a low cost.
2

Takarabt, Sofiane. "Évaluation pré-silicium de circuits sécurisés face aux attaques par canal auxiliaire." Electronic Thesis or Diss., Institut polytechnique de Paris, 2021. http://www.theses.fr/2021IPPAT015.

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Les systèmes embarqués sont constamment menacés par diverses attaques, notamment les attaques side-channel. Pour garantir un certain niveau de sécurité, les implémentations cryptographiques doivent valider des tests d’évaluation recommandés par les standards de certifications, et ainsi répondre aux besoins du marché. Pour cette raison, il est nécessaire d’implémenter des contremesures fiables pour contrer ce type d’attaques. Néanmoins, une fois ces contremesures implémentées, les tests de vérification et de validation peuvent s’avérer très coûteux en temps et en argent. Ainsi, minimiser le nombre d’allers-retours, entre l’étape de conception et l’étape d’évaluation est primordial. Nous allons explorer une classe très large d’attaques existantes (passives et actives), et proposer des méthodes d’évaluations au niveau pré-silicium, permettant d’un côté, de détecter les différents types de fuites qu’un attaquant donné pourrait exploiter, et de l’autre, exposer des techniques de protection permettant de contrer ces attaques, tout en respectant l’aspect performance et taille en silicium. Nous nous basons dans nos analyses sur des méthodes formelles et empiriques, pour tracer l’impact de chaque vulnérabilité sur les différents niveaux d’abstraction du circuit, et ainsi proposer des contremesures optimales
Embedded systems are constantly threatened by various attacks, including side-channel attacks. To guarantee a certain level of security, cryptographic implementations must validate evaluation tests recommended by the certification standards, and thus meet the market needs. For this reason, it is necessary to implement reliable countermeasures to counter this type of attacks. However, once these countermeasures are implemented, verification and validation tests can be very costly in terms of time and money. Thus, optimizing the lifecycle of the circuit, between the design stage and the evaluation stage is paramount. We will explore a very broad class of existing attacks (passive and active), and propose methods of pre-silicon level assessments, allowing on the one hand, to detect the different types of leakages that a given attacker can exploit, and on the other hand, expose different techniques to counter these attacks, while respecting the performance and area aspect. In our analyses, we apply formal and empirical methods to track the impact of each vulnerability on the different abstraction levels of the circuit, and thus propose optimal countermeasures
3

Wu, Yu-hsin, and 吳育星. "Optimization of Signal Integrity by Using Amplitude Adjustment in a Pre-Silicon Full-Transmission Evaluation." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/63144969227910399384.

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碩士
國立中央大學
電機工程研究所碩士在職專班
99
In the recent years, as the High definition video and bulk size format data transfer became popular, the Gb/s level high speed differential transmission signals like HDMI, SATA and USB3.0 are instead of the traditional style became more popular in 3C market. The newest generation transmission interface had been developed for this requirement In the Gb/s high speed, these loadings became the major factors for signal integrity. How to estimate the signal integrity of high speed differential pairs is more important for real product in Pre-silicon full-transmission evaluation. In this paper, we defined the PSFTE flow to simulate and analyze the signal integrity from die to far-end in Pre-silicon stage. Then we can use amplitude adjustment method to optimize the signal integrity for different full transmission line. It can avoid not only the extra cost from the version change, the most important is the timing delay will cause more business loss.

Book chapters on the topic "Pre-silicon evaluation":

1

Rahman, Ismail Abdul, and Frank L. Riley. "High quality silicon nitride powder derived from Malaysian rice husks." In Chemistry and Technology of Silicon and Tin, 377–83. Oxford University PressOxford, 1992. http://dx.doi.org/10.1093/oso/9780198555803.003.0029.

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Abstract a-Silicon nitride powder has been prepared by nitriding pyrolysed rice husks incorporated with 4 per cent pre-formed silicon nitride at a temperature of about 1450°C and under a 95 per cent N/5 per cent H atmosphere. The silicon nitride powder is obtained in the form of equiaxed, sub-micrometer, and uniformly distributed particles. A material evaluation based on its powder characteristics, hot-pressing behaviour, and other properties shows that this silicon nitride is of a good quality compared to that of the best currently available commercial powders. Thus, rice husks are a good, cheap, and readily available raw material for the production of high quality silicon nitride.

Conference papers on the topic "Pre-silicon evaluation":

1

Perdomo, Elias, Alexander Kropotov, Francelly Katherine Cano Ladino, Syed Zafar, Teresa Cervero, Xavier Martorell Bofill, and Behzad Salami. "Makinote: An FPGA-Based HW/SW Platform for Pre-Silicon Emulation of RISC-V Designs." In RAPIDO '24: Rapid Simulation and Performance Evaluation for Design. New York, NY, USA: ACM, 2024. http://dx.doi.org/10.1145/3642921.3642928.

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Takarabt, Sofiane, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, and Youssef Souissi. "Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification." In 2018 IEEE 3rd International Verification and Security Workshop (IVSW). IEEE, 2018. http://dx.doi.org/10.1109/ivsw.2018.8494881.

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Esposito, C., C. De Martino, S. Lehmann, Zhixing Zhao, M. Schroter, and M. Spirito. "Pre-Silicon direct Calibration/De-embedding Evaluation and Device Parameters Uncertainty Estimation." In 2021 97th ARFTG Microwave Measurement Conference (ARFTG). IEEE, 2021. http://dx.doi.org/10.1109/arftg52261.2021.9640156.

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Rusu, Alecsandra, Emilian David, Marina Țopa, Vasile Grosu, Andi Buzo, and Georg Pelz. "Improvement and Performance Evaluation of an Adaptive Method for Integrated Circuits Pre-silicon Verification." In 2023 International Symposium on Signals, Circuits and Systems (ISSCS). IEEE, 2023. http://dx.doi.org/10.1109/isscs58449.2023.10190850.

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Nikiforov, Dima, Shengjun Chris Dong, Chengyi Lux Zhang, Seah Kim, Borivoje Nikolic, and Yakun Sophia Shao. "RoSÉ: A Hardware-Software Co-Simulation Infrastructure Enabling Pre-Silicon Full-Stack Robotics SoC Evaluation." In ISCA '23: 50th Annual International Symposium on Computer Architecture. New York, NY, USA: ACM, 2023. http://dx.doi.org/10.1145/3579371.3589099.

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Tiwari, Santosh K., and Brian K. Paul. "Fabrication of TiO2 and SiO2 Thin Films by Room Temperature Liquid Phase Deposition." In ASME 2007 International Manufacturing Science and Engineering Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/msec2007-31093.

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Mesoporous and dense titanium dioxide (TiO2) and silicon dioxide (SiO2) films were deposited directly from nanoparticle colloidal suspensions on quartz using a liquid phase deposition technique. The quartz surface was pre-treated with an -OH group to activate the deposition surface for crack-free adhesion. The deposited films were characterized with the help of scanning electron microscope for microstructural evaluation. An optical profilometer was used to measure the optical properties of the SiO2 film. The reflectance and transmittance patterns of the film were analyzed to determine the index of refraction of the film.
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Newton, Christopher D., Steven P. Jordan, Martin R. Bache, and Louise Gale. "High Temperature Fatigue Assessment of a SiCf/SiC Ceramic Matrix Composite Using Advanced Monitoring Techniques." In ASME Turbo Expo 2019: Turbomachinery Technical Conference and Exposition. American Society of Mechanical Engineers, 2019. http://dx.doi.org/10.1115/gt2019-90355.

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Abstract Laboratory based experiments to assess the “damage tolerance” of any new material system are a pre-requisite to engineering design, especially for aerospace components. In the case of CMCs, macro-scale specimens are preferred containing representative fibre-matrix architectures that support the definition of mechanical properties under service representative stress states. The combination of complex internal structure and inevitable processing artefacts within CMCs provides numerous sites for damage initiation. Damage then progresses in an inhomogeneous manner prior to ultimate failure at some critical location. Traditional techniques employed for strain measurement (extensometry/strain gauges) prove to be ineffective tools when testing these advanced composites. More complex characterization is essential in order to assess the localised response of the material. Advanced techniques, specifically digital image correlation and acoustic emission, have been applied to the evaluation of an CVI/MI silicon carbide reinforced/silicon carbide CMC tested at the elevated temperature of 800°C under fatigue loading. The spatial and temporal indications of damage were correlated to the observable forms of damage initiation and progression. Ancillary use of an in-situ SEM loading stage provided insight into the crack opening and closing mechanisms active within this material when under cyclic stress.
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Tedesco, Sarah, Ming Shi, Jason Coryell, Qi Lu, and Jianfeng Wang. "New Generation Press Hardening Steels with Tensile Strength of 1.7-2.0 GPa and Enhanced Bendability." In HT2021. ASM International, 2021. http://dx.doi.org/10.31399/asm.cp.ht2021p0180.

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Abstract Press hardening steel (PHS) applications predominately use 22MnB5 AlSi coated in the automotive industry. This material has a limited supply chain. Increasing the tensile strength and bendability of the PHS material will enable light-weighting while maintaining crash protection. In this paper, a novel PHS is introduced, and properties are compared to 22MnB5. The new Coating Free PHS (CFPHS) steel, 25MnCr, has increased carbon, with chromium and silicon additions for oxidation resistance. Its ultimate tensile strength (UTS) of 1.7 GPa with bending angle above 55° at 1.4mm thickness improves upon the 22MnB5 grade. This steel is not pre-coated, is oxidation resistant at high temperature, thus eliminating the need for AlSi or shot blasting post processing to maintain surface quality. Microstructural mechanisms used to enhance bendability and energy absorption are discussed for the novel steel. Performance evaluations such as: weldability, component level crush and intrusion testing and e-coat adhesion, are conducted on samples from industrial coils.
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Ume, I. Charles, Jie Gong, Razid Ahmad, and Abel Valdes. "Laser Ultrasonic Inspection of Solder Bumps in Flip Chip Packages Using Virtual Package Device as Reference." In ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-39970.

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Flip chip package is widely used in the electronic device manufacturing industry. The top side of a flip chip device is manufactured with solder bumps. The device is then flipped on its top so that the solder bumps can be bonded to a substrate, forming the mechanical and electrical connection between the device and substrate. As a result, the solder bumps are sandwiched between the silicon die and the substrate, making them no longer visible for usual inspection. A novel solder joint inspection system capable of evaluating the quality of the hidden solder bumps on a flip chip package has been developed using laser ultrasound techniques. The system pulses a laser onto the top surface of a chip package to generate ultrasonic waves in the package and excite structural vibrations which can then be measured using an interferometer. Since defective solder bumps cause changes in the transient vibration response of a tested sample, quality of the tested sample can be assessed by correlating its vibration responses to that of a known good device. A limitation of this implementation is the necessity of a known-good reference chip package, which typically involves expensive testing using alternate methods. In this paper, the development of a method capable of generating a virtual reference chip package is presented. This method, called Hybrid Reference Method, uses a statistical approach to find which packages in a sample set are most similar and then averages their time domain signals to generate a virtual chip package, known as the Hybrid Reference Package. The signals associated with Hybrid Reference Package are then correlated with the time domain signals obtained from the packages under inspection to obtain a quality signature. Finally, defective and non-defective chip packages are separated by estimating a beta distribution that fits the quality signature histogram of the inspected packages and then determining a cutoff threshold for an acceptable quality signature. This method was applied to two types of flip chip packages where no pre-established known-good reference package was available. The results of this quality analysis were validated by comparison with electrical test and X-ray results.

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