Journal articles: 'Power MOSFETs'

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Lichtenwalner, Daniel J., Brett Hull, Vipindas Pala, Edward Van Brunt, Sei-Hyung Ryu, Joe J. Sumakeris, Michael J. O’Loughlin, Albert A. Burk, Scott T. Allen, and John W. Palmour. "Performance and Reliability of SiC Power MOSFETs." MRS Advances 1, no. 2 (2016): 81–89. http://dx.doi.org/10.1557/adv.2015.57.

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ABSTRACTDue to the wide bandgap and other key materials properties of 4H-SiC, SiC MOSFETs offer performance advantages over competing Si-based power devices. For example, SiC can more easily be used to fabricate MOSFETs with very high voltage ratings, and with lower switching losses. Silicon carbide power MOSFET development has progressed rapidly since the market release of Cree’s 1200V 4H-SiC power MOSFET in 2011. This is due to continued advancements in SiC substrate quality, epitaxial growth capabilities, and device processing. For example, high-quality epitaxial growth of thick, low-doped SiC has enabled the fabrication of SiC MOSFETs capable of blocking extremely high voltages (up to 15kV); while dopant control for thin highly-doped epitaxial layers has helped enable low on-resistance 900V SiC MOSFET production. Device design and processing improvements have resulted in lower MOSFET specific on-resistance for each successive device generation. SiC MOSFETs have been shown to have a long device lifetime, based on the results of accelerated lifetime testing, such as high-temperature reverse-bias (HTRB) stress and time-dependent dielectric breakdown (TDDB).

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Funaki, Tsuyoshi, Yuki Nakano, and Takashi Nakamura. "Comparative Study of SiC MOSFETs in High Voltage Switching Operation." Materials Science Forum 717-720 (May 2012): 1081–84. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1081.

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SiC power device is expected to have high breakdown voltage with low on resistance, which cannot be attainable for conventional Si device. This study evaluates the switching performance of high voltage SiC MOSFETs with comparing to that of conventional Si power MOSFET having equivalent breakdown voltage. To this end, turn-on and turn-off switching operation of MOSFETs are assessed with resistive load for same conduction current density. Though the on resistance of SiC MOSFETs are quite lower than Si MOSFET, especially for trench gate type. But, SiC MOSFETs have larger terminal capacitance. Therefore, SiC MOSFETs show slower switching speed than Si MOSFETs for same current density condition.

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Ejury, Jens. "Advanced Thermal Simulation Model for Power MOSFETs." International Symposium on Microelectronics 2013, no. 1 (January 1, 2013): 000598–603. http://dx.doi.org/10.4071/isom-2013-wa64.

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Modern Power MOSFETs are widely used for high efficiency SMPS applications. Also, they provide very low on-resistance which reduces conduction losses in Oring or eFuse applications. These applications as well as others have transition states in which they drive the MOSFET in linear mode operation during turn-on and turn-off events respectively. The high cell density in modern Power MOSFETs provokes uneven current distribution in linear mode operation which locally stresses certain cell areas more than others. To prevent destruction, the SOA of these MOSFETs has a thermal limit line boundary imposed. With existing L3 MOSFET models it is possible to simulate temperature rise and power loss of the entire MOSFET. However, the local heating effect is not represented in this model. Here, a wrapper is being introduced. It converts a standard L3-model into a model that incorporates a dynamic representation of the entire SOA diagram. The temperature rise follows the hottest cell so that simulations in linear mode become a valid way to predict the highest junction temperature. The limitations of this approach will be outlined.

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Prado, Edemar O., Pedro C. Bolsi, Hamiltom C. Sartori, and José R. Pinheiro. "An Overview about Si, Superjunction, SiC and GaN Power MOSFET Technologies in Power Electronics Applications." Energies 15, no. 14 (July 20, 2022): 5244. http://dx.doi.org/10.3390/en15145244.

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This work presents a comparative analysis among four power MOSFET technologies: conventional Silicon (Si), Superjunction (SJ), Silicon Carbide (SiC) and Gallium Nitride (GaN), indicating the voltage, current and frequency ranges of the best performance for each technology. For this, a database with 91 power MOSFETs from different manufacturers was built. MOSFET losses are related to individual characteristics of the technology: drain-source on-state resistance, input capacitance, Miller capacitance and internal gate resistance. The total losses are evaluated considering a drain-source voltage of 400 V, power levels from 1 kW to 16 kW (1 A–40 A) and frequencies from 1 kHz to 500 kHz. A methodology for selecting power MOSFETs in power electronics applications is also presented.

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Matocha, Kevin, Peter A. Losee, Arun Gowda, Eladio Delgado, Greg Dunne, Richard Beaupre, and Ljubisa Stevanovic. "Performance and Reliability of SiC MOSFETs for High-Current Power Modules." Materials Science Forum 645-648 (April 2010): 1123–26. http://dx.doi.org/10.4028/www.scientific.net/msf.645-648.1123.

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We address the two critical challenges that currently limit the applicability of SiC MOSFETs in commercial power conversion systems: high-temperature gate oxide reliability and high total current rating. We demonstrate SiC MOSFETs with predicted gate oxide reliability of >106 hours (100 years) operating at a gate oxide electric field of 4 MV/cm at 250°C. To scale to high total currents, we develop the Power Overlay planar packaging technique to demonstrate SiC MOSFET power modules with total on-resistance as low as 7.5 m. We scale single die SiC MOSFETs to high currents, demonstrating a large area SiC MOSFET (4.5mm x 4.5 mm) with a total on-resistance of 30 m, specific on-resistance of 5 m-cm2 and blocking voltage of 1400V.

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Jadli, Utkarsh, Faisal Mohd-Yasin, Hamid Amini Moghadam, Peyush Pande, Mayank Chaturvedi, and Sima Dimitrijev. "A Method for Selection of Power MOSFETs to Minimize Power Dissipation." Electronics 10, no. 17 (September 3, 2021): 2150. http://dx.doi.org/10.3390/electronics10172150.

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A balance between static and dynamic losses of a power MOSFET is always desirable for accomplishing the maximum efficiency for a specific power converter. The standard semiconductor theory suggests that a minimum power dissipation in a MOSFET can be achieved by selecting a specific device active area. However, for power circuit designers, the active device area is unknown given that only datasheet parameters are available. Hence, in this paper, we propose a simple method, based on semiconductor theory, to select optimum power MOSFET from a family of MOSFETs using only datasheet parameters. By applying this optimization method to the specific power supply circuit under development, power engineers can select the best transistors to yield lowest power losses for the systems under development.

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Lichtenwalner, Daniel J., Akin Akturk, James McGarrity, Jim Richmond, Thomas Barbieri, Brett Hull, Dave Grider, Scott Allen, and John W. Palmour. "Reliability of SiC Power Devices against Cosmic Ray Neutron Single-Event Burnout." Materials Science Forum 924 (June 2018): 559–62. http://dx.doi.org/10.4028/www.scientific.net/msf.924.559.

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High-energy neutrons produced by cosmic ray interactions with our atmosphere are known to cause single-event burnout (SEB) failure in power devices operating at high fields. We have performed accelerated high-energy neutron SEB testing of SiC and Si power devices at the Los Alamos Neutron Science Center (LANCSE). Comparing Wolfspeed SiC MOSFETs having different voltage (900V – 3300V) and current (3.5A – 72A) ratings, we find a universal behavior when scaling failure rates by active area, and scaling drain bias by avalanche voltage. Moreover, diodes and MOSFETs behave similarly, revealing that the SiC drift dominates the failure characteristics for both device types. This universal scaling holds for SiC MOSFETs from other manufacturers as well. The SEB characteristics of Si power IGBT and MOSFET devices show that near their rated voltages failure rates of Si devices can be 10X higher than that of comparable SiC MOSFET devices. Thus, Si devices are more susceptible to SEB failure from voltage overshoot conditions.

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Kampitsis, Georgios E., Stavros A. Papathanassiou, and Stefanos N. Manias. "Comparative Analysis of the Thermal Stress of Si and SiC MOSFETs during Short Circuits." Materials Science Forum 856 (May 2016): 362–67. http://dx.doi.org/10.4028/www.scientific.net/msf.856.362.

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In this paper, the performance of silicon (Si) and silicon carbide (SiC) power MOSFETs during short circuits is investigated. The response of both semiconductors is examined under hard switch fault and fault under load conditions using a short circuit tester board. In addition, their failure mechanism is recorded and analyzed. Examination results show that the SiC MOSFET fails in the energy limiting mode, due to gate oxide rupture, while the Si MOSFET is destructed during the power limiting mode, at the beginning of the fault. The electro-thermal characterization of these devices is performed through three-dimensional finite element analysis, utilizing the experimentally extracted power dissipation for each transistor. Simulation results confirm the exceptional ruggedness that SiC power MOSFETs exhibit outside their safe operating area.

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Kannan, Ramani, Saranya Krishnamurthy, Chay Che Kiong, and Taib B. Ibrahim. "Impact of gamma-ray irradiation on dynamic characteristics of Si and SiC power MOSFETs." International Journal of Electrical and Computer Engineering (IJECE) 9, no. 2 (April 1, 2019): 1453. http://dx.doi.org/10.11591/ijece.v9i2.pp1453-1460.

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Power electronic devices in spacecraft and military applications requires high radiation tolerant. The semiconductor devices face the issue of device degradation due to their sensitivity to radiation. Power MOSFET is one of the primary components of these power electronic devices because of its capabilities of fast switching speed and low power consumption. These abilities are challenged by ionizing radiation which damages the devices by inducing charge built-up in the sensitive oxide layer of power MOSFET. Radiations degrade the oxides in a power MOSFET through Total Ionization Dose effect mechanism that creates defects by generation of excessive electron–hole pairs causing electrical characteristics shifts. This study investigates the impact of gamma ray irradiation on dynamic characteristics of silicon and silicon carbide power MOSFET. The switching speed is limit at the higher doses due to the increase capacitance in power MOSFETs. Thus, the power circuit may operate improper due to the switching speed has changed by increasing or decreasing capacitances in power MOSFETs. These defects are obtained due to the penetration of Cobalt60 gamma ray dose level from 50krad to 600krad. The irradiated devices were evaluated through its shifts in the capacitance-voltage characteristics, results were analyzed and plotted for the both silicon and silicon carbide power MOSFET.

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Bottaro, Enrico, Santi Agatino Rizzo, and Nunzio Salerno. "Circuit Models of Power MOSFETs Leading the Way of GaN HEMT Modelling—A Review." Energies 15, no. 9 (May 7, 2022): 3415. http://dx.doi.org/10.3390/en15093415.

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Gallium nitride high-electron-mobility transistor (GaN HEMT) is a key enabling technology for obtaining high-efficient and compact power electronic systems. At the design stage of a power converter, the proper modelling of the GaN HEMT is essential to benefit from their good features and to account for the limits of the current technology. Circuit models of power MOSFETs have been deeply investigated by academia and industry for a long time. These models are able to emulate the datasheet information, and they are usually provided by device manufacturers as netlists that can be simulated in any kind of SPICE-like software. This paper firstly highlights the similarities and differences between MOSFETs and GaN HEMTs at the datasheet level. According to this analysis, the features of MOSFET circuit models that can be adopted for GaN HEMT modelling are discussed. This task has been accomplished by overviewing the literature on MOSFETs circuit models as well as analysing manufacturers netlists, thus highlighting the models MOSFETs valid or adaptable to GaN HEMTs. The study has revealed show that some models can be adapted for the GaN HEMT devices to emulate static characteristics at room temperature while the MOSFET models of dynamic characteristics can be used for GaN HEMT devices. This study enables the devices modellers to speed up the GaN HEMT modelling thanks to the use of some well-established MOSFET models. In this perspective, some suggestions to develop accurate GaN HEMT models are also provided.

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Langpoklakpam, Catherine, An-Chen Liu, Kuo-Hsiung Chu, Lung-Hsing Hsu, Wen-Chung Lee, Shih-Chen Chen, Chia-Wei Sun, Min-Hsiung Shih, Kung-Yen Lee, and Hao-Chung Kuo. "Review of Silicon Carbide Processing for Power MOSFET." Crystals 12, no. 2 (February 11, 2022): 245. http://dx.doi.org/10.3390/cryst12020245.

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Owing to the superior properties of silicon carbide (SiC), such as higher breakdown voltage, higher thermal conductivity, higher operating frequency, higher operating temperature, and higher saturation drift velocity, SiC has attracted much attention from researchers and the industry for decades. With the advances in material science and processing technology, many power applications such as new smart energy vehicles, power converters, inverters, and power supplies are being realized using SiC power devices. In particular, SiC MOSFETs are generally chosen to be used as a power device due to their ability to achieve lower on-resistance, reduced switching losses, and high switching speeds than the silicon counterpart and have been commercialized extensively in recent years. A general review of the critical processing steps for manufacturing SiC MOSFETs, types of SiC MOSFETs, and power applications based on SiC power devices are covered in this paper. Additionally, the reliability issues of SiC power MOSFET are also briefly summarized.

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Baliga, B. Jayant, Woong Je Sung, Ki Jeong Han, J. Harmon, A. Tucker, and S. Syed. "PRESiCE^TM: Process Engineered for Manufacturing SiC Electronic Devices." Materials Science Forum 924 (June 2018): 523–26. http://dx.doi.org/10.4028/www.scientific.net/msf.924.523.

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PowerAmerica sponsored the development by NCSU of a process for manufacturing power MOSFETs and JBS Rectifiers in 2015. This process, named PRESiCETM, was successful in making 1.2 kV rated state-of-the-art 4H-SiC power devices (MOSFETs, BiDFETs, and JBS Rectifiers) in the X-Fab foundry. In addition, we were successful in monolithically integrating a JBS fly-back rectifier into the power MOSFET structure to create the power JBSFET which allows saving significant (~ 40 %) chip area and reducing package count in half. In the second year (2016), NCSU has qualified the process for manufacturing these power devices at X-Fab.

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Luo, Qixiao. "Research on the advantages and development status of new material MOSFET." Highlights in Science, Engineering and Technology 33 (February 21, 2023): 210–18. http://dx.doi.org/10.54097/hset.v33i.5313.

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When using MOSFETs, in order to improve the operating speed, so that higher power density and lower functional consumption can be obtained in the process, researchers have explored in multiple dimensions. In this paper, three popular new material MOSFETs are mainly explained, including SiC MOSFET, GaN MOSFET and graphene MOSFET. This paper introduces their advantages and their development status, so as to compare the advantages of new materials. In conclusion, By adding materials, the electron mobility and stability of the FET can be increased in some situation. The research in this paper will undoubtedly promote the further development of MOSFET.

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Matocha, Kevin, Sujit Banerjee, and Kiran Chatty. "Advanced SiC Power MOSFETs Manufactured on 150mm SiC Wafers." Materials Science Forum 858 (May 2016): 803–6. http://dx.doi.org/10.4028/www.scientific.net/msf.858.803.

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An advanced silicon carbide power MOSFET process was developed and implemented on a high-volume 150mm silicon production line. SiC power MOSFETs fabricated on this 150mm silicon production line were demonstrated with blocking voltage of 1700V with VGS=0V. These SiC MOSFETs have a specific on-resistance as low as 3.1 mΩ-cm2 at room temperature, increasing to 6.7 mΩ-cm2 at 175°C. Devices were packaged in TO-247 package and measured to have on-resistance of 45 mΩ with VGS=20V at room temperature. Clamped inductive switching characterization of these SiC MOSFETs shows turn-off losses as low as 110 uJ (700V, 19.5A). The high-temperature gate bias stability was characterized at positive (+20) and negative gate bias (-10V) at 175°C. After 750 hours of gate stress at a gate bias of VGS=+20V and 175°C, we observe less than a 250mV shift in the threshold voltage. After 750 hours of stress at VGS=-10V and 175°C, we characterize a threshold voltage shift less than 100mV. This shows promise for high-volume production of reliable SiC MOSFETs on 150mm wafers.

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Choi, Cheol-Woong, Jae-Hyeon So, Jae-Sub Ko, and Dae-Kyong Kim. "Influence Analysis of SiC MOSFET’s Parasitic Capacitance on DAB Converter Output." Electronics 12, no. 1 (December 30, 2022): 182. http://dx.doi.org/10.3390/electronics12010182.

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This paper proposes the influence analysis of silicon carbide (SiC) MOSFET’s parasitic output capacitance on a dual active bridge (DAB) converter. Power converters are required for DC grids and energy storage. Because SiC metal-oxide-semiconductor FETs (MOSFETs) have lower on-state resistance and faster reverse recovery time than Si MOSFETs, they can be controlled with lower losses and higher frequencies. MOSFETs have a parasitic capacitance. Because of the output parasitic capacitance, the switch voltage does not rise instantaneously during switching but has a delay. The output parasitic capacitance of the switch depends on its drain-to-source voltage, and this parasitic capacitance affects the output of the DAB converter by delaying the switch voltage. In this paper, in order to analyze the effect of the parasitic capacitance on the DAB converter output, the delay time was calculated through a formula, and this value was compared with a simulated value. In addition, the effect of the parasitic capacitance of the SiC MOSFET on the output of the DAB converter was presented by comparing the actual output voltage with the ideal output voltage and analyzing the effect of the output voltage according to the delay.

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Zhu, Shengnan, Tianshi Liu, Junchong Fan, Arash Salemi, Marvin H. White, David Sheridan, and Anant K. Agarwal. "A New Cell Topology for 4H-SiC Planar Power MOSFETs for High-Frequency Switching." Materials 15, no. 19 (September 27, 2022): 6690. http://dx.doi.org/10.3390/ma15196690.

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A new cell topology named the dodecagonal (a polygon with twelve sides, short for Dod) cell is proposed to optimize the gate-to-drain capacitance (Cgd) and reduce the specific ON-resistance (Ron,sp) of 4H-SiC planar power MOSFETs. The Dod and the octagonal (Oct) cells are used in the layout design of the 650 V SiC MOSFETs in this work. The experimental results confirm that the Dod-cell MOSFET achieves a 2.2× lower Ron,sp, 2.1× smaller high-frequency figure of merit (HF-FOM), higher turn on/off dv/dt, and 29% less switching loss than the fabricated Oct-cell MOSFET. The results demonstrate that the Dod cell is an attractive candidate for high-frequency power applications.

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Wang, Teng, Xin Wan, Hu Jin, Hao Li, Yabin Sun, Renrong Liang, Jun Xu, and Lirong Zheng. "Optimization of the Cell Structure for Radiation-Hardened Power MOSFETs." Electronics 8, no. 6 (May 28, 2019): 598. http://dx.doi.org/10.3390/electronics8060598.

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Power MOSFETs specially designed for space power systems are expected to simultaneously meet the requirements of electrical performance and radiation hardness. Radiation-hardened (rad-hard) power MOSFET design can be achieved via cell structure optimization. This paper conducts an investigation of the cell geometrical parameters with major impacts on radiation hardness, and a rad-hard power MOSFET is designed and fabricated. The experimental results validate the devices’ total ionizing dose (TID) and single event effects (SEE) hardness to suitably satisfy most space power system requirements while maintaining acceptable electrical performance.

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Yun, Minghui, Miao Cai, Daoguo Yang, Yiren Yang, Jing Xiao, and Guoqi Zhang. "Bond Wire Damage Detection Method on Discrete MOSFETs Based on Two-Port Network Measurement." Micromachines 13, no. 7 (July 7, 2022): 1075. http://dx.doi.org/10.3390/mi13071075.

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Bond wire damage is one of the most common failure modes of metal-oxide semiconductor field-effect transistor (MOSFET) power devices in wire-welded packaging. This paper proposes a novel bond wire damage detection approach based on two-port network measurement by identifying the MOSFET source parasitic inductance (LS). Numerical calculation shows that the number of bond wire liftoffs will change the LS, which can be used as an effective bond wire damage precursor. Considering a power MOSFET as a two-port network, LS is accurately extracted from frequency domain impedance (Z−parameter) using a vector network analyzer under zero biasing conditions. Bond wire cutoff experiments are employed to validate the proposed approach for bond wire damage detection. The result shows that LS increases with the rising severity of bond wire faults, and even the slight fault shows a high sensitivity, which can be effectively used to quantify the number of bond wire liftoffs of discrete MOSFETs. Meanwhile, the source parasitic resistance (RS) extracted from the proposed two-port network measurement can be used for the bond wire damage detection of high switching frequency silicon carbide MOSFETs. This approach offers an effective quality screening technology for discrete MOSFETs without power on treatment.

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Choi, Won Suk, Sung Mo Young, Richard L. Woodin, A. W. Witt, and J. Shovlin. "A High Performance CCM PFC Circuit Using a SiC Schottky Diode and a Si SuperFET^TM Switch." Materials Science Forum 600-603 (September 2008): 1235–38. http://dx.doi.org/10.4028/www.scientific.net/msf.600-603.1235.

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SuperFETTM MOSFETs and silicon carbide (SiC) Schottky diodes are applied to continuous conduction mode active power factor correction pre-regulators. SuperFETTM MOSFETs can reduce power losses dramatically with their extremely low RDS(ON) and fast switching. The SiC Schottky diode has virtually zero reverse recovery current and high thermal conductivity, and is close to an ideal diode for a CCM PFC circuit. Due to these outstanding switching characteristics, frequency can be increased. In this paper, the SiC Schottky diode’s and SuperFETTM MOSFET’s performance have been verified in a CCM PFC boost converter. These products can reduce the total power losses and enhance the system efficiency.

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Green, Ronald, Aivars J. Lelis, and Daniel B. Habersat. "Charge Trapping in Sic Power MOSFETs and its Consequences for Robust Reliability Testing." Materials Science Forum 717-720 (May 2012): 1085–88. http://dx.doi.org/10.4028/www.scientific.net/msf.717-720.1085.

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Threshold voltage (VT) instability remains an important issue for the performance, reliability, and qualification of SiC power MOSFET devices. The direct application of existing reliability test standards to SiC power MOSFETs can in some cases result in an inconsistent pass/fail response for a given device. To ensure SiC MOSFET device reliability, some modifications to existing test methods may be necessary..

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Albrecht, Matthaeus, Tobias Erlbacher, Anton Bauer, and Lothar Frey. "Improving 5V Digital 4H-SiC CMOS ICs for Operating at 400°C Using PMOS Channel Implantation." Materials Science Forum 963 (July 2019): 827–31. http://dx.doi.org/10.4028/www.scientific.net/msf.963.827.

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In this work, the impact of a shallow aluminum channel implantation on the channel properties of SiC p-MOSFETs and digital SiC CMOS devices is investigated. For this purpose, p-MOSFETs, CMOS inverters and ring oscillators with different channel implantation doses were fabricated and electrically characterized. The threshold voltage of the resulting p-MOSFETs was shifted from-5 V to-3.6 V whereas the effective channel mobility was slightly decreased from 11.8 cm2/Vs to 10.2 cm2/Vs for a p-MOSFET channel implantation dose of 2∙1013 cm-2 compared to the non-implanted channel. The resulting p-MOSFETs enable SiC CMOS logic circuits to operate with a 5 V power supply and to satisfy 5 V TTL input level specification over the whole temperature range of 25°C to 400°C. Furthermore the propagation delay time of inverters was reduced by 80% at 25°C and 40% at 400°C compared to inverters without p-MOSFET channel implantation.

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Lichtenwalner, Daniel J., Shadi Sabri, Edward Van Brunt, Brett Hull, Sei Hyung Ryu, Philipp Steinmann, Amy Romero, et al. "Accelerated Testing of SiC Power Devices under High-Field Operating Conditions." Materials Science Forum 1004 (July 2020): 992–97. http://dx.doi.org/10.4028/www.scientific.net/msf.1004.992.

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Power metal-oxide-semiconductor field-effect transistors (MOSFETs) experience conditions of high field during normal operation. During switching conditions, unexpected transient events may occur which force devices into avalanche or short circuit conditions. Moreover, silicon carbide devices typically experience higher fields in the gate oxide and drift regions than comparable Si devices due to channel and drift property differences. A summary of SiC MOSFET reliability and ruggedness test results are reported here. Reliability tests under high field conditions: positive-bias and negative-bias temperature instability (PBTI, NBTI) to examine threshold stability; time-dependent dielectric breakdown (TDDB) for gate oxide lifetime extrapolation; high-temperature reverse bias (HTRB); and HTRB testing under high neutron flux to determine terrestrial neutron single-event burnout (SEB) rates. High-power ruggedness evaluation is presented for SiC MOSFETs under forced avalanche conditions (unclamped inductive switching (UIS)) and under short-circuit operation to bound device safe operating areas. Overall results demonstrate the intrinsic reliability of SiC MOSFETs.

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Qiu, Guoqing, Kedi Jiang, Shengyou Xu, Xin Yang, and Wei Wang. "Modeling and analysis of the characteristics of SiC MOSFET." Journal of Physics: Conference Series 2125, no. 1 (November 1, 2021): 012051. http://dx.doi.org/10.1088/1742-6596/2125/1/012051.

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Abstract Although the superior performance of SiC MOSFET devices has beenvalidated by many studies, it is necessary to overcome many technical bottlenecks to make SiC MOSFET gradually replace Si-based power devices into the mainstream. In view of the current situation where the performance of SiC MOSFETs in power conversion devices cannot be evaluated well at this stage, it is necessary to carry out fine modeling of SiC MOSFETs and establish accurate simulation models. In this paper, the powerful mathematical processing capability and rich modules of Matlab/Simulink are used to build a SiC MOSFET model, and then the product data sheet is compared with the fitted data. The results show that the switching simulation waveforms are in general agreement with the data sheet waveforms, and the error is less than 7%. Verifing the accuracy of the model and reducing the difficulty of modeling, it provides a new idea for establishing the circuit simulation model of SiC MOSFET in Matlab/Simulink.

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van Zeghbroeck, Bart, and Hamid Fardi. "Comparison of 3C-SiC and 4H-SiC Power MOSFETs." Materials Science Forum 924 (June 2018): 774–77. http://dx.doi.org/10.4028/www.scientific.net/msf.924.774.

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A comprehensive comparison of 3C-SiC and 4H-SiC power MOSFETs was performed, aimed at quantifying and comparing the devices’ on-resistance and switching loss. To this end, the relevant material parameters were collected using experimental data where available, or those obtained by simulation. This includes the bulk mobility as a function of doping density, the breakdown field as a function of doping and the MOSFET channel mobility. A device model was constructed and then used to calculate the on-resistance and breakdown voltage of a properly scaled device as a function of the doping density of the blocking layer. A SPICE model was constructed to explore the switching transients and switching losses. The simulations indicate that, for the chosen material parameters, a 600 V 3C-SiC MOSFET has an on-resistance, which is less than half that of a 4H-SiC MOSFET as are the switching losses in the device.

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Han, Ki Jeong, B. Jayant Baliga, and Woong Je Sung. "1.2 kV 4H-SiC Split-Gate Power MOSFET: Analysis and Experimental Results." Materials Science Forum 924 (June 2018): 684–88. http://dx.doi.org/10.4028/www.scientific.net/msf.924.684.

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This paper presents a 1.2kV-rated 4H-SiC Split-Gate power MOSFET (SG-MOSFET) with superior high frequency figures-of-merit (HF-FOM). Electrical characteristics including reverse transfer capacitance and gate-to-drain charge are measured from fabricated devices on a 6-inch SiC wafer, demonstrating excellent performance. Compared to the conventional MOSFETs, the SG-MOSFET provides about 7x smaller HF-FOM [RonxCgd] and 2x smaller HF-FOM [RonxQgd] with improved reverse transfer capacitance and gate-to-drain charge.

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Prado, Edemar O., Pedro C. Bolsi, Hamiltom C. Sartori, and José R. Pinheiro. "Design of Uninterruptible Power Supply Inverters for Different Modulation Techniques Using Pareto Front for Cost and Efficiency Optimization." Energies 16, no. 3 (January 26, 2023): 1314. http://dx.doi.org/10.3390/en16031314.

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This work presents a design for uninterruptible power supply inverters using Pareto front optimization for improved cost and efficiency. Three PWM modulation techniques applied to the full-bridge inverter are analyzed. As a result, the best MOSFET design solution in terms of the cost and efficiency of the inverter is evaluated based on a database with 47 power MOSFETs. Using the Pareto front, the optimal and sub-optimal solutions are compared, considering the three modulation techniques and the characteristics of MOSFETs manufactured for different voltage levels. Thermal and electrical measurements are used to validate the models.

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Qin, Mo, Xun, Zhang, and Dong. "A Digital-Controlled SiC-Based Solid State Circuit Breaker with Soft Switch-Off Method for DC Power System." Electronics 8, no. 8 (July 26, 2019): 837. http://dx.doi.org/10.3390/electronics8080837.

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Due to the lower on-state resistance, direct current (DC) solid state circuit breakers (SSCBs) based on silicon-carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) can reduce on-state losses and the investment of the cooling system when compared to breakers based on silicon (Si) MOSFETs. However, SiC MOSFETs, with smaller die area and higher current density, lead to weaker short-circuit ability, shorter short-circuit withstand time and higher protection requirements. To improve the reliability and short-circuit capability of SiC-based DC solid state circuit breakers, the short-circuit fault mechanisms of Si MOSFETs and SiC MOSFETs are revealed. Combined with the desaturation detection (DESAT), a “soft turn-off” short-circuit protection method based on source parasitic inductor is proposed. When the DESAT protection is activated, the “soft turn-off” method can protect the MOSFET against short-circuit and overcurrent. The proposed SSCB, combined with the flexibility of the DSP, has the μs-scale ultrafast response time to overcurrent detection. Finally, the effectiveness of the proposed method is validated by the experimental platform. The method can reduce the voltage stress of the power device, and it can also suppress the short-circuit current.

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Rahimo, Munaf. "Performance Evaluation and Expected Challenges of Silicon Carbide Power MOSFETs for High Voltage Applications." Materials Science Forum 897 (May 2017): 649–54. http://dx.doi.org/10.4028/www.scientific.net/msf.897.649.

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This paper presents an overview of the main technical requirements of high voltage Silicon Carbide MOSFETs rated above 3300V when compared to the well-established requirements of Silicon IGBTs and diodes. Combined with a performance evaluation of existing 3300 V SiC MOSFET prototypes from ROHM, the paper will discuss the benefits and challenges facing these devices for targeting mainstream and future topologies employed in high power applications such as those in grid systems, railway traction and industrial drives. The paper will also attempt to provide an outlook into potential development trends towards exploiting the full benefits of SiC MOSFETs.

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Peters, Dethard, Reinhold Schörner, Peter Friedrichs, and Dietrich Stephani. "SiC Power MOSFETs – Status, Trends and Challenges." Materials Science Forum 527-529 (October 2006): 1255–60. http://dx.doi.org/10.4028/www.scientific.net/msf.527-529.1255.

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SiC power MOSFETs are attractive electronic power switches for innovative power supply and motor drive solutions. The paper discusses this statement and specifies market segments offering the best chances for a commercialization. Due to well-known difficulties in achieving adequate channel conductivity, a lot of SiC-MOSFET publications focus on the channel mobility. However, for a power MOSFET this is only one important parameter affecting the performance. Other characteristics have to be considered too for an honest evaluation: transfer characteristics and blocking capability over the standard operation temperature range, handling of gate oxide stress and related reliability issues, capability of paralleling, dynamic stability, body diode characteristics, reproducibility of the fabrication process and device size. Various attempts have been made in recent years in order to address these features. Approaches differ in the use of different crystal orientations and polytypes, accumulation or inversion channel, implanted or epitaxially grown channels and novel oxidation techniques. Worldwide a trend to the planar DIMOS concept can be observed. Our present results are shown for a power SiC MOSFET designed for 10 A / 1200 V. Key data are a specific on-resistance of 12 m1cm2, the desired low but positive increase of the onresistance with temperature, static avalanche (20 mA DC @1574 V), short-circuit stability at 600 V for 20 9s and robust switching behavior.

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Zheng, Xueyan, Lifeng Wu, Yong Guan, and Xiaojuan Li. "Analysis of the Degradation of MOSFETs in Switching Mode Power Supply by Characterizing Source Oscillator Signals." Mathematical Problems in Engineering 2013 (2013): 1–7. http://dx.doi.org/10.1155/2013/302563.

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Switching Mode Power Supply (SMPS) has been widely applied in aeronautics, nuclear power, high-speed railways, and other areas related to national strategy and security. The degradation of MOSFET occupies a dominant position in the key factors affecting the reliability of SMPS. MOSFETs are used as low-voltage switches to regulate the DC voltage in SMPS. The studies have shown that die-attach degradation leads to an increase in on-state resistance due to its dependence on junction temperature. On-state resistance is the key indicator of the health of MOSFETs. In this paper, an online real-time method is presented for predicting the degradation of MOSFETs. First, the relationship between an oscillator signal of source and on-state resistance is introduced. Because oscillator signals change when they age, a feature is proposed to capture these changes and use them as indicators of the state of health of MOSFETs. A platform for testing characterizations is then established to monitor oscillator signals of source. Changes in oscillator signal measurement were observed with aged on-state resistance as a result of die-attach degradation. The experimental results demonstrate that the method is efficient. This study will enable a method to predict the failure of MOSFETs to be developed.

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Fujihira, Keiko, Naruhisa Miura, Tomokatsu Watanabe, Yukiyasu Nakao, Naoki Yutani, Kenichi Ohtsuka, Masayuki Imaizumi, Tetsuya Takami, and Tatsuo Oomori. "Realization of Low On-Resistance 4H-SiC Power MOSFETs by Using Retrograde Profile in P-Body." Materials Science Forum 556-557 (September 2007): 827–30. http://dx.doi.org/10.4028/www.scientific.net/msf.556-557.827.

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Inversion-type 4H-SiC power MOSFETs using p-body implanted with retrograde profiles have been fabricated. The Al concentration at the p-body surface (Nas) is varied in the range from 5×1015 to 2×1018 cm-3. The MOSFETs show normally-off characteristics. While the Ron is 3 cm2 at Eox = (Vg-Vth)/dox ≅ 3 MV/cm for the MOSFET with the Nas of 2×1018 cm-3, the Ron is reduced by a decrease in the Nas and 26 mcm2 is attained for the device with the Nas of 5×1015 cm-3. The inversion channel mobility and threshold voltage are improved with a decrease in the Nas. By modifying the structural parameter of the MOSFET, a still smaller Ron of 7 mcm2 is achieved with a blocking voltage of 1.3 kV.

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Wu, Li-Feng, Yong Guan, Xiao-Juan Li, and Jie Ma. "Anomaly Detection and Degradation Prediction of MOSFET." Mathematical Problems in Engineering 2015 (2015): 1–5. http://dx.doi.org/10.1155/2015/573980.

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The MOSFET is an important power electronic transistor widely used in electrical systems. Its reliability has an effect on the performance of systems. In this paper, the failure models and mechanisms of MOSFETs are briefly analyzed. The on-resistanceRonis the key failure precursor parameter representing the degree of degradation. Based on the experimental data, a nonlinear dual-exponential degradation model for MOSFETs is obtained. Then, we present an approach for MOSFET degradation state prediction using a strong tract filter based on the obtained degradation model. Lastly, the proposed algorithm is shown to perform effectively on experimental data. Thus, it can provide early warning and enhance the reliability of electrical systems.

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Xiong, Yali, Xu Cheng, Xiangcheng Wang, Pavan Kumar, Lina Guo, and Z. John Shen. "Performance Analysis of Trench Power MOSFETs in High-Frequency Synchronous Buck Converter Applications." International Journal of Power Management Electronics 2008 (June 9, 2008): 1–9. http://dx.doi.org/10.1155/2008/412175.

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This paper investigates the performance perspectives and theoretical limitations of trench power MOSFETs in synchronous rectifier buck converters operating in the MHz frequency range. Several trench MOSFET technologies are studied using a mixed-mode device/circuit modeling approach. Individual power loss contributions from the control and synchronous MOSFETs, and their dependence on switching frequency between 500 kHz and 5 MHz are discussed in detail. It is observed that the conduction loss contribution decreases from 40% to 4% while the switching loss contribution increases from 60% to 96% as the switching frequency increases from 500 KHz to 5 MHz. Beyond 1 MHz frequency there is no obvious benefit to increase the die size of either SyncFET or CtrlFET. The RDS(ON)×QG figure of merit (FOM) still correlates well to the overall converter efficiency in the MHz frequency range. The efficiency of the hard switching buck topology is limited to 80% at 2 MHz and 65% at 5 MHz even with the most advanced trench MOSFET technologies.

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Dhar, Sarit, Shurui Wang, John R. Williams, Sokrates T. Pantelides, and Leonard C. Feldman. "Interface Passivation for Silicon Dioxide Layers on Silicon Carbide." MRS Bulletin 30, no. 4 (April 2005): 288–92. http://dx.doi.org/10.1557/mrs2005.75.

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AbstractSilicon carbide is a promising semiconductor for advanced power devices that can outperform Si devices in extreme environments (high power, high temperature, and high frequency). In this article, we discuss recent progress in the development of passivation techniques for the SiO2/4H-SiC interface critical to the development of SiC metal oxide semiconductor field-effect transistor (MOSFET) technology. Significant reductions in the interface trap density have been achieved, with corresponding increases in the effective carrier (electron) mobility for inversion-mode 4H-SiC MOSFETs. Advances in interface passivation have revived interest in SiC MOSFETs for a potentially lucrative commercial market for devices that operate at 5 kV and below.

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Zhao, Jian H. "Silicon Carbide Power Field-Effect Transistors." MRS Bulletin 30, no. 4 (April 2005): 293–98. http://dx.doi.org/10.1557/mrs2005.76.

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AbstractSilicon carbide power field-effect transistors, including power vertical-junction FETs (VJFETs) and metal oxide semiconductor FETs (MOSFETs), are unipolar power switches that have been investigated for high-temperature and high-power-density applications. Recent progress and results will be reviewed for different device designs such as normally-OFF and normally-ON VJFETs, double-implanted MOSFETs, and U-shaped-channel MOSFETs. The advantages and disadvantages of SiC VJFETs and MOSFETs will be discussed. Remaining challenges will be identified.

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Tayade, Vinod Pralhad, and Swapnil Laxman Lahudkar. "Implementation of 20 nm Graphene Channel Field Effect Transistors Using Silvaco TCAD Tool to Improve Short Channel Effects over Conventional MOSFETs." Advances in Technology Innovation 7, no. 1 (October 5, 2021): 18–29. http://dx.doi.org/10.46604/aiti.2021.8098.

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In recent years, demands for high speed and low power circuits have been raised. As conventional metal oxide semiconductor field effect transistors (MOSFETs) are unable to satisfy the demands due to short channel effects, the purpose of the study is to design an alternative of MOSFETs. Graphene FETs are one of the alternatives of MOSFETs due to the excellent properties of graphene material. In this work, a user-defined graphene material is defined, and a graphene channel FET is implemented using the Silvaco technology computer-aided design (TCAD) tool at 100 nm and scaled to 20 nm channel length. A silicon channel MOSFET is also implemented to compare the performance. The results show the improvement in subthreshold slope (SS) = 114 mV/dec, ION/IOFF ratio = 14379, and drain induced barrier lowering (DIBL) = 123 mV/V. It is concluded that graphene FETs are suitable candidates for low power applications.

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Liu, Hongyu, Jianing Li, Yuanjie Lv, Yuangang Wang, Xiaoli Lu, Shaobo Dun, Tingting Han, et al. "Improved electrical performance of lateral β-Ga₂O₃ MOSFETs utilizing slanted fin channel structure." Applied Physics Letters 121, no. 20 (November 14, 2022): 202101. http://dx.doi.org/10.1063/5.0119694.

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In this Letter, lateral slanted-fin-channel β-Ga2O3 metal-oxide-semiconductor field effect transistors (MOSFETs) are demonstrated. A 600-nm thick n-type doped channel layer is adopted to improve output characteristics. The tri-gate structure enhances gate control in the proposed β-Ga2O3 MOSFETs, showing an on/off ratio as high as 109. In particular, the slanted-fin-channel structure, mainly located in the gate region, reduces the peak electric field in the Ga2O3 channel due to the gradual regulation of a threshold voltage. The slanted-fin-channel β-Ga2O3 MOSFETs show a breakdown voltage ( Vbr) of 2400 V and a power figure-of-merit of 193 MW/cm2, which are almost 2 and 5.5 times larger, respectively, than those of conventional straight-fin-channel devices. These results imply that the slanted-fin channel structure provides a viable way of fabricating high-performance β-Ga2O3 MOSFET power devices.

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38

Hoffmann, Felix, Stefan Schmitt, and Nando Kaminski. "Comparison of the H3TRB Performance of Silicon and Silicon Carbide Power Modules." Materials Science Forum 1062 (May 31, 2022): 487–92. http://dx.doi.org/10.4028/p-7j50kd.

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In this work, the H3TRB performance of power modules with SiC MOSFET chips is investigated and compared to their silicon counterparts with similar electrical ratings. For this purpose, SiC MOSFETs and silicon IGBT chips are packaged in the same housing and with the same packaging technology and an H3TRB test is performed on both types of test devices. The results show that while both types exhibit an excellent H3TRB performance, the SiC MOSFETs had a significantly longer time to failure but also a wider failure distribution. Hence, the investigations presented in this paper confirm that properly designed SiC devices feature an equal or even better ruggedness against electro-chemical stress than standard silicon devics and are equally suitable for applications, which require operation in harsh environments.

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SHENAI, K., K. F. GALLOWAY, and R. D. SCHRIMPF. "THE EFFECTS OF SPACE RADIATION EXPOSURE ON POWER MOSFETS: A REVIEW." International Journal of High Speed Electronics and Systems 14, no. 02 (June 2004): 445–63. http://dx.doi.org/10.1142/s0129156404002454.

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Power MOSFETs are a commonly used device for many switching and power control applications. Their upper frequency limit spans a fairly broad range, from 1 MHz to 10 MHz. These devices are frequently used in spaceborne electronic systems where they encounter radiation exposure during operation. This paper reviews the current technology, its high frequency capability, the future trends for power MOSFET technology, and the degradation that the power VDMOS technology experiences in the space radiation environment.

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Matacena, Ilaria, Luca Maresca, Michele Riccio, Andrea Irace, Giovanni Breglio, and Santolo Daliento. "Experimental Analysis of C-V and I-V Curves Hysteresis in SiC MOSFETs." Materials Science Forum 1062 (May 31, 2022): 669–75. http://dx.doi.org/10.4028/p-bzki64.

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SiC MOSFETs have already replace silicon-based device in power applications, even if some technological issues are still not solved. The most important of them is related to the complex traps distribution at SiC/SiO2 interface. Interface traps affect the overall device behavior, modifying channel mobility and introducing hysteresis. In this work experimental C-V and I-V curves are carried out on various commercial SiC MOSFET at different temperatures. The focus is the comparison of hysteresis arising in trench and planar SiC MOSFETs.

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Mbonane, Sandile H., and Viranjay Srivastava. "Class-B Power Amplifier with Si-Based Double-Gate MOSFET: A Circuit Perspective." Key Engineering Materials 907 (January 21, 2022): 50–56. http://dx.doi.org/10.4028/www.scientific.net/kem.907.50.

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This research work designs a power amplifier with the use of Silicon-based Double-Gate (DG) MOSFET. It is a novel device used to amplify the input signal of an audio signal, etc. This research paper provides information on the problem identification in the existing models and its design objectives with its design constraints. It also reduces crossover distortion due to DG MOSFET instead of BJTs and MOSFETs in the class-B power amplifier. This is a low-power device for the mA range using SiO2 as a dielectric material.

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Müting, Johanna, Bhagyalakshmi Kakarla, and Ulrike Grossner. "Comprehensive and Detailed Study on the Modeling of Commercial SiC Power MOSFET Devices Using TCAD." Materials Science Forum 897 (May 2017): 553–56. http://dx.doi.org/10.4028/www.scientific.net/msf.897.553.

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The main scattering mechanisms reducing the channel mobility and thus the typical performance of a SiC power MOSFET are reviewed. It is demonstrated that the Poisson equation within the drift-diffusion model is able to account for the effects of ionized impurity scattering. Furthermore, a correlation between the size of macro-or nanosteps at the SiC/SiO2 interface and the corresponding fitting parameter within the Lombardi surface roughness model is established. By qualitatively reproducing the typical performance of a commercial SiC power MOSFET a baseline for the TCAD modeling of power MOSFETs is provided.

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Katsueda, Mineo, and Tetsuo Iijima. "Switching power losses of power MOSFETs." Electrical Engineering in Japan 105, no. 6 (1985): 136–42. http://dx.doi.org/10.1002/eej.4391050616.

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Barbagallo, Carmelo, Santi Agatino Rizzo, Giacomo Scelba, Giuseppe Scarcella, and Mario Cacciato. "On the Lifetime Estimation of SiC Power MOSFETs for Motor Drive Applications." Electronics 10, no. 3 (January 30, 2021): 324. http://dx.doi.org/10.3390/electronics10030324.

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This work presents a step-by-step procedure to estimate the lifetime of discrete SiC power MOSFETs equipping three-phase inverters of electric drives. The stress of each power device when it is subjected to thermal jumps from a few degrees up to about 80 °C was analyzed, starting from the computation of the average power losses and the commitment of the electric drive. A customizable mission profile was considered where, by accounting the working conditions of the drive, the corresponding average power losses and junction temperatures of the SiC MOSFETs composing the inverter can be computed. The tool exploits the Coffin–Manson theory, rainflow counting, and Miner’s rule for the lifetime estimation of the semiconductor power devices. Different operating scenarios were investigated, underlying their impact on the lifetime of SiC MOSFETs devices. The lifetime estimation procedure was realized with the main goal of keeping limited computational efforts, while providing an effective evaluation of the thermal effects. The method enables us to set up any generic mission profile from the electric drive model. This gives us the possibility to compare several operating scenario of the drive and predict the worse operating conditions for power devices. Finally, although the lifetime estimation tool was applied to SiC power MOSFET devices for a general-purpose application, it can be extended to any type of power switch technology.

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Kim, Tae-Woo. "Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications." Electronics 9, no. 1 (December 26, 2019): 29. http://dx.doi.org/10.3390/electronics9010029.

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We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

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Ekanayake, Gihan, Mahesh Patil, Jae-Hyeong Seo, and Moo-Yeon Lee. "Numerical Study on Heat Transfer Characteristics of the 36V Electronic Control Unit System for an Electric Bicycle." Energies 11, no. 10 (September 20, 2018): 2506. http://dx.doi.org/10.3390/en11102506.

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The objective of this study was to numerically investigate the heat transfer characteristics of a 36V electronic control unit (ECU) system of an electric bicycle and to validate the experimental data. The temperatures of the ECU heatsink, seven metal-oxide-silicon field effect transistors (MOSFETs) and two capacitors of the 36V ECU system were numerically derived under variable operating conditions including power dissipation, thermal grease, ambient temperature and heatsink material, to analyze the heat transfer characteristics. When the thermal conductivity of the thermal grease increased from 0.01 W/m °C to 3.0 W/m° C, the temperatures of the seven MOSFETs and the two capacitors decreased by 51.245% and 3.58%, respectively. When the total power dissipation increased from 2.57 MW/m3 to 4.26 MW/m3, the temperatures of the ECU heatsink, seven MOSFETs and the two capacitors increased by 20.95%, 30.31% and 21.54%, respectively. Furthermore, increasing the ambient temperatures from 30 °C to 40 °C resulted in an increase in the temperatures of the ECU heatsink, MOSFET and capacitor by 24.75%, 9.93% and 22.04% respectively.. These numerically derived temperatures for the MOSFET and the ECU heatsink were validated with the experimental results within a range of 7.2% and 1.7%, respectively. This confirmed that the applied numerical model was valid.

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Satyanarayana, B. V. V., and M. Durga Prakash. "Design and Analysis of Heterojunction Tunneling Transistor (HETT) based Standard 6T SRAM Cell." International Journal of Engineering & Technology 7, no. 3.29 (August 24, 2018): 8. http://dx.doi.org/10.14419/ijet.v7i3.29.18450.

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Subthreshold Swing (SS) of MOSFETs, which determines the low voltage operation of portable mobile devices, cannot reduce below 60mV/dec that restricts MOSFETs for ultra-low power applications. This work presents design and implementation of high ON current, improved Miller capacitance and reduced Subthreshold Swing heterojunction tunneling transistors (HETTs) for portable electronic systems. The performance of HETT with MOSFET has been compared. In this work, the overlapping of gate/oxide on to source can increase the band to band tunneling (BTBT) and improves the ON current of the transistor. Miller capacitance effect can be reduced by the use of low band offset materials and low energy states of materials like Ge or SiGe. This, in turn, results in better performance characteristics for the transistor.The Proposed design and implementation of HETT include both N-type HETT (NHETT) and P-type HETT (PHETT) fabrications and the performance characteristics analysis of both NHETT and PHETT are provided. The advantages and limitations of both NHETT and PHETT for beyond CMOS technologies, in addition to the basic and structural differences between HETTs and conventional MOSFETs to facilitate the use of HETT in place of MOSFET have been elaborated in detail. The construction process of HETT is not at all completely different which is suitable to MOS Design process and is applicable for portable mobile applications. The power analysis of HETT based standard 6T SRAM cell is provided and the performance is verified with the conventional MOSFET based 6T SRAM cell.

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Bansal, Deepika, Bal Chand Nagar, Brahamdeo Prasad Singh, and Ajay Kumar. "Low Power Wide Fan-in Domino OR Gate Using CN-MOSFETs." International Journal of Sensors, Wireless Communications and Control 10, no. 1 (February 7, 2020): 55–62. http://dx.doi.org/10.2174/2210327909666190207163639.

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Background & Objective: In this paper, a modified pseudo domino configuration has been proposed to improve the leakage power consumption and Power Delay Product (PDP) of dynamic logic using Carbon Nanotube MOSFETs (CN-MOSFETs). The simulations for proposed and published domino circuits are verified by using Synopsys HSPICE simulator with 32nm CN-MOSFET technology which is provided by Stanford. Methods: The simulation results of the proposed technique are validated for improvement of wide fan-in domino OR gate as a benchmark circuit at 500 MHz clock frequency. Results: The proposed configuration is suitable for cascading of the high performance wide fan-in circuits without any charge sharing. Conclusion: The performance analysis of 8-input OR gate demonstrate that the proposed circuit provides lower static and dynamic power consumption up to 62 and 40% respectively, and PDP improvement is 60% as compared to standard domino circuit.

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Kaplar, R. J., D. R. Hughart, S. Atcitty, J. D. Flicker, S. DasGupta, and M. J. Marinella. "Performance and Reliability Characterization of 1200 V Silicon Carbide Power MOSFETs at High Temperatures." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2013, HITEN (January 1, 2013): 000275–80. http://dx.doi.org/10.4071/hiten-wp11.

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Commercially available, 1200 V SiC power MOSFETs have been characterized under bias-temperature stress conditions. Two generations of devices from a single manufacturer were tested. For the first-generation MOSFETs, both plastic- and metal-packaged devices were evaluated, whereas for the second-generation MOSFETs, only plastic-packaged devices were tested. Threshold voltage was observed to decrease with increasing temperature in the absence of gate bias stress, as expected. Drain leakage current increased with increasing temperature above the rated temperature of 125°C for first-generation plastic-packaged parts, with the leakage ~10× higher for the plastic-packaged parts compared to the metal-packaged parts. A negative gate voltage was shown to reduce drain leakage current for the metal-packaged parts only, suggesting a parasitic leakage path associated with the plastic packaging. The threshold voltage shift ΔVT was minimal for T < 125°C. ΔVT increased with increasing temperature above 125°C, and was larger for negative gate voltage bias stress, suggesting that the oxide is more sensitive to trapping of holes than trapping of electrons. ΔVT was insensitive to the type of package. The second-generation SiC MOSFET showed significantly less susceptibility to bias temperature stress, especially for negative gate voltage, indicating improvement in device design and/or processing in the second-generation MOSFET. Switching gate stress showed complex behavior, with a rapid initial shift in VT followed by a much slower shift. Initial testing indicates a strong dependence on duty cycle and possible influence of self-heating. More detailed study of reliability under switching conditions is needed.

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Xie, Li Jun, Jin Yuan Li, and Kun Shan Yu. "Study on Loss Calculation for Inverter Based on 1200V SiC MOSFET." Applied Mechanics and Materials 672-674 (October 2014): 906–13. http://dx.doi.org/10.4028/www.scientific.net/amm.672-674.906.

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SiC MOSFETs are expected as one of next generation power devices for their superior performances compared with conventional Si power devices and have become one of the new promising substitude to Si devices. The characteristics of 1200V SiC MOSFET are presented first and the power losses analysis model of SiC devices are given. As losses of power devices are essential parameters in converter design, the power dissipation of SiC MOSFET in SPWM inverter are calculated. In this paper, whether a free-wheeling-diode necessary is illustrated from the point of power dissipation and choice is made based on the power loss. According to the analysis result, the inverter without SBD shows less power losses, which can reduce the cost and volume of inverter.

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Journal articles on the topic 'Power MOSFETs'

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