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1
Amberetu, Mathew Atekwana. "Lateral superjunction power MOSFETs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp05/MQ63012.pdf.
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Dharmawardana, Kahanawita Gamaethiralalage Padmapani. "High performance power MOSFETs." Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.621963.
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Leedham, Robert John. "High frequency switching with power MOSFETs." Thesis, University of Cambridge, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.627468.
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Chen, Yuhui. "Resonant Gate Drive Techniques for Power MOSFETs." Thesis, Virginia Tech, 2000. http://hdl.handle.net/10919/10099.
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With the use of the simplistic equivalent circuits, loss mechanism in conventional power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) gate drive circuits is analyzed. Resonant gate drive techniques are investigated and a new resonant gate drive circuit is presented. The presented circuit adds minor complexity to conventional gate drivers but reduces the MOSFET gate drive loss very effectively. To further expand its use in driving Half-Bridge MOSFETs, another circuit is proposed in this thesis. The later circuit simplifies the isolation circuitry for the top MOSFET and meanwhile consumes much lower power than conventional gate drivers.Master of Science
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Xiangxiang, Fang. "Characterization and Modeling of SiC Power MOSFETs." The Ohio State University, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=osu1354687371.
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Liu, Jingjing Michelle. "Strain induced effects on lateral power MOSFETs." [Gainesville, Fla.] : University of Florida, 2009. http://purl.fcla.edu/fcla/etd/UFE0041290.
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Zupac, Dragan 1961. "ESD-induced noncatastrophic damage in power MOSFETs." Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/291470.
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Electrostatic discharge (ESD) may, depending on the energy of the pulse, cause either catastrophic failures or degradation of MOSFETs. Effects of noncatastrophic positive Human-Body Model (HBM) ESD stress at the gate of power MOSFETs are investigated in this work. Noncatastrophic damage is manifested in the form of positive charge trapping in the gate oxide. In p-channel devices used in this study, the charge injection and trapping occur predominantly in the gate oxide areas lying above the p-body region. In p-channel devices used, the charge is injected mainly from the p-drain region. Based on the polarity of the pulse and the regions observed to contribute to charge injection, a model of ESD-induced charge injection from the silicon into the oxide is proposed. Finally, the effects of noncatastrophic ESD events on the radiation response of n-channel power MOSFETs are reported.
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DE, GASPERI SERGIO. "Integrated health condition monitoring for power MOSFETs." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2022. http://hdl.handle.net/10281/392351.
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I semiconduttori di potenza hanno un ruolo cruciale nella conversione e distribuzione dell'energia elettrica.
I MOSFET di potenza, in particolare, possono essere trovati in una grande varietà di applicazioni, quali elettronica di consumo, settore automotive o nella rete elettrica. Una tecnologia così obiquitaria è naturalmente soggetta a incesstanti sforzi di ottimizzazione dei costi di produzione.
La minimizzazione dell'impiego di materiali è il modo più diretto per ottimizzare i costi, ed implica una riduzione dell'area di silicio utilizzata per ogni dispositivo. Questo a sua volta porta ad un aumento delle densità di potenza termica dissipata.
Di conseguenza, i MOSFET di potenza devono poter operare sopportando intensi stress termomeccanici, che costituiscono un importante rischio di affidabilità in molti campi di applicazione.
Questa tesi incentrata su una tecnologia DMOS verticale, per la quale per la quale la degradazione della metallitazione di potenza è la principale causa di rottura tra quelle legate a stress termomeccanico.
Un metodo percorribile per il miglioramento dell'affidabilità dei dispositivi presi in considerazione è l'implementazione di capacità di prognosi delle condizioni di integrità del dispositivo. In questa tesi è proposta un'indagine sperimentale di due metodi di implementazione.
Il primo metodo consiste nella realizzazione di una struttura non vitale per il funzionamento del dispositivo di potenza. Tale struttura, come la metallizazione di potenza, si degrada a causa dello stress termomeccanico, che provoca cortocircuiti nella struttura stessa.
Il secondo metodo proposto si affida alla misura della temperatura del dispositivo in diversi punti durante un transiente di potenza. La degradazione della metallizazione di potenza porta alla rottura del dispositivo proprio perché induce dei cambiamenti nelle proprietà termiche dello stesso, pertanto, delle misure termiche possono consentire di monitorare i risultati del processo di degradazione.
Gli esperimenti hanno parzialmente confermato la validità dei metodi presi in considerazione, ma le forme di implementazione testate non sono applicabili in un contesto industriale. Per entrambi gli esperimenti condotti, sia i limiti di tempo che la necessità di affrontare campi molto diversi tra loro (circuit design, technology development, test engineering, scienze dei materiali) hanno costituito una sfida significativa. L'esperienza acquisita nello sviluppo delle due tecniche ha portato, come risultato, alla definizione di un concept per una terza tecnica, descritta nell'ultimo capitolo della tesi.
Concludendo, questa tesi dimostra la possibilità di sviluppare tecniche innovative per la soluzione del problema posto, e i risultati ottenuti pongono le basi per eventuali future indagini, che potrebbero avere maggiore successo nella realizzazione di implementazioni efficaci.Power semiconductors have a crucial role in conversion and distribution of electric energy. Power MOSFETs, especially, can be found in a large variety of applications, like consumer electronics, automotive or grid applications. Such an ubiquitous technology is indeed subject to unceasing cost-optimization efforts. Minimization of materials usage is the most straightforward way to cost optimization, and it comes together with a decrease in the footprint size of devices. This comes at cost of an increase in power densities, and therfore an increase in heat dissipation per unit area. As a result, during operation, power MOSFETs need to withstand intense thermo-mechanical stress, which is the main reliability concern on many application fields. This thesis is focused on a vertical DMOS technology, for which power metallization degradation is the main stress-related failure cause. A possible way to improve reliability of power MOSFETs is to implement in-situ prognostic health management capabilities: in this thesis, two implementation methods are experimentally investigated. The first method consists of building a non-vital structure that shares the same degradation driving force as power metallization, although the degradation process is different. Thermo-mechanical stress results in the formation of short circuits into the non-vital structure, which are electrically detectable. The second method here proposed relies on local temperature measurements in different spots of the DMOS during power transients. Power metallization degradation leads to failure precisely because it modifies the thermal behavior of the device, therefore, temperature measurements may allow to directly observe the outcome of degradation. Experiments partially validate the investigated health monitoring principles, but the implementation tested so far are not reliable enough for industrial application. For both experiments, time limitations and the need for different actions in very diverse fields (circuit design, technology development, test engineering, materials science) posed a remarkable challenge. As a result, the experience acquired in the development of the two techniques shaped a concept for a third solution, that is only conceptually described in the last part of this thesis. As a conclusion, this thesis demonstrates that innovative solutions to the problem can be developed through an effort on different fields of expertise, and the achieved preliminary results pose a promising outlook for further investigations, which may successfully develop robust and reliable implementations.
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Safarjameh, Kourosh 1961. "Fast-neutron-induced resistivity change in power MOSFETs." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277011.
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Fast neutron irradiation tests were performed to determine the correlation of change of drain-source resistance and neutron fluence for power MOSFETs. The Objectives of the tests were: (1) to detect and measure the degradation of critical MOSFET device parameters as a function of neutron fluence (2) to compare the experimental results and the theoretical model. In general, the drain-source resistance increased from 1 Ohm to 100 Ohm after exposure to fast neutron fluence of 3 x 1014 neut/cm2, and decreased by a factor of five after high temperature annealing.
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Fayyaz, Asad. "Performance and robustness characterisation of SiC power MOSFETs." Thesis, University of Nottingham, 2018. http://eprints.nottingham.ac.uk/48937/.
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Over the last few years, significant advancements in the SiC power MOSFET fabrication technology has led to their wide commercial availability from various manufacturers. As a result, they have now transitioned from being a research activity to becoming an industrial reality. SiC power MOSFET technology offers great benefits in the electrical energy conversion domain which have been widely discussed and partially demonstrated. Superior material properties of SiC and the consequent advantages are both later discussed here. For any new device technology to be widely implemented in power electronics applications, it’s crucial to thoroughly investigate and then validate for robustness, reliability and electrical parameter stability requirements set by the industry. This thesis focuses on device characterisation of state-of-the-art SiC power MOSFETs from different manufacturers during short circuit and avalanche breakdown operation modes under a wide range of operating conditions. The functional characterisation of packaged DUTs was thoroughly performed outside of the safe operating area up until failure test conditions to obtain absolute device limitations. For structural characterisation, Infrared thermography on bare die DUTs was also performed with an aim to observe hotspots and/or degradation of the structural features of the device. The experimental results are also complemented by 2D TCAD simulation results in order to get a further insight into the underlying physical mechanisms behind failure during such operation regimes. Moreover, the DUTs were also tested for body diode characterisation with an aim to observe degradation and instability of electrical device parameters which may adversely affect the performance of the overall system. Such investigations are really important and act as a feedback to device manufacturers for further technological improvements in order to overcome the highlighted issues with an aim to bring about advancements in device design to meet the ever-increasing demands of power electronics.
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Kulisek, Jonathan Andrew. "The Effects of Nuclear Radiation on Schottky Power Diodes and Power MOSFETs." The Ohio State University, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=osu1267502877.
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Wang, Wei. "Power Module with Series-connected MOSFETs in Flip-chip Configuration." Thesis, Virginia Tech, 2010. http://hdl.handle.net/10919/36036.
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Power module design is needed for high system performance and reliability, especially in terms of high efficiency and high power density. Low parasitic impedance and thermal management is desired for the lower power loss and device stress.
For power module with high efficiency and improved breakdown voltage, this thesis proposes a novel series-connected power MOSFETs module. Three IRF7832 MOSFETs (30 V breakdown voltage) in series are simulated in a chopper circuit. The drain-source voltage sharing in switching off-mode shows that the devices can share voltage within their breakdown ranges. The switching characteristics are studied, and the switching energy losses without parasitic inductance and with 5 nH parasitic inductances are 203.38 µJ and 316.49 µJ, respectively. The critical parasitic inductance is the one connecting the source of the upper MOSFET and the drain of the middle MOSFET. The switching energy loss due to critical parasitic inductance is about 44.4% of the total switching energy loss. The layout is designed for the double-substrates direct-bond module and wire-bonded module using direct-bond-copper (DBC) substrate. Based on layout dimensions and packaging materials, the packaging moduleâ s parasitic parameters are obtained using Ansoft® Q3D extractor. Using parasitic inductance values from simulation, the switching energy losses of direct-bond module and wire-bonded module are 296.18 µJ and 238.99 µJ, respectively. Thermal management is then studied using Ansoft® ePhysics. The MOSFET junction-to-air thermal resistances of the double-substrate direct-bond module and the single-substrate wire-bonded module are 33oC/W and 82oC/W, respectively. Hence, by comparing the direct-bond module with a wire-bonded power module, direct-bond module shows lower parasitic impedances and better thermal management.
To test the breakdown voltage of series-connected power MOSFETs module, three TI DualCoolTM N-channel NexFET Power MOSFETs (25 V breakdown voltage) in series are assembled using flip-chip direct-bond technology. Three samples are assembled and the breakdown voltages are measured by using high-power curve tracer as 76 V, 82 V, and 72 V. The more accurate method for testing breakdown voltages by digital voltmeter obtains 77.51 V, 82.31 V, and 73.06 V. The series-connected power MOSFETs module shows compact volume, low parasitic impedances, thermal resistances and improved breakdown voltage. This power module has strong potential for use in applications that require minimized packaging size and parasitic inductance for high voltage, high switching frequency, and high efficiency.Master of Science
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Evans, J. L. "The design and manufacture of trench gated power MOSFETs." Thesis, University of Cambridge, 1997. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.598877.
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During the past five years, power MOSFET technology has enjoyed an enormous growth in popularity as device performances have increased and costs have dropped, allowing the power MOSFET to become attractive to a very wide number of applications. The DMOS transistor has been the dominant power MOSFET technology for the past twenty years. However the demands placed on power MOSFET costs and performances by such markets as the automotive and communications sectors, has meant that the trench gated power MOSFET (or UMOSFET) is seen as the technology of the future. This project was funded by the Ford Motor Company under the Teaching Company Scheme to specifically develop a low cost power device technology for the automotive market. This dissertation reports work which falls into three categories: 1. Theoretical - a new description of the operation of the power MOSFET is presented. This has proved valuable in describing and predicting the behaviour of power MOSFETs especially when operating at high current densities. 2. Conceptual - a new manufacturing technique for trench gated power MOSFETs is described which substantially improves the achievable performance of such devices through the elimination of critical alignment steps. Dramatic cost reductions are possible too with the elimination of expensive implants, sub-micron lithography steps etc. A complete one mask version of the proposed process flow is also described. 3. Practical - extensive experimental work is discussed, addressing the many manufacturing concerns relating to trench gated devices. Extensive use is made of electrical and physical modelling programs to quantify predictions, and to verify the validity of proposed processes in the absence of experimental results. A program has been written specifically to accurately model the effect of the gate arrays of such devices on the switching performance. An interesting comparison is made between the proposed novel manufacturing technique and current state of the art DMOS and UMOS devices, as well as a comparison of high voltage power MOSFETs and IGBTs manufactured using the same technique.
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Landowski, Matthew. "DESIGN AND MODELING OF RADIATION HARDENED LATERAL POWER MOSFETS." Master's thesis, University of Central Florida, 2009. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/2823.
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Galactic-cosmic-rays (GCR) exist in space from unknown origins. A cosmic ray is a very high energy electron, proton, or heavy ion. As a GCR transverses a power semiconductor device, electron-hole-pairs (ehps) are generated along the ion track. Effects from this are referred to as single-event-effects (SEEs). A subset of a SEE is single-event burnout (SEB) which occurs when the parasitic bipolar junction transistor is triggered leading to thermal runaway. The failure mechanism is a complicated mix of photo-generated current, avalanche generated current, and activation of the inherent parasitic bipolar transistor. Current space-borne power systems lack the utility and advantages of terrestrial power systems. Vertical-double-diffused MOSFETs (VDMOS) is by far the most common power semiconductor device and are very susceptible to SEEs by their vertical structure. Modern space power switches typically require system designers to de-rate the power semiconductor switching device to account for this. Consequently, the power system suffers from increased size, cost, and decreased performance. Their switching speed is limited due to their vertical structure and cannot be used for MHz frequency applications limiting the use of modern digital electronics for space missions. Thus, the Power Semiconductor Research Laboratory at the University of Central Florida in conjunction with Sandia National Laboratories is developing a rad-hard by design lateral-double-diffused MOSFET (LDMOS). The study provides a novel in-depth physical analysis of the mechanisms that cause the LDMOS to burnout during an SEE and provides guidelines for making the LDMOS rad-hard to SEB. Total dose radiation, another important radiation effect, can cause threshold voltage shifts but is beyond the scope of this study. The devices presented have been fabricated with a known total dose radiation hard CMOS process. Single-event burnout data from simulations and experiments are presented in the study to prove the viability of using the LDMOS to replace the VDMOS for space power systems. The LDMOS is capable of higher switching speeds due to a reduced drain-gate feedback capacitance (Miller Capacitor). Since the device is lateral it is compatible with complimentary-metal-oxide-semiconductor (CMOS) processes, lowering developing time and fabrication costs. High switching frequencies permit the use of high density point-of-load conversion and provide a fast dynamic response.M.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE
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Shea, Patrick Michael. "Lateral power MOSFETs hardened against single event radiation effects." Doctoral diss., University of Central Florida, 2011. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4705.
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The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metrics.ID: 030646200; System requirements: World Wide Web browser and PDF reader.; Mode of access: World Wide Web.; Thesis (Ph.D.)--University of Central Florida, 2011.; Includes bibliographical references (p. 161-166).
Ph.D.
Doctorate
Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering
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Yiin, Andy Jyhpyng 1962. "Gate-charge characterization of irradiated N-channel power MOSFETs." Thesis, The University of Arizona, 1991. http://hdl.handle.net/10150/277890.
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The effects of ionizing-radiation-induced oxide-trapped and interface-trapped charges on gate-charge measurements of power MOSFETs are investigated. Both radiation-hardened and commercial DMOS power transistors are tested in this study. Experimental results show that: (1) the radiation-induced interface-trapped charge is related to the changes in the plateau length, and (2) the radiation-induced charges at threshold can be directly measured from the changes in the gate-to-source charge. A new charge separation technique based on the gate-charge measurement is developed. Moreover, the radiation-induced changes in the gate-charge curve provide information on the shift in threshold voltage, the increase in the plateau length, and the effective changes in gate-to-source capacitance and charge. This information should be used by the power-supply designers to compensate for radiation-induced changes in the power-MOSFET characteristics.
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Hoagland, Richard W. "Time domain device modeling of High Frequency Power MOSFETs." Thesis, This resource online, 1993. http://scholar.lib.vt.edu/theses/available/etd-01102009-063443/.
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NEDELJKOVIC, SONJA R. "PARAMETER EXTRACTION AND DEVICE PHYSICS PROJECTIONS ON LATERAL LOW VOLTAGE POWER MOSFET CONFIGURATIONS." University of Cincinnati / OhioLINK, 2001. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1005163403.
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Welchko, Brian A. "A High Power DC Motor Controller for an Electric Race Car Using Power Mosfets." Ohio University / OhioLINK, 1996. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1239733975.
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Welchko, Brian A. "A high power DC motor controller for an electrical race car using power MOSFETS." Ohio : Ohio University, 1996. http://www.ohiolink.edu/etd/view.cgi?ohiou1239733975.
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Rong, Hua. "Development of 4H-SiC power MOSFETs for high voltage applications." Thesis, University of Warwick, 2015. http://wrap.warwick.ac.uk/79426/.
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Silicon carbide is a promising wide bandgap semiconductor for high-power, high-temperature and high frequency devices, owing to its high breakdown electric field strength, high thermal conductivity and ability to grow high quality SiO2 layers by thermal oxidation. Although the SiC power MOSFET (metal-oxide-semiconductor field effect transistor) is preferred as a power switch, it has suffered from low channel mobility with only single digit field effect mobility achieved using standard oxidation process (1200◦C thermal oxidation). As such, this thesis is focussed on the development of 4H-SiC MOSFETs (both lateral and vertical MOSFETs) to improve the channel mobility and breakdown characteristics of these devices. In this work, high temperature nitridation using N2O has been investigated on MOS capacitors and MOSFETs, both with gate oxides grown directly in N2O environment or in a O2 ambient followed by a N2O post-oxidation annealing process. Results have demonstrated that at high temperature (>1200◦C) there is a significant improvement in the interface trap density to as low as (1.5x10^11cm-2eV-1) and field effect channel mobility (19cm2/V.s) of 4H-SiC MOSFET compare with a lower temperature (between 800 and 1200◦C) oxidation (1x10^12cm-2eV-1 and 4cm2/V.s). Nitridation temperatures of 1300◦C was found to be the most effective method for increasing the field effect channel mobility and reducing threshold voltage. The number of working devices per sample also increased after N2O nitridation at 1300◦C as observed for both lateral and vertical MOSFETs. Other post oxidation techniques have also been investigated such as phosphorous passivation using solid SiP2O7 planar diffusion source (PDS). The peak value of the field effect mobility for 4H-SiC MOSFET after phosphorus passivation is approximately 80cm2/V.s, which is four times more than the valued obtained using high temperature N2O annealing. Different JTE structures have been designed and simulated including single-zone JTE, space modulated JTE (SMJTE) and the novel two-step mesa JTE structures. It was found that for the same doping concentration the SM two-zone JTE and SMJTE have higher breakdown voltage than the single zone JTE. With SMJTE, the device could achieve more than 90% of the ideal parallel plane voltage from simulations and 86% from the breakdown test of the fabricated devices.
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Nassif-Khalil, Sameh G. "CMOS-compatible power MOSFETs for on-chip DC/DC converters." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2000. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape4/PQDD_0023/MQ50383.pdf.
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Wahle, Peter Joseph 1961. "Radiation effects on power MOSFETs under simulated space radiation conditions." Thesis, The University of Arizona, 1989. http://hdl.handle.net/10150/277024.
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Application of power MOSFETs in spaceborne power converters was simulated by exposing devices to low-dose-rate ionizing radiation. Both radiation-hardened and nonhardened devices were tested with constant and switched gate biases during irradiation. In addition, some of the devices were under load. The threshold-voltage shifts were strongly bias dependent. The threshold-voltage shift of the nonhardened parts was approximately dose-rate independent, while the hardened parts exhibited significant dose-rate dependence. A pre-anneal dose-rate dependence was found for the interface-state buildup of the switched and positively biased devices, but the results for the switched devices were qualitatively different than those for the positively biased devices. The buildup of interface trapped charge was found to be the primary contributor to mobility degradation, which results in reduced drive capability and slower operation of the devices. These results indicate that new methods need to be utilized to accurately predict the performance of power MOSFETs in space environments.
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Hasan, Samil Mukhlisin Yauma 1967. "Neutron irradiation effects on the breakdown voltage of power MOSFETs." Thesis, The University of Arizona, 1993. http://hdl.handle.net/10150/278361.
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The effect of neutron irradiation on power metal-oxide-semiconductor field effect transistors (power MOSFETs) breakdown voltage has been investigated. Power MOSFETs of both n- and p-channel with manufacturer's rated breakdown voltage between 100 to 500V were radiated up to accumulated neutron fluence of 5x10¹⁴ neutron/cm² Considerable increase in the breakdown voltages were observed in n-type MOSFETs after 10¹³ neutron/cm² and to p-type MOSFETs after 10¹² neutron/cm² The increase in breakdown voltages is due to the decrease in the mean free path caused by the neutron-irradiation-induced defects. The effect of positive trapped charge oxide and the termination structure to the breakdown voltage were considered. S-PISCES 2B device simulation was used to investigate the change in the b coefficient of Chynoweth's law that relates to the mean free path. Two empirical models are presented: one predicts the power MOSFET breakdown voltage after a certain amount of neutron fluence and the other considers the change in the b coefficient after some amount of neutron radiation to predict the change of breakdown voltage in a device simulation.
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Linewih, Handoko, and h. linewih@griffith edu au. "Design and Application of SiC Power MOSFET." Griffith University. School of Microelectronic Engineering, 2003. http://www4.gu.edu.au:8080/adt-root/public/adt-QGU20030506.013152.
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This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.
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Linewih, Handoko. "Design and Application of SiC Power MOSFET." Thesis, Griffith University, 2003. http://hdl.handle.net/10072/367638.
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This thesis focuses on the design of high voltage MOSFET on SiC and its application in power electronic systems. Parameters extraction for 4H SiC MOS devices is the main focus of the first topic developed in this thesis. Calibration of two-dimensional (2-D) device and circuit simulators (MEDICI and SPICE) with state-of-the-art 4H SiC MOSFETs data are performed, which includes the mobility parameter extraction. The experimental data were obtained from lateral N-channel 4H SiC MOSFETs with nitrided oxide-semiconductor interfaces, exhibiting normal mobility behavior. The presence of increasing interface-trap density (Dit) toward the edge of the conduction band is included during the 2-D device simulation. Using measured distribution of interface-trap density for simulation of the transfer characteristics leads to good agreement with the experimental transfer characteristic. The results demonstrate that both MEDICI and SPICE simulators can be used for design and optimization of 4H SiC MOSFETs and the circuits utilizing these MOSFETs. Based on critical review of SiC power MOSFETs, a new structure of SiC accumulation-mode MOSFET (ACCUFET) designed to address most of the open issues related to MOS interface is proposed. Detailed analysis of the important design parameters of the novel structure is performed using MEDICI with the parameter set used in the calibration process. The novel structure was also compared to alternative ACCUFET approaches, specifically planar and trench-gate ACCUFETs. The comparison shows that the novel structure provides the highest figure of merit for power devices. The analysis of circuit advantages enabled by the novel SiC ACCUFET is given in the final part of this thesis. The results from circuit simulation show that by utilizing the novel SiC ACCUFET the operating frequency of the circuit can be increased 10 times for the same power efficiency of the system. This leads to dramatic improvements in size, weight, cost and thermal management of power electronic systems.Thesis (PhD Doctorate)
Doctor of Philosophy (PhD)
School of Microelectronic Engineering
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Huang, Chender 1960. "Characterization of interface trap density in power MOSFETs using noise measurements." Thesis, The University of Arizona, 1988. http://hdl.handle.net/10150/276872.
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Low-frequency noise has been measured on commercial power MOSFETs. These devices, fabricated with the VDMOS structure, exhibit a 1/f type noise spectrum. The interface state density obtained from noise measurements was compared with that obtained from the subthreshold-slope method. Reasonable agreement was found between the two measurements. The radiation effects on the noise power spectral density were also investigated. The results indicated that the noise can be attributed to the generation of interface traps near the Si-SiO₂ interface. The level of interface traps generated by radiation was bias dependent. The positive gate bias gave rise to the largest interface-trap density.
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Mulpuri, Vamsi. "Failure Analysis and High Temperature Characterization of Silicon Carbide Power MOSFETs." University of Akron / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=akron151076214366849.
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Dibra, Donald [Verfasser]. "Single Pulse Safe Operating Area of Trench Power MOSFETs in Automotive Power Integrated Circuits / Donald Dibra." München : Verlag Dr. Hut, 2011. http://d-nb.info/1018982922/34.
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Xiong, Yali. "MODELING AND ANALYSIS OF POWER MOSFETS FOR HIGH FREQUENCY DC-DC CONVERTERS." Doctoral diss., University of Central Florida, 2008. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3589.
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Evolutions in integrated circuit technology require the use of a high-frequency synchronous buck converter in order to achieve low cost, low profile, fast transient response and high power density. However, high frequency operation leads to increased power MOSFET switching losses. Optimization of the MOSFETs plays an important role in improving converter performance. This dissertation focuses on revealing the power loss mechanism of power MOSFETs and the relationship between power MOSFET structure and its power loss. The analytical device model, combined with circuit modeling, cannot reveal the relationship between device structure and its power loss due to the highly non-linear characteristics of power MOSFETs. A physically-based mixed device/circuit modeling approach is used to investigate the power losses of the MOSFETs under different operating conditions. The physically based device model, combined with SPICE-like circuit simulation, provides an expeditious and inexpensive way of evaluating and optimizing circuit and device concepts. Unlike analytical or other SPICE models of power MOSFETs, the numerical device model, relying little on approximations or simplifications, faithfully represents the behavior of realistic power MOSFETs. The impact of power MOSFET parameters on efficiency of synchronous buck converters, such as gate charge, on resistance, reverse recovery, is studied in detail in this thesis. The results provide a good indication on how to optimize power MOSFETs used in VRMs. The synchronous rectifier plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact SyncFET's performance. This thesis gives a detailed analysis of the SyncFET operation mechanism and provides several techniques to reduce its body-diode influence and suppress its false Cdv/dt trigger-n. This thesis also investigates the influence of several circuit level parameters on the efficiency of the synchronous buck converter, such as input voltage, circuit parasitic inductance, and gate resistance to provide further optimization of synchronous buck converter design.Ph.D.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering PhD
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Akram, Farhan. "Gate driver solutions for high power density SMPS using Silicon Carbide MOSFETs." Thesis, Mittuniversitetet, Institutionen för elektronikkonstruktion, 2021. http://urn.kb.se/resolve?urn=urn:nbn:se:miun:diva-41188.
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Discrete silicon carbide (SiC) power devices have unique characteristics that outpace those of silicon (Si) counterparts. The improved physical features have provided better faster switching, greater current densities, lower on-resistance, and temperature performances. However, there is lack of suitable commercial gate drivers that are compatible for high-voltage, and high-speed devices. There has been a great research effort required for the advancement of gate drivers for high voltage SiC transistors. A drive circuit for a SiC MOSFET needs to be optimized in normal operation to give best efficiency and same drive circuit should secure the MOSFET under unsuitable conditions. To ensure the rapid switching of these advanced SiC MOSFETs, a gate driver capable of providing the high current capability is required. In this work, three different high-power-density, high-speed, and high-noise-immunity gate driver modules for 10 kV SiC MOSFET were built and optimized. Double-pulse test was developed for the dynamic characterization of SiC MOSFETs and gate drivers. This setup provided clean measurements of DUT voltage and current under well-defined conditions and correlated to simulation results. Designed gate drivers have thoroughly investigated to test and compare it with our future design. The influential parameters such as dV/dt, dI/dt, and gate driving capability of gate driver were adjusted according to the requirements. The short circuit protection test was performed to check the reliability of driver modules in worst conditions. Furthermore, a DC-DC converter was designed and tested with the advanced gate drivers. The driver modules were tested in designed converter under different load conditions and influential parameters were successfully demonstrated. The driver modules effectively helped in reducing the EMI and switching losses. These designed gate drivers and prototype converter provide all the attractive features and can be widely implemented in industrial applications for energy efficient systems.
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Hopkins, Andrew Neil. "Ancillary techniques for enabling high efficiency power conversion with super junction MOSFETs." Thesis, University of Bristol, 2018. https://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.738328.
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Ralston, Parrish Elaine. "Design and Verification of a High Voltage, Capacitance Voltage Measurement System for Power MOSFETs." Thesis, Virginia Tech, 2008. http://hdl.handle.net/10919/36169.
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There is a need for a high voltage, capacitance voltage (HV, CV) measurement system for the measurement and characterization of silicon carbide (SiC) power MOSFETs. The following study discusses the circuit layout and automation software for a measurement system that can perform CV measurements for all three MOSFET capacitances, CGS, CDS, and CGD. This measurement system can perform low voltage (0â 40V) and high voltage (40â 5kV) measurements. Accuracy of the measurement system can be safely and effectively adjusted based on the magnitude of the MOSFET capacitance. An IRF1010N power MOSFET, a CoolMos, and a prototype SiC power MOSFET are all measured and their results are included in this study. All of the results for the IRF1010N and the CoolMos can be verified with established characteristics of power MOSFET capacitance. Results for the SiC power MOSFET prove that more testing and further development of SiC MOSFET fabrication is needed.Master of Science
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Chern, Winston. "Prospects of germanium-based MOSFETs and tunnel transistors for low power digital logic." Thesis, Massachusetts Institute of Technology, 2017. http://hdl.handle.net/1721.1/109010.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2017.Cataloged from PDF version of thesis.
Includes bibliographical references (pages 157-167).
Moore's law has driven technological improvements for decades by halving the areal footprint of the transistor every two years and increasing the performance of making integrated circuits while reducing their cost. The ability to reduce the footprint of the device was enabled by advances in processing technology, novel materials and device design. As ever-smaller footprints are desired, power density limitations and performance degradation require more innovations on all fronts. Recently introduced improvements to integrated circuits are high-K and metal gate for MOSFETs (45-nm node onward), the FinFET (22-nm node onward) and air gaps between copper interconnects (14-nm node) illustrating that at every new technology node there needs to be a materials or process-related improvement to reduce power and maintain performance. Other approaches are also being explored or taken to further improve the MOSFET performance in future technology nodes, namely use of channel materials with higher carrier mobility such as SiGe and Ge for p-MOSFETs, III-V compound semiconductors for n-MOSFETs and steep subthreshold swing devices such as tunnel field effect transistors (TFETs). This work evaluates both approaches utilizing germanium (Ge) and strained-Ge as a material to understand the benefits and drawbacks to both approaches. Hypothetically, high carrier mobility and velocity channel materials can lower the overall power consumption because lower power supply voltage is required to obtain the same amount of current. Germanium and strained-Ge are candidates for the channel material of p-MOSFETs. MOSFETs made using Ge and strained-Ge as the channel material are evaluated based upon the ITRS roadmap requirements using experimental results in this work and data from literature. The approach for using TFETs was evaluated in this work also using germanium as a channel material. TFETs can have a steep subthreshold swing (SS), better than the minimum of 60 mV/decade at room temperature for a MOSFET, which also reduces the total power and supply voltage required for operation. The reduced SS is hypothetically achieved through the band-to-band tunneling which allows for the filtering of the Fermi-tail distribution of carriers. Experimentally, TFETs have not generally shown the steeper than Fermi-tail SS promised by the theory and this work uses both results from fabricated strained-Si/strained-Ge TFETs as well as modeling to explain why this has been the case. The challenges for both technologies are outlined in this thesis and suggestions are made on approaches to tackling their respective intrinsic problems from the point of view of Ge-based devices.
by Winston Chern.
Ph. D.
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Sachdeva, Rishi. "A two-stage gate drive scheme for snubberless operation of power MOSFETs and IGBTs." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 2001. http://www.collectionscanada.ca/obj/s4/f2/dsk3/ftp04/mq65166.pdf.
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Smith, Mark John. "Low temperature phonon-drag thermoelectric power calculations in GaAs/GaAlAs heterojunctions and Si MOSFETs." Thesis, University of Warwick, 1989. http://wrap.warwick.ac.uk/4163/.
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The effect on the electron transport of the confinement of the electrons to a narrow channel in GaAs/GaAlAs heterojunctions and Si MOSFETs is reflected in quantities like the thermopower (S) which is sensitive to the transport of both heat and charge. The calculations described here confirm that in these systems S is dominated by phonondrag (Sg) at temperatures (T) around 1-10K and reveals more sensitivity than previously imagined. Simple models and the Boltzmann transport formalism have been investigated. The formalism enhances the predictions of the simple models and reproduces the simple S. formulae in appropriate limits. Amplification of S9 in quasi-2D arises from the loss of the momentum conservation constraint across the channel at small widths b. Earlier calculations were numerically inaccurate and greatly overestimate -S9 by ignoring screening. An effective multi-subband screening dielectric function is defined which reduces to the single subband approximation at small b and low electron density (n). Nondegeneracy has also been included. It is an important consideration despite the low temperatures of most of the data. The treatment of electron confinement has been improved and the temperature dependence of the polarizability investigated. It is unimportant in the current experimental systems but significant at lower n and higher T. The piezoelectric scattering mechanism has been introduced and dominates S. in the heterojunction for T <1K. A dominant 2D wavevector component has been defined for the phonon population at given T which is very helpful in understanding S9. A correction for the energy dependence of the electron relaxation-time is necessary and demonstrates the dependence of S. upon the dominant electron scattering mechanism. The calculations of S. in the quantum-limit and boundary scattering regime now explain the measured S in heterojunctions and peaks in -Sg/T3 in the MOSFET up to an accuracy better than 10% without adjustable parameters.
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Marzoughi, Alinaghi. "Investigating Impact of Emerging Medium-Voltage SiC MOSFETs on Medium-Voltage High-Power Applications." Diss., Virginia Tech, 2018. http://hdl.handle.net/10919/81822.
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For decades, the Silicon-based semiconductors have been the solution for power electronics applications. However, these semiconductors have approached their limits of operation in blocking voltage, working temperature and switching frequency. Due to material superiority, the relatively-new wide-bandgap semiconductors such as Silicon-Carbide (SiC) MOSFETs enable higher voltages, switching frequencies and operating temperatures when compared to Silicon technology, resulting in improved converter specifications. The current study tries to investigate the impact of emerging medium-voltage SiC MOSFETs on industrial motor drive application, where over a quarter of the total electricity in the world is being consumed.
Firstly, non-commercial SiC MOSFETs at 3.3 kV and 400 A rating are characterized to enable converter design and simulation based on them. In order to feature the best performance out of the devices under test, an intelligent high-performance gate driver is designed embedding required functionalities and protections. Secondly, total of three converters are targeted for industrial motor drive application at medium-voltage and high-power range. For this purpose the cascaded H-bridge, the modular multilevel converter and the 5-L active neutral point clamped converters are designed at 4.16-, 6.9- and 13.8 kV voltage ratings and 3- and 5 MVA power ratings. Selection of different voltage and power levels is done to elucidate variation of different parameters within the converters versus operating point.
Later, comparisons are done between the surveyed topologies designed at different operating points based on Si IGBTs and SiC MOSFETs. The comparison includes different aspects such as efficiency, power density, semiconductor utilization, energy stored in converter structure, fault containment, low-speed operation capability and parts count (for a measure of reliability). Having the comparisons done based on simulation data, an H-bridge cell is implemented using 3.3 kV 400 A SiC MOSFETs to evaluate validity of the conducted simulations.
Finally, a novel method is proposed for series-connecting individual SiC MOSFETs to reach higher voltage devices. Considering the fact that currently the SiC MOSFETs are not commercially available at voltages higher above 1.7 kV, this will enable implementation of converters using medium-voltage SiC MOSFETs that are achieved by stacking commercially-available 1.7 kV MOSFETs. The proposed method is specifically developed for SiC MOSFETs with high dv/dt rates, while majority of the existing solutions could only work merely with slow Si-based semiconductors.Ph. D.
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Kosier, Steven Louie 1966. "The effects of ionizing radiation on the breakdown voltage of p-channel power MOSFETs." Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/277798.
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The effects of ionizing radiation on the breakdown voltage of p-channel power MOSFETs were examined through two-dimensional simulation. The response of a reverse-biased n+-p junction to positive oxide-trapped charge, Not, is examined in detail, and analytical expressions for its characteristics are derived. These results provide insight into the breakdown performance of p-channel power MOSFETs in ionizing radiation environments, whose performance was found to be very different from corresponding n-channel power MOSFETs. Insights gained through analysis of p-channel devices suggest a termination/isolation scheme, the VLD-FRR, that will enhance p-channel device reliability in radiation environments. Two introductory chapters, which also serve as literature reviews, are provided. The buildup of Not in thick oxides and breakdown voltage of the power DMOS transistor are both reviewed, with attention focused on p-channel devices in both cases. Finally, suggestions for future work are given.
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Pastorek, Matej. "Fabrication and characterization of III-V MOSFETs for high performance and low power applications." Thesis, Lille 1, 2017. http://www.theses.fr/2017LIL10186/document.
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La réduction de la taille des circuits CMOS vers des dimensions extrêmement petites est telle que son élément constitutif, le MOSFET à base de Silicium, commence à souffrir d’une faible efficacité de puissance. L’une des alternatives qui ne peut être écartée est le concept du transistor MOSFET à base de matériaux III-V. Ses propriétés de transport extraordinaires, apportées par les matériaux III-V, promettent de réduire la tension d’alimentation des circuits CMOS sans réduire leur performance. Cette transition technologique pourrait aboutir non seulement à des circuits CMOS plus petits, plus écologiques mais aussi à des circuits co-intégrés avec des technologies RF. C’est dans ce contexte que nous présentons, dans ce travail de thèse, la fabrication et la caractérisation des transistors MOSFET Ultra-Thin Body (UTB) à base d’InAs et du transistor FinFET à base d’InAs. La combinaison d’une longueur de grille extrêmement réduite, d’une faible résistance d’accès et d’une mobilité impressionnante dans le canal d’InAs a permis d’obtenir des courants importants (IMAX=2000mA/mm pour LG=25nm). Egalement, l‘utilisation des architectures du canal de type ultra mince et FinFET permet d’obtenir un bon contrôle électrostatique. De plus, une spécificité du procédé technologique présentée dans ce travail est les réalisations des contacts et du canal par une épitaxie par jets moléculaires (MBE) localiséeScaling the size of CMOS circuits to extremely small dimensions gets the semiconductor industry to a point where its cornerstone, Silicon-based MOSFET starts to suffer a poor power efficiency. In the quest for alternative solutions cannot be omitted a concept of III-V MOSFET. Its outstanding transport properties hold a promise of reduced CMOS supply voltage without compromising the performance. This can path a way not only to the smaller, greener electronics but also to more co-integrated RF and CMOS electronics. In this context, we present fabrication and characterization of Ultra-Thin body InAs MOSFETs and InAs FinFET. Synergy of a deeply scaled gate length, low access resistance and a high mobility of InAs channel enabled to obtain impressively high drain currents (IMAX=2000mA/mm for LG=25nm). Equally, the introduction of Ultra-Thin body and FinFET channel design provides an improved electrostatic control. A specific feature of the process presented in this work is a fabrication of contacts and channel by localized molecular beam epitaxy MBE epitaxy
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Broadmeadow, Mark A. "Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications." Thesis, Queensland University of Technology, 2015. https://eprints.qut.edu.au/82868/4/Mark%20Broadmeadow%20Thesis.pdf.
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This thesis proposes a novel gate drive circuit to improve the switching performance of MOSFET power switches in power electronic converters. The proposed topology exploits the cascode configuration, allowing the minimisation of switching losses in the presence of practical circuit constraints, which enables efficiency and power density improvements. Switching characteristics of the new topology are investigated and key mechanisms that control the switching process are identified. Unique analysis tools and techniques are also developed to demonstrate the application of the cascode gate drive circuit for switching performance optimisation.
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Zetterling, Carl-Mikael. "Silicon dioxide and aluminium nitride as gate dielectric for high temperature and high power silicon carbide MOSFETs." Doctoral thesis, KTH, Electronic Systems Design, 1997. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-2514.
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Silicon carbide (SIC) is a wide bandgap semiconductor thathas been suggested as a replacement for silicon in applicationsusing high voltages, high frequencies, high temperatures orcombinations thereof. Several basic process steps need to bedeveloped for reliable manufacturing of long-term stableelectronic devices. One important process step is the formationof an insulator on the silicon carbide surface that may be usedas a) a gate dielectric, b) for device isolation or c) forpassivation of the surface. Silicon dioxide and aluminumnitride have been suggested for these purposes. This thesiscovers the investigation of some formation methods for boththese materials on 4H and 6H silicon carbide, and theelectrical characterisation of the resulting films.
Commercially available n-type and p-type 4H and 6H SICwafers have been used, and both the silicon face and the carbonface have been investigated. Silicon dioxide has been formed byseveral methods: a) dry thermal oxidation with or without theaddition of TCA (trichloroethane), b) wet oxidation inpyrogenic steam or with awater bubbler, c) oxide deposition byPECVD (plasma enhanced chemical vapor deposition) or LPCVD (lowpressure chemical vapor deposition) and d) oxidation of aevaporated or LPCVD deposited sacrificial layer of silicon. Theinfluence of various cleaning methods prior to oxidation hasbeen studied, as well as post-oxidation and post-metallisationannealing. The aluminum nitride films were grown by MOCVD(metal organic chemical vapor deposition) under various processconditions.
Oxidation kinetics have been studied for dry thermaloxidation at 1200 0C. The redistribution of aluminum (p-typedopant in SiC) during dry thermal oxidation has beeninvestigated using SIMS (secondary ion mass spectrometry). Themorphology of the aluminum nitride was determined using x-raydiffraction rocking curves, RHEED (reflection high energyelectron diffraction) and AFM (atomic force microscopy). Thequality of the silicon dioxide used as gate dielectric has beendetermined using breakdown field measurements. High frequencycapacitance-voltage measurements have been used on bothinsulators to a) verify thickness measurements made with othermethods, b) to determine fixed oxide charges by measuring theflatband voltage shifts and c) to quantitatively compare theamount of interface states.
For electrical characterisation either aluminum, titanium ordoped polysilicon circular gate contacts of various sizes wereformed on the insulator surface. Flat MOS capacitors weremainly used for the electrical characterisation. U-grooved MOScapacitors, manufactured by RIE (reactive ion etching), wereused to test the quality of oxides grown on vertical surfaces.Two types of MOSFETs (metal oxide semiconductor field effecttransistors) have been fabricated: vertical U-grooved andlateral devices.
Keywords:silicon carbide, thermal oxidation, silicondioxide, metal organic chemical vapor deposition (MOCVD),aluminum nitride, capacitance-voltage measurements, MOSFET.
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Francisco, sousa alves Luciano. "Series-connected SiC-MOSFETs : A Novel Multi-Step Packaging Concept and New Gate Drive Power Supply Configurations." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT050.
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Ce travail de thèse étudie de nouvelles configurations d'alimentation de commande rapprochée et un nouveau concept de packaging afin d'améliorer les performances des MOSFETs SiC connectés en série. Les nouvelles configurations de commande rapprochée sont proposées afin de réduire les courants de bruit qui circulent dans la partie commande du système électrique. De plus, une nouvelle alimentation de commande de grille est proposée pour augmenter le dv / dt de la cellule de commutation. Ces améliorations, c'est-à-dire la réduction du courant de bruit et l'amplification du dv/dt, sont obtenues en modifiant l'impédance des circuits de commande de grille. Le nouveau concept de packaging est proposé afin d'améliorer les performances d’équilibrage de tension. Les nouvelles configurations de commande rapprochée et les concepts de packaging sont introduits et analysés grâce à des modèles analytique et des simulations. Ensuite, des essayes expérimentales sont effectuées pour confirmer que les concepts proposés sont meilleurs que les concepts traditionnels en termes d'équilibrage de tension, de vitesse de commutation et de réduction EMI conduiteThis work investigates new gate drive power supply configurations and a novel multi-steppackaging concept in order to improve the performance of series-connected SiC-MOSFETs. The new gate drive configurations are proposed in order to reduce noise currents that circulate in the control part of the electrical system. Furthermore, a new gate drive power supply is proposed to increase the dv/dt of the switching cell. These improvements, i.e., noise current reduction and dv/dt boosting, are achieved by modifying the impedance of the gate drive circuitry. The novel multi-step packaging concept is proposed in order to improve the voltage sharing performance. The proposed package geometry considers optimal dielectric isolation for each device leading to a multi-step geometry. It has a significant impact on the parasitic capacitances introduced by the packaging structure that are responsible for voltageunbalances. The new gate driver configurations and the proposed multi-step packaging concepts are introduced and analysed thanks to equivalent models and time domain simulations. Then, experimental set-ups are performed to confirm that the proposed concepts are better than traditional ones in terms of voltage balancing, switching speed and conducted EMI reduction
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Johnson, Gregory Howard 1965. "Features of a heavy-ion-generated-current filament used in modeling single-event burnout of power MOSFETs." Thesis, The University of Arizona, 1990. http://hdl.handle.net/10150/277796.
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Power MOSFETs are often required to operate in a space radiation environment; therefore, they are susceptible to a catastrophic failure mode called single-event burnout. Single-event burnout of power MOSFETs is initiated by the passage of an energetic-heavy ion through the parasitic BJT inherent to the power-MOSFET structure. The electron-hole pairs generated by the ion support a short-lived current source which imposes a base-emitter voltage on the parasitic BJT. If a sufficient base-emitter voltage is imposed, the parasitic BJT enters second breakdown and burnout of the MOSFET occurs. A semi-analytical model has been developed to predict the energy required of the incident ion to initiate burnout. This thesis addresses the portion of this model which relates the energy of the incident ion to the base-emitter voltage imposed on the parasitic BJT. The initial base-emitter potential is determined using image-source techniques.
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Pang, Yon Sup. "Design and modeling of non-uniformly doped deep-submicron pocket MOSFETs for low-voltage low-power applications." Diss., The University of Arizona, 2000. http://hdl.handle.net/10150/279886.
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Laterally non-uniformly doped 0.1-μm pocket n-MOSFETs satisfying specifications of off-state current, on-state current, sensitivity of off-state current to channel length and 1V power-supply voltage have been designed for low-voltage low-power applications. To determine a viable range of the deep-submicron pocket n-MOSFET structural parameters---the dopant concentration at the center region (Nc), the dopant concentration at the pocket region (Np) and the length of the pocket region (Lp), a unique viable design space locating the deep-submicron devices meeting all the device specifications have been constructed, using computer algorithms developed and implemented in the programming language of the two-dimensional device simulator, Medici. For known Nc, vs. Lp, the pocket n-MOSFETs for low-power applications are located in an upper area of higher Np vs. Lp of the viable design space while the devices for high-performance applications are located in a lower area of lower Np vs. Lp of the viable design space. Well-designed deep-submicron pocket n-MOSFETs prove to be promising candidates to improve short-channel effects as well as switching performance in comparing the 0.1-μm pocket n-MOSFETs located within the viable design space to 0.1-μm conventional bulk n-MOSFETs selected to meet the same specifications. The 0.1-μm pocket n-MOSFETs located within the viable design space can be partitioned into two types of pocket devices based on gate controllability of channel- and depletion-layer charges. Analytical models for subthreshold and above-threshold currents in the deep-submicron pocket n-MOSFETs have been developed for the first time to generate the off-state and the on-state currents, and the design-space boundaries for the on- and the off-state currents. The models are based on solutions of the drift-diffusion current transport and the 1-D Poisson's equations, the charge sheet approximation, subthreshold surface potential models based on solutions of the quasi-two-dimensional Poisson's equation, a quasi-two-dimensional velocity saturation model, realistic mobility models, and analytical formulas for model parameters. The analytical models provide explicit relations between process, device and model parameters of the deep-submicron pocket n-MOSFETs, and reduce time and cost of the two-dimensional device simulation. Some algorithms developed for generating ID - V DS characteristics and constructing the design-space boundaries are described.
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Balasubramanian, Venkatesh. "Characterization of sub-90 nm Gate Length RF MOSFETs using Large Signal Network Analyzer." The Ohio State University, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=osu1230671230.
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Jabs, Dominic Verfasser], Christoph [Akademischer Betreuer] [Jungemann, and Tibor [Akademischer Betreuer] Grasser. "Hot-carrier degradation at avalanche breakdown: microscopic simulation of power MOSFETs / Dominic Jabs ; Christoph Antonius Jungemann, Tibor Grasser." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://d-nb.info/1162553898/34.
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Jabs, Dominic [Verfasser], Christoph [Akademischer Betreuer] Jungemann, and Tibor [Akademischer Betreuer] Grasser. "Hot-carrier degradation at avalanche breakdown: microscopic simulation of power MOSFETs / Dominic Jabs ; Christoph Antonius Jungemann, Tibor Grasser." Aachen : Universitätsbibliothek der RWTH Aachen, 2017. http://nbn-resolving.de/urn:nbn:de:101:1-2018071111001536929864.
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Gopalakrishna, Keshava. "Frequency Characterization of Si, SiC,and GaN MOSFETs Using Buck ConverterIn CCM as an Application." Wright State University / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=wright1387661422.
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Bernoux, Béatrice. "Caractérisation de MOSFETs de puissance cyclés en avalanche pour des applications automobiles micro-hybrides." Thesis, Toulouse, INSA, 2010. http://www.theses.fr/2010ISAT0007/document.
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Les travaux de recherche présentés dans ce mémoire, portent sur la conception et l’étude de MOSFETs de puissance faible tension pour des applications automobiles micro-hybrides de type alterno-démarreur. Pour certaines de ces applications, en plus des modes de fonctionnement standards passant et bloqué, les composants développés doivent être capables de fonctionner en mode d’avalanche à fort courant et à des températures élevées. Pour reproduire en laboratoire ces conditions de fonctionnement, les MOSFETs sont soumis à un test UIS répétitif spécifique. Afin d’évaluer la température du silicium pendant ce test, plusieurs méthodes de mesure de température ont été développées et comparées. En parallèle, un suivi des paramètres électriques standards (BVDSS, IDSS, RDSon…) tout au long du test est effectué, dans le but de déterminer l’impact de l’avalanche répétitive sur le transistor. Seule la RDSon des MOSFETs semble évoluer avec le nombre d’impulsions d’avalanche. Ce phénomène est expliqué par la méthode de mesure de RDSon et par la variation de la résistance du métal source pendant le cyclage. En effet, différentes observations ont permis de constater un vieillissement de la métallisation de source du composant, accompagné d’une modification de sa résistivité. Divers types de métaux et de techniques d’assemblage ont alors été expérimentés pour tenter de limiter cet effet. Aussi des structures de test ont été conçues pour étudier l’évolution du métal et pour pouvoir comparer rapidement le comportement de différentes métallisationsResearch work presented in this thesis concern the conception and the study of low voltage power MOSFETs for micro hybrid vehicles (starter alternator). For some of these applications, developed transistors must be able to operate in classical ON and OFF state mode and in avalanche mode at high current and high temperature. To reproduce this operating mode, MOSFETs are submitted to a specific repetitive UIS test. In order to evaluate silicon’s temperature during this test, several temperature measurement methods have been developed and compared. In parallel, in order to understand the impact of repetitive avalanche on the transistor, standard electrical parameters (BVDSS, IDSS, RDSon…) are monitored during the test. The only parameter that seems to be shifting with the number of cycles is the RDSon. This phenomenon is due to the measurement method and to a variation of source metallization resistance during cycling. Indeed several observations have shown source metallization ageing and a shift in its resistivity. Different metallization and assembly parameters have been tested to limit this phenomenon. Also various test structures have been designed to study metallization evolution and to compare different metallization behaviors
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Aviñó, Salvadó Oriol. "Contribution to the study of the SiC MOSFETs gate oxide." Thesis, Lyon, 2018. http://www.theses.fr/2018LYSEI110/document.
Full textAbstract:
Les MOSFET en SiC sont appelées à remplacer les IGBT en Silicium pour des applications de demandant une plus forte vitesse de commutation. Cependant, les MOSFET en SiC ont encore quelques problèmes de fiabilité, tels que la robustesse de la diode interne ou bien la robustesse de l'oxyde de grille. Cette dernière est liée à l’oxyde de grille des composants du type MOSFET. Des instabilités de la tension de seuil sont aussi signalées. Cette thèse aborde ces deux sujets sur des MOSFET commerciaux 1200 V. L'étude de la diode interne met en évidence que les caractéristiques I-V (de la diode intrinsèque) demeurent stables après l'application d'un stress. Cependant, une dérive surprenante de la tension de seuil apparaît. Des tests complémentaires, en stressant le canal à la place de la diode, avec les mêmes contraintes n'ont pas montré de dérive significative de la tension de seuil. Donc, l'application d'un stress en courant quand le composant est en mode d'accumulation semble favoriser l'apparition des instabilités de la tension de seuil. La robustesse de l'oxyde de grille concerne les instabilités de la tension de seuil, mais aussi l'estimation de la durée de vie à des conditions d'opération nominales. Les résultats obtenus montrent que la durée de vie de l'oxyde de grille n'est plus un problème. Pourtant, le suivi du courant de grille pendant les tests ainsi que les caractérisations de la capacité de grille mettent en évidence des translations de la courbe C(V) à cause des phénomènes d’injection des porteurs et de piégeage, mais aussi la possible présence d’ions mobiles. Aussi, une bonne analyse des dégradations et dérives liées à l’oxyde de grille doit être réaliséeSiC power MOSFETs are called to replace Si IGBT for some medium and high power applications (hundreds of kVA). However, even if crystallographic defects have been drastically reduced, SiC MOSFETs are always concerned by some robustness issues such as the internal diode robustness or the robustness of the gate oxide. The last one especially affects MOSFETs devices and is linked to the apparition of instabilities in the threshold voltage. This thesis focuses on these two issues. The study of the internal diode robustness highlighted that the I-V curve (of the intrinsic diode) remains stable after the application of a current stress in static mode, but also with the DUT placed in a converter with inductive switchings. These are the most stressful conditions. However, a surprising drift in the threshold voltage has been observed when some devices operates under these conditions; in static mode or in a converter. Complementary tests stressing the channel instead of the internal diode in the same temperature and dissipated power, have not resulted in a drift of the threshold voltage. Thus, the application of a current stress when the device is in accumulation regime could favour the apparition of instabilities in the threshold voltage. The study of the gate oxide focus in the instabilities of the threshold voltage, but also on the expected lifetime of the oxide at nominal conditions. Results obtained shown that the expected lifetime (TDDB) of the oxide is no longer a problem. Indeed, tests realized in static mode, but also in a converter under inductive switching conditions resulted in expected lifetimes well above 100 years. However, the monitoring of the gate current during the test and gate capacitance characterizations C(V) highlighted a shift in the capacitance due to carrier injection and trapping phenomena and probably to the presence of mobile-ions. Still regarding the instabilities of the threshold voltage, classic tests resulted in no significant variations of the threshold voltage at 150 _C. However, at 200 _C the drift observed for some manufacturers is higher than +30%. This is unacceptable for high-temperature applications and evidence that the quality of the gate oxide and the SiC=SiO2 interface must continue to be improved, together with the manufacturing methods to minimize the presence of mobile ions in the substrate