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Journal articles on the topic 'Polymer Charge Trapping Memory'

Author: Grafiati
Published: 6 September 2023

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1

Prime, D., S. Paul, and P. W. Josephs-Franks. "Gold nanoparticle charge trapping and relation to organic polymer memory devices." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 367, no. 1905 (October 28, 2009): 4215–25. http://dx.doi.org/10.1098/rsta.2009.0141.

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Nanoparticle-based polymer memory devices (PMDs) are a promising technology that could replace conventional silicon-based electronic memory, offering fast operating speeds, simple device structures and low costs. Here we report on the current state of nanoparticle PMDs and review some of the problems that are still present in the field. We also present new data regarding the charging of gold nanoparticles in metal–insulator–semiconductor capacitors, showing that charging is possible under the application of an electric field with a trapped charge density due to the nanoparticles of 3.3×10 12 cm −2 .
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2

Casalbore-Miceli, Giuseppe, Nadia Camaioni, Alessandro Geri, Giovanni Ridolfi, Alberto Zanelli, Maria C. Gallazzi, Michele Maggini, and Tiziana Benincori. "“Solid state charge trapping”: Examples of polymer systems showing memory effect." Journal of Electroanalytical Chemistry 603, no. 2 (May 2007): 227–34. http://dx.doi.org/10.1016/j.jelechem.2007.02.007.

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3

Murari, Nishit M., Ye-Jin Hwang, Felix Sunjoo Kim, and Samson A. Jenekhe. "Organic nonvolatile memory devices utilizing intrinsic charge-trapping phenomena in an n-type polymer semiconductor." Organic Electronics 31 (April 2016): 104–10. http://dx.doi.org/10.1016/j.orgel.2016.01.015.

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4

Rajeev, V. R., and K. N. Narayanan Unni. "Polymer electret-based organic field-effect transistor memory with a solution-processable bilayer (PαMS/ cross-linked PVP) gate dielectric." European Physical Journal Applied Physics 97 (2022): 17. http://dx.doi.org/10.1051/epjap/2022210175.

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Pentacene based organic field-effect transistors (OFETs) were fabricated, with both cross-linked poly vinyl phenol (CL-PVP) and a bilayer of poly(α-methylstyrene) (PαMS)/ CL-PVP as gate dielectric. The PαMS layer decreases the surface energy of the gate dielectric and increases the hydrophobic nature, which leads to favorable growth of pentacene and the corresponding field-effect mobility, though at a higher gate voltage span, increases three times compared to that of the device with only CL-PVP as the gate dielectric. OFET with bilayer polymer gate dielectric exhibited non-volatile memory behavior with an on-off ratio 103, retention time >103 s and a large memory window of −25 V. The memory effect observed in the device was due to the charge trapping in the PαMS layer, with CL-PVP acting as a blocking dielectric. Our studies indicate that the bilayer dielectric, comprising of solution-processable PαMS/CL-PVP is a good choice for obtaining non-volatile electret memory on an OFET platform.
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Wu, Chao, Yongping Dan, Wei Wang, Xiangyang Lu, and Xinqiang Wang. "Solution processed nonvolatile polymer transistor memory with discrete distributing molecular semiconductor microdomains as the charge trapping sites." Semiconductor Science and Technology 33, no. 9 (July 30, 2018): 095003. http://dx.doi.org/10.1088/1361-6641/aad2b9.

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6

He, Dongwei, Hao Zhuang, Haifeng Liu, Hongzhang Liu, Hua Li, and Jianmei Lu. "Adjustment of conformation change and charge trapping in ion-doped polymers to achieve ternary memory performance." Journal of Materials Chemistry C 1, no. 47 (2013): 7883. http://dx.doi.org/10.1039/c3tc31759e.

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7

Baeg, Kang-Jun, Yong-Young Noh, and Dong-Yu Kim. "Charge transfer and trapping properties in polymer gate dielectrics for non-volatile organic field-effect transistor memory applications." Solid-State Electronics 53, no. 11 (November 2009): 1165–68. http://dx.doi.org/10.1016/j.sse.2009.07.003.

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8

Ling, Haifeng, Wen Li, Huanqun Li, Mingdong Yi, Linghai Xie, Laiyuan Wang, Yangxing Ma, Yan Bao, Fengning Guo, and Wei Huang. "Effect of thickness of polymer electret on charge trapping properties of pentacene-based nonvolatile field-effect transistor memory." Organic Electronics 43 (April 2017): 222–28. http://dx.doi.org/10.1016/j.orgel.2017.01.017.

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9

Zhang, Bo, Qihang Gao, Boping Wang, Hong Wang, Chao Lu, Jiashu Gao, Rui Zhao, and Xiaobing Yan. "Effects of oxygen conditions during deposition on memory performance of metal/HfO2/SiO2/Si structured charge trapping memory." Materials Research Express 6, no. 8 (May 10, 2019): 086306. http://dx.doi.org/10.1088/2053-1591/ab1df0.

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10

Wang, Wei, Sun Kak Hwang, Kang Lib Kim, Ju Han Lee, Suk Man Cho, and Cheolmin Park. "Highly Reliable Top-Gated Thin-Film Transistor Memory with Semiconducting, Tunneling, Charge-Trapping, and Blocking Layers All of Flexible Polymers." ACS Applied Materials & Interfaces 7, no. 20 (May 15, 2015): 10957–65. http://dx.doi.org/10.1021/acsami.5b02213.

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11

Lorenzi, Paolo, Rosario Rao, Gabriella Ghidini, Fabrizio Palma, and Fernanda Irrera. "Charge Trapping Non Volatile Memory." ECS Transactions 25, no. 7 (December 17, 2019): 269–76. http://dx.doi.org/10.1149/1.3203965.

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12

Campbell, Alasdair J., Donal D. C. Bradley, and David G. Lidzey. "Charge trapping in polymer diodes." Optical Materials 9, no. 1-4 (January 1998): 114–19. http://dx.doi.org/10.1016/s0925-3467(97)00145-6.

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13

El-Atab, Nazek, Ayse Ozcan, Sabri Alkis, Ali K. Okyay, and Ammar Nayfeh. "Silicon nanoparticle charge trapping memory cell." physica status solidi (RRL) - Rapid Research Letters 8, no. 7 (May 12, 2014): 629–33. http://dx.doi.org/10.1002/pssr.201409157.

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14

Ping-Hung Tsai, Kuei-Shu Chang-Liao, Te-Chiang Liu, Tien-Ko Wang, Pei-Jer Tzeng, Cha-Hsin Lin, L. S. Lee, and Ming-Jinn Tsai. "Charge-Trapping-Type Flash Memory Device With Stacked High-$k$ Charge-Trapping Layer." IEEE Electron Device Letters 30, no. 7 (July 2009): 775–77. http://dx.doi.org/10.1109/led.2009.2022287.

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15

Meng, Jianling, Rong Yang, Jing Zhao, Congli He, Guole Wang, Dongxia Shi, and Guangyu Zhang. "Nanographene charge trapping memory with a large memory window." Nanotechnology 26, no. 45 (October 22, 2015): 455704. http://dx.doi.org/10.1088/0957-4484/26/45/455704.

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16

Spassov, Dencho, Albena Paskaleva, Elżbieta Guziewicz, Wojciech Wozniak, Todor Stanchev, Tsvetan Ivanov, Joanna Wojewoda-Budka, and Marta Janusz-Skuza. "Charge Storage and Reliability Characteristics of Nonvolatile Memory Capacitors with HfO2/Al2O3-Based Charge Trapping Layers." Materials 15, no. 18 (September 9, 2022): 6285. http://dx.doi.org/10.3390/ma15186285.

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Flash memories are the preferred choice for data storage in portable gadgets. The charge trapping nonvolatile flash memories are the main contender to replace standard floating gate technology. In this work, we investigate metal/blocking oxide/high-k charge trapping layer/tunnel oxide/Si (MOHOS) structures from the viewpoint of their application as memory cells in charge trapping flash memories. Two different stacks, HfO2/Al2O3 nanolaminates and Al-doped HfO2, are used as the charge trapping layer, and SiO2 (of different thickness) or Al2O3 is used as the tunneling oxide. The charge trapping and memory windows, and retention and endurance characteristics are studied to assess the charge storage ability of memory cells. The influence of post-deposition oxygen annealing on the memory characteristics is also studied. The results reveal that these characteristics are most strongly affected by post-deposition oxygen annealing and the type and thickness of tunneling oxide. The stacks before annealing and the 3.5 nm SiO2 tunneling oxide have favorable charge trapping and retention properties, but their endurance is compromised because of the high electric field vulnerability. Rapid thermal annealing (RTA) in O2 significantly increases the electron trapping (hence, the memory window) in the stacks; however, it deteriorates their retention properties, most likely due to the interfacial reaction between the tunneling oxide and the charge trapping layer. The O2 annealing also enhances the high electric field susceptibility of the stacks, which results in better endurance. The results strongly imply that the origin of electron and hole traps is different—the hole traps are most likely related to HfO2, while electron traps are related to Al2O3. These findings could serve as a useful guide for further optimization of MOHOS structures as memory cells in NVM.
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17

Fukuda, M., T. Nakanishi, and Y. Nara. "New nonvolatile memory with charge-trapping sidewall." IEEE Electron Device Letters 24, no. 7 (July 2003): 490–92. http://dx.doi.org/10.1109/led.2003.815002.

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18

Liu, Jinqiu, Jianxin Lu, Bo Xu, Yidong Xia, Jiang Yin, and Zhiguo Liu. "Al2O3–Cu2O composite charge-trapping nonvolatile memory." Journal of Materials Science: Materials in Electronics 28, no. 1 (August 25, 2016): 928–33. http://dx.doi.org/10.1007/s10854-016-5609-8.

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19

Spassov, Dencho, and Albena Paskaleva. "Challenges to Optimize Charge Trapping Non-Volatile Flash Memory Cells: A Case Study of HfO2/Al2O3 Nanolaminated Stacks." Nanomaterials 13, no. 17 (August 30, 2023): 2456. http://dx.doi.org/10.3390/nano13172456.

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The requirements for ever-increasing volumes of data storage have urged intensive studies to find feasible means to satisfy them. In the long run, new device concepts and technologies that overcome the limitations of traditional CMOS-based memory cells will be needed and adopted. In the meantime, there are still innovations within the current CMOS technology, which could be implemented to improve the data storage ability of memory cells—e.g., replacement of the current dominant floating gate non-volatile memory (NVM) by a charge trapping memory. The latter offers better operation characteristics, e.g., improved retention and endurance, lower power consumption, higher program/erase (P/E) speed and allows vertical stacking. This work provides an overview of our systematic studies of charge-trapping memory cells with a HfO2/Al2O3-based charge-trapping layer prepared by atomic layer deposition (ALD). The possibility to tailor density, energy, and spatial distributions of charge storage traps by the introduction of Al in HfO2 is demonstrated. The impact of the charge trapping layer composition, annealing process, material and thickness of tunneling oxide on the memory windows, and retention and endurance characteristics of the structures are considered. Challenges to optimizing the composition and technology of charge-trapping memory cells toward meeting the requirements for high density of trapped charge and reliable storage with a negligible loss of charges in the CTF memory cell are discussed. We also outline the perspectives and opportunities for further research and innovations enabled by charge-trapping HfO2/Al2O3-based stacks.
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20

Shen, Yuxin, Zhaohao Zhang, Qingzhu Zhang, Feng Wei, Huaxiang Yin, Qianhui Wei, and Kuo Men. "A Gd-doped HfO2 single film for a charge trapping memory device with a large memory window under a low voltage." RSC Advances 10, no. 13 (2020): 7812–16. http://dx.doi.org/10.1039/d0ra00034e.

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In this study, a performance-enhanced charge trapping memory device with a Pt/Gd-doped HfO2/SiO2/Si structure has been investigated, where Gd-doped HfO2 acts as a charge trapping and blocking layer.
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21

LIU, JING, and HAI-BO ZHANG. "SELF-CONSIST CHARGING PROCESS OF POLYMER IRRADIATED BY INTERMEDIATE-ENERGY ELECTRON BEAM." Surface Review and Letters 21, no. 05 (September 29, 2014): 1450062. http://dx.doi.org/10.1142/s0218625x14500620.

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This paper reports on the electron scattering, charge transport and charge trapping of a polymer subjected to intermediate-energy electron beam in a self-consist charging model. Numerical simulation of a charging balance is performed using incident intermediate-energy electron current and leakage current, and the space charging characteristics are examined. The mechanisms involve various microscopic parameters that are related to the space potential and the characteristics of the polymer as well as to the effects of the space charge, electron charge, hole charge and trapped charge itself. The dynamic transporting and trapping properties of a polymer are investigated, and the space potential is evaluated using various parameters of irradiation. Trapping of electrons is determined using Poole–Frenkel trapping–detrapping mechanisms. Various types of space charging behavior are observed by controlling irradiation conditions. Furthermore, the peak location of space charge is simulated and validated by Sessler's experimental data in microscopic perspective.
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22

El-Atab, Nazek, Irfan Saadat, Krishna Saraswat, and Ammar Nayfeh. "Nanoislands-Based Charge Trapping Memory: A Scalability Study." IEEE Transactions on Nanotechnology 16, no. 6 (November 2017): 1143–46. http://dx.doi.org/10.1109/tnano.2017.2764745.

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23

Liu, Y., T. Nabatame, T. Matsukawa, K. Endo, S. O'uchi, J. Tsukada, H. Yamauchi, et al. "(Invited) Charge Trapping Type SOI-FinFET Flash Memory." ECS Transactions 61, no. 2 (March 24, 2014): 263–80. http://dx.doi.org/10.1149/06102.0263ecst.

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24

Malliaras, G. G., V. V. Krasnikov, H. J. Bolink, and G. Hadziioannou. "Control of charge trapping in a photorefractive polymer." Applied Physics Letters 66, no. 9 (February 27, 1995): 1038–40. http://dx.doi.org/10.1063/1.114230.

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25

Gong, Changjie, Xin Ou, Bo Xu, Xuexin Lan, Yan Lei, Jianxin Lu, Yan Chen, et al. "Enhanced charge storage performance in AlTi4Ox/Al2O3multilayer charge trapping memory devices." Japanese Journal of Applied Physics 53, no. 8S3 (July 7, 2014): 08NG02. http://dx.doi.org/10.7567/jjap.53.08ng02.

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26

Specht, M., H. Reisinger, F. Hofmann, T. Schulz, E. Landgraf, R. J. Luyken, W. Rösner, M. Grieb, and L. Risch. "Charge trapping memory structures with Al2O3 trapping dielectric for high-temperature applications." Solid-State Electronics 49, no. 5 (May 2005): 716–20. http://dx.doi.org/10.1016/j.sse.2004.09.003.

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27

Choi, Sangmoo, Myungjun Cho, Chandan B. Samantaray, Sanghun Jeon, Chungwoo Kim, and Hyunsang Hwang. "Improved Charge-Trapping Nonvolatile Memory with Dy-doped HfO2as Charge-Trapping Layer and Al2O3as Blocking Layer." Japanese Journal of Applied Physics 43, No. 7A (June 18, 2004): L882—L884. http://dx.doi.org/10.1143/jjap.43.l882.

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28

Jin, Rui, Xiaoyan Liu, Gang Du, Jinfeng Kang, and Ruqi Han. "Effect of trapped charge accumulation on the retention of charge trapping memory." Journal of Semiconductors 31, no. 12 (December 2010): 124016. http://dx.doi.org/10.1088/1674-4926/31/12/124016.

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29

El-Atab, Nazek, Ayman Rizk, Ali K. Okyay, and Ammar Nayfeh. "Zinc-oxide charge trapping memory cell with ultra-thin chromium-oxide trapping layer." AIP Advances 3, no. 11 (November 2013): 112116. http://dx.doi.org/10.1063/1.4832237.

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30

Wang Jia-Yu, Dai Yue-Hua, Zhao Yuan-Yang, Xu Jian-Bin, Yang Fei, Dai Guang-Zhen, and Yang Jin. "Research on charge trapping memory’s over erase." Acta Physica Sinica 63, no. 20 (2014): 203101. http://dx.doi.org/10.7498/aps.63.203101.

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31

Huang, X., and P. T. Lai. "HfTiON as Charge-Trapping Layer for Nonvolatile Memory Applications." ECS Transactions 45, no. 3 (April 27, 2012): 355–60. http://dx.doi.org/10.1149/1.3700900.

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32

Specht, M., R. Kommling, F. Hofmann, V. Klandzievski, L. Dreeskornfeld, W. Weber, J. Kretz, et al. "Novel Dual Bit Tri-Gate Charge Trapping Memory Devices." IEEE Electron Device Letters 25, no. 12 (December 2004): 810–12. http://dx.doi.org/10.1109/led.2004.838621.

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33

Huang, X. D., Johnny K. O. Sin, and P. T. Lai. "BaTiO3 as charge-trapping layer for nonvolatile memory applications." Solid-State Electronics 79 (January 2013): 285–89. http://dx.doi.org/10.1016/j.sse.2012.09.005.

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34

Kang, Sung Hoon, Todd Crisp, Ioannis Kymissis, and Vladimir Bulović. "Memory effect from charge trapping in layered organic structures." Applied Physics Letters 85, no. 20 (November 15, 2004): 4666–68. http://dx.doi.org/10.1063/1.1819991.

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35

Tang, Zhenjie, Dongqiu Zhao, Rong Li, and Xinhua Zhu. "Improved Memory Characteristics by NH3Post Annealing for ZrO2Based Charge Trapping Nonvolatile Memory." Transactions on Electrical and Electronic Materials 15, no. 1 (February 25, 2014): 16–19. http://dx.doi.org/10.4313/teem.2014.15.1.16.

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36

Kunz, A., P. W. M. Blom, and J. J. Michels. "Charge carrier trapping controlled by polymer blend phase dynamics." Journal of Materials Chemistry C 5, no. 12 (2017): 3042–48. http://dx.doi.org/10.1039/c6tc05065d.

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37

Wang, Jer, Chyuan Kao, Chien Wu, Chun Lin, and Chih Lin. "Nb2O5 and Ti-Doped Nb2O5 Charge Trapping Nano-Layers Applied in Flash Memory." Nanomaterials 8, no. 10 (October 8, 2018): 799. http://dx.doi.org/10.3390/nano8100799.

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High-k material charge trapping nano-layers in flash memory applications have faster program/erase speeds and better data retention because of larger conduction band offsets and higher dielectric constants. In addition, Ti-doped high-k materials can improve memory device performance, such as leakage current reduction, k-value enhancement, and breakdown voltage increase. In this study, the structural and electrical properties of different annealing temperatures on the Nb2O5 and Ti-doped Nb2O5(TiNb2O7) materials used as charge-trapping nano-layers in metal-oxide-high k-oxide-semiconductor (MOHOS)-type memory were investigated using X-ray diffraction (XRD) and atomic force microscopy (AFM). Analysis of the C-V hysteresis curve shows that the flat-band shift (∆VFB) window of the TiNb2O7 charge-trapping nano-layer in a memory device can reach as high as 6.06 V. The larger memory window of the TiNb2O7 nano-layer is because of a better electrical and structural performance, compared to the Nb2O5 nano-layer.
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38

Kobayashi, Kiyoteru, and Hiroshi Mino. "Hole trapping capability of silicon carbonitride charge trap layers." European Physical Journal Applied Physics 91, no. 1 (July 2020): 10101. http://dx.doi.org/10.1051/epjap/2020190297.

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We have evaluated the hole trapping capability of the silicon carbonitride (SiCN) dielectric film for application in metal-oxide-nitride-oxide-silicon (MONOS)-type non-volatile memory devices. After a great number of holes were injected to the SiCN charge trap layer of memory capacitors at high applied voltages, the flat-band voltage shift ΔV fb,h of the capacitors was saturated and the charge centroid location of holes trapped in the SiCN layer was found to reach at 1.8–2.0 nm from the blocking oxide-charge trap layer interface. Using the obtained ΔV fb,h and charge centroid values, the maximum density of holes trapped in the SiCN layer was estimated to be 1.2 × 1013 holes/cm2, which was higher than that trapped in a silicon nitride charge trap layer (=1.0 × 1013 holes/cm2). It is concluded that the high density of trapped holes caused large ΔV fb,h in the memory capacitors with the SiCN layer.
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39

Shih, Wen-Chieh, Chih-Hao Cheng, Joseph Ya-min Lee, and Fu-Chien Chiu. "Charge-Trapping Devices Using Multilayered Dielectrics for Nonvolatile Memory Applications." Advances in Materials Science and Engineering 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/548329.

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Charge-trapping devices using multilayered dielectrics were studied for nonvolatile memory applications. The device structure is Al/Y2O3/Ta2O5/SiO2/Si (MYTOS). The MYTOS field effect transistors were fabricated using Ta2O5as the charge storage layer and Y2O3as the blocking layer. The electrical characteristics of memory window, program/erase characteristics, and data retention were examined. The memory window is about 1.6 V. Using a pulse voltage of 6 V, a threshold voltage shift of ~1 V can be achieved within 10 ns. The MYTOS transistors can retain a memory window of 0.81 V for 10 years.
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40

Yoo, Jae-Hoon, Won-Ji Park, So-Won Kim, Ga-Ram Lee, Jong-Hwan Kim, Joung-Ho Lee, Sae-Hoon Uhm, and Hee-Chul Lee. "Preparation of Remote Plasma Atomic Layer-Deposited HfO2 Thin Films with High Charge Trapping Densities and Their Application in Nonvolatile Memory Devices." Nanomaterials 13, no. 11 (June 1, 2023): 1785. http://dx.doi.org/10.3390/nano13111785.

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Optimization of equipment structure and process conditions is essential to obtain thin films with the required properties, such as film thickness, trapped charge density, leakage current, and memory characteristics, that ensure reliability of the corresponding device. In this study, we fabricated metal–insulator–semiconductor (MIS) structure capacitors using HfO2 thin films separately deposited by remote plasma (RP) atomic layer deposition (ALD) and direct-plasma (DP) ALD and determined the optimal process temperature by measuring the leakage current and breakdown strength as functions of process temperature. Additionally, we analyzed the effects of the plasma application method on the charge trapping properties of HfO2 thin films and properties of the interface between Si and HfO2. Subsequently, we synthesized charge-trapping memory (CTM) devices utilizing the deposited thin films as charge-trapping layers (CTLs) and evaluated their memory properties. The results indicated excellent memory window characteristics of the RP-HfO2 MIS capacitors compared to those of the DP-HfO2 MIS capacitors. Moreover, the memory characteristics of the RP-HfO2 CTM devices were outstanding as compared to those of the DP-HfO2 CTM devices. In conclusion, the methodology proposed herein can be useful for future implementations of multiple levels of charge-storage nonvolatile memories or synaptic devices that require many states.
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41

Kurtash, Vladislav, Sebastian Thiele, Sobin Mathew, Heiko O. Jacobs, and Joerg Pezoldt. "Designing MoS2 channel properties for analog memory in neuromorphic applications." Journal of Vacuum Science & Technology B 40, no. 3 (May 2022): 030602. http://dx.doi.org/10.1116/6.0001815.

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In this paper, we introduce analog nonvolatile random access memory cells for neuromorphic computing. The analog memory cell [Formula: see text] channel is designed based on the simulation model including Fowler–Nordheim tunneling through a charge-trapping stack, trapping process, and transfer characteristics to describe a full write/read circle. 2D channel materials provide scaling to higher densities as well as preeminent modulation of the conductance by the accumulated space charge from the oxide trapping layer. In this paper, the main parameters affecting the distribution of memory states and their total number are considered. The dependence of memory state distribution on channel doping concentration and the number of layers is given. In addition, how the nonlinearity of memory state distribution can be overcome by variation of operating conditions and by applying pulse width modulation to the bottom gate voltage is also shown.
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42

Zhu, Hao, John E. Bonevich, Haitao Li, Curt A. Richter, Hui Yuan, Oleg Kirillov, and Qiliang Li. "Discrete charge states in nanowire flash memory with multiple Ta2O5 charge-trapping stacks." Applied Physics Letters 104, no. 23 (June 9, 2014): 233504. http://dx.doi.org/10.1063/1.4883717.

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43

Yang, Tao, Hong Wang, Bo Zhang, and Xiaobing Yan. "Enhanced memory characteristics of charge trapping memory by employing graphene oxide quantum dots." Applied Physics Letters 116, no. 10 (March 9, 2020): 103501. http://dx.doi.org/10.1063/1.5135623.

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44

Huang, X. D., P. T. Lai, L. Liu, and J. P. Xu. "Nitrided SrTiO3 as charge-trapping layer for nonvolatile memory applications." Applied Physics Letters 98, no. 24 (June 13, 2011): 242905. http://dx.doi.org/10.1063/1.3601473.

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45

Ji, Yongsung, Minhyeok Choe, Byungjin Cho, Sunghoon Song, Jongwon Yoon, Heung Cho Ko, and Takhee Lee. "Organic nonvolatile memory devices with charge trapping multilayer graphene film." Nanotechnology 23, no. 10 (February 24, 2012): 105202. http://dx.doi.org/10.1088/0957-4484/23/10/105202.

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46

Huang, X. D., P. T. Lai, and J. K. O. Sin. "Charge-Trapping Characteristics of Ga2O3 Nanocrystals for Nonvolatile Memory Applications." ECS Solid State Letters 1, no. 5 (September 10, 2012): Q45—Q47. http://dx.doi.org/10.1149/2.005206ssl.

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47

Yun-Cheng, Song, Liu Xiao-Yan, Du Gang, Kang Jin-Feng, and Han Ru-Qi. "Carriers recombination processes in charge trapping memory cell by simulation." Chinese Physics B 17, no. 7 (July 2008): 2678–82. http://dx.doi.org/10.1088/1674-1056/17/7/053.

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48

Padovani, A., L. Larcher, D. Heh, and G. Bersuker. "Modeling TANOS Memory Program Transients to Investigate Charge-Trapping Dynamics." IEEE Electron Device Letters 30, no. 8 (August 2009): 882–84. http://dx.doi.org/10.1109/led.2009.2024622.

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49

Zhu, Hao, Christina A. Hacker, Sujitra J. Pookpanratana, Curt A. Richter, Hui Yuan, Haitao Li, Oleg Kirillov, Dimitris E. Ioannou, and Qiliang Li. "Non-volatile memory with self-assembled ferrocene charge trapping layer." Applied Physics Letters 103, no. 5 (July 29, 2013): 053102. http://dx.doi.org/10.1063/1.4817009.

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Mondal, Sandip, and V. Venkataraman. "All inorganic solution processed three terminal charge trapping memory device." Applied Physics Letters 114, no. 17 (April 29, 2019): 173502. http://dx.doi.org/10.1063/1.5089743.

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