Dissertations / Theses on the topic 'Polygonal Voltage Space Vector Structures'

Induction motors are mainly powered by two-level inverters in low-voltage, low-power drive applications. For medium and high voltage applications, a conventional two-level inverter needs high voltage rated switches, operates at high switching frequency to get better voltage quality, and produces high dv/dt at switching instants. While operating at six-step mode for full speed operation, a conventional two-level inverter produces low-order harmonics, mainly 5th, 7th, 11th, 13th, 17th, 19th, and so on. These lower-order harmonics produce torque pulsations, which can damage the motor and affects produced torque and power. Conventionally these low order harmonics are suppressed or eliminated by employing bulky and costly passive filters, which degrades dynamic performance of the motor. Another technique based on modified pulse width modulation is selective harmonic elimination, which suppresses fundamental voltage along with harmonics resulting in underutilization of the DC-link voltage. Multi-level inverters are widely employed in high power and high voltage motor drive applications due to lower harmonic distortion and lower dv/dt in the phase voltage. However, multi-level inverters produce hexagonal space vector structure (SVS) and introduce lower-order harmonics in phase voltage during operat= ion in overmodulation region. Also, as the levels increases, number of switches, number of capacitors, diodes and isolated power supplies also increases.       Polygonal SVS is a method for eliminating lower-order harmonics in full operating region. This thesis addresses the above-mentioned issues by generating a two-level and multi-level 24-sided polygonal SVS with real active vectors instead of switched average vectors. Each active vector is a real vector in contrast to switched average vectors in literature. The generation of real 24-sided vectors minimizes switching losses and improves the quality of phase voltage compared to switched averaged vectors technique. 24-sided polygonal SVS scheme eliminates lower order harmonics up to 19th order from motor phase voltage throughout the modulation range. The first work presents a method of generating 24-sided polygonal SVS comprised of 24 real active vectors and a zero vector. In the second work, a multilevel 24-sided polygonal SVS is presented, which suppresses higher order harmonics along with elimination of lower order harmonics from motor phase voltage. In the third work, an inverter circuit to generate a thirteen-level 24-sided polygonal SVS comprised of 288 real active vectors and a zero vector is presented. The SVS generated in third work is denser than the scheme pr= esented in the second work, which further improves output voltage quality, without altering the power circuit topology. In all above three works, vector timing computation is required, and reference vector is realized by time averaging nearest three vectors. To ensure the elimination of timing computation, a 24-sided polygon must be available for reference vector of any magnitude. In the fourth work, a variable speed induction motor drive to generate 24-stepped voltage waveform throughout modulation range is presented.       Inverter circuit is realized using primary and secondary inverters feeding an open-end winding induction motor. Primary and secondary inverters are implemented by cascading two-level inverters. DC sources for both inverters are realized using a simple star-delta transformer combination. The presented concepts are verified with laboratory prototypes. The presented work is suitable for medium voltage and medium power induction motor drive applications.
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A conventional 2-level inverter is the most prevalent DC-AC converter used to drive an induction motor. A conventional 2-level inverter produces a hexagonal voltage space vector structure. To extract maximum voltage from a DC-link, the inverter has to operate in overmodulation region. During this region of operation, a hexagonal space vector structure generates undesirable lower order harmonics, which in turn produce torque pulsations in the motor shaft. To avoid this problem, the inverter can be operated in the linear modulation region of the space vector structure at a high switching frequency. Always to operate the inverter in linear modulation region, the inverter has to be supplied with a DC-link of higher voltage and hence the DC source is underutilized. In addition, higher frequency switching at linear modulation is not an accepted solution for a high power drive because of the high power dissipation in the switches due to the switching loss. Methods like passive filtering technique and selective harmonic elimination techniques are adopted to filter and eliminate the harmonics while operating at lower switching frequencies. These techniques limit the maximum fundamental extracted from the DC-link. One other elegant method to eliminate the lower order harmonics and to extract the maximum fundamental voltage from the DC-link is by modulating the inverter using higher sided polygonal structures. First part of the work proposes a novel polygonal voltage space vector structure having 30 sides using a single DC-link. The space vector structure eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. The topology consists of a DC-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is cancelled by the secondary inverter which acts as a switched capacitive filter. Further, second part of the work is obtaining, a multilevel inverter scheme generating a 30-sided space vector structure with congruent triangles. The scheme being multilevel reduces the dv/dt and further reduces the harmonic content in the output voltage. The proposed scheme is implemented using a single DC-link on an open end induction motor. The open end induction motor is fed with primary inverter from one end and secondary inverter from the other end. Primary inverter is fed from an active DC-link and supplies all the required active power for the scheme. Secondary inverter is a capacitor fed inverter which acts as the switched capacitive filter. In third research work, the generation of an even denser 30-sided multilevel space vector structure using a single DC-link for an open end induction motor drive is presented. The resultant space vector structure has 15-concentric 30-sided polygons. The proposed scheme also eliminates lower order harmonics till 25th order from motor phase voltage throughout the modulation range. The dv/dt stress in the phase voltage applied to the motor will also be highly reduced owing to the multilevel structure. The topology consists of an active DC-link fed 3-level primary inverter and a capacitor fed 5-level secondary inverter connected to either end of an open end induction motor. In fourth research work, a very high resolution multilevel voltage space vector structure having 117-concentric 30-sided polygons of different radii is proposed. In this work, non-aligned 30-sided polygons i.e. regular 30-sided polygons which are not symmetric with respect to alpha and beta axis are also considered for inverter operation, for the first time. The denseness of space vector structure allows to use nearest level switching, enabling further reduction of switching loss in the system. The feasibility of all the proposed scheme is proved by experimental results during open loop v/f and field oriented control. All the schemes used in this thesis requires only a single DC-link for its operation, which enables easy four quadrant operation by using a single active front end converter. All the above mentioned features make the schemes best suited for high power medium voltage applications.

Multilevel voltage source inverter transformed conversion of DC to AC for medium to high power application. With increasing electric power demand, the multilevel converter allows high power density converters for medium to high voltage high power applications. Motor drives, high voltage DC (HVDC) transmission, renewable energy systems, and electric traction are some applications that employ multilevel converters. Conventional two-level inverters need to switch between full DC link to ground potential and require voltage blocking equal to the supply voltage. In addition, 2-level inverters require harmonic filters for filtering harmonics in the output voltage. The filters are costly and bulky and dissipate power, decreasing the system's overall efficiency. Multilevel inverters overcome the disadvantages of conventional inverters by switching intermediate voltage levels between DC link voltage and zero voltage. The higher resolution in the inverter voltage levels reduces the output voltage error compared to the required sinusoidal waveform and improves the harmonic quality. The converter's switching frequency is reduced to minimise the switching losses, thereby increasing the system efficiency. The dv/dt of the multilevel converter is less, which reduces the switching stress on the device and brings down the conductive and radiative emissions. Multilevel inverters can also utilise time-tested low voltage semiconductor technologies to build the converters, improving the system's reliability and easy component availability. Basic and most popular multilevel topologies are cascaded H-bridge inverter, neutral point clamped inverter and flying capacitor inverter. Another class of hybrid multilevel inverters is obtained by cascading basic multilevel inverter cells, which can generate high-quality output voltage waveforms with greater voltage levels. Hybrid multilevel inverters for induction motor drives are also obtained by configuring the motor as an open-end and feeding on both sides of the induction motor. The conventional voltage source inverter generates a hexagonal space vector structure. The inverters are required to operate in the overmodulation region for maximum utilisation of the available DC-link. Operating in the overmodulation region generates lower-order harmonics in the phase voltage and causes several undesirable problems in the systems. The linear modulation range of the hexagonal space vector structure is 90.7\% of the peak fundamental voltage for the maximum modulation index. Induction motor drives using hexagonal space vector structure suffer from torque pulsations on the motor shaft, which could even lead to total system failure. The harmonics in the system affect the dynamic performance of closed-loop current control of the motor and generate significant power loss. Various techniques have been proposed in the literature to suppress the problems caused by harmonics. Increasing the switching frequency of the converter is one such method to reduce the effect of harmonics by having lowest harmonics only at switching frequency, which is easy to filter out. High switching frequency is not a practical solution for medium and high power applications due to the high magnitude of switching loss in the device, resulting in worse electromagnetic compatibility performance. Also, the increased switching frequency is only effective for operation within the linear modulation range. Another conventional method for harmonic suppression is using passive filters. But, for variable frequency operation like in induction motor drives, filtering out lower order harmonics requires bulky filters, which increases the system's size and cost and adds to the resistive loss. Moreover, the addition of the filter to the system affects the system's dynamic performance and reduces the fundamental voltage at the output. Selective harmonic elimination (SHE) is a special pulse width modulation (PWM) to suppress the harmonics by introducing fixed notches in the output. SHE operates with a low switching frequency but suffers from low DC-link utilisation due to the introduction of the notches. Also, the method becomes complex for the elimination of multiple harmonics and has poor dynamic performance. An elegant method to eliminate harmonics in the output voltage is to realise space vector structures with inherent harmonic elimination. Polygonal space vector structure with a higher number of sides than a hexagon, such as 12-sided polygon and 18-sided polygon, eliminates lower order harmonics. 12-sided polygon eliminates the lower order harmonics of the order 5th and 7th and has harmonics only from 11th and 13th. 18-sided polygon eliminates the harmonics up to the 13th order and only harmonics from the 17th and 19th order. The polygons with a higher number of sides are closer to a circle geometrically and have an increased linear modulation region than hexagon (6-sided) for a given DC-link voltage. Generating higher fundamental voltage inverter operations compare to hexagon for the same DC-link voltage leads to better DC-link utilisation. Schemes generating multilevel polygonal space vector structures have evolved to incorporate the advantages of multilevel converters. There are several challenges to generating multilevel polygonal structures, including the requirement of large capacitance, the complexity of PWM techniques etc. Power circuit topologies with a single DC source to generate polygonal space vector structures have evolved but suffer from the requirement of large capacitor size. This thesis proposes a capacitor size reduction methodology and a simple PWM strategy for multilevel polygonal space vector structure. Chapter 1 introduces various harmonic suppression schemes and topologies for generating multilevel inverter polygonal space vector structures. A multilevel 12-sided polygonal voltage space vector generation scheme for variable-speed drive applications with a single DC-link operation requires an enormous capacitance value for cascaded H-bridge (CHB) filters when operated at lower speeds. The multilevel 12-sided polygonal structure is obtained in existing schemes by cascading a flying capacitor inverter with a CHB. Chapter 2 proposes a new scheme to minimise the capacitance requirement for full-speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimise the selection of vector redundancies among the CHBs to minimise the floating capacitors' voltage ripple. The algorithm computes the optimal vector redundancies by considering the instantaneous capacitor voltages and the phase currents. Chapter 3 proposes a simple unified pulse width modulation (PWM) strategy for multilevel polygonal space vector structure (SVS) partitioned into symmetric triangles for the first time. The algorithm obtains the PWM timing durations for a 2-level polygonal voltage SVS in a sampling duration using only the sampled reference values of voltages. The PWM timings obtained for a 2-level structure are then mapped to multilevel SVS. The matrices used for this mapping remain the same irrespective of the sides of the polygon. The smallest triangle encompassing the reference voltage vector in the multilevel structure is identified using this algorithm along with the PWM timings for which the voltage vectors forming the vertices of this smallest triangle are applied. The algorithm involves only operations like addition, multiplication, and logical comparisons. A general implementation scheme for an N-level, p-sided polygon is presented in this paper. A novel 5-level 18-sided SVS is also proposed in this paper. The scheme incorporates the advantages of harmonic elimination due to an 18-sided polygon and the inherent advantages of a multilevel inverter. A multilevel variable speed induction motor drive scheme using an 18-sided polygon with a very dense voltage space vector structure (SVS) is proposed in chapter 4. The proposed SVS consists of 101 concentric layers of 18-sided polygons. The 18-sided polygonal SVS eliminates lower order harmonics 5th, 7th, 11th and 13th orders from the output voltage for the entire modulation range. The linear modulation range of the 18-sided polygon is extended to 99\% of the base speed compared to 90.7\% of the hexagonal SVS. It also has higher peak phase fundamental voltage at the output and better DC-link utilisation than conventional inverters. The SVS is generated by superposition of 5-level main hexagonal SVS of radius VDC and 5-level auxiliary hexagonal SVS of radius 0.379VDC. The dense voltage space vector structure facilitates the generation of reference by nearest vector switching in the 18-sided polygon, reducing the semiconductor devices' switching. The vector switched to realise the reference voltage in a sampling period is only one polygonal vector throughout the modulation range, drastically reducing switching loss and electromagnetic emissions. Simulation and experimental results of the proposed drive scheme are presented to prove the effectiveness of the drive scheme. The inverter is modelled and extensively simulated using a MATLAB-SIMULINK environment. An experimental setup using inverter modules is set up to test the inverter. The semiconductor switches used are SKM75GB12T4 and IRF260N. Gate drive circuits based on opto-isolated IC M5792L from Mitsubishi and capacitive isolated IC ISO5451 from Texas Instruments are used. TMS320F28335 DSP from Texas Instruments and XC2S200 FPGA from Xilinx were used as the controllers for realising the hardware prototype. A 3-phase open-end induction motor of ratings 15 kW, 415 V, and 4-pole is used for testing the proposed drive schemes.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Multilevel inverters (MLI) are widely used in a host of industrial applications ranging from renewable energy systems, to electric vehicles, to distributed generation. Due to the switching nature of the output voltage, MLI generate harmonics in output voltage at switching frequency. The harmonics in output voltage generate harmonic currents in the load, which may lead to losses in the system, and may also cause torque pulsations for motor drive applications. Hence, it is necessary to improve the harmonic performance (Total Harmonic Distortion-THD) of the output voltage. To improve the THD of the output voltage, passive filters may be incorporated to suppress the switching frequency harmonics. To optimize the component size in the filter, inverters are operated at high switching frequency. The high switching frequency in MLI generates electro-magnetic interference (EMI) and large dv/dt in the switching devices and motor load. Due to these drawbacks, the passive filtering solution is not very attractive. To overcome the aforementioned drawbacks, polygonal space vector structures have been proposed. This solution leads to generation of polygonal voltage space vector structures with sides greater than 6, in the over-modulation region. By switching on the vertices of dense space vector structure, lower order harmonics in phase voltage are suppressed with increased utilization of DC link voltage. Polygonal space vector structures can be generated by using a secondary inverter fed with a capacitive supply. The polygon is generated by superposition of the primary and secondary inverter space vectors. Polygonal space vector generation offers many advantages over conventional solutions. Polygonal space vector structures offer increased linear modulation range, which leads to maximum utilization of the DC link supply. In this scheme the main power delivery inverter fed with the active DC link supply is switched at low switching frequency. The reduced switching frequency reduces switching losses and reduces dv/dt. The secondary inverter is fed with a capacitive supply which is balanced at a fraction of the DC link voltage supply. The capacitive supply is balanced at it's nominal voltage during motoring/braking operation by using a novel capacitor balancing scheme. The presence of a single active supply to provide power for motoring operation reduces system complexity and facilitates four quadrant operation. The secondary inverter fed with low voltage capacitive supply is switched at high frequency for suppression of harmonics generated by low switching frequency primary inverter. The secondary inverter can be realized using low voltage semiconductor devices as the blocking voltage requirements for the secondary inverter are considerably lower. The secondary inverter does not provide any active power for motoring operation and hence acts as a switched capacitive filter. Compared to the conventional bulky passive filtering solutions, the switched capacitive filter is cost effective.

Multilevel voltage source inverters have become a widely accepted and cost-effective power converter technology for applications requiring high-power medium-voltage control. The demand of power level requirement has reached operational limits of megawatt range. Multilevel inverters (MLI) find applications in power transmission and distribution systems like HVDC which are connected with high voltage network lines and controlled ac drives operating at medium voltage levels. For low voltage applications, most prevalent topology which dominates industrial drives is conventional two-level inverter. With state of the art semiconductor technology, self-commutating converters with arrangement of several low voltage devices, help achieving voltage ranges till hundreds of kilovolts. Apart from high voltage operational capability, advantages like power quality control, better electromagnetic compatibility, lower switching losses, keep multilevel inverters a class above the conventional two-level inverters. In order to attain good waveform quality, the inverter needs to switch at very high frequencies. The harmonics appear only at switching frequency sidebands, which can be easily filtered externally. But, considering large voltage stress handled by the devices in two-level inverter and large switching loss in the devices degrade the efficiency of system substantially. Specific to applications like medium voltage drives, the major issues on electromagnetic interference, device stress, harmonic performance, and dv/dt control are mostly addressed by employing multilevel inverters. Most popular multilevel inverter topologies are neutral-point clamped inverters, flying capacitor inverters, and cascaded H-bridge inverters. These basic MLIs are further used to obtain hybrid multilevel inverters generating more number of voltage levels. Other applications of multilevel inverters include photovoltaic, hydel and wind energy systems, energy storage and management systems, electric vehicle applications, traction drives etc. As a 24-sided polygon is closer to a circle than a hexagon or a 12-sided polygon, the above presented schemes generate high quality motor phase voltage waveforms without using any external filters. A physical sine-wave filter can be completely relaxed for such variable speed drive applications, and the dynamic performance is never compromised since the filtering action is performed by switched capacitors. The topologies and modulation techniques presented are optimized for low switching frequency operation of large voltage blocking inverters and shifting relatively higher frequency switchings to low voltage cascaded H-Bridge inverters. Above all, single DC source operation can bring down the cost and complexity of the system drastically enabling easier back to back operation for drive. Also, such schemes can be directly driven from battery operated systems in electric vehicles without any passive sine filters. With all the mentioned advantages, the proposed drive schemes are highly suitable for high performance, medium voltage drive applications.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

Variable-speed Induction motor drives are nowadays used for various kinds of industrial processes, transportation systems, wind turbines and household appliances in the world. The majority of drives are for general purpose speed control applications where accurate speed control is not required for entire speed range. But for high dynamic drive application, very precise and fast control of induction motor drive is essential. For such applications, sophisticated and well-performing control design is a key issue. Precise and accurate torque control of the Induction Motor (IM) can only be accomplished by vector control and direct torque control. In terms of space vector theory, vector control implies that the instantaneous torque is controlled by way of the stator current vector that is orthogonal to the rotor flux vector. Precise knowledge of the rotor flux angle is therefore essential for a vector controlled IM. IMs do not allow the flux position to be easily measured, so most modern vector controlled IM drives rely on flux estimation. This means that the flux angle is derived from a flux estimator, using the dynamic model of the IM. Given that the rotor speed of the IM is measured by a mechanical shaft sensor. Flux estimation is a fairly easy task. However, vector control of IM without mechanical shaft speed sensor is of current interest in industrial environment. The driving motivations behind the development in sensorless control are lower cost, improved reliability and operating environment. In this thesis, a sensorless vector control scheme for rotor flux estimation using current error space phasor based hysteresis controller is proposed including the method for estimation of leakage inductance, Ls. For frequencies of operation less than 25 Hz, the rotor voltage and hence the rotor flux position is computed during the inverter zero voltage space vector using steady state model of IM. For above 25 Hz, active vector period and steady state model of IM is used. The whole rotor flux estimation scheme is dependent on current error space phasor and the steady state motor model, with rotor flux as a reference vector. Since no terminal voltage sensing is involved, dead time effects will not create problem in rotor flux sensing at low frequencies of operation. But appropriate device on-state drop are compensated at low frequencies (below 5 Hz) of operation to achieve a steady state operation up to less than 1 Hz. A constant switching frequency hysteresis current controller is used in inner current control loop for the PWM regulation, with smooth transition of operation to six-step mode operation. A simple Ls estimation based on current error space phasor is also proposed to nullify the deteriorating effect on rotor flux estimation. The parameter sensitivity of the control scheme to changes in the stator resistance Rs is also investigated. The drive scheme is tested up to a low frequency operation less than 1 Hz. The extensive simulation and experiment results are presented to show the proposed scheme’s good dynamic performance extending up to six-step operation. In contrast to vector control, direct torque control (DTC) method requires the knowledge of stator resistance only and thereby decreasing the associated sensitivity to parameters variation and the elimination of speed information. DTC as compared to vector control does not require co-ordinate transformation and PI controller. DTC is easy to implement because it needs only two hysteresis comparators and a lookup table for both flux and torque control. This thesis also investigates the possibilities in improvement of direct torque control scheme for high performance induction motor drive applications. Here, two schemes are proposed based on the direct torque control scheme for IM drive using 12-sided polygonal voltage space vectors for fast torque control. The torque control scheme based on DTC algorithm is proposed using 12-sided polygonal voltage space vector. The basic DTC scheme is used to control the torque. But the IM drive is open-end type. For torque control, the voltage space vectors orthogonal to stator flux vector in 12-sided polygonal space vector structure are used as hexagonal space vector based DTC scheme. The advantages achieved due to 12-sided polygonal space vector are mainly fast torque control and small torque ripple. The fast transient of torque with precise control is achieved using voltage space vector placed with a resolution of ±15. The torque ripple will be less as 6n±1 (n=odd) harmonic torque is totally eliminated from the whole range of PWM modulation. The comparative analysis of proposed 12-sided polygonal voltage space vector based DTC and conventional hexagonal space vector based DTC is also presented. Extensive simulation and experiment results are also presented to show the fast torque control at speeds of operation ranging from 5 Hz to the rated speed. The concept of 12-sided polygonal space vector based DTC is further extended for a variable speed control scheme using estimated fundamental stator voltage for sector identification. The conventional DTC scheme uses stator flux vector for identification of the sector and the switching vector are selected based on this sector information to control stator flux and torque. However, the proposed DTC scheme selects switching vectors based on the sector information of the estimated fundamental stator voltage vector and its relative position with respect to the stator flux vector. The fundamental stator voltage estimation is based on the steady state model of IM and information of synchronous frequency which is derived from computed stator flux using a low pass filter technique. The proposed DTC scheme utilizes the exact position of fundamental stator voltage vector and stator flux vector position to select optimal switching vector for fast control of torque with small variation of stator flux within hysteresis band. The present DTC scheme allows the full load torque control with fast transient response to very low speeds of operation below 5 Hz. The extensive simulation and experiment results are presented to show the fast torque control for speed of operation from zero speed to rated speed. However, the present scheme will have all the advantages of DTC scheme using stator flux vector for sector identification. All the above propositions are first simulated by MATLAB/Simulink and subsequently verified by an experimental laboratory prototype. The proposed control schemes are experimentally verified on a 3.7 kW IM drive. The control algorithms of the sensorless vector control using current error space phasor as well as DTC using 12-sided polygonal voltage space vector are completely implemented on a TI TMS320LF2812 DSP controller platform. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of sensorless vector control, direct torque control and current hysteresis controller. The thesis concludes with suggestion for further exploration.

Variable-speed Induction motor drives are nowadays used for various kinds of industrial processes, transportation systems, wind turbines and household appliances in the world. The majority of drives are for general purpose speed control applications where accurate speed control is not required for entire speed range. But for high dynamic drive application, very precise and fast control of induction motor drive is essential. For such applications, sophisticated and well-performing control design is a key issue. Precise and accurate torque control of the Induction Motor (IM) can only be accomplished by vector control and direct torque control. In terms of space vector theory, vector control implies that the instantaneous torque is controlled by way of the stator current vector that is orthogonal to the rotor flux vector. Precise knowledge of the rotor flux angle is therefore essential for a vector controlled IM. IMs do not allow the flux position to be easily measured, so most modern vector controlled IM drives rely on flux estimation. This means that the flux angle is derived from a flux estimator, using the dynamic model of the IM. Given that the rotor speed of the IM is measured by a mechanical shaft sensor. Flux estimation is a fairly easy task. However, vector control of IM without mechanical shaft speed sensor is of current interest in industrial environment. The driving motivations behind the development in sensorless control are lower cost, improved reliability and operating environment. In this thesis, a sensorless vector control scheme for rotor flux estimation using current error space phasor based hysteresis controller is proposed including the method for estimation of leakage inductance, Ls. For frequencies of operation less than 25 Hz, the rotor voltage and hence the rotor flux position is computed during the inverter zero voltage space vector using steady state model of IM. For above 25 Hz, active vector period and steady state model of IM is used. The whole rotor flux estimation scheme is dependent on current error space phasor and the steady state motor model, with rotor flux as a reference vector. Since no terminal voltage sensing is involved, dead time effects will not create problem in rotor flux sensing at low frequencies of operation. But appropriate device on-state drop are compensated at low frequencies (below 5 Hz) of operation to achieve a steady state operation up to less than 1 Hz. A constant switching frequency hysteresis current controller is used in inner current control loop for the PWM regulation, with smooth transition of operation to six-step mode operation. A simple Ls estimation based on current error space phasor is also proposed to nullify the deteriorating effect on rotor flux estimation. The parameter sensitivity of the control scheme to changes in the stator resistance Rs is also investigated. The drive scheme is tested up to a low frequency operation less than 1 Hz. The extensive simulation and experiment results are presented to show the proposed scheme’s good dynamic performance extending up to six-step operation. In contrast to vector control, direct torque control (DTC) method requires the knowledge of stator resistance only and thereby decreasing the associated sensitivity to parameters variation and the elimination of speed information. DTC as compared to vector control does not require co-ordinate transformation and PI controller. DTC is easy to implement because it needs only two hysteresis comparators and a lookup table for both flux and torque control. This thesis also investigates the possibilities in improvement of direct torque control scheme for high performance induction motor drive applications. Here, two schemes are proposed based on the direct torque control scheme for IM drive using 12-sided polygonal voltage space vectors for fast torque control. The torque control scheme based on DTC algorithm is proposed using 12-sided polygonal voltage space vector. The basic DTC scheme is used to control the torque. But the IM drive is open-end type. For torque control, the voltage space vectors orthogonal to stator flux vector in 12-sided polygonal space vector structure are used as hexagonal space vector based DTC scheme. The advantages achieved due to 12-sided polygonal space vector are mainly fast torque control and small torque ripple. The fast transient of torque with precise control is achieved using voltage space vector placed with a resolution of ±15. The torque ripple will be less as 6n±1 (n=odd) harmonic torque is totally eliminated from the whole range of PWM modulation. The comparative analysis of proposed 12-sided polygonal voltage space vector based DTC and conventional hexagonal space vector based DTC is also presented. Extensive simulation and experiment results are also presented to show the fast torque control at speeds of operation ranging from 5 Hz to the rated speed. The concept of 12-sided polygonal space vector based DTC is further extended for a variable speed control scheme using estimated fundamental stator voltage for sector identification. The conventional DTC scheme uses stator flux vector for identification of the sector and the switching vector are selected based on this sector information to control stator flux and torque. However, the proposed DTC scheme selects switching vectors based on the sector information of the estimated fundamental stator voltage vector and its relative position with respect to the stator flux vector. The fundamental stator voltage estimation is based on the steady state model of IM and information of synchronous frequency which is derived from computed stator flux using a low pass filter technique. The proposed DTC scheme utilizes the exact position of fundamental stator voltage vector and stator flux vector position to select optimal switching vector for fast control of torque with small variation of stator flux within hysteresis band. The present DTC scheme allows the full load torque control with fast transient response to very low speeds of operation below 5 Hz. The extensive simulation and experiment results are presented to show the fast torque control for speed of operation from zero speed to rated speed. However, the present scheme will have all the advantages of DTC scheme using stator flux vector for sector identification. All the above propositions are first simulated by MATLAB/Simulink and subsequently verified by an experimental laboratory prototype. The proposed control schemes are experimentally verified on a 3.7 kW IM drive. The control algorithms of the sensorless vector control using current error space phasor as well as DTC using 12-sided polygonal voltage space vector are completely implemented on a TI TMS320LF2812 DSP controller platform. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of sensorless vector control, direct torque control and current hysteresis controller. The thesis concludes with suggestion for further exploration.

Multilevel converters have become the direct accepted solution for high power converter applications. They are used in wide variety of power electronic applications like power transmission and distribution, electric motor drives, battery management and renewable energy management to name a few. For medium and high voltage motor drives, especially induction motor drives, the use of multilevel voltage source inverters have become indispensible. A high voltage multilevel inverter could be realized using low voltage switching devices which are easily available and are of low cost. A multilevel inverter generates voltage waveforms of very low harmonic distortion by switching between voltage levels of reasonably small amplitude differences. Thus the dv/dt of the output voltage waveform is small and hence the electromagnetic interference generated is less. Because of better quality output generation, the switching frequency of the multilevel inverters could be reduced to control the losses. Thus, a multilevel converter stands definitely a class apart in terms of performance from a conventional two-level inverter. Many multilevel inverter topologies for induction motor drives are available in the literature. The basic multilevel topologies are the neutral point clamped (NPC) inverter, flying capacitor (FC) inverter and the cascaded H-bridge (CHB) inverter. Various other hybrid multilevel topologies have been proposed by using the basic multilevel inverter topologies. It is also possible to obtain multilevel output by using conventional two-level inverters feeding an open-end winding induction motor from both sides. All the conventional multilevel voltage source inverters generate hexagonal (6 sided polygons) voltage space vector structures. When an inverter with hexagonal space vector structure is operated in the over modulation range, significant low order harmonics are generated in the phase voltage output. Over modulation operation is required for the full utilization of the available DC-link voltage and hence maximum power generation. Among the harmonics generated, the fifth and seventh harmonics are of significant magnitudes. These harmonics generate torque ripple in the motor output and are undesirable in high performance motor drive applications. The presence of these harmonics further creates problems in the closed loop current control of a motor, affecting the dynamic performance. Again, the harmonic currents generate losses in the stator windings. Therefore, in short, the presence of harmonic voltages in the inverter output is undesirable. Many methods have been proposed to eliminate or mitigate the effect of the harmonics. One solution is to operate the inverter at high switching frequency and thereby push the harmonics generated to high frequencies. The stator leakage inductance offers high impedance to the high frequency harmonics and thus the harmonic currents generated are negligible. But, high switching frequency brings switching losses and high electromagnetic interference generation in the drive system. And also, high switching frequency operation is effective only in the linear modulation range. Another solution is to use passive harmonic filters at the inverter output. For low order harmonics, the filter components would be bulky and costly. The loss created by the filters degrades the efficiency of the drive system as well. The presence of a filter also affects the dynamic performance of the drive system during closed loop operation. Special pulse width modulation (PWM) techniques like selective harmonic elimination (SHE) PWM can prevent the generation of a particular harmonic from the phase voltage output. The disadvantages of such schemes are limited modulation index, poor dynamic performance and extensive offline computations. An elegant harmonic elimination method is to generate a voltage space vector structure having more number of sides like a dodecagon (12 sided polygons) or an octadecagon (18 sided polygons) rather than a hexagon. Inverter topologies generating dodecagonal voltage space vector structure eliminate fifth and seventh order harmonics, represented as 6n 1; n = odd harmonics, from the phase voltages and hence from the motor phase currents, throughout the entire modulation range. The first harmonics appearing the phase voltage are the 11th and 13th harmonics. Another advantage is the increased linear modulation range of operation for a given DC-link voltage, because geometrically dodecagon is closer to circle than a hexagon. An octadecagonal structure eliminates the 11th and 13th harmonics as well from the phase voltage output. The harmonics present in the phase voltage are of the order 18n 1; n = 1; 2; 3; :::. Thus the total harmonics distortion (THD) of the phase voltage is further improved. The linear modulation range also gets enhanced compared to hexagonal and dodecagonal structures. Multilevel dodecagonal and octadecagonal space vector structures combines the advantages of both multilevel structure and dodecagonal and octadecagonal structure and hence are very attractive solutions for high performance induction motor drive schemes. Chapter 1 of this thesis introduces the multilevel in-verter topologies generating hexagonal, dodecagonal and octadecagonal voltage space vector structures. Inverter topologies generating multilevel dodecagonal and octadecago-nal voltage space vector structures have been proposed before but using multiple DC sources delivering active power. The presence of more than one DC source in the inverter topology makes the back to back operation (four-quadrant operation) of the drive system difficult. And also the drive system becomes more costly and bulky. This thesis proposes induction motor drive schemes generating multilevel dodecagonal and octadecagonal volt-age space vector structures using a single DC source. In Chapter 2, an induction motor drive scheme generating a six-concentric multilevel dodecagonal voltage space vector structure using a single DC source is proposed for an open-end winding induction motor. In the topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a DC source (Vdc) which delivers the entire active power, whereas the secondary inverter DC-link is maintained by a capacitor at a voltage of 0:289Vdc, which is self-balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small DC-link voltage. Hence, switching losses are small for both primary and secondary inverters. An open-loop V/f scheme was used to test the topology and modulation scheme. In the work proposed in Chapter 3, the topology and modulation scheme used in the first work is modified for a star connected induction motor. Again, the scheme uses only a single DC source and generates a six-concentric multilevel space vector struc-ture. The power circuit topology is realized using a three-level flying capacitor (FC) inverter cascaded with an H-bridge (CHB). The capacitors in the CHB inverter are maintained at a voltage level of 0:1445Vdc. The FC inverter switches between volt-age levels of [Vdc; 0:5Vdc; 0] and the CHB inverter switches between voltage levels of [+01445Vdc; 0; 0:1445Vdc]. The PWM scheme generates a quasi-square waveform output from the FC inverter. This results in very few switchings of the FC inverter in a funda-mental cycle and hence the switching losses are controlled. The CHB inverter switches Ch. 0: at high frequency compared to the FC inverter and cancels the low order harmonics (6n 1; n = odd) generated by the FC inverter. Even though the CHB operates at higher switching frequency, the switchings are at low voltage thereby controlling the losses. The linear modulation range of operation is extended to 48:8Hz for a base frequency of 50Hz. An open-loop V/f scheme was used to test the topology and modulation scheme. In Chapter 4, a nine-concentric multilevel octadecagonal space vector structure is proposed for the first time, again using a single DC source. The circuit topology remains same as the work in Chapter 3, except that the CHB capacitor voltage is maintained at 0:1895Vdc. The 5th; 7th; 11th and 13th harmonics are eliminated from the phase voltage output. The linear modulation range is enhanced to 49:5Hz for a base speed of 50Hz. An open-loop V/f scheme and rotor field oriented control scheme were used to test the proposed drive system. All the proposed drive schemes have been extensively simulated and tested in hard-ware. Simulation was performed in MATLAB-SIMULINK environment. For implement-ing the inverter topology, SKM75GB12T4 IGBT modules were used. The control al-gorithms were implemented using a DSP (TI’s TMS320F28334) and an FPGA (Xilinx Spartan XC3S200). A 1kW , 415V , 4-pole induction motor was used for the experiment purpose. The above mentioned induction motor drive schemes generate phase voltage outputs in which the low order harmonics are absent. The linear modulation range is extended near to the base frequency of operation compared to hexagonal space vector structure. In the inverter topologies, the secondary inverters or the CHB inverters functions as harmonic filters and delivers zero active power. The primary inverter in the topologies switches at low frequency, reducing the power loss. Single DC source requirement brings down the cost of the system as well as permitting easy four-quadrant operation. This is also advantageous in battery operated systems like EV applications. With these features and advantages, the proposed drive schemes are suitable for high performance, medium voltage induction motor drive applications.

Multilevel converters have become the direct accepted solution for high power converter applications. They are used in wide variety of power electronic applications like power transmission and distribution, electric motor drives, battery management and renewable energy management to name a few. For medium and high voltage motor drives, especially induction motor drives, the use of multilevel voltage source inverters have become indispensible. A high voltage multilevel inverter could be realized using low voltage switching devices which are easily available and are of low cost. A multilevel inverter generates voltage waveforms of very low harmonic distortion by switching between voltage levels of reasonably small amplitude differences. Thus the dv/dt of the output voltage waveform is small and hence the electromagnetic interference generated is less. Because of better quality output generation, the switching frequency of the multilevel inverters could be reduced to control the losses. Thus, a multilevel converter stands definitely a class apart in terms of performance from a conventional two-level inverter. Many multilevel inverter topologies for induction motor drives are available in the literature. The basic multilevel topologies are the neutral point clamped (NPC) inverter, flying capacitor (FC) inverter and the cascaded H-bridge (CHB) inverter. Various other hybrid multilevel topologies have been proposed by using the basic multilevel inverter topologies. It is also possible to obtain multilevel output by using conventional two-level inverters feeding an open-end winding induction motor from both sides. All the conventional multilevel voltage source inverters generate hexagonal (6 sided polygons) voltage space vector structures. When an inverter with hexagonal space vector structure is operated in the over modulation range, significant low order harmonics are generated in the phase voltage output. Over modulation operation is required for the full utilization of the available DC-link voltage and hence maximum power generation. Among the harmonics generated, the fifth and seventh harmonics are of significant magnitudes. These harmonics generate torque ripple in the motor output and are undesirable in high performance motor drive applications. The presence of these harmonics further creates problems in the closed loop current control of a motor, affecting the dynamic performance. Again, the harmonic currents generate losses in the stator windings. Therefore, in short, the presence of harmonic voltages in the inverter output is undesirable. Many methods have been proposed to eliminate or mitigate the effect of the harmonics. One solution is to operate the inverter at high switching frequency and thereby push the harmonics generated to high frequencies. The stator leakage inductance offers high impedance to the high frequency harmonics and thus the harmonic currents generated are negligible. But, high switching frequency brings switching losses and high electromagnetic interference generation in the drive system. And also, high switching frequency operation is effective only in the linear modulation range. Another solution is to use passive harmonic filters at the inverter output. For low order harmonics, the filter components would be bulky and costly. The loss created by the filters degrades the efficiency of the drive system as well. The presence of a filter also affects the dynamic performance of the drive system during closed loop operation. Special pulse width modulation (PWM) techniques like selective harmonic elimination (SHE) PWM can prevent the generation of a particular harmonic from the phase voltage output. The disadvantages of such schemes are limited modulation index, poor dynamic performance and extensive offline computations. An elegant harmonic elimination method is to generate a voltage space vector structure having more number of sides like a dodecagon (12 sided polygons) or an octadecagon (18 sided polygons) rather than a hexagon. Inverter topologies generating dodecagonal voltage space vector structure eliminate fifth and seventh order harmonics, represented as 6n 1; n = odd harmonics, from the phase voltages and hence from the motor phase currents, throughout the entire modulation range. The first harmonics appearing the phase voltage are the 11th and 13th harmonics. Another advantage is the increased linear modulation range of operation for a given DC-link voltage, because geometrically dodecagon is closer to circle than a hexagon. An octadecagonal structure eliminates the 11th and 13th harmonics as well from the phase voltage output. The harmonics present in the phase voltage are of the order 18n 1; n = 1; 2; 3; :::. Thus the total harmonics distortion (THD) of the phase voltage is further improved. The linear modulation range also gets enhanced compared to hexagonal and dodecagonal structures. Multilevel dodecagonal and octadecagonal space vector structures combines the advantages of both multilevel structure and dodecagonal and octadecagonal structure and hence are very attractive solutions for high performance induction motor drive schemes. Chapter 1 of this thesis introduces the multilevel in-verter topologies generating hexagonal, dodecagonal and octadecagonal voltage space vector structures. Inverter topologies generating multilevel dodecagonal and octadecago-nal voltage space vector structures have been proposed before but using multiple DC sources delivering active power. The presence of more than one DC source in the inverter topology makes the back to back operation (four-quadrant operation) of the drive system difficult. And also the drive system becomes more costly and bulky. This thesis proposes induction motor drive schemes generating multilevel dodecagonal and octadecagonal volt-age space vector structures using a single DC source. In Chapter 2, an induction motor drive scheme generating a six-concentric multilevel dodecagonal voltage space vector structure using a single DC source is proposed for an open-end winding induction motor. In the topology, two three-level inverters drive an open-end winding IM, one inverter from each side. DC-link of primary inverter is from a DC source (Vdc) which delivers the entire active power, whereas the secondary inverter DC-link is maintained by a capacitor at a voltage of 0:289Vdc, which is self-balanced during the inverter operation. The PWM scheme implemented ensures low switching frequency for primary inverter. Secondary inverter operates at a small DC-link voltage. Hence, switching losses are small for both primary and secondary inverters. An open-loop V/f scheme was used to test the topology and modulation scheme. In the work proposed in Chapter 3, the topology and modulation scheme used in the first work is modified for a star connected induction motor. Again, the scheme uses only a single DC source and generates a six-concentric multilevel space vector struc-ture. The power circuit topology is realized using a three-level flying capacitor (FC) inverter cascaded with an H-bridge (CHB). The capacitors in the CHB inverter are maintained at a voltage level of 0:1445Vdc. The FC inverter switches between volt-age levels of [Vdc; 0:5Vdc; 0] and the CHB inverter switches between voltage levels of [+01445Vdc; 0; 0:1445Vdc]. The PWM scheme generates a quasi-square waveform output from the FC inverter. This results in very few switchings of the FC inverter in a funda-mental cycle and hence the switching losses are controlled. The CHB inverter switches Ch. 0: at high frequency compared to the FC inverter and cancels the low order harmonics (6n 1; n = odd) generated by the FC inverter. Even though the CHB operates at higher switching frequency, the switchings are at low voltage thereby controlling the losses. The linear modulation range of operation is extended to 48:8Hz for a base frequency of 50Hz. An open-loop V/f scheme was used to test the topology and modulation scheme. In Chapter 4, a nine-concentric multilevel octadecagonal space vector structure is proposed for the first time, again using a single DC source. The circuit topology remains same as the work in Chapter 3, except that the CHB capacitor voltage is maintained at 0:1895Vdc. The 5th; 7th; 11th and 13th harmonics are eliminated from the phase voltage output. The linear modulation range is enhanced to 49:5Hz for a base speed of 50Hz. An open-loop V/f scheme and rotor field oriented control scheme were used to test the proposed drive system. All the proposed drive schemes have been extensively simulated and tested in hard-ware. Simulation was performed in MATLAB-SIMULINK environment. For implement-ing the inverter topology, SKM75GB12T4 IGBT modules were used. The control al-gorithms were implemented using a DSP (TI’s TMS320F28334) and an FPGA (Xilinx Spartan XC3S200). A 1kW , 415V , 4-pole induction motor was used for the experiment purpose. The above mentioned induction motor drive schemes generate phase voltage outputs in which the low order harmonics are absent. The linear modulation range is extended near to the base frequency of operation compared to hexagonal space vector structure. In the inverter topologies, the secondary inverters or the CHB inverters functions as harmonic filters and delivers zero active power. The primary inverter in the topologies switches at low frequency, reducing the power loss. Single DC source requirement brings down the cost of the system as well as permitting easy four-quadrant operation. This is also advantageous in battery operated systems like EV applications. With these features and advantages, the proposed drive schemes are suitable for high performance, medium voltage induction motor drive applications.

Multi-level inverters play a significant role in high power drive systems for induction motors. Interest in multi-level inverters started with the three-level, neutral point clamped (NPC) inverter. Now there are many topologies for higher number of levels such as the, flying capacitor and cascaded H-bridge etc. The advantage of multi-level inverters is the reduced voltage stress on the switching devices, lower dv/dt and lower harmonic content. The voltage space vector structure in a multi-level inverter has a hexagonal periphery similar to that in a two-level inverter. In the over-modulation region in multi-level inverters, there is the presence of lower order harmonics such as 5th and 7th in the output voltage, and this can be avoided by using a voltage space vector scheme with more than six polygonal voltage space vectors such as 12, 18, 24 etc. These polygonal voltage space vectors can be generated by using multi-level inverter topologies, by cascading two-level inverter structures with asymmetric DC-links. This thesis deals with the development of 12-sided and 18-sided polygonal voltage space vector schemes for induction motor drives. With the 12-sided polygonal structure, all the 5th and 7th harmonic orders and 6n±1, n=1, 3, 5.. are absent throughout the modulation range, and in the 18-sided voltage space vector scheme, 5th, 7th, 11th and 13th harmonics are absent throughout the modulation range. With the absence of the low order frequencies in the proposed polygonal space vector structures, high frequency PWM schemes are not needed for voltage control. This is an advantage over conventional schemes. Also, due to the absence of lower order harmonics throughout the modulation range, special compensated synchronous reference frame PI controllers are not needed in current controlled vector control schemes in over-modulation. In this thesis a method is proposed for generating 12-sided polygonal voltage space vectors for an induction motor fed from one side. A cascaded combination of three two-level inverters is used with asymmetrical DC-links. A simple space vector PWM scheme based only on the sampled reference phase amplitudes are used for the inverter output voltage control. The reference space vector is sampled at different sampling rates depending on the frequency of operation. The number of samples in a sector is chosen to keep the overall switching frequency around 1kHz, in order to minimize switching losses. The voltage space vectors that make up the two sides of the sector in which the reference vector lies, are time averaged using volt-sec balance, to result in the reference vector. In the proposed 12-sided PWM scheme all the harmonics of the order 6n±1, n=1, 3, 5... are eliminated from the phase voltage, throughout the modulation range. In multi-level inverters steps are taken to eliminate common-mode voltage. Common-mode voltage is defined as one third of the sum of the three pole voltages of the inverter for a three phase system. Bearings are found to fail prematurely in drives with fast rising voltage pulses and high frequency switching. The alternating common-mode voltage generated by the PWM inverter contributes to capacitive couplings from stator body to rotor body. This generates motor shaft voltages causing bearing currents to flow from rotor to stator body and then to the ground. There can be a flashover between the bearing races. Also a phenomenon termed EDM (Electro-discharge machining) effect occurs and may damage the bearings. Common-mode voltage has to be eliminated in order to overcome these effects. In multi-level inverters redundancy of space vector locations is used to eliminate common-mode voltages. In the present thesis a 12-sided polygonal voltage space vector based inverter with an open-end winding induction motor is proposed, in which the common-mode voltage variation at the poles of the inverter is eliminated. In this scheme, there is a three-level inverter on each side of the open-end winding of the induction motor. The three-level inverter is made by cascading two, two-level inverters with unequal DC-link voltages. Appropriate space vectors are selected from opposite sides such that the sum of the pole voltages on each side is a constant. Also during the PWM operation when the zero vector is applied, identical voltage levels are used on both sides of the open-end windings, in order to make the phase voltages zero, while the common-mode voltage is kept constant. This way, common-mode voltage variations are eliminated throughout the modulation range by appropriately selecting the voltage vectors from opposite ends. In this method all the harmonics of 6n±1, n=1, 3, 5.. and triplen orders are eliminated. In the 12-sided polygonal voltage space vector methods, the 11th and 13th harmonics though attenuated are not eliminated. In the 18-sided polygonal voltage space vector method the 11th and 13th harmonics are eliminated along with the 5th and 7th harmonics. This scheme consists of an open-end winding induction motor fed from one side by a two-level inverter and the other side by a three-level inverter comprising of two cascaded two-level inverters. Asymmetric DC-links of a particular ratio are present. The 12-sided and 18-sided polygonal voltage space vector methods have been first simulated using SIMULINK and then verified experimentally on a 1.5kW induction motor drive. In the simulation as well as the experimental setup the starting point is the generation of the three reference voltages v, vB and vC . A method for determining the sector in which the reference vector lies by comparing the values of the scaled sampled instantaneous reference voltages is proposed. For the reference vector lying in a sector between the two active vectors, the first vector is to be kept on for T1 duration and the second vector for T2 duration. These timing durations can be found from the derived formula, using the sampled instantaneous values of the reference voltages and the sector information. From the pulse widths and the sector number, the voltage level at which a phase in the inverter has to be maintained is uniquely determined from look-up tables. Thus, once the pole voltages are determined the phase voltages can be easily determined for simulation studies. By using a suitable induction motor model in the simulation, the effect of the PWM scheme on the motor current can be easily obtained. The simulation studies are experimentally verified on a 1.5kW open-end winding induction motor drive. A V/f control scheme is used for the study of the drive scheme for different speeds of operation. A DSP (TMS320LF2407A) is used for generating the PWM signals for variable speed operation. The 12-sided polygonal voltage space vector scheme with the motor fed from a single side has a simple power bus structure and it is also observed that the pole voltage is clamped to zero for 30% of the time duration of one cycle of operation. This will increase the overall efficiency. The proposed scheme eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range. The 12-sided polygonal voltage space vector scheme with common-mode elimination requires the open-end winding configuration of the induction motor. Two asymmetrical DC-links are required which are common to both sides. The leg of the high voltage inverter is seen to be switched only for 50% duration in a cycle of operation. This will also reduce switching losses considerably. The proposed scheme not only eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range, but also maintains the common-mode voltage on both sides constant. The common-mode voltage variation is eliminated. This eliminates bearing currents and shaft voltages which can damage the motor bearings. In the 18-sided polygonal voltage space vector based inverter, the 11th and 13th harmonics are eliminated along with the 5th and 7th. Here also an open-end winding induction motor is used, with a two-level inverter on one side and a three-level inverter on the other side. A pole of the two-level inverter is at clamped to zero voltage for 50% of the time and a pole of the three-level inverter is clamped to zero for 30% of the time for one cycle of operation. The 18-sided polygonal voltage space vectors show the highest maximum peak fundamental voltage in the 18-step mode of 0.663Vdc compared to 0.658Vdc in the 12-step mode of the 12-sided polygonal voltage space vector scheme and 0.637Vdc in the six-step mode of a two-level inverter or conventional multi-level inverter (where Vdc is the radius of the space vector polygon). Though the schemes proposed are verified on a low power laboratory prototype, the principle and the control algorithm development are general in nature and can be easily extended to induction motor drives for high power applications.

Multi-level inverters play a significant role in high power drive systems for induction motors. Interest in multi-level inverters started with the three-level, neutral point clamped (NPC) inverter. Now there are many topologies for higher number of levels such as the, flying capacitor and cascaded H-bridge etc. The advantage of multi-level inverters is the reduced voltage stress on the switching devices, lower dv/dt and lower harmonic content. The voltage space vector structure in a multi-level inverter has a hexagonal periphery similar to that in a two-level inverter. In the over-modulation region in multi-level inverters, there is the presence of lower order harmonics such as 5th and 7th in the output voltage, and this can be avoided by using a voltage space vector scheme with more than six polygonal voltage space vectors such as 12, 18, 24 etc. These polygonal voltage space vectors can be generated by using multi-level inverter topologies, by cascading two-level inverter structures with asymmetric DC-links. This thesis deals with the development of 12-sided and 18-sided polygonal voltage space vector schemes for induction motor drives. With the 12-sided polygonal structure, all the 5th and 7th harmonic orders and 6n±1, n=1, 3, 5.. are absent throughout the modulation range, and in the 18-sided voltage space vector scheme, 5th, 7th, 11th and 13th harmonics are absent throughout the modulation range. With the absence of the low order frequencies in the proposed polygonal space vector structures, high frequency PWM schemes are not needed for voltage control. This is an advantage over conventional schemes. Also, due to the absence of lower order harmonics throughout the modulation range, special compensated synchronous reference frame PI controllers are not needed in current controlled vector control schemes in over-modulation. In this thesis a method is proposed for generating 12-sided polygonal voltage space vectors for an induction motor fed from one side. A cascaded combination of three two-level inverters is used with asymmetrical DC-links. A simple space vector PWM scheme based only on the sampled reference phase amplitudes are used for the inverter output voltage control. The reference space vector is sampled at different sampling rates depending on the frequency of operation. The number of samples in a sector is chosen to keep the overall switching frequency around 1kHz, in order to minimize switching losses. The voltage space vectors that make up the two sides of the sector in which the reference vector lies, are time averaged using volt-sec balance, to result in the reference vector. In the proposed 12-sided PWM scheme all the harmonics of the order 6n±1, n=1, 3, 5... are eliminated from the phase voltage, throughout the modulation range. In multi-level inverters steps are taken to eliminate common-mode voltage. Common-mode voltage is defined as one third of the sum of the three pole voltages of the inverter for a three phase system. Bearings are found to fail prematurely in drives with fast rising voltage pulses and high frequency switching. The alternating common-mode voltage generated by the PWM inverter contributes to capacitive couplings from stator body to rotor body. This generates motor shaft voltages causing bearing currents to flow from rotor to stator body and then to the ground. There can be a flashover between the bearing races. Also a phenomenon termed EDM (Electro-discharge machining) effect occurs and may damage the bearings. Common-mode voltage has to be eliminated in order to overcome these effects. In multi-level inverters redundancy of space vector locations is used to eliminate common-mode voltages. In the present thesis a 12-sided polygonal voltage space vector based inverter with an open-end winding induction motor is proposed, in which the common-mode voltage variation at the poles of the inverter is eliminated. In this scheme, there is a three-level inverter on each side of the open-end winding of the induction motor. The three-level inverter is made by cascading two, two-level inverters with unequal DC-link voltages. Appropriate space vectors are selected from opposite sides such that the sum of the pole voltages on each side is a constant. Also during the PWM operation when the zero vector is applied, identical voltage levels are used on both sides of the open-end windings, in order to make the phase voltages zero, while the common-mode voltage is kept constant. This way, common-mode voltage variations are eliminated throughout the modulation range by appropriately selecting the voltage vectors from opposite ends. In this method all the harmonics of 6n±1, n=1, 3, 5.. and triplen orders are eliminated. In the 12-sided polygonal voltage space vector methods, the 11th and 13th harmonics though attenuated are not eliminated. In the 18-sided polygonal voltage space vector method the 11th and 13th harmonics are eliminated along with the 5th and 7th harmonics. This scheme consists of an open-end winding induction motor fed from one side by a two-level inverter and the other side by a three-level inverter comprising of two cascaded two-level inverters. Asymmetric DC-links of a particular ratio are present. The 12-sided and 18-sided polygonal voltage space vector methods have been first simulated using SIMULINK and then verified experimentally on a 1.5kW induction motor drive. In the simulation as well as the experimental setup the starting point is the generation of the three reference voltages v, vB and vC . A method for determining the sector in which the reference vector lies by comparing the values of the scaled sampled instantaneous reference voltages is proposed. For the reference vector lying in a sector between the two active vectors, the first vector is to be kept on for T1 duration and the second vector for T2 duration. These timing durations can be found from the derived formula, using the sampled instantaneous values of the reference voltages and the sector information. From the pulse widths and the sector number, the voltage level at which a phase in the inverter has to be maintained is uniquely determined from look-up tables. Thus, once the pole voltages are determined the phase voltages can be easily determined for simulation studies. By using a suitable induction motor model in the simulation, the effect of the PWM scheme on the motor current can be easily obtained. The simulation studies are experimentally verified on a 1.5kW open-end winding induction motor drive. A V/f control scheme is used for the study of the drive scheme for different speeds of operation. A DSP (TMS320LF2407A) is used for generating the PWM signals for variable speed operation. The 12-sided polygonal voltage space vector scheme with the motor fed from a single side has a simple power bus structure and it is also observed that the pole voltage is clamped to zero for 30% of the time duration of one cycle of operation. This will increase the overall efficiency. The proposed scheme eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range. The 12-sided polygonal voltage space vector scheme with common-mode elimination requires the open-end winding configuration of the induction motor. Two asymmetrical DC-links are required which are common to both sides. The leg of the high voltage inverter is seen to be switched only for 50% duration in a cycle of operation. This will also reduce switching losses considerably. The proposed scheme not only eliminates all harmonics of the order 6n±1, n=1, 3, 5…for the complete modulation range, but also maintains the common-mode voltage on both sides constant. The common-mode voltage variation is eliminated. This eliminates bearing currents and shaft voltages which can damage the motor bearings. In the 18-sided polygonal voltage space vector based inverter, the 11th and 13th harmonics are eliminated along with the 5th and 7th. Here also an open-end winding induction motor is used, with a two-level inverter on one side and a three-level inverter on the other side. A pole of the two-level inverter is at clamped to zero voltage for 50% of the time and a pole of the three-level inverter is clamped to zero for 30% of the time for one cycle of operation. The 18-sided polygonal voltage space vectors show the highest maximum peak fundamental voltage in the 18-step mode of 0.663Vdc compared to 0.658Vdc in the 12-step mode of the 12-sided polygonal voltage space vector scheme and 0.637Vdc in the six-step mode of a two-level inverter or conventional multi-level inverter (where Vdc is the radius of the space vector polygon). Though the schemes proposed are verified on a low power laboratory prototype, the principle and the control algorithm development are general in nature and can be easily extended to induction motor drives for high power applications.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

In high-power electric drives, multilevel inverters are generally deployed to address issues such as electromagnetic interference, switch voltage stress and harmonic distortion. The switching frequency of the inverter is always kept low, of the order of 1KHz or even less to reduce switching losses and synchronous pulse width modulation (PWM) is used to avoid the problem of sub-harmonics and beat frequencies. This is particularly important if the switching frequency is very low. The synchronous PWM is getting popularity as its realization is very easy with digital controllers compared to analog controllers. Neutral-point-clamped (NPC) inverters, cascaded H-bridge, and flying-capacitor multilevel inverters are some of the popular schemes used for high-power applications. Hybrids of these multilevel inverters have also been proposed recently to take advantage of the basic configurations. Multilevel inverters can also be realized by feeding the induction motor from both ends (open-end winding) using conventional inverter structures. For controlling the output voltage of these inverters, various PWM techniques are used. Chapter-1 of this thesis provides an over view of the various multilevel inverter schemes preceded by a discussion on basic two-level VSI topology. The inverters used in motor drive applications have to be operated in over-modulation range in order to extract the maximum fundamental output voltage that is possible from the dc-link. Operation in this high modulation range is required to meet temporary overloads or to have maximum power operation in the high speed range (flux weakened region). This, however, introduces a substantial amount of low order harmonics in the Motor phase voltages. Due to these low-order harmonic frequencies, the dynamic performance of the drive is lost and the current control schemes are severely affected especially due to 5th and 7th harmonic components. Further, due to these low-order harmonics and non-linear PWM operation in over-modulation region, frequent over-current fault conditions occur and reliability of the drive is jeopardized. The twelve sided-polygonal space vector diagram (dodecagonal space vectors) can be used to overcome the problem of low order 5th and 7th harmonics and to give more range for linear modulation while keeping the switching frequency at a minimum compared to conventional hexagonal space vector based inverters. Thus, the dodecagonal space-vector switching can be viewed as an engineering compromise between low switching frequency and quality load current waveform. Most of the previous works of dodecagonal space-vector generation schemes are based on NPC inverters. However, sophisticated charge control schemes are required in NPC inverters to deal with the neutral-point voltage fluctuation and the neutral-point voltage shifting issues. The losses in the clamping diodes are another major concern. In the second chapter, a multilevel dodecagonal space-vector generation scheme based on flying capacitor topology, utilizing an open end winding induction motor is presented. The neutral point charge-balancing problem reported in the previous works is not present in this scheme, the clamping diodes are eliminated and the number of power supplies required has been reduced. The capacitors have inherent charge balancing capability, and the charge control is done once in every switching cycle, which gives tight voltage control for the capacitors. For the speed control of induction motors, the space-vector PWM scheme is more advantageous than the sine-triangle PWM as it gives a more linear range of operation and improved harmonic performance. One major disadvantage with the conventional space-vector PWM is that the trigonometric operations demand formidable computational efforts and look-up tables. Carrier based, common-mode injected PWM schemes have been proposed to simplify the PWM process. However, the freedom of selecting the PWM switching sequences is limited here. Another way of obtaining SVPWM is using the reference voltage samples and the nearest vector information to switch appropriate devices for proper time intervals, realizing the reference vector in an average sense. In-formation regarding the sector and nearest vectors can be easily obtained by comparing the instantaneous amplitudes of the reference voltages. This PWM approach is pro-posed for the speed control of the motor in this thesis. The trigonometric operations and the requirement of large look-up tables in the conventional SVPWM are avoided in this method. It has the additional advantage that the switching sequences can be decided at will, which is helpful in reducing further, the harmonic distortion in certain frequency ranges. In this way, this method tries to combine the advantages of vector based methods (conventional SVPWM) and scalar methods (carrier-based methods). The open-end winding schemes allowed the required phase voltage levels to be generated quite easily by feeding from both ends of the windings. Thus, most of the multilevel inverters based on dodecagonal space-vector structures relied on induction motors with open-end windings. The main disadvantage of open-end winding induction motor is that six wires are to be run from the inverter to the motor, which may be unacceptable in certain applications. Apart from the inconvenience of laying six wires, the voltage reflections in the wires can lead to over voltages at the motor terminals, causing insulation failures. Where as the topology presented in chapter-2 of this thesis uses open-end winding motor with flying-capacitor inverters for the generation of dodecagonal space-vectors, the topology presented in chapter-3 utilizes a cascade connection of flying-capacitors and floating H-bridge cells to generate the same set of voltage space-vectors, thus allowing any standard induction motor as the load. Of the methods used for the speed control of induction motors, namely sine-triangle PWM and space vector PWM, the latter that provides extra modulation range is naturally preferred. It is a well-understood fact that the way in which the PWM switching sequences are applied has a significant influence on the harmonic performance of the drive. However, this topic has not been addressed properly for dodecagonal voltage space-vector based multilevel inverter drives. In chapter-4 of the thesis, this aspect is taken into ac-count and the notion of “harmonic flux trajectories” and “stator flux ripple” are used to analyze the harmonic performance of the various PWM switching schemes. Although the PWM method used in this study is similar to that in chapter-2, the modification in the PWM switching sequence in the PWM algorithm yields significant improvements in harmonic performance. The proposed topologies and PWM schemes are extensively simulated and experimentally verified. The control scheme was implemented using a DSP processor running at a clock frequency 150MHz and a four-pole, 3.7kW, 50Hz, 415V three-phase induction motor was used as the load. Since the PWM ports are limited in a DSP, a field-programmable gate array (FPGA) was used to decode the PWM signals from the DSP to generate timing information required for PWM sequencing for all the power devices. The same FPGA was used to generate the dead-time signals for the power devices also.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.

For medium and high-voltage drive applications, multilevel inverters are very popular. It is due to their superior performance compared to 2-level inverters such as reduced harmonic content in the output voltage and current, lower common mode voltage and dv=dt, and lesser voltage stress on power switches. The popular circuit topologies for multilevel inverters are neutral point clamped, cascaded H-bridge and flying capacitor based circuits. There exist different combinations of these basic topologies to realize multilevel inverters with modularity, better fault tolerance, and reliability. Due to these advantages, multilevel converters are getting good acceptance from the industry, and researchers all over the world are continuously trying to improve the performance of these converters. To meet such demands, three multilevel inverter topologies are proposed in this thesis. These topologies can be used for high-power induction motor drives, and the concepts presented are also applicable for synchronous motor drives, grid-connected inverters, etc. To get nearly sinusoidal phase current waveforms, the switching frequency of the conventional inverter has to be increased. It will lead to higher switching losses and electromagnetic interference. The problem with lower switching frequency is the intro- duction of low order harmonics in phase currents and undesirable torque ripple in the motor. The 5th and 7th harmonics are dominant for hexagonal voltage space-vector based low frequency switching, and it is possible to eliminate these harmonics by dodecagonal switching. Further improvement in the waveform quality is possible by octadecagonal voltage space-vectors. In this case, the complete elimination of 11th and 13th harmonic is possible for the entire modulation range. The concepts of dodecagonal and octadecagonal voltage space-vectors are used in the proposed inverter topologies. The first topology proposed in this thesis consists of cascaded connection of two H-bridge cells. The two cells are fed from unequal DC voltage sources having a ratio of 1 : 0:366, and this inverter can produce six concentric dodecagonal voltage space- vectors. This ratio of voltages can be obtained easily from a combination of star-delta transformers, since 1 : 0:366 = ( p 3 + 1) : 1. The cascaded connection of two H-bridge cells can generate nine asymmetric pole voltage levels, and the combined three-phase inverter can produce 729 voltage space-vectors (9 9 9). From this large number of combinations, only certain voltage space-vectors are selected, which forms dodecagonal pattern. In the case of conventional multilevel inverters, the voltage space-vector diagram consists of equilateral triangles of equal size, but for the proposed inverter, the triangular regions are isosceles and are having different sizes. By properly placing the voltage space-vectors in a sampling period, it is possible to achieve lower switching frequency for the individual cells, with substantial improvement in the harmonic spectrum of the output voltage. During the experimental veri cation, the motor is operated at di erent speeds using open loop v=f control method. The samples taken are always synchronised with the start of the sector to get synchronised PWM. The number of samples per sector is decreased with increase in the fundamental frequency to limit the switching frequency. Even though many topologies are available in literature, the most preferred topology for drives application such as traction drives is the 3-level NPC structure. This implies that the industry is still looking for viable alternatives to construct multilevel inverter topologies based on available power circuits. The second work focuses on the development of a multilevel inverter for variable speed medium-voltage drive application with dodecagonal voltage space-vectors, using lesser number of switches and power sources compared to earlier implementations. It can generate three concentric 12-sided polygonal voltage space-vectors and it is based on commonly available 2-level and 3-level inverters. A simple PWM timing computation method based on the hexagonal space-vector PWM is developed. The sampled values of the three-phase reference voltages are initially converted to the timings of a two-level inverter. These timings are mapped to the dodecagonal timings using a change of basis transformation. The voltage space- vector diagram of the proposed drive consists of sixty isosceles triangular regions, and the dodecagonal timings calculated are converted to the timings of the inner triangles. A searching algorithm is used to identify the triangular region in which the reference vector is located. A front-end recti er that may be easily implemented using standard star-delta transformers is also developed, to provide near-unity power factor. To test the performance of the inverter drive, an open-loop v=f control is used on a three-phase induction motor under no-load condition. The harmonic spectra of the phase voltages were computed in order to analyse the harmonic distortion of the waveforms. The carrier frequency was kept around 1.2 KHz for the entire range of operation. If the switching frequency is decreased, the conventional hexagonal space-vector based switching introduce signifi cant 5th, 7th, 11th and 13th harmonics in the phase currents. Out of these dominant harmonics, the 5th and 7th harmonics can be completely suppressed using dodecagonal voltage space-vector based switching as observed in the first and second work. It is also possible to remove the 11th and the 13th harmonics by using voltage space-vectors with 18 sides. The last topology is based on multilevel octadecagonal (18-sided polygon) voltage space-vectors, and it has better harmonic performance than the previously mentioned topologies. Here, a multilevel inverter system capable of producing three octadecagonal voltage space-vectors is proposed for the fi rst time, along with a simple timing calculation method. The conventional three-level inverters are only required to construct the proposed drive. Four asymmetric power supply voltages with 0:3054Vdc, 0:3473Vdc, 0:2266Vdc and 0:1207Vdc are required for the operation of the drive, and it is the main drawback of the circuit. Generally front-end isolation transformer is essential for high-power drives and these asymmetric voltages can be easily obtained from the multiple windings of the isolation transformer. The total harmonic distortion of the phase current is improved due to the 18-sided voltage space-vector switching. The ratio of the radius of the largest polygon and its inscribing circle is cos10 = 0:985. This ratio in the case of hexagonal voltage space-vector modulation is cos30 = 0:866, which means that the range of the linear modulation for the proposed scheme is signifi cantly higher. The drive is designed for open-end winding induction motors and it has better fault tolerance. It any of the inverter fails, it can be easily bypassed and the drive will be still functional with reduced speed. Open loop v=f control and rotor flux oriented vector control schemes were used during the experimental verifi cation. TMS320F2812 DSP platform was used to execute the control code for the proposed drive schemes. For the entire range of operation, the carrier was synchronized with the fundamental. For the synchronization, the sampling period is varied dynamically so that the number of samples in a triangular region is fi xed, keeping the switching frequency around 1.2 KHz. The average execution time for the v=f code was found to be 20 S, where as for vector control it took nearly 100 S. The PWM terminals and I/O lines of the DSP is used to output the timings and the triangle number respectively. To convert the triangle number and the timings to IGBT gate drive logic, an FPGA (XC3S200) was used. A constant dead-time of 1.5 S is also implemented inside the FPGA. Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. Hall-effect sensors were used to measure the phase currents and DC bus voltages. An incremental shaft position encoder with 2500 pulse per revolution is also connected to the motor shaft, to measure the angular velocity. 1200 V, 75 A IGBT half-bridge module is used to realize the switches. The concepts were initially simulated and experimentally verifi ed using laboratory prototypes at low power. While these concepts maybe easily extended to higher power levels by using suitably rated devices, the control techniques presented shall still remain applicable.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.

MU LT I L E V E L inverters are becoming the preferred choice for medium voltage high power applications. Multilevel inverters have a number of inherent advantages over conventional two level inverters. The output voltage has multiple steps or levels, resulting in reduced dV/dt, which leads to lower electromagnetic interference, making it easier to meet electromagnetic compatibility (EMC) regulations. Multilevel inverters have a much lower effective switching frequency, which leads to a reduction in switching losses. The output voltage of multilevel inverters has a much lower harmonic content. In applications such as power conversion or grid-connection, filters need to be much smaller, or can be eliminated. In motor drive applications, the low harmonic content results in smoother, ripple-free shaft torque. The neutral-point clamped (NPC), cascaded H-bridge (CHB) and flying capacitor (FC) topologies were among the earliest multilevel topologies. NPC topologies require additional clamping diodes to clamp the output to the DC bus midpoint. CHB topologies use a number of isolated DC suplies to generate multilevel output. FC topologies work with a single DC link but use additional floating capacitors. Since then, a number derivatives and improvements to these topologies have been proposed. Topologies with low switch counts are desirable because of the corresponding reduction in system size and cost. A low total component count is also desirable since it results in better reliability. Induction motors in high power applications are often operated in the open-end configuration. Here, the start terminals of the motor phase windings are connected to one three phase inverter, while the end terminals are connected to a second three-phase inverter. The two inverters are typically powered by isolated supplies to prevent the flow of common mode currents through the motor. The open end configuration has a number of advantages It can be used with nearly all high power motors with no need for electrical or mechanical modification, since all six winding terminal are available externally. The two inverters driving the open-end motor are effectively cascaded. As a result, two inverters of lower voltage and power rating can replace a single inverter with higher voltage and power rating. In addition, if one of the inverter fails, it can be bypassed and the system can be operated at reduced power. In many applications such as heating, ventilation and air conditioning (HVAC), the load power is proportional to the cube of the shaft speed, so a 50% reduction in power translates to only 20% reduction in speed, thereby improving overall system reliability. The cascading of inverters also enables multilevel operation, which is exploited for the topologies proposed in this thesis. In the open-end configuration it is important to ensure that both the DC supplies deliver power to the load. Otherwise, power can circulate through the motor windings. In addition, if the two inverters are powered by rectifier supplies, the DC bus of one inverter can charge uncontrollably, resulting in distortion of phase voltages and currents. If DC bus overcharging continues unchecked the DC bus voltage can even exceed the system rating, resulting in permanent damage. This thesis proposes two novel topologies for open-end induction motor drives with low switch counts. Both topologies are powered by two unequal, isolated DC sources having DC voltages in a 3:1 ratio. Multiple levels in the output voltage are obtained using a number of floating capacitors in each phase. Modulation and control schemes are also proposed for both topologies to ensure that DC bus overcharging never occurs, while all the capacitor voltages are kept balanced at their nominal values. The first of these two topologies is a nine level inverter for open end induction motor drives. It consists of two three-level flying capacitor inverters connected to the induction motor in the open end configuration. The two inverters are powered by DC sources of voltage 6VDC/8 and 2VDC/8, which generates an effective phase voltage having nine levels in steps of VDC/8. This topology has only eight switches and two floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 217 space vector locations. A space-vector based formulation is used to determine the pole voltage of the inverter such that DC bus over charging is prevented. In addition, selection of switching states is used to balance the voltages of all floating capacitors. This scheme allows the floating capacitors to be charged up during system startup, thereby eliminating the need for separate pre-charging circuitry. A level-shifted carrier PWM based modulation scheme has been developed, which can be used with both scalar and vector control schemes. The gating signal for switches turning on must be delayed by a small amount (to allow the complementary switch to turn of), failing which current shoot through can occur. This delay is called dead time, during which gate signals to both complementary devices are turned of. Under certain conditions in the flying capacitor topology, the pole voltage can contain large undesirable transients during the dead time which result in phase current distortion, and electromagnetic noise. A novel scheme to eliminate this problem is proposed using a digital state machine approach. The switching state for each subsequent switching interval is determined based on the present switching state such that the pole voltage does not contain a transient, without affecting the phase voltage of the inverter, and irrespective of the current magnitude or direction. The state machine was implemented using an FPGA, and required an additional computation time of just 20ns, which is much smaller than the inverter dead time duration of typically 2.5µs. The second novel topology proposed in this thesis is a seventeen level inverter for an open end induction motor drive. Here, one three-level inverter and one seven-level inverter are connected to the two ends of the induction machine. The three-level inverter is a flying capacitor inverter. The seven-level inverter is a hybrid topology – it consists of an H-bridge cascaded to each phase of a three level flying capacitor inverter. This scheme is also powered by two isolated DC sources in 3:1 ratio with magnitudes 12VDC/16 and 4VDC/16. The effective phase voltage has seventeen levels in steps of VDC/16. This topology has a total of twelve switches and three floating capacitors per phase. The space vector structure for this topology is hexagonal, and has 817 space-vector locations. Space vector analysis was used to determine the pole voltages, and the switching states such that DC bus overcharging is prevented while also balancing the voltages of the floating capacitors. A non-iterative algorithm was developed for determining the switching states, suitable for implementation in digital logic using an FPGA. The scheme is able to charge the all capacitors at startup as well, eliminating the need for separate pre-charging circuits. Hardware prototypes were built for both the topologies described above for experimental verification, and used to drive a three phase 50Hz, 1.5kW, four pole induction motor in V/f control mode. The inverters topologies were built using 1200V, 75A IGBT half-bridge modules (Semikron SKM75GB12T4) with hybrid opto-isolated gate drivers (Mitsubishi M57962). Three phase rectifiers were used to create the asymmetric DC supplies Hall effect sensors were used to sense the DC link and floating capacitor voltages and phase currents (LEM LV20P voltage sensors and LA55 current sensors). Signal conditioning circuitry was built using discrete components. The PWM signals and V/f controller were implemented using a digital signal processor (Texas Instruments TMS320F28335). Synchronous PWM with was used to eliminate sub-harmonics from the phase voltage, and to ensure three-phase and half-wave symmetry. The internal ADC of the DSP was used for sampling all voltages and currents. The remaining digital logic for switch state selection was implemented on a FPGA (Xilinx Spartan3 XC3S200). Dead time functionality was also implemented within the FPGA, eliminating the need for separate dead time hardware. Both topologies were first tested for steady state operation over the full modulation range, and the pole voltages, phase voltages and phase currents were recorded. System startup, and the ability of the controllers to balance all the capacitors at startup was tested next. The capacitor voltages were also observed during sudden loading, by quickly accelerating the motor. Finally, the phenomenon of DC bus overcharging was also demonstrated. These results demonstrate the suitability of the proposed topology for a number of applications, including industrial drives, alternate energy systems, power conversion and electric traction.