Academic literature on the topic 'Polygonal Voltage Space Vector Structures'

Switching converters are used in electric drive applications to produce variable voltage, variable frequency supply which generates harmful large dv/dt and high-frequency common mode voltages (CMV). Multilevel inverters generate lower CMV as compared to conventional two-level inverters. This paper presents simple carrier-based technique to control the common mode voltages in multilevel inverters using different structures of sine-triangle comparison method such as phase disposition (PD), phase opposition disposition (POD) by adding common mode voltage offset signal to actual reference voltage signal. This paper also presented the method to optimize the magnitude of this offset signal to reduce CMV and total harmonic distortion in inverter output voltage. The presented techniques give comparable performance as obtained in complex space vector-based control strategy, in terms of number of commutations, magnitude, and rate of change of CMV and harmonic profile of inverter output voltage. Simulation and experimental results presented confirm the effectiveness of the proposed techniques to control the common mode voltages.

Abstract The mathematical model of the five-phase squirrel-cage induction motor and the system of the dual five-phase voltage source inverter have been presented. The control methods and control systems of the field-oriented control of the five-phase induction motor with an open-end stator winding are described. The structures of the direct fieldoriented control system (DFOC) and the Indirect Field-oriented control system (IFOC) with PI controllers in outer and inner control loops are analyzed. A method of space vector modulation used to control the system of the dual five-phase voltage source inverter has been discussed. The results of simulation studies of the field-oriented control methods are presented. Comparative analysis of the simulation results was carried out.

Induction motors are mainly powered by two-level inverters in low-voltage, low-power drive applications. For medium and high voltage applications, a conventional two-level inverter needs high voltage rated switches, operates at high switching frequency to get better voltage quality, and produces high dv/dt at switching instants. While operating at six-step mode for full speed operation, a conventional two-level inverter produces low-order harmonics, mainly 5th, 7th, 11th, 13th, 17th, 19th, and so on. These lower-order harmonics produce torque pulsations, which can damage the motor and affects produced torque and power. Conventionally these low order harmonics are suppressed or eliminated by employing bulky and costly passive filters, which degrades dynamic performance of the motor. Another technique based on modified pulse width modulation is selective harmonic elimination, which suppresses fundamental voltage along with harmonics resulting in underutilization of the DC-link voltage. Multi-level inverters are widely employed in high power and high voltage motor drive applications due to lower harmonic distortion and lower dv/dt in the phase voltage. However, multi-level inverters produce hexagonal space vector structure (SVS) and introduce lower-order harmonics in phase voltage during operat= ion in overmodulation region. Also, as the levels increases, number of switches, number of capacitors, diodes and isolated power supplies also increases.       Polygonal SVS is a method for eliminating lower-order harmonics in full operating region. This thesis addresses the above-mentioned issues by generating a two-level and multi-level 24-sided polygonal SVS with real active vectors instead of switched average vectors. Each active vector is a real vector in contrast to switched average vectors in literature. The generation of real 24-sided vectors minimizes switching losses and improves the quality of phase voltage compared to switched averaged vectors technique. 24-sided polygonal SVS scheme eliminates lower order harmonics up to 19th order from motor phase voltage throughout the modulation range. The first work presents a method of generating 24-sided polygonal SVS comprised of 24 real active vectors and a zero vector. In the second work, a multilevel 24-sided polygonal SVS is presented, which suppresses higher order harmonics along with elimination of lower order harmonics from motor phase voltage. In the third work, an inverter circuit to generate a thirteen-level 24-sided polygonal SVS comprised of 288 real active vectors and a zero vector is presented. The SVS generated in third work is denser than the scheme pr= esented in the second work, which further improves output voltage quality, without altering the power circuit topology. In all above three works, vector timing computation is required, and reference vector is realized by time averaging nearest three vectors. To ensure the elimination of timing computation, a 24-sided polygon must be available for reference vector of any magnitude. In the fourth work, a variable speed induction motor drive to generate 24-stepped voltage waveform throughout modulation range is presented.       Inverter circuit is realized using primary and secondary inverters feeding an open-end winding induction motor. Primary and secondary inverters are implemented by cascading two-level inverters. DC sources for both inverters are realized using a simple star-delta transformer combination. The presented concepts are verified with laboratory prototypes. The presented work is suitable for medium voltage and medium power induction motor drive applications.
PMRF

A conventional 2-level inverter is the most prevalent DC-AC converter used to drive an induction motor. A conventional 2-level inverter produces a hexagonal voltage space vector structure. To extract maximum voltage from a DC-link, the inverter has to operate in overmodulation region. During this region of operation, a hexagonal space vector structure generates undesirable lower order harmonics, which in turn produce torque pulsations in the motor shaft. To avoid this problem, the inverter can be operated in the linear modulation region of the space vector structure at a high switching frequency. Always to operate the inverter in linear modulation region, the inverter has to be supplied with a DC-link of higher voltage and hence the DC source is underutilized. In addition, higher frequency switching at linear modulation is not an accepted solution for a high power drive because of the high power dissipation in the switches due to the switching loss. Methods like passive filtering technique and selective harmonic elimination techniques are adopted to filter and eliminate the harmonics while operating at lower switching frequencies. These techniques limit the maximum fundamental extracted from the DC-link. One other elegant method to eliminate the lower order harmonics and to extract the maximum fundamental voltage from the DC-link is by modulating the inverter using higher sided polygonal structures. First part of the work proposes a novel polygonal voltage space vector structure having 30 sides using a single DC-link. The space vector structure eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. The topology consists of a DC-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is cancelled by the secondary inverter which acts as a switched capacitive filter. Further, second part of the work is obtaining, a multilevel inverter scheme generating a 30-sided space vector structure with congruent triangles. The scheme being multilevel reduces the dv/dt and further reduces the harmonic content in the output voltage. The proposed scheme is implemented using a single DC-link on an open end induction motor. The open end induction motor is fed with primary inverter from one end and secondary inverter from the other end. Primary inverter is fed from an active DC-link and supplies all the required active power for the scheme. Secondary inverter is a capacitor fed inverter which acts as the switched capacitive filter. In third research work, the generation of an even denser 30-sided multilevel space vector structure using a single DC-link for an open end induction motor drive is presented. The resultant space vector structure has 15-concentric 30-sided polygons. The proposed scheme also eliminates lower order harmonics till 25th order from motor phase voltage throughout the modulation range. The dv/dt stress in the phase voltage applied to the motor will also be highly reduced owing to the multilevel structure. The topology consists of an active DC-link fed 3-level primary inverter and a capacitor fed 5-level secondary inverter connected to either end of an open end induction motor. In fourth research work, a very high resolution multilevel voltage space vector structure having 117-concentric 30-sided polygons of different radii is proposed. In this work, non-aligned 30-sided polygons i.e. regular 30-sided polygons which are not symmetric with respect to alpha and beta axis are also considered for inverter operation, for the first time. The denseness of space vector structure allows to use nearest level switching, enabling further reduction of switching loss in the system. The feasibility of all the proposed scheme is proved by experimental results during open loop v/f and field oriented control. All the schemes used in this thesis requires only a single DC-link for its operation, which enables easy four quadrant operation by using a single active front end converter. All the above mentioned features make the schemes best suited for high power medium voltage applications.

Multilevel voltage source inverter transformed conversion of DC to AC for medium to high power application. With increasing electric power demand, the multilevel converter allows high power density converters for medium to high voltage high power applications. Motor drives, high voltage DC (HVDC) transmission, renewable energy systems, and electric traction are some applications that employ multilevel converters. Conventional two-level inverters need to switch between full DC link to ground potential and require voltage blocking equal to the supply voltage. In addition, 2-level inverters require harmonic filters for filtering harmonics in the output voltage. The filters are costly and bulky and dissipate power, decreasing the system's overall efficiency. Multilevel inverters overcome the disadvantages of conventional inverters by switching intermediate voltage levels between DC link voltage and zero voltage. The higher resolution in the inverter voltage levels reduces the output voltage error compared to the required sinusoidal waveform and improves the harmonic quality. The converter's switching frequency is reduced to minimise the switching losses, thereby increasing the system efficiency. The dv/dt of the multilevel converter is less, which reduces the switching stress on the device and brings down the conductive and radiative emissions. Multilevel inverters can also utilise time-tested low voltage semiconductor technologies to build the converters, improving the system's reliability and easy component availability. Basic and most popular multilevel topologies are cascaded H-bridge inverter, neutral point clamped inverter and flying capacitor inverter. Another class of hybrid multilevel inverters is obtained by cascading basic multilevel inverter cells, which can generate high-quality output voltage waveforms with greater voltage levels. Hybrid multilevel inverters for induction motor drives are also obtained by configuring the motor as an open-end and feeding on both sides of the induction motor. The conventional voltage source inverter generates a hexagonal space vector structure. The inverters are required to operate in the overmodulation region for maximum utilisation of the available DC-link. Operating in the overmodulation region generates lower-order harmonics in the phase voltage and causes several undesirable problems in the systems. The linear modulation range of the hexagonal space vector structure is 90.7\% of the peak fundamental voltage for the maximum modulation index. Induction motor drives using hexagonal space vector structure suffer from torque pulsations on the motor shaft, which could even lead to total system failure. The harmonics in the system affect the dynamic performance of closed-loop current control of the motor and generate significant power loss. Various techniques have been proposed in the literature to suppress the problems caused by harmonics. Increasing the switching frequency of the converter is one such method to reduce the effect of harmonics by having lowest harmonics only at switching frequency, which is easy to filter out. High switching frequency is not a practical solution for medium and high power applications due to the high magnitude of switching loss in the device, resulting in worse electromagnetic compatibility performance. Also, the increased switching frequency is only effective for operation within the linear modulation range. Another conventional method for harmonic suppression is using passive filters. But, for variable frequency operation like in induction motor drives, filtering out lower order harmonics requires bulky filters, which increases the system's size and cost and adds to the resistive loss. Moreover, the addition of the filter to the system affects the system's dynamic performance and reduces the fundamental voltage at the output. Selective harmonic elimination (SHE) is a special pulse width modulation (PWM) to suppress the harmonics by introducing fixed notches in the output. SHE operates with a low switching frequency but suffers from low DC-link utilisation due to the introduction of the notches. Also, the method becomes complex for the elimination of multiple harmonics and has poor dynamic performance. An elegant method to eliminate harmonics in the output voltage is to realise space vector structures with inherent harmonic elimination. Polygonal space vector structure with a higher number of sides than a hexagon, such as 12-sided polygon and 18-sided polygon, eliminates lower order harmonics. 12-sided polygon eliminates the lower order harmonics of the order 5th and 7th and has harmonics only from 11th and 13th. 18-sided polygon eliminates the harmonics up to the 13th order and only harmonics from the 17th and 19th order. The polygons with a higher number of sides are closer to a circle geometrically and have an increased linear modulation region than hexagon (6-sided) for a given DC-link voltage. Generating higher fundamental voltage inverter operations compare to hexagon for the same DC-link voltage leads to better DC-link utilisation. Schemes generating multilevel polygonal space vector structures have evolved to incorporate the advantages of multilevel converters. There are several challenges to generating multilevel polygonal structures, including the requirement of large capacitance, the complexity of PWM techniques etc. Power circuit topologies with a single DC source to generate polygonal space vector structures have evolved but suffer from the requirement of large capacitor size. This thesis proposes a capacitor size reduction methodology and a simple PWM strategy for multilevel polygonal space vector structure. Chapter 1 introduces various harmonic suppression schemes and topologies for generating multilevel inverter polygonal space vector structures. A multilevel 12-sided polygonal voltage space vector generation scheme for variable-speed drive applications with a single DC-link operation requires an enormous capacitance value for cascaded H-bridge (CHB) filters when operated at lower speeds. The multilevel 12-sided polygonal structure is obtained in existing schemes by cascading a flying capacitor inverter with a CHB. Chapter 2 proposes a new scheme to minimise the capacitance requirement for full-speed operation by creating vector redundancies using modular and equal voltage CHBs. Also, an algorithm has been developed to optimise the selection of vector redundancies among the CHBs to minimise the floating capacitors' voltage ripple. The algorithm computes the optimal vector redundancies by considering the instantaneous capacitor voltages and the phase currents. Chapter 3 proposes a simple unified pulse width modulation (PWM) strategy for multilevel polygonal space vector structure (SVS) partitioned into symmetric triangles for the first time. The algorithm obtains the PWM timing durations for a 2-level polygonal voltage SVS in a sampling duration using only the sampled reference values of voltages. The PWM timings obtained for a 2-level structure are then mapped to multilevel SVS. The matrices used for this mapping remain the same irrespective of the sides of the polygon. The smallest triangle encompassing the reference voltage vector in the multilevel structure is identified using this algorithm along with the PWM timings for which the voltage vectors forming the vertices of this smallest triangle are applied. The algorithm involves only operations like addition, multiplication, and logical comparisons. A general implementation scheme for an N-level, p-sided polygon is presented in this paper. A novel 5-level 18-sided SVS is also proposed in this paper. The scheme incorporates the advantages of harmonic elimination due to an 18-sided polygon and the inherent advantages of a multilevel inverter. A multilevel variable speed induction motor drive scheme using an 18-sided polygon with a very dense voltage space vector structure (SVS) is proposed in chapter 4. The proposed SVS consists of 101 concentric layers of 18-sided polygons. The 18-sided polygonal SVS eliminates lower order harmonics 5th, 7th, 11th and 13th orders from the output voltage for the entire modulation range. The linear modulation range of the 18-sided polygon is extended to 99\% of the base speed compared to 90.7\% of the hexagonal SVS. It also has higher peak phase fundamental voltage at the output and better DC-link utilisation than conventional inverters. The SVS is generated by superposition of 5-level main hexagonal SVS of radius VDC and 5-level auxiliary hexagonal SVS of radius 0.379VDC. The dense voltage space vector structure facilitates the generation of reference by nearest vector switching in the 18-sided polygon, reducing the semiconductor devices' switching. The vector switched to realise the reference voltage in a sampling period is only one polygonal vector throughout the modulation range, drastically reducing switching loss and electromagnetic emissions. Simulation and experimental results of the proposed drive scheme are presented to prove the effectiveness of the drive scheme. The inverter is modelled and extensively simulated using a MATLAB-SIMULINK environment. An experimental setup using inverter modules is set up to test the inverter. The semiconductor switches used are SKM75GB12T4 and IRF260N. Gate drive circuits based on opto-isolated IC M5792L from Mitsubishi and capacitive isolated IC ISO5451 from Texas Instruments are used. TMS320F28335 DSP from Texas Instruments and XC2S200 FPGA from Xilinx were used as the controllers for realising the hardware prototype. A 3-phase open-end induction motor of ratings 15 kW, 415 V, and 4-pole is used for testing the proposed drive schemes.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Multilevel converters are finding increased attention in industry and academia as the preferred choice of electronic power conversion for high power applications. They have a wide application area in a variety of industries involving transportation and energy management, a significant portion of which comprises of multilevel inverter fed induction motor drives. Multilevel inverters are ideally suitable for high power drives, since the switching frequency of the devices is limited for high power applications. In low power drives, the switching frequency is often in the range of tens of kHz, so that switching frequency harmonics are pushed higher in the frequency spectrum thereby the size and cost of the filter are reduced. But higher switching frequency has its own drawbacks, in particular for high voltage, high power applications. They cause large dv/dt stress on the motor and the devices, increased EMI problems and higher switching losses. An engineering trade-o is thus needed to select the minimum switching frequency without compromising on the output voltage quality. The present work is an alternate approach in this direction. Here, new inverter topologies and PWM strategies are developed that can eliminate a set of harmonics in the phase voltage using 12-sided polygonal space vector diagrams, also called dodecagonal space vector diagrams. A dodecagonal space vector diagram has many advantages over a hexagonal one. Switching space vectors on a dodecagon will not produce any harmonics of the order 6n 1, (n=odd) in the phase voltage. The next set of harmonics thus reside at 12n 1, (n=integer). By increasing the number of samples in a sector, it is also possible to suppress the lower order harmonics and a nearly sinusoidal voltage can be obtained. This is possible to achieve at a low switching frequency of the inverters. At the same time, a dodecagon is closer to a circle than a hexagon; so the linear modulation range is extended by about 6.6% compared to the hexagonal case. For a 50 Hz rated frequency operation, under constant V/f ratio, the linear modulation can be achieved upto a frequency of 48.3 Hz. Also, the harmonics of the order 6n 1, (n=odd) are absent in the over-modulation region. Maximum fundamental voltage is obtained from this inverter at the end of over-modulation region, where the phase voltage becomes a 12-step waveform. The present work is developed on dodecagonal space vector diagrams. The entire work can be summarized and explained through Fig. 1. This figure shows the development of hexagonal and dodecagonal space vector diagrams. It is known that, 3-level and 5-level space vector diagrams have been developed as an improvement over 2-level ones. They Figure 1: Development of hexagonal and dodecagonal space vector diagrams have better harmonic performance, reduced dv/dt stress on the motor and devices, better electromagnetic compatibility and improvement of efficiency over 2-level space vector diagrams. This happens because the instantaneous error between the reference vector and the switching vectors reduces, as the space vector density increases in the diagram. This is shown at the top of the figure. In the bottom part, the development of the dodecagonal space vector diagram is shown, which is the contribution of this thesis work. This is explained in brief in the following lines. Initially, a space vector diagram is proposed which switches on hexagonal space vectors in lower-modulation region and dodecagonal space vectors in the higher modulation region. As the reference vector length increases, voltage vectors at the vertices of the outer dodecagon and the vertices from the outer most hexagon is used for PWM control. This results in highly suppressed 5th and 7th order harmonics thereby improving the harmonic profile of the motor current. This leads to the 12-step operation at rated voltage where all the 5th and 7th order harmonics are completely eliminated. At the same time, the linear range of modulation extends upto 96.6% of base speed. Because of this, and the high degree of suppression of lower order harmonics, smooth acceleration of the motor upto rated speed is possible. The presence of multilevel space vector structure also limits the switching frequency of the inverters. In the next work, the single dodecagonal space vector diagram is improved upon to form two concentric dodecagons spanning the space vector plane (Fig. 1). The radius of the outer dodecagon is double the inner one. It reduces the device rating and the dv/dt stress on the devices to half compared to existing 12-sided schemes. The entire space vector diagram is divided into smaller sized isosceles triangles. PWM switching on these smaller triangles reduces the inverter switching frequency without compromising on the output voltage quality. The space vector diagram is further refined to accommodate six concentric dodecagons in the space vector plane (Fig. 1). Here the space vector diagram is characterized by alternately placed dodecagons which become closer to each other at higher radii. As such the harmonics in the phase voltage are reduced, in particular at higher modulation indices. At the same time, because of the dodecagonal space vector structure, all the 6n ± 1, (n=odd) harmonics are eliminated from the phase voltage. A nearly sinusoidal phase voltage can be generated without resorting to high frequency switching of the inverters. The above space vector diagrams are developed using different inverter circuits. The first work is developed from cascaded combination of three 2-level inverters, while the second and third works use 3-level NPC inverters feeding an open end induction motor drive. The circuit topologies are explained in detail in the respective chapters. Apart from this, PWM switching schemes and detailed analysis on duty cycle calculations using the concept of volt-second balance are also presented. They show that with proper switching schemes, the proposed configurations can substantially reduce the overall loss of the inverter. Other operational issues like capacitor voltage balancing of 3-level NPC inverters and improvement of input current drawn from the grid are also covered. All the above propositions are first simulated by MATLAB and subsequently verified by an experimental laboratory prototype. Motor current waveforms both at steady state and transient conditions during motor acceleration show that the induction motor can be fed from nearly sinusoidal voltage at all operating conditions. Simplified comparative studies are also made with the proposed converters and higher level inverters in terms of output voltage quality and losses. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of multilevel inverter. The thesis concludes with some interesting ideas for further thought and exploration.

Multilevel inverters (MLI) are widely used in a host of industrial applications ranging from renewable energy systems, to electric vehicles, to distributed generation. Due to the switching nature of the output voltage, MLI generate harmonics in output voltage at switching frequency. The harmonics in output voltage generate harmonic currents in the load, which may lead to losses in the system, and may also cause torque pulsations for motor drive applications. Hence, it is necessary to improve the harmonic performance (Total Harmonic Distortion-THD) of the output voltage. To improve the THD of the output voltage, passive filters may be incorporated to suppress the switching frequency harmonics. To optimize the component size in the filter, inverters are operated at high switching frequency. The high switching frequency in MLI generates electro-magnetic interference (EMI) and large dv/dt in the switching devices and motor load. Due to these drawbacks, the passive filtering solution is not very attractive. To overcome the aforementioned drawbacks, polygonal space vector structures have been proposed. This solution leads to generation of polygonal voltage space vector structures with sides greater than 6, in the over-modulation region. By switching on the vertices of dense space vector structure, lower order harmonics in phase voltage are suppressed with increased utilization of DC link voltage. Polygonal space vector structures can be generated by using a secondary inverter fed with a capacitive supply. The polygon is generated by superposition of the primary and secondary inverter space vectors. Polygonal space vector generation offers many advantages over conventional solutions. Polygonal space vector structures offer increased linear modulation range, which leads to maximum utilization of the DC link supply. In this scheme the main power delivery inverter fed with the active DC link supply is switched at low switching frequency. The reduced switching frequency reduces switching losses and reduces dv/dt. The secondary inverter is fed with a capacitive supply which is balanced at a fraction of the DC link voltage supply. The capacitive supply is balanced at it's nominal voltage during motoring/braking operation by using a novel capacitor balancing scheme. The presence of a single active supply to provide power for motoring operation reduces system complexity and facilitates four quadrant operation. The secondary inverter fed with low voltage capacitive supply is switched at high frequency for suppression of harmonics generated by low switching frequency primary inverter. The secondary inverter can be realized using low voltage semiconductor devices as the blocking voltage requirements for the secondary inverter are considerably lower. The secondary inverter does not provide any active power for motoring operation and hence acts as a switched capacitive filter. Compared to the conventional bulky passive filtering solutions, the switched capacitive filter is cost effective.

Multilevel voltage source inverters have become a widely accepted and cost-effective power converter technology for applications requiring high-power medium-voltage control. The demand of power level requirement has reached operational limits of megawatt range. Multilevel inverters (MLI) find applications in power transmission and distribution systems like HVDC which are connected with high voltage network lines and controlled ac drives operating at medium voltage levels. For low voltage applications, most prevalent topology which dominates industrial drives is conventional two-level inverter. With state of the art semiconductor technology, self-commutating converters with arrangement of several low voltage devices, help achieving voltage ranges till hundreds of kilovolts. Apart from high voltage operational capability, advantages like power quality control, better electromagnetic compatibility, lower switching losses, keep multilevel inverters a class above the conventional two-level inverters. In order to attain good waveform quality, the inverter needs to switch at very high frequencies. The harmonics appear only at switching frequency sidebands, which can be easily filtered externally. But, considering large voltage stress handled by the devices in two-level inverter and large switching loss in the devices degrade the efficiency of system substantially. Specific to applications like medium voltage drives, the major issues on electromagnetic interference, device stress, harmonic performance, and dv/dt control are mostly addressed by employing multilevel inverters. Most popular multilevel inverter topologies are neutral-point clamped inverters, flying capacitor inverters, and cascaded H-bridge inverters. These basic MLIs are further used to obtain hybrid multilevel inverters generating more number of voltage levels. Other applications of multilevel inverters include photovoltaic, hydel and wind energy systems, energy storage and management systems, electric vehicle applications, traction drives etc. As a 24-sided polygon is closer to a circle than a hexagon or a 12-sided polygon, the above presented schemes generate high quality motor phase voltage waveforms without using any external filters. A physical sine-wave filter can be completely relaxed for such variable speed drive applications, and the dynamic performance is never compromised since the filtering action is performed by switched capacitors. The topologies and modulation techniques presented are optimized for low switching frequency operation of large voltage blocking inverters and shifting relatively higher frequency switchings to low voltage cascaded H-Bridge inverters. Above all, single DC source operation can bring down the cost and complexity of the system drastically enabling easier back to back operation for drive. Also, such schemes can be directly driven from battery operated systems in electric vehicles without any passive sine filters. With all the mentioned advantages, the proposed drive schemes are highly suitable for high performance, medium voltage drive applications.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

MULTILEVEL inverters are the preferred choice of converters for electronic power conversion for high power applications. They are gaining popularity in variety of industrial applications including electric motor drives, transportation, energy management, transmission and distribution of power. A large portion of energy conversion systems comprises of multilevel inverter fed induction motor drives. The multilevel inverters are ideal for such applications, since the switching frequency of the devices can be kept low. In conventional two level inverters, to get nearly sinusoidal phase current waveform, the switching frequency of the inverter is increased and the harmonics in the currents are pushed higher in the frequency spectrum to reduce the size and cost of the filters. But higher switching frequency has its own drawbacks – in particular for medium voltage, high power applications. They cause large dv_/ dt stresses on the motor terminals and the switching devices, leading to increased electromagnetic interference (EMI) problems and higher switching losses. Harmonics in the motor currents can further be minimized by adopting dodecagonal voltage space vector (SV) switching (12-sided polygon). In case of dodecagonal SV switching, the fifth and seventh order (6n , 1, n = odd) harmonics are completely eliminated for the full modulation range including over modulation and twelve step operation in the motor phase voltages and currents. In addition to low order harmonic current suppression, the linear modulation range for dodecagonal SV switching is also more by 6% when compared to that of the conventional hexagonal SV switching. The dodecagonal voltage SV structure is made possible by connecting two inverters with DC-link voltages Vd and 0:366Vd on either side of an open-end winding induction motor. The dodecagonal space vector switching can be used to produce better quality phase voltage and current waveforms and overcome the problem of low order fifth and seventh harmonic currents and to improve the range for linear modulation while reducing the switching frequency of the inverters when compared to that of the conventional hexagonal space vector based inverters. This thesis focuses on three aspects of multilevel dodecagonal space vector structures (i) Two new power circuit topologies that generate a multilevel dodecagonal voltage space vector structure with symmetric triangles, (ii) A multilevel dodecagonal SV structure with nineteen concentric dodecagons, (iii) Pulse width modulation (PWM) timing calculation methods for a general N-level dodecagonal SV structure. (i) Two new power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles with minimum number of DC link power supplies and floating capacitor H-bridges are proposed. The first power topology is composed of two hybrid cascaded five level inverters connected to either side of an open end winding induction machine. Each inverter consists of a three level neutral point clamped (NPC) inverter, cascaded with an isolated capacitor fed H-bridge making it a five level inverter. The second topology is a hybrid topology for a normal induction motor (star or delta connected), where the power is fed to the motor only from one side. The proposed scheme retains all the advantages of multilevel topologies as well the advantages of the dodecagonal voltage space vector structure. Both topologies have inherent capacitor balancing for floating H-bridges for all modulation indices including transient operations. The proposed topologies do not require any pre-charging circuitry for startup. PWM timing calculation method for space vector modulation is also explored in this chapter. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any iterative searching, off-line computation, look-up tables or angle estimation. Experimental results for steady state operation and transient operation are also presented to validate the proposed concept. (ii) A multilevel dodecagonal voltage space vector structure with nineteen concentric do-decagons is proposed for the first time. This space vector structure is achieved by connecting two sets of asymmetric hybrid five level inverters on either side of an open-end winding induction motor. The dodecagonal structure is made possible by proper selection of DC-link voltages and switching states of the inverters. In addition to that, a generic and simple method for calculation of PWM timings using only sampled reference values (v and v ) is proposed. This enables the scheme to be used for any closed loop application like vector control. Also, a new switching technique is proposed which ensures minimum switching while eliminating the fifth and seventh order harmonics and suppressing the eleventh and thirteenth harmonics, eliminating the need for bulky filters. The motor phase voltage is a 24-stepped waveform for the entire modulation range thereby reducing the number of switchings of the individual inverter modules. Experimental results for steady state operation, transient operation including start-up have been presented and the results of Fast Fourier Transform (FFT) analysis is also presented for validating the proposed concept. (iii) A method to obtain PWM timings for a general N-level dodecagonal voltage space vector structure using only sampled reference values is proposed. Typical methods that are used to find PWM timings for dodecagonal SV structures use modulation index and the reference vector angle, to get the timings T1 and T2 using trigonometric calculations. This method requires look-up tables and is difficult to implement in closed loop systems. The proposed method requires only two additions to compute these timings. For multilevel case, typical iterative methods need timing calculations (matrix multiplications) to be performed for each triangle. The proposed method is generic and can be extended to any number of levels with symmetric structures and does not require any iterative searching for locating the triangle in which the tip of the reference vector lies. The algorithm outputs the triangle number and the PWM timing values of T0, T1 and T2 which can be set as the compare values for any carrier based PWM module to obtain space vector PWM like switching sequences. Simulation and experimental results for steady state and transient conditions have been presented to validate the proposed method. A 3.7 kW, 415 V, 50 Hz, 4-pole open-end winding induction motor was used for the experimental studies. The semiconductor switches that were used to realize the power circuit for the experiment were 75 A, 1200 V insulated-gate bipolar transistor (IGBT) half-bridge modules (SKM75GB12T4). Opto-isolated gate drivers with desaturation protection (M57962L) were used to drive the IGBTs. For the speed control and PWM timing computation a digital signal processor (DSP-TMS320F28335) with a clock frequency of 150 MHz was used. For modulation frequencies 10 Hz and below, a constant sampling frequency of 1 kHz was used as the frequency modulation ratio is high. For modulation frequencies above 10 Hz, synchronous PWM strategy was used. The time duration Ts is the sampling interval for which the timings T1 , T2 and T0 are calculated. As in the case of any synchronous PWM method, the duration of sampling time (Ts) is a function of the fundamental frequency of the modulating signal. In this case, Ts = 1_.fm • 12n) sec. where fm is fundamental frequency in Hertz and ‘n’ is the number of samples per 30ý dodecagonal sector. The PWM timings and the triangle data (from the DSP) is fed to field programmable gate array (FPGA) (SPARTAN XC3S200) clocked at 50 MHz where the actual gating pulses are generated. The capacitor balancing algorithm and the dead-time modules were implemented within FPGA. No external hardware was used for generation of dead-time. The dead-time block generates a constant dead-time of 2 s for all the switches. Extensive testing was done for steady state operations and transient operations including quick acceleration and start-up to validate the proposed concepts. With the advantages like extension of linear modulation range, elimination of fifth and seventh harmonics in phase voltages and currents for the full modulation range, suppression of eleventh and thirteenth harmonics in phase voltages and currents, reduced device voltage ratings, lesser dv_dt stresses on devices and motor phase windings, lower switching frequency, inherent cascaded H-bridge (CHB) capacitor balancing, the proposed space vector structures, the inverter power circuit topologies, the switching techniques and the PWM timing calculation methods can be considered as viable schemes for medium voltage, high power motor drive applications.

Variable-speed Induction motor drives are nowadays used for various kinds of industrial processes, transportation systems, wind turbines and household appliances in the world. The majority of drives are for general purpose speed control applications where accurate speed control is not required for entire speed range. But for high dynamic drive application, very precise and fast control of induction motor drive is essential. For such applications, sophisticated and well-performing control design is a key issue. Precise and accurate torque control of the Induction Motor (IM) can only be accomplished by vector control and direct torque control. In terms of space vector theory, vector control implies that the instantaneous torque is controlled by way of the stator current vector that is orthogonal to the rotor flux vector. Precise knowledge of the rotor flux angle is therefore essential for a vector controlled IM. IMs do not allow the flux position to be easily measured, so most modern vector controlled IM drives rely on flux estimation. This means that the flux angle is derived from a flux estimator, using the dynamic model of the IM. Given that the rotor speed of the IM is measured by a mechanical shaft sensor. Flux estimation is a fairly easy task. However, vector control of IM without mechanical shaft speed sensor is of current interest in industrial environment. The driving motivations behind the development in sensorless control are lower cost, improved reliability and operating environment. In this thesis, a sensorless vector control scheme for rotor flux estimation using current error space phasor based hysteresis controller is proposed including the method for estimation of leakage inductance, Ls. For frequencies of operation less than 25 Hz, the rotor voltage and hence the rotor flux position is computed during the inverter zero voltage space vector using steady state model of IM. For above 25 Hz, active vector period and steady state model of IM is used. The whole rotor flux estimation scheme is dependent on current error space phasor and the steady state motor model, with rotor flux as a reference vector. Since no terminal voltage sensing is involved, dead time effects will not create problem in rotor flux sensing at low frequencies of operation. But appropriate device on-state drop are compensated at low frequencies (below 5 Hz) of operation to achieve a steady state operation up to less than 1 Hz. A constant switching frequency hysteresis current controller is used in inner current control loop for the PWM regulation, with smooth transition of operation to six-step mode operation. A simple Ls estimation based on current error space phasor is also proposed to nullify the deteriorating effect on rotor flux estimation. The parameter sensitivity of the control scheme to changes in the stator resistance Rs is also investigated. The drive scheme is tested up to a low frequency operation less than 1 Hz. The extensive simulation and experiment results are presented to show the proposed scheme’s good dynamic performance extending up to six-step operation. In contrast to vector control, direct torque control (DTC) method requires the knowledge of stator resistance only and thereby decreasing the associated sensitivity to parameters variation and the elimination of speed information. DTC as compared to vector control does not require co-ordinate transformation and PI controller. DTC is easy to implement because it needs only two hysteresis comparators and a lookup table for both flux and torque control. This thesis also investigates the possibilities in improvement of direct torque control scheme for high performance induction motor drive applications. Here, two schemes are proposed based on the direct torque control scheme for IM drive using 12-sided polygonal voltage space vectors for fast torque control. The torque control scheme based on DTC algorithm is proposed using 12-sided polygonal voltage space vector. The basic DTC scheme is used to control the torque. But the IM drive is open-end type. For torque control, the voltage space vectors orthogonal to stator flux vector in 12-sided polygonal space vector structure are used as hexagonal space vector based DTC scheme. The advantages achieved due to 12-sided polygonal space vector are mainly fast torque control and small torque ripple. The fast transient of torque with precise control is achieved using voltage space vector placed with a resolution of ±15. The torque ripple will be less as 6n±1 (n=odd) harmonic torque is totally eliminated from the whole range of PWM modulation. The comparative analysis of proposed 12-sided polygonal voltage space vector based DTC and conventional hexagonal space vector based DTC is also presented. Extensive simulation and experiment results are also presented to show the fast torque control at speeds of operation ranging from 5 Hz to the rated speed. The concept of 12-sided polygonal space vector based DTC is further extended for a variable speed control scheme using estimated fundamental stator voltage for sector identification. The conventional DTC scheme uses stator flux vector for identification of the sector and the switching vector are selected based on this sector information to control stator flux and torque. However, the proposed DTC scheme selects switching vectors based on the sector information of the estimated fundamental stator voltage vector and its relative position with respect to the stator flux vector. The fundamental stator voltage estimation is based on the steady state model of IM and information of synchronous frequency which is derived from computed stator flux using a low pass filter technique. The proposed DTC scheme utilizes the exact position of fundamental stator voltage vector and stator flux vector position to select optimal switching vector for fast control of torque with small variation of stator flux within hysteresis band. The present DTC scheme allows the full load torque control with fast transient response to very low speeds of operation below 5 Hz. The extensive simulation and experiment results are presented to show the fast torque control for speed of operation from zero speed to rated speed. However, the present scheme will have all the advantages of DTC scheme using stator flux vector for sector identification. All the above propositions are first simulated by MATLAB/Simulink and subsequently verified by an experimental laboratory prototype. The proposed control schemes are experimentally verified on a 3.7 kW IM drive. The control algorithms of the sensorless vector control using current error space phasor as well as DTC using 12-sided polygonal voltage space vector are completely implemented on a TI TMS320LF2812 DSP controller platform. These are some of the constituents for chapters 2, 3 and 4 in this thesis. Additionally, the first chapter also covers a brief survey on some of the recent progresses made in the field of sensorless vector control, direct torque control and current hysteresis controller. The thesis concludes with suggestion for further exploration.