Relevant bibliographies by topics / Planar device architecture

Academic literature on the topic 'Planar device architecture'

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Published: 4 June 2021
Last updated: 6 February 2022

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Journal articles on the topic "Planar device architecture"

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Misra, Ravi K., Sigalit Aharon, Michael Layani, Shlomo Magdassi, and Lioz Etgar. "A mesoporous–planar hybrid architecture of methylammonium lead iodide perovskite based solar cells." Journal of Materials Chemistry A 4, no. 37 (2016): 14423–29. http://dx.doi.org/10.1039/c6ta06960f.

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We report a hybrid mesoporous–planar architecture of methylammonium lead iodide perovskite based solar cells, to combine the benefits of both the mesoporous and planar architectures in a single device.
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Bhattacharya, Debajit, and Niraj K. Jha. "FinFETs: From Devices to Architectures." Advances in Electronics 2014 (September 7, 2014): 1–21. http://dx.doi.org/10.1155/2014/365689.

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Since Moore’s law driven scaling of planar MOSFETs faces formidable challenges in the nanometer regime, FinFETs and Trigate FETs have emerged as their successors. Owing to the presence of multiple (two/three) gates, FinFETs/Trigate FETs are able to tackle short-channel effects (SCEs) better than conventional planar MOSFETs at deeply scaled technology nodes and thus enable continued transistor scaling. In this paper, we review research on FinFETs from the bottommost device level to the topmost architecture level. We survey different types of FinFETs, various possible FinFET asymmetries and their impact, and novel logic-level and architecture-level tradeoffs offered by FinFETs. We also review analysis and optimization tools that are available for characterizing FinFET devices, circuits, and architectures.
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Tarabella, Giuseppe, Simone Luigi Marasso, Valentina Bertana, Davide Vurro, Pasquale D’Angelo, Salvatore Iannotta, and Matteo Cocuzza. "Multifunctional Operation of an Organic Device with Three-Dimensional Architecture." Materials 12, no. 8 (April 25, 2019): 1357. http://dx.doi.org/10.3390/ma12081357.

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This work aims to show the feasibility of an innovative approach for the manufacturing of organic-based devices with a true three-dimensional and customizable structure that is made possible by plastic templates, fabricated by additive manufacturing methods, and coated by conducting organic thin films. Specifically, a three-dimensional prototype based on a polyamide structure covered by poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) using the dip-coating technique demonstrated a multifunctional character. The prototype is indeed able to operate both as a three-terminal device showing the typical response of organic electrochemical transistors (OECTs), with a higher amplification performance with respect to planar (2D) all-PEDOT:PSS OECTs, and as a two-terminal device able to efficiently implement a resistive sensing of water vaporization and perspiration, showing performances at least comparable to that of state-of-art resistive humidity sensors based on pristine PEDOT:PSS. To our knowledge, this is the first reported proof-of-concept of a true 3D structured OECT, obtained by exploiting a Selective laser sintering approach that, though simple in terms of 3D layout, paves the way for the integration of sensors based on OECTs into three-dimensional objects in various application areas.
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Ravariu, Cristian, Elena Manea, and Catalin Parvulescu. "An Appropriate Diffusion Process Changes the Behaviour of a Planar-Nothing on Insulator Device." Defect and Diffusion Forum 399 (February 2020): 115–22. http://dx.doi.org/10.4028/www.scientific.net/ddf.399.115.

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The paper investigates the tunneling currents through the gate terminals of the last MOSFET production and proposes a related structure, noted as p-NOI (planar-Nothing On Insulator) device. In fact, the p-NOI structure can arise as parasitic device in any MOSFET having a gate insulator sub-10nm thickness or can be separately produced to offer a tunneling device. The work principle of a p-NOI structure consists in the Fowler-Nordheim's tunneling of a thin insulator. Its architecture is derived from the Nothing On Insulator (NOI) device, using oxide instead vacuum. Essentially, the p-NOI current follows a metal-insulator-semiconductor trajectory. A critical issue is the field effect of a transistor that must be fulfilled by independent p-NOI device. In this purpose, a diffusion process seems to be the key. A planar p-NOI device with top three terminals is proposed. A diffusion process along to the Si-surface is a key technological step that offers distinct current traces.
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Malosio, Matteo, Francesco Corbetta, Francisco Ramìrez Reyes, Hermes Giberti, Giovanni Legnani, and Lorenzo Molinari Tosatti. "On a Two-DoF Parallel and Orthogonal Variable-Stiffness Actuator: An Innovative Kinematic Architecture." Robotics 8, no. 2 (May 27, 2019): 39. http://dx.doi.org/10.3390/robotics8020039.

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Variable-Stiffness Actuators are continuously increasing in importance due to their characteristics that can be beneficial in various applications. It is undisputed that several one-degree-of-freedom (DoF) solutions have been developed thus far. The aim of this work is to introduce an original two-DoF planar variable-stiffness mechanism, characterized by an orthogonal arrangement of the actuation units to favor the isotropy. This device combines the concepts forming the basis of a one-DoF agonist-antagonist variable-stiffness mechanism and the rigid planar parallel and orthogonal kinematic one. In this paper, the kinematics and the operation principles are set out in detail, together with the analysis of the mechanism stiffness.
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Godlewski, M., E. Guziewicz, S. Gierałtowska, G. Łuka, T. Krajewski, Ł. Wachnicki, and K. Kopalko. "Barriers in Miniaturization of Electronic Devices and the Ways to Overcome Them - from a Planar to 3D Device Architecture." Acta Physica Polonica A 116, Supplement (December 2009): S—19—S—21. http://dx.doi.org/10.12693/aphyspola.116.s-19.

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Zhou, Zheng, Jia Xu, Li Xiao, Jing Chen, Zhan'ao Tan, Jianxi Yao, and Songyuan Dai. "Efficient planar perovskite solar cells prepared via a low-pressure vapor-assisted solution process with fullerene/TiO2 as an electron collection bilayer." RSC Advances 6, no. 82 (2016): 78585–94. http://dx.doi.org/10.1039/c6ra14372e.

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Turren-Cruz, Silver-Hamill, Anders Hagfeldt, and Michael Saliba. "Methylammonium-free, high-performance, and stable perovskite solar cells on a planar architecture." Science 362, no. 6413 (October 11, 2018): 449–53. http://dx.doi.org/10.1126/science.aat3583.

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Currently, perovskite solar cells (PSCs) with high performances greater than 20% contain bromine (Br), causing a suboptimal bandgap, and the thermally unstable methylammonium (MA) molecule. Avoiding Br and especially MA can therefore result in more optimal bandgaps and stable perovskites. We show that inorganic cation tuning, using rubidium and cesium, enables highly crystalline formamidinium-based perovskites without Br or MA. On a conventional, planar device architecture, using polymeric interlayers at the electron- and hole-transporting interface, we demonstrate an efficiency of 20.35% (stabilized), one of the highest for MA-free perovskites, with a drastically improved stability reached without the stabilizing influence of mesoporous interlayers. The perovskite is not heated beyond 100°C. Going MA-free is a new direction for perovskites that are inherently stable and compatible with tandems or flexible substrates, which are the main routes commercializing PSCs.
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Ju, J. H., X. J. Shi, and S. F. Yu. "(Invited) A Comparison of Device Architecture, Electrical Performance and Process Flow between FinFET and Planar MOSFETs." ECS Transactions 60, no. 1 (February 27, 2014): 745–50. http://dx.doi.org/10.1149/06001.0745ecst.

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Huang, Pei-Chen, and Chang-Chun Lee. "Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique." Materials 14, no. 18 (September 11, 2021): 5226. http://dx.doi.org/10.3390/ma14185226.

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Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.
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Dissertations / Theses on the topic "Planar device architecture"

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Ruess, Frank Joachim Physics Faculty of Science UNSW. "Atomically controlled device fabrication using STM." Awarded by:University of New South Wales. Physics, 2006. http://handle.unsw.edu.au/1959.4/24855.

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We present the development of a novel, UHV-compatible device fabrication strategy for the realisation of nano- and atomic-scale devices in silicon by harnessing the atomic-resolution capability of a scanning tunnelling microscope (STM). We develop etched registration markers in the silicon substrate in combination with a custom-designed STM/ molecular beam epitaxy system (MBE) to solve one of the key problems in STM device fabrication ??? connecting devices, fabricated in UHV, to the outside world. Using hydrogen-based STM lithography in combination with phosphine, as a dopant source, and silicon MBE, we then go on to fabricate several planar Si:P devices on one chip, including control devices that demonstrate the efficiency of each stage of the fabrication process. We demonstrate that we can perform four terminal magnetoconductance measurements at cryogenic temperatures after ex-situ alignment of metal contacts to the buried device. Using this process, we demonstrate the lateral confinement of P dopants in a delta-doped plane to a line of width 90nm; and observe the cross-over from 2D to 1D magnetotransport. These measurements enable us to extract the wire width which is in excellent agreement with STM images of the patterned wire. We then create STM-patterned Si:P wires with widths from 90nm to 8nm that show ohmic conduction and low resistivities of 1 to 20 micro Ohm-cm respectively ??? some of the highest conductivity wires reported in silicon. We study the dominant scattering mechanisms in the wires and find that temperature-dependent magnetoconductance can be described by a combination of both 1D weak localisation and 1D electron-electron interaction theories with a potential crossover to strong localisation at lower temperatures. We present results from STM-patterned tunnel junctions with gap sizes of 50nm and 17nm exhibiting clean, non-linear characteristics. We also present preliminary conductance results from a 70nm long and 90nm wide dot between source-drain leads which show evidence of Coulomb blockade behaviour. The thesis demonstrates the viability of using STM lithography to make devices in silicon down to atomic-scale dimensions. In particular, we show the enormous potential of this technology to directly correlate images of the doped regions with ex-situ electrical device characteristics.
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Books on the topic "Planar device architecture"

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Darragh, Joan. Museum design: Planning and building for art. Oxford: Oxford University Press, 1993.

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Darragh, Joan. Museum design: Planning and building for art. New York: Oxford University Press in association with the American Federation of Arts and the National Endowment for the Arts, 1993.

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Crosbie, Michael J. Ten Houses: Alfredo DeVido Association. Rockport, 1998.

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Book chapters on the topic "Planar device architecture"

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Valori, Marcello, Vito Basile, Simone Pio Negri, Paolo Scalmati, Chiara Renghini, and Irene Fassi. "Towards the Automated Coverlay Assembly in FPCB Manufacturing: Concept and Preliminary Tests." In IFIP Advances in Information and Communication Technology, 36–50. Cham: Springer International Publishing, 2021. http://dx.doi.org/10.1007/978-3-030-72632-4_3.

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AbstractIn modern electronics, flexible and rigid-flex PCBs are largely used due to their intrinsic versatility and performance, allowing to increase the available volume, or enabling connection between unconstrained components. Rigid-flex PCBs consists of rigid board portions with flexible interconnections and are commonly used in a wide variety of industrial applications. However, the assembly process of these devices still has some bottlenecks. Specifically, they require the application of cover layers (namely, coverlays), to provide insulation and protection of the flexible circuits. Due to the variability in planar shape and dimensions, the coverlay application is still performed manually, requiring troublesome manipulation steps and resulting in undetermined time-cycle and precision.This paper aims at the improvement of the industrial process currently performed, by proposing an approach for the automation of Kapton coverlay manipulation and application. Since these products are commercially provided as a film with a protective layer to be removed, the peeling issue is addressed, representing a challenging step of the automated process; the results of a systematic series of tests, performed in order to validate the peeling strategy, are reported in the paper. The overall assembly strategy relies on the development of a customized multi-hole vacuum gripper, whose concept is presented and contextualized in the proposed assembly process by outlining a suitable workcell architecture.
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Linder, Barry P., Eduard A. Cartier, Siddarth A. Krishnan, Chunyan E. Tian, and Vijay Narayanan. "Reliability Issues in Planar and Nonplanar (FinFET) Device Architectures." In Micro- and Nanoelectronics, 137–55. CRC Press, 2017. http://dx.doi.org/10.1201/b17597-7.

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Retamar, Ángel, Daniel Ibaseta, Andrés G. Mangas, Iván Gallego, Irene Alonso Canella, and Lucía Fernández. "An Introduction to IWoT." In Advances in Business Information Systems and Analytics, 113–58. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-3805-9.ch005.

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The major drawback of the industrial internet of things is the lack of interoperability across the plethora of IoT platforms. Cross-platform services often require the development of complex software components for protocol translation, device discovery, and thing lifecycle management. As a result, these systems are too expensive and hard to develop. The W3C Consortium launched the Web of Things Working Group to develop the standards for open interoperability in the internet of things. This chapter presents the web of things specifications for systems architecture and communication protocols and how they can be applied in industrial domains, building the industrial web of things. Finally, this chapter shows that this industrial web of things is built upon a network of systems and devices linked with universal open standards such as enterprise systems, which are nowadays communicated through the conventional “web of pages,” as a key player in the Industry 4.0 revolution.
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Retamar, Ángel, Daniel Ibaseta, Andrés G. Mangas, Iván Gallego, Irene Alonso Canella, and Lucía Fernández. "An Introduction to IWoT." In Research Anthology on Cross-Industry Challenges of Industry 4.0, 1877–914. IGI Global, 2021. http://dx.doi.org/10.4018/978-1-7998-8548-1.ch095.

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The major drawback of the industrial internet of things is the lack of interoperability across the plethora of IoT platforms. Cross-platform services often require the development of complex software components for protocol translation, device discovery, and thing lifecycle management. As a result, these systems are too expensive and hard to develop. The W3C Consortium launched the Web of Things Working Group to develop the standards for open interoperability in the internet of things. This chapter presents the web of things specifications for systems architecture and communication protocols and how they can be applied in industrial domains, building the industrial web of things. Finally, this chapter shows that this industrial web of things is built upon a network of systems and devices linked with universal open standards such as enterprise systems, which are nowadays communicated through the conventional “web of pages,” as a key player in the Industry 4.0 revolution.
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Singh, Garima. "Examining Software-Defined Networking for Cloud-Based IoT Systems." In Advances in Wireless Technologies and Telecommunication, 192–215. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-3445-7.ch010.

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The Internet of Things (IoT) represents the current and future state of the internet. The large number of things (objects) connected to the internet produces a huge amount of data that needs a lot of effort and processing operations to transfer it to useful information. Maximizing the utilization of this paradigm requires fine-grained QoS support for differentiated application requirements, context-aware semantic information retrieval, and quick and easy deployment of resources, among many other objectives. These objectives can only be achieved if components of the IoT can be dynamically managed end-to-end across heterogeneous objects, transmission technologies, and networking architectures. In this chapter, Software Defined Systems (SDS) is described as a new paradigm to hide all complexity in traditional system architecture by abstracting all the controls and management operations from the underling devices (things in the IoT) and setting them inside a middleware layer, a software layer, using a software-based control plane.
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Marques, Gonçalo. "Ambient Assisted Living and Internet of Things." In Harnessing the Internet of Everything (IoE) for Accelerated Innovation Opportunities, 100–115. IGI Global, 2019. http://dx.doi.org/10.4018/978-1-5225-7332-6.ch005.

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The study of systems and architectures for ambient assisted living (AAL) is undoubtedly a topic of great relevance given the ageing of the world population. On the one hand, AAL technologies are designed to meet the needs of the ageing population in order to maintain their independence as long as possible. On the other hand, internet of things (IoT) proposes that various “things,” which include not only communication devices but also every other physical object on the planet, are going to be connected and will be controlled across the internet. The continuous technological advancements turn possible to build smart objects with great capabilities for sensing and connecting turn possible several advancements in AAL and IoT systems architectures. Advances in networking, sensors, and embedded devices have made it possible to monitor and provide assistance to people in their homes. This chapter reviews the state of art on AAL and IoT and their applications for enhanced indoor living environments and occupational health.
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N. Hattori, Azusa, and Ken Hattori. "Creation and Evaluation of Atomically Ordered Side- and Facet-Surface Structures of Three-Dimensional Silicon Nano-Architectures." In 21st Century Surface Science - a Handbook. IntechOpen, 2020. http://dx.doi.org/10.5772/intechopen.92860.

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The realization of three-dimensional (3D)-architected nanostructures, that is, the transformation from novel two-dimensional (2D) film-based devices to 3D complex nanodevices, is of crucial importance with the progress of scaling down devices to nanometer order. However, little attention has been devoted to controlling the atomic ordering and structures of side-surfaces on 3D structures, while techniques for controlling and investigating 2D surfaces, namely, surface science, have been established only for planar 2D surfaces. We have established an original methodology that enables atomic orderings and arrangements of surfaces with arbitrary directions to be observed on 3D figured structures by developing diffraction and microscopy techniques. An original technique, namely, directly and quantitatively viewing the side- and facet-surfaces at the atomic scale by reflection high-energy electron diffraction (RHEED) and low-energy electron diffraction (LEED), can be used to determine process parameters in etching. This chapter introduces methods of evaluation by RHEED and LEED based on a reciprocal space map and methods of creating various atomically flat 111 and {100} side-surfaces of 3D Si nano-architectures and tilted 111 facet-surfaces fabricated by lithography dry and wet etching processes, followed by annealing treatment in vacuum.
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Nagaraju, Mamillapally, and Mulukutla Trivikram. "PIR-Enabled Security System for Internet of Things Using Raspberry Pi." In Exploring the Convergence of Big Data and the Internet of Things, 113–28. IGI Global, 2018. http://dx.doi.org/10.4018/978-1-5225-2947-7.ch009.

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Internet of Things (IoT) is an evolution of mobile, home and embedded systems that can be connected to internet increasing greater capabilities of data analytics to extract meaningful information, which can further used for decision making. Billions of devices are connected to internet and soon its number may grow higher than number of human beings on this planet. These connected devices integrated together can become a network of intelligent systems that share data over the cloud to analyze. IoT is an emerging technology where several machines are embedded with low power consuming sensors that allow them to rely data from each other with little or no human intervention. Especially, PIR motion sensor plays a key role in security systems for detecting movements, intrusion and occupancy by interacting with other devices simultaneously like alarms, cameras etc. In this paper, researchers studied IoT applications using PIR motion sensor and proposed architecture and algorithms to be implemented for better development of security systems.
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Caviglione, Luca, and Mauro Coccoli. "Enhancement of e-Learning Systems and Methodologies through Advancements in Distributed Computing Technologies." In Internet and Distributed Computing Advancements, 45–69. IGI Global, 2012. http://dx.doi.org/10.4018/978-1-4666-0161-1.ch002.

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The evolution of the Internet, distributed architectures, and Grid-oriented frameworks can change the way people acquire and disseminate both knowledge and experience, thus the way they learn. Therefore, one can envisage new e-learning models, based on a more efficient users’ interaction, that also empowers the hands-on experience. This will improve learning outcomes, while reducing the need of physical devices and removing the inherent boundaries. Moreover, this reduces costs by promoting the sharing of resources and learning assets. From this perspective, the chapter discusses the integration of classical e-learning paradigms with new advancements of distributed computing, such as: 1) the usage of Peer-to-Peer (P2P) to produce network-independent overlays, also by enabling direct student-to-student exchanges; 2) the integration, through grid-based middleware, of real or virtual devices, plants and Sensors Network (SN) within the e-learning environment; and 3) the adoption of a distributed e-learning system to spread culture through mobile devices, with an emphasis on satellite communications.
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McCray, W. Patrick. "Could Small Be Beautiful?" In The Visioneers. Princeton University Press, 2017. http://dx.doi.org/10.23943/princeton/9780691176291.003.0006.

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This chapter discusses the growing interest in nanotechnology. As the excitement of the space program waned, new technological frontiers were found not beyond our planet but with the manipulation of matter at the smallest scales. Instead of imagining a future that started with settlements floating in the inky vacuum of space, this new future derived from manipulations of the cell's interior machinery and the integrated circuit's crystalline architecture. Scientists and engineers combined their increasing abilities to engineer organisms and devices with an interactive and interventionist approach to modifying the physical world in new and unexpected ways. Biotechnology and microelectronics provided a core foundation for activities that Drexler initially called “molecular engineering,” which later acquired the “nanotechnology” moniker.
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Conference papers on the topic "Planar device architecture"

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Shahidi, Ghavam G. "From 2D-planar to 3D-non-planar device architecture: A scalable path forward?" In 2013 IEEE Custom Integrated Circuits Conference - CICC 2013. IEEE, 2013. http://dx.doi.org/10.1109/cicc.2013.6658477.

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Lin, Chung-Hsun, Josephine Chang, Michael Guillorn, Andres Bryant, Phil Oldiges, and Wilfried Haensch. "Non-planar device architecture for 15nm node: FinFET or trigate?" In 2010 IEEE International SOI Conference. IEEE, 2010. http://dx.doi.org/10.1109/soi.2010.5641060.

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Adjokatse, Sampson, Hong-hua Fang, Jane Kardula, and Maria Antonietta Loi. "Effect of substrate layer and Device Architecture on Photophysics and Device Performance of Planar Perovskite Solar Cells." In 3rd International Conference on Perovskite Thin Film Photovoltaics, Photonics and Optoelectronics. Valencia: Fundació Scito, 2017. http://dx.doi.org/10.29363/nanoge.abxpvperopto.2018.113.

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Barabadi, Banafsheh, Yogendra K. Joshi, and Satish Kumar. "Prediction of Transient Thermal Behavior of Planar Interconnect Architecture Using Proper Orthogonal Decomposition Method." In ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems. ASMEDC, 2011. http://dx.doi.org/10.1115/ipack2011-52133.

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A major challenge in maintaining quality and reliability in today’s microelectronics devices comes from the ever increasing level of integration in the device fabrication as well as the high level of current densities that are carried through the microchip during operation. Cyclic thermal events during operation, stemming from Joule heating of the metal lines, can lead to fatigue failure due to the varying thermal expansion coefficients of the different materials that compose the microchip package. To aid in the avoidance of such device failures, it is imperative to develop a predictive capability for the thermal response of micro-electronic circuits. This work studied the problem of transient Joule heating in interconnects in a two-dimensional (2D) inhomogeneous system using a reduced order modeling approach of the Proper Orthogonal Decomposition (POD) method and Galerkin Projection Technique. This study considers an interconnect structure embedded in the bulk of a microelectronic device. The effect of different types of current pulses, pulse duration, and pulse amplitude were investigated. By using a representative step function as the heat source, the model predicted the exact transient thermal behavior of the system for all other cases without generating any new observations, using just a few POD modes. To validate this unique capability, the result of the POD model was compared with a finite element (FE) model developed in LS-DYNA®. The behaviors of the POD models were in good agreements with the corresponding FE models. This close correlation provides the capability of predicting other cases based on a smaller sample set which can significantly decrease the computational cost.
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Parvais, B., A. Mercha, N. Collaert, R. Rooyackers, I. Ferain, M. Jurczak, V. Subramanian, et al. "The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET." In 2009 International Symposium on VLSI Technology, Systems, and Applications (VLSI-TSA). IEEE, 2009. http://dx.doi.org/10.1109/vtsa.2009.5159300.

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Bah, Thierno-Moussa, Stanjen Didenko, Stephane Monfray, Thomas Skotnicki, Emmanuel Dubois, and Jean-Francois Robillard. "Performance Evaluation of Silicon Based Thermoelectric Generators Interest of Coupling Low Thermal Conductivity Thin Films and a Planar Architecture." In 48th European Solid-State Device Research Conference (ESSDERC 2018). IEEE, 2018. http://dx.doi.org/10.1109/essderc.2018.8486919.

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Karpov, Eduard G., and Ievgen Nedrygailov. "Nonadiabatic Chemical to Electrical Energy Conversion in Planar Schottky Nanostructures." In ASME 2010 International Mechanical Engineering Congress and Exposition. ASMEDC, 2010. http://dx.doi.org/10.1115/imece2010-40634.

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Nonadiabatic energy dissipation by electron subsystem of nanostructured solids unveil interesting opportunities for the solid-state energy conversion and sensor applications. We found that planar Pd/n-SiC, Pt/n-GaP and Pd/n-GaP Schottky structures with nanometer thickness metallization demonstrates a nonadiabatic channel for the conversion into electricity the energy of a catalytic hydrogen-to-water oxidation process on the metal layer surface. The observed abovethermal current greatly complements the usual thermionic emission current, and its magnitude is linearly proportional to the rate of formation and desorption of product water molecules from the nanostructure surface. The possibilities and advantages of utilizing the nonadiabatic functionality in a novel class of chemical-to-electrical energy conversion devices are discussed. The technology has a potential for a very high volumetric energy density due to the intrinsically planar device architecture.
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Tomita, M., H. Takezawa, K. Mesaki, T. Matsukawa, T. Matsuki, and T. Watanabe. "Evaluation of Multi-stage, Unileg, Si-nanowire Thermoelectric Generator with A Cavity-free and Planar Device Architecture." In 2019 International Conference on Solid State Devices and Materials. The Japan Society of Applied Physics, 2019. http://dx.doi.org/10.7567/ssdm.2019.c-1-01.

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Rubbert, L., P. Renaud, and J. Gangloff. "Design and Optimization for a Cardiac Active Stabilizer Based on Planar Parallel Compliant Mechanisms." In ASME 2012 11th Biennial Conference on Engineering Systems Design and Analysis. American Society of Mechanical Engineers, 2012. http://dx.doi.org/10.1115/esda2012-82278.

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Giving assistance to surgeons during beating heart procedures is currently a great challenge in medical robotics: a high level of safety is required while the beating heart yields high forces and dynamics. In this article, we investigate the design of an active cardiac stabilizer that will provide a motionless area of interest during the surgery. A device architecture is introduced that is based on planar parallel mechanisms. Such mechanisms are particularly interesting for their manufacturing simplicity and compactness. With the considered architecture, spherical compliant joints based on a planar structure need to be designed. Here we present the use of a 3-RRR spherical parallel mechanism. Its kinematic and stiffness analysis are performed using pseudo-rigid body modeling. An optimization of the mechanism is then achieved, using a modified ant colony optimization technique. The achievable performance of this type of compliant spherical joint is then discussed before concluding on the device adequacy with respect to the surgical requirements.
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Myszka, David H., Austin M. Fischer, and Andrew P. Murray. "A Study on the Influence of Planar Mechanism Design on Energy Use During Controlled Movements." In ASME 2018 International Design Engineering Technical Conferences and Computers and Information in Engineering Conference. American Society of Mechanical Engineers, 2018. http://dx.doi.org/10.1115/detc2018-85650.

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This paper presents a study on the energy utilization of planar automation mechanisms that operate with controlled moves. Designers of factory automation for pick & place tasks often select multiple degree-of-freedom robotic devices. With multiple degrees-of-freedom, task flexibility is available, but many operations require little or no flexibility. The majority of research on the energy usage of these robot devices for pick & place tasks focuses on path planning. The study presented in this paper explores the energy savings in using low degree-of-freedom devices and the influence of design parameter selection. Energy predictor equations are developed and confirmed through experimentation. Various positioning mechanisms of differing dimensions are studied for trends in energy utilization. Lastly, an actuator control strategy is proposed for further reducing energy requirements. The study concludes that energy usage can be substantially decreased in pick & place applications by reducing the degrees of freedom of the device, implementing a prudent mechanism architecture, ideally selecting mechanism dimensions and optimally controlling the actuator(s).
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