Relevant bibliographies by topics / PCoC - Power Chip on Chip

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'PCoC - Power Chip on Chip'

Author: Grafiati
Published: 11 January 2025

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles

Select a source type:

Consult the lists of relevant articles, books, theses, conference reports, and other scholarly sources on the topic 'PCoC - Power Chip on Chip.'

Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.

You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.

Journal articles on the topic "PCoC - Power Chip on Chip"

1

Tan, N., and S. Eriksson. "Low-power chip-to-chip communication circuits." Electronics Letters 30, no. 21 (October 13, 1994): 1732–33. http://dx.doi.org/10.1049/el:19941178.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Yerman, AlexanderJ. "4538170 Power chip package." Microelectronics Reliability 26, no. 3 (January 1986): 594. http://dx.doi.org/10.1016/0026-2714(86)90686-4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

FOK, C. W., and D. L. PULFREY. "FULL-CHIP POWER-SUPPLY NOISE: THE EFFECT OF ON-CHIP POWER-RAIL INDUCTANCE." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 573–82. http://dx.doi.org/10.1142/s0129156402001472.

Full text
Abstract:
The importance of on-chip power-rail inductance in generating delta-I power-supply noise is examined in this paper using systematic circuit simulation of the complete integrated-circuit power net. This source of noise is compared to the resistive IR drop in the net, and to the delta-I noise due to both high-inductance- and low-inductance-bonding packages. Results are presented for a typical on-chip power net in 0.18 μm CMOS technology, and it is demonstrated that the inductance of this on-chip power net is the dominant contributor to the full-chip power-supply noise. The simultaneous switching events which produce the triggering current transients for the delta-I noise are taken to arise from core-logic switching; the mitigating, de-coupling role of the capacitance of non-switching gates within the core-logic block is considered.
APA, Harvard, Vancouver, ISO, and other styles
4

Laha, Soumyasanta, Savas Kaya, David W. Matolak, William Rayess, Dominic DiTomaso, and Avinash Kodi. "A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects." IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 34, no. 2 (February 2015): 186–98. http://dx.doi.org/10.1109/tcad.2014.2379640.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Eireiner, M., S. Henzler, X. Zhang, J. Berthold, and D. Schmitt-Landsiedel. "Impact of on-chip inductance on power supply integrity." Advances in Radio Science 6 (May 26, 2008): 227–32. http://dx.doi.org/10.5194/ars-6-227-2008.

Full text
Abstract:
Abstract. Based on product related scenarios, the impact of on-chip inductance on power supply integrity is analyzed. The impact of varying current profiles is shown to be minimal. In a regular power grid with regular bump connections, the impact of on-chip inductance on the cycle average of the supply voltage can be neglected, even for a worst case estimation of on-chip inductance. Whereas, the maximum transient power supply drop can be significantly underestimated by neglecting on-chip inductance. The impact of on-chip inductance in a System-on-Chip (SoC) environment also can be neglected if the on-chip inductance is conservativly estimated.
APA, Harvard, Vancouver, ISO, and other styles
6

Pathak, Divya, Houman Homayoun, and Ioannis Savidis. "Smart Grid on Chip: Work Load-Balanced On-Chip Power Delivery." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25, no. 9 (September 2017): 2538–51. http://dx.doi.org/10.1109/tvlsi.2017.2699644.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Kose, Selçuk, and Eby G. Friedman. "Distributed On-Chip Power Delivery." IEEE Journal on Emerging and Selected Topics in Circuits and Systems 2, no. 4 (December 2012): 704–13. http://dx.doi.org/10.1109/jetcas.2012.2226378.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Costlow, T. "Vision chip slashes power consumption." IEEE Intelligent Systems 18, no. 6 (November 2003): 6–7. http://dx.doi.org/10.1109/mis.2003.1249162.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Perotto, J.-F., C. Piguet, and C. Voirol. "One-chip low-power multiprocessor." Microprocessing and Microprogramming 28, no. 1-5 (March 1990): 129–32. http://dx.doi.org/10.1016/0165-6074(90)90161-2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Li, Jun Hui, Lei Han, Ji An Duan, and Jue Zhong. "Features of Machine Variables in Thermosonic Flip Chip." Key Engineering Materials 339 (May 2007): 257–62. http://dx.doi.org/10.4028/www.scientific.net/kem.339.257.

Full text
Abstract:
An assembly bed on thermosonic flip chip bonding was set up, two different structures of tool tips were designed, and a series of experiments on flip chip and bonding machine variables were carried out. Lift-off characteristics of thermosonic flip chip were investigated by using Scanning Electron Microscope (JSM-6360LV), and vibration features of tool tips driven by high frequency were tested by using PSV-400-M2 Laser Doppler Vibrometer. Results show that, for chip-press model, slippage and rotation phenomena between tool tip and chip have been solved by using tool with greater area tip pattern during flip-chip bonding process, and welding failures appeared in chip-collet model have been controlled. Greater area pattern on tool tip is better than small area pattern. The power of ‘n’ bumps on flip chip bonding is far smaller than that of n×(the power of single wire bonding). The power is directly proportion to vibration displacement driven by the power, high-power decrease positioning precision of flip chip bonding or result in slippage and rotation phenomena. The proper machine variables ranges for thermosonic flip chip had been obtained.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Dissertations / Theses on the topic "PCoC - Power Chip on Chip"

1

Derkacz, Pawel. "Convertisseur GaN optimisé vis-à-vis de la CEM." Electronic Thesis or Diss., Université Grenoble Alpes, 2024. http://www.theses.fr/2024GRALT067.

Full text
Abstract:
Cette thèse étudie les possibilités de réduction des interférences électromagnétiques pour les convertisseurs d'électroniques de puissance utilisant des transistors GaN dans trois domaines principaux: la stratégie de contrôle, la conception des circuits imprimés ainsi que l'agencement des composants de puissance et les éléments magnétiques à haute fréquence. Sur la base d'un convertisseur Buck, l’impact de la contribution de la commutation dure et douce sur le bruit conduit généré (mode commun (CM) et mode différentiel (DM)) a été étudiée. L'effet positif de la commutation douce sur la réduction des perturbations CEM dans une gamme de fréquence spécifique a été démontré. L'impact des attributs de la conception de l'agencement a également été observé et la nécessité de l'optimiser a été soulignée. Ensuite, une étude détaillée de l'identification des éléments parasites dans un seul bras d'onduleur est présentée. Des domaines spécifiques de préoccupation ont été détaillés et examinés plus loin dans la thèse. Le flux de travail de simulation développé dans Digital Twin utilisé pour étudier l'impact des éléments de disposition individuels sur la CEM est présenté. Le banc d'essai de laboratoire utilisé pour les mesures CEM est également présenté, ainsi qu'une description des précautions nécessaires. En outre, les deux concepts clés mis en œuvre dans l'agencement - le blindage et le Power-Chip-on-Chip (PCoC) - sont présentés. Leur efficacité dans la réduction des interférences électromagnétiques de près de 20~dB a été confirmée par la simulation et l'expérimentation. Enfin, le concept d'inducteur intégré est présenté, qui peut être mis en œuvre en même temps que les solutions précédentes. L'efficacité d'un inducteur intégré planaire connecté au point central du pont a été démontrée par des études de simulation. La méthode de l'auteur pour identifier l'impédance de l'inducteur intégré et les principaux éléments parasites (en termes de CEM) a également été développée et présentée en détail. En conclusion, ce travail présente une série de solutions qui réduisent de manière significative l'EMI dans les convertisseurs à base de GaN, qui ont été validées par simulation et expérience et qui peuvent être appliquées à tous les types de convertisseurs électroniques de puissance
The thesis investigates the possibility of EMI mitigation for power electronic converters with GaN transistors in three key areas: control strategy, layout design, and integrated magnetic filter. Based on a Buck converter, the contribution of hard and soft switching to the generated conducted noise (Common Mode (CM) and Differential Mode (DM)) has been investigated. The positive effect of soft switching on EMI reduction in a specific frequency range was demonstrated. The impact of layout design attributes was also observed and the need to optimize it was highlighted. Next, a detailed study of the identification of parasitic elements in a single inverter leg is presented. Specific areas of concern were detailed and considered later in the thesis. The developed simulation workflow in Digital Twin used to study the impact of individual layout elements on EMC is presented. The laboratory test bench used for EMC measurements is also presented, together with a description of the necessary experimental precautions. Furthermore, the two key concepts implemented in the layout - shielding and Power-Chip-on-Chip (PCoC) - are presented. Their effectiveness in reducing EMI by almost 20~dB was confirmed by simulation and experiment. Finally, the Integrated Inductor concept is presented, which can be implemented together with the previous solutions. The effectiveness of a planar Integrated Inductor connected to the middle point of the bridge was demonstrated by simulation studies. The author's method for identifying the impedance of the Integrated Inductor and the key parasitic elements (in terms of EMC) has also been developed and presented in details. In conclusion, the work presents a series of solutions that significantly reduce EMI in GaN-based converters, which have been validated by simulation and experiment and can be applied to all types of power electronic converters
APA, Harvard, Vancouver, ISO, and other styles
2

Belfiore, Guido, Laszlo Szilagyi, Ronny Henker, and Frank Ellinger. "Low power laser driver design in 28nm CMOS for on-chip and chip-to-chip optical interconnect." SPIE, 2015. https://tud.qucosa.de/id/qucosa%3A34801.

Full text
Abstract:
This paper discusses the challenges and the trade-offs in the design of laser drivers for very-short distance optical communications. A prototype integrated circuit is designed and fabricated in 28 nm super-low-power CMOS technology. The power consumption of the transmitter is 17.2 mW excluding the VCSEL that in our test has a DC power consumption of 10 mW. The active area of the driver is only 0.0045 mm². The driver can achieve an error-free (
APA, Harvard, Vancouver, ISO, and other styles
3

Ochana, Andrew. "Power cycling of flip chip assemblies." Thesis, Loughborough University, 2004. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.418328.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Mischenko, Alexandre. "On-chip cooling and power generation." Thesis, University of Cambridge, 2007. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.612857.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Peter, Eldhose. "Power efficient on-chip optical interconnects." Thesis, IIT Delhi, 2016. http://localhost:8080/iit/handle/2074/7224.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Wu, Wei-Chung. "On-chip charge pumps." Diss., Georgia Institute of Technology, 2001. http://hdl.handle.net/1853/13451.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip." Thesis, Brest, 2013. http://www.theses.fr/2013BRES0029.

Full text
Abstract:
Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoC
Multiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis
APA, Harvard, Vancouver, ISO, and other styles
8

Hamwi, Khawla. "Low Power Design Methodology and Photonics Networks on Chip for Multiprocessor System on Chip." Electronic Thesis or Diss., Brest, 2013. http://www.theses.fr/2013BRES0029.

Full text
Abstract:
Les systèmes multiprocesseurs sur puce (MPSoC)s sont fortement émergent comme principaux composants dans les systèmes embarqués à hautes performances. La principale complexité dans la conception et l’implémentation des MPSoC est la communication entre les cœurs. Les réseaux sur puce (NoC) sont considérés comme la solution pour cet effet. ITRS prédit que des centaines de cœurs seront utilisées dans la génération future de système sur puce (SoC), ce qui va donc augmenter les coûts de l’évolutivité, de bande passante et de l’implémentation des réseaux sur puce (NoC)s. Ces problèmes sont présents dans diverses tendances technologiques dans le domaine des semiconducteurs et de la photonique. Cette thèse préconise l'utilisation de la synthèse NoC comme l'approche la plus appropriée pour exploiter ces tendances technologiques et rattraper les exigences des applications. A partir de plusieurs méthodologies de conception basées sur la technologie FPGA et des techniques d'estimation basse énergie (HLS) pour plusieurs IPs, nous proposons une implémentation ASIC basée sur la technologie 3D Tezzaron. Multi-FPGA technologie est utilisée pour valider la conception MPSoC avec 64 processeurs Butterfly NoC. La synthèse NoC est basée sur le regroupement de maîtres et d’esclaves générant des architectures asymétriques avec un soutien approprié pour les demandes très haut débit par optique NoC (ONoC), tandis que les demandes de bande passante inférieure sont traitées par électronique NoC. Une programmation linéaire est proposée comme une solution pour la synthèse NoC
Multiprocessor systems on chip (MPSoC)s are strongly emerging as main components in high performance embedded systems. Several challenges can be determined in MPSoC design like the challenge which comes from interconnect infrastructure. Network-on-Chip (NOC) with multiple constraints to be satisfied is a promising solution for these challenges. ITRS predicts that hundreds of cores will be used in future generation system on chip (SoC) and thus raises the issue of scalability, bandwidth and implementation costs for NoCs. These issues are raised within the various technological trends in semiconductors and photonics. This PhD thesis advocates the use of NoC synthesis as the most appropriate approach to exploit these technological trends catch up with the applications requirements. Starting with several design methodologies based on FPGA technology and low power estimation techniques (HLS) for several IPs, we propose an ASIC implementation based on 3D Tezzaron technology. Multi-FPGA technology is used to validate MPSoC design with up to 64 processors with Butterfly NoC. NoC synthesis is based on a clustering of masters and slaves generating asymmetric architectures with appropriate support for very high bandwidth requests through Optical NoC (ONoC) while lower bandwidth requests are processed by electronic NoC. A linear programming is proposed as a solution to the NoC synthesis
APA, Harvard, Vancouver, ISO, and other styles
9

Lai, Yin Hing. "High power flip-chip light emitting diode /." View abstract or full-text, 2004. http://library.ust.hk/cgi/db/thesis.pl?ELEC%202004%20LAI.

Full text
Abstract:
Thesis (M. Phil.)--Hong Kong University of Science and Technology, 2004.
Includes bibliographical references (leaves 60-68). Also available in electronic version. Access restricted to campus users.
APA, Harvard, Vancouver, ISO, and other styles
10

Singhal, Rohit. "Data integrity for on-chip interconnects." Texas A&M University, 2003. http://hdl.handle.net/1969.1/5929.

Full text
Abstract:
With shrinking feature size and growing integration density in the Deep Sub- Micron (DSM) technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. Especially, in system-onchip (SoC) designs, where parallel interconnects run over large distances, they pose difficult research and design problems. This work presents an approach for evaluating the data carrying capacity of such wires. The method treats the delay and reliability in interconnects from an information theoretic perspective. The results point to an optimal frequency of operation for a given bus dimension for maximum data transfer rate. Moreover, this optimal frequency is higher than that achieved by present day designs which accommodate the worst case delays. This work also proposes several novel ways to approach this optimal data transfer rate in practical designs.From the analysis of signal propagation delay in long wires, it is seen that the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication theory, these "good" signals arriving early can be used to predict/correct the "few" signals that arrive late. In addition to this correction based on prediction, the approaches use coding techniques to eliminate high delay cases to generate a higher transmission rate. The work also extends communication theoretic approaches to other areas of VLSI design. Parity groups are generated based on low output delay correlation to add redundancy in combinatorial circuits. This redundancy is used to increase the frequency of operation and/or reduce the energy consumption while improving the overall reliability of the circuit.
APA, Harvard, Vancouver, ISO, and other styles
More sources

Books on the topic "PCoC - Power Chip on Chip"

1

Allard, Bruno, ed. Power Systems-On-Chip. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Silvano, Cristina, Marcello Lajolo, and Gianluca Palermo, eds. Low Power Networks-on-Chip. Boston, MA: Springer US, 2011. http://dx.doi.org/10.1007/978-1-4419-6911-8.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Silvano, Cristina. Low Power Networks-on-Chip. Boston, MA: Springer Science+Business Media, LLC, 2011.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
4

Vaisband, Inna P., Renatas Jakushokas, Mikhail Popovich, Andrey V. Mezhiba, Selçuk Köse, and Eby G. Friedman. On-Chip Power Delivery and Management. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-29395-0.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Hu, John, and Mohammed Ismail. CMOS High Efficiency On-chip Power Management. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-9526-1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Hu, John. CMOS High Efficiency On-chip Power Management. New York, NY: Springer Science+Business Media, LLC, 2011.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
7

Tanzawa, Toru. On-chip High-Voltage Generator Design. New York, NY: Springer New York, 2013.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
8

Jakushokas, Renatas, Mikhail Popovich, Andrey V. Mezhiba, Selçuk Köse, and Eby G. Friedman. Power Distribution Networks with On-Chip Decoupling Capacitors. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-7871-4.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Popovich, Mikhhail, Andrey V. Mezhiba, and Eby G. Friedman. Power Distribution Networks with On-Chip Decoupling Capacitors. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-71601-5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Jakushokas, Renatas. Power distribution networks with on-chip decoupling capacitors. 2nd ed. New York: Springer, 2011.

Find full text
APA, Harvard, Vancouver, ISO, and other styles
More sources

Book chapters on the topic "PCoC - Power Chip on Chip"

1

Veendrick, Harry. "Chip Performance and Power." In Bits on Chips, 189–201. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-76096-4_11.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Schuermans, Stefan, and Rainer Leupers. "Network on Chip Experiments." In Power Estimation on Electronic System Level using Linear Power Models, 97–140. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-030-01875-7_5.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Itoh, Kiyoo. "Low-Power Memory Circuits." In VLSI Memory Chip Design, 389–423. Berlin, Heidelberg: Springer Berlin Heidelberg, 2001. http://dx.doi.org/10.1007/978-3-662-04478-0_7.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Elrabaa, Muhammad S., Issam S. Abu-Khater, and Mohamed I. Elmasry. "BiCMOS On-Chip Drivers." In Advanced Low-Power Digital Circuit Techniques, 125–52. Boston, MA: Springer US, 1997. http://dx.doi.org/10.1007/978-1-4419-8546-0_6.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Bracke, Wouter, Robert Puers, and Chris Van Hoof. "Generic Sensor Interface Chip." In Ultra Low Power Capacitive Sensor Interfaces, 17–72. Dordrecht: Springer Netherlands, 2007. http://dx.doi.org/10.1007/978-1-4020-6232-2_3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Bakker, Fred. "The computer chip industry." In Unleashing the Power of European Innovation, 111–18. London: Routledge, 2024. http://dx.doi.org/10.4324/9781032703381-18.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

Alou, Pedro, José A. Cobos, Jesus A. Oliver, Bruno Allard, Benôit Labbe, Aleksandar Prodic, and Aleksandar Radic. "Control Strategies and CAD Approach." In Power Systems-On-Chip, 1–92. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch1.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Kulkarni, Santosh, and Cian O'Mathuna. "Magnetic Components for Increased Power Density." In Power Systems-On-Chip, 93–132. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch2.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Voiron, Frédéric. "Dielectric Components for Increased Power Density." In Power Systems-On-Chip, 133–55. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch3.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Labbe, Benoît, and Bruno Allard. "On-board Power Management DC/DC Inductive Converter." In Power Systems-On-Chip, 157–77. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2016. http://dx.doi.org/10.1002/9781119377702.ch4.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Conference papers on the topic "PCoC - Power Chip on Chip"

1

Wang, Zihao, Dexian Yan, Wenze Yuan, Xiaomeng Liu, Sheng Ding, Xiangjun Li, Zhaochun Wu, Lu Nie, and Xiaohai Cui. "Study on CPW Microwave Power Sensor Chip." In 2024 International Conference on Microwave and Millimeter Wave Technology (ICMMT), 1–3. IEEE, 2024. http://dx.doi.org/10.1109/icmmt61774.2024.10672367.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Xu, Yang, Iqbal Husain, Harvey West, Wensong Yu, and Douglas Hopkins. "Development of an ultra-high density Power Chip on Bus (PCoB) module." In 2016 IEEE Energy Conversion Congress and Exposition (ECCE). IEEE, 2016. http://dx.doi.org/10.1109/ecce.2016.7855040.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Novotny, M., J. Jankovsky, and I. Szendiuch. "Chip Power Interconnection." In 2007 30th International Spring Seminar on Electronics Technology. IEEE, 2007. http://dx.doi.org/10.1109/isse.2007.4432844.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

Carley, Larry Richard. "Chip-to-chip RF Communications and Power Delivery via On-chip Antennas." In the 24th Annual International Conference. New York, New York, USA: ACM Press, 2018. http://dx.doi.org/10.1145/3241539.3270100.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Testa, Paolo Valerio, Vincent Ries, Corrado Carta, and Frank Ellinger. "200 GHz chip-to-chip wireless power transfer." In 2018 IEEE Radio and Wireless Symposium (RWS). IEEE, 2018. http://dx.doi.org/10.1109/rws.2018.8304962.

Full text
APA, Harvard, Vancouver, ISO, and other styles
6

Oveis-Gharan, Masoud, and Gul Khan. "Power and Chip-Area Aware Network-on-Chip Modeling for System on Chip Simulation." In Seventh International Conference on Simulation Tools and Techniques. ICST, 2014. http://dx.doi.org/10.4108/icst.simutools.2014.254626.

Full text
APA, Harvard, Vancouver, ISO, and other styles
7

FOK, C. W., and D. L. PULFREY. "FULL-CHIP POWER-SUPPLY NOISE: THE EFFECT OF ON-CHIP POWER-RAIL INDUCTANCE." In Proceedings of the 2002 Workshop on Frontiers in Electronics (WOFE-02). WORLD SCIENTIFIC, 2003. http://dx.doi.org/10.1142/9789812796912_0031.

Full text
APA, Harvard, Vancouver, ISO, and other styles
8

Meijer, M., J. P. de Gyvez, and R. Otten. "On-chip digital power supply control for system-on-chip applications." In ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design. IEEE, 2005. http://dx.doi.org/10.1109/lpe.2005.195537.

Full text
APA, Harvard, Vancouver, ISO, and other styles
9

Meijer, Maurice, José Pineda de Gyvez, and Ralph Otten. "On-chip digital power supply control for system-on-chip applications." In the 2005 international symposium. New York, New York, USA: ACM Press, 2005. http://dx.doi.org/10.1145/1077603.1077677.

Full text
APA, Harvard, Vancouver, ISO, and other styles
10

Onizuka, Kohei, Makoto Takamiya, Hiroshi Kawaguchi, and Takayasu Sakurai. "A design methodology of chip-to-chip wireless power transmission system." In 2007 IEEE International Conference on Integrated Circuit Design and Technology. IEEE, 2007. http://dx.doi.org/10.1109/icicdt.2007.4299559.

Full text
APA, Harvard, Vancouver, ISO, and other styles

Reports on the topic "PCoC - Power Chip on Chip"

1

Lee, Fred, Qiang Li, Yipeng Su, Shu Ji, David Reusch, Dongbin Hou, Mingkai Mu, and Wenli Zhang. Power Supplies on a Chip (PSOC). Office of Scientific and Technical Information (OSTI), January 2015. http://dx.doi.org/10.2172/1167001.

Full text
APA, Harvard, Vancouver, ISO, and other styles
2

Mehrotra, Vivek. Integrated Power Chip Converter for Solid State Lighting. Office of Scientific and Technical Information (OSTI), September 2013. http://dx.doi.org/10.2172/1569260.

Full text
APA, Harvard, Vancouver, ISO, and other styles
3

Michelogiannakis, George, and John Shalf. Variable-Width Datapath for On-Chip Network Static Power Reduction. Office of Scientific and Technical Information (OSTI), November 2013. http://dx.doi.org/10.2172/1164909.

Full text
APA, Harvard, Vancouver, ISO, and other styles
4

SCHROEPPEL, RICHARD C., CHERYL L. BEAVER, TIMOTHY J. DRAELOS, RITA A. GONZALES, and RUSSELL D. MILLER. A Low-Power VHDL Design for an Elliptic Curve Digital Signature Chip. Office of Scientific and Technical Information (OSTI), September 2002. http://dx.doi.org/10.2172/802030.

Full text
APA, Harvard, Vancouver, ISO, and other styles
5

Rahman, Abdur, Mohammad Marufuzzaman, Jason Street, James Wooten, Veera Gnaneswar Gude, Randy Buchanan, and Haifeng Wang. A comprehensive review on wood chip moisture content assessment and prediction. Engineer Research and Development Center (U.S.), February 2024. http://dx.doi.org/10.21079/11681/48220.

Full text
Abstract:
Wood chips are the primary sources of raw materials for numerous industries, including pelleting mills, biorefineries, pulp-and-paper industries, and biomass-based power generation facilities. Unfortunately, when wood chips are utilized as a renewable and environmentally friendly resource, industries are constantly challenged by the consistency of the wood chip qualities (e.g., moisture/ash contents, size distributions) - a historically recognized problem on a global scale. Among other wood chip quality attributes, the moisture content is considered the most pressing one as it directly impacts the energy content, storage stability, and handling properties of the raw and finished products. Therefore, accurate wood chip moisture content prediction can help optimize the drying process and reduce energy consumption. In this review, a survey was conducted on various techniques and models employed for predicting wood chip moisture content. The advantages and limitations of these approaches, as well as their potential applications and future directions were also discussed. This review aims to provide a comprehensive overview of the current state-of-the-art in wood chip moisture content prediction and to highlight the challenges and opportunities for further research and development in this field.
APA, Harvard, Vancouver, ISO, and other styles
6

Raychev, Nikolay. Can human thoughts be encoded, decoded and manipulated to achieve symbiosis of the brain and the machine. Web of Open Science, October 2020. http://dx.doi.org/10.37686/nsrl.v1i2.76.

Full text
Abstract:
This article discusses the current state of neurointerface technologies, not limited to deep electrode approaches. There are new heuristic ideas for creating a fast and broadband channel from the brain to artificial intelligence. One of the ideas is not to decipher the natural codes of nerve cells, but to create conditions for the development of a new language for communication between the human brain and artificial intelligence tools. Theoretically, this is possible if the brain "feels" that by changing the activity of nerve cells that communicate with the computer, it is possible to "achieve" the necessary actions for the body in the external environment, for example, to take a cup of coffee or turn on your favorite music. At the same time, an artificial neural network that analyzes the flow of nerve impulses must also be directed at the brain, trying to guess the body's needs at the moment with a minimum number of movements. The most important obstacle to further progress is the problem of biocompatibility, which has not yet been resolved. This is even more important than the number of electrodes and the power of the processors on the chip. When you insert a foreign object into your brain, it tries to isolate itself from it. This is a multidisciplinary topic not only for doctors and psychophysiologists, but also for engineers, programmers, mathematicians. Of course, the problem is complex and it will be possible to overcome it only with joint efforts.
APA, Harvard, Vancouver, ISO, and other styles
7

Sela, Hanan, Eduard Akhunov, and Brian J. Steffenson. Population genomics, linkage disequilibrium and association mapping of stripe rust resistance genes in wild emmer wheat, Triticum turgidum ssp. dicoccoides. United States Department of Agriculture, January 2014. http://dx.doi.org/10.32747/2014.7598170.bard.

Full text
Abstract:
The primary goals of this project were: (1) development of a genetically characterized association panel of wild emmer for high resolution analysis of the genetic basis of complex traits; (2) characterization and mapping of genes and QTL for seedling and adult plant resistance to stripe rust in wild emmer populations; (3) characterization of LD patterns along wild emmer chromosomes; (4) elucidation of the multi-locus genetic structure of wild emmer populations and its correlation with geo-climatic variables at the collection sites. Introduction In recent years, Stripe (yellow) rust (Yr) caused by Pucciniastriiformis f. sp. tritici(PST) has become a major threat to wheat crops in many parts of the world. New races have overcome most of the known resistances. It is essential, therefore, that the search for new genes will continue, followed by their mapping by molecular markers and introgression into the elite varieties by marker-assisted selection (MAS). The reservoir of genes for disease and pest resistance in wild emmer wheat (Triticumdicoccoides) is an important resource that must be made available to wheat breeders. The majority of resistance genes that were introgressed so far in cultivated wheat are resistance (R) genes. These genes, though confering near-immunity from the seedling stage, are often overcome by the pathogen in a short period after being deployed over vast production areas. On the other hand, adult-plant resistance (APR) is usually more durable since it is, in many cases, polygenic and confers partial resistance that may put less selective pressure on the pathogen. In this project, we have screened a collection of 480 wild emmer accessions originating from Israel for APR and seedling resistance to PST. Seedling resistance was tested against one Israeli and 3 North American PST isolates. APR was tested on accessions that did not have seedling resistance. The APR screen was conducted in two fields in Israel and in one field in the USA over 3 years for a total of 11 replicates. We have found about 20 accessions that have moderate stripe rust APR with infection type (IT<5), and about 20 additional accessions that have novel seedling resistance (IT<3). We have genotyped the collection using genotyping by sequencing (GBS) and the 90K SNP chip array. GBS yielded a total 341K SNP that were filtered to 150K informative SNP. The 90K assay resulted in 11K informative SNP. We have conducted a genome-wide association scan (GWAS) and found one significant locus on 6BL ( -log p >5). Two novel loci were found for seedling resistance. Further investigation of the 6BL locus and the effect of Yr36 showed that the 6BL locus and the Yr36 have additive effect and that the presence of favorable alleles of both loci results in reduction of 2 grades in the IT score. To identify alleles conferring adaption to extreme climatic conditions, we have associated the patterns of genomic variation in wild emmer with historic climate data from the accessions’ collection sites. The analysis of population stratification revealed four genetically distinct groups of wild emmer accessions coinciding with their geographic distribution. Partitioning of genomic variance showed that geographic location and climate together explain 43% of SNPs among emmer accessions with 19% of SNPs affected by climatic factors. The top three bioclimatic factors driving SNP distribution were temperature seasonality, precipitation seasonality, and isothermality. Association mapping approaches revealed 57 SNPs associated with these bio-climatic variables. Out of 21 unique genomic regions controlling heading date variation, 10 (~50%) overlapped with SNPs showing significant association with at least one of the three bioclimatic variables. This result suggests that a substantial part of the genomic variation associated with local adaptation in wild emmer is driven by selection acting on loci regulating flowering. Conclusions: Wild emmer can serve as a good source for novel APR and seedling R genes for stripe rust resistance. APR for stripe rust is a complex trait conferred by several loci that may have an additive effect. GWAS is feasible in the wild emmer population, however, its detection power is limited. A panel of wild emmer tagged with more than 150K SNP is available for further GWAS of important traits. The insights gained by the bioclimatic-gentic associations should be taken into consideration when planning conservation strategies.
APA, Harvard, Vancouver, ISO, and other styles
You might also be interested in the extended bibliographies on the topic 'PCoC - Power Chip on Chip' for particular source types:
Journal articles Dissertations / Theses Books
We offer discounts on all premium plans for authors whose works are included in thematic literature selections. Contact us to get a unique promo code!

To the bibliography