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Journal articles on the topic 'Patterned Ground Shield'

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Author: Grafiati
Published: 10 December 2022
Last updated: 29 January 2023

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1

Syahadah Yusof, Nur, Norlaili Mohd Noh, Jagadheswaran Rajendran, Asrulnizam Abd Manaf, Shukri Korakkottil Kunhi Mohd, Yusman Mohd. Yusof, Harikrishnan Ramiah, and Mohamed Fauzi Bin Packeer Mohamed. "Electronic controlled CMOS inductor with patterned metal ground shields for fine inductance tuning application." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (May 1, 2019): 937. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp937-948.

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This paper is on an inductance fine tuning technique which benefits from the idea of varying the number of metal plates of an inductor’s pattern ground shield (PGS) shorted to ground to change its magnetic fields. This technique is unique because the geometry and physical shape of the inductor remains untouched from its form in the process design kit (PDK) while the inductance is being tuned. The number of metal shields shorted to ground was controlled by an electronic circuit which consists of analog-to-digital converters and active switches. Both Sonnet EM simulator and Cadence Virtuoso were used for the inductor and circuit simulations. From the simulation, it was found that the inductance increased while the Q-factor decreased as more metal shields were shorted to ground. For instance, at 1.6 GHz, the simulated inductance was 8.8 nH when all metals were floated and 9.4 nH when all metals were shorted to ground. On the other hand, the simulated Q-factor was 10.4 when all metals were floated and 9.8 when all metals were shorted to ground. From both simulation and measured results, both inductance and inductance tuning range increased with frequency. From the measured results too, the inductance observed was 9.4 nH at 1.6 GHz, 10.8 nH at 2 GHz, and 13.5 nH at 2.5 GHz when all the metal shields were shorted to ground. The inductance tuning range was 6.2% at 1.6 GHz, 12.5% at 2 GHz, and 20% at 2.5 GHz. The measured results showed good correlation with the simulated results trend, but with smaller value of inductance, inductance tuning range and Q-factor.
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2

Tiemeijer, Luuk F., Ralf M. T. Pijper, Ramon J. Havens, and Olivier Hubert. "Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes." IEEE Transactions on Microwave Theory and Techniques 55, no. 3 (March 2007): 561–70. http://dx.doi.org/10.1109/tmtt.2007.891691.

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3

Nishikawa, Kazuyasu, Kenji Shintani, and Satoshi Yamakawa. "Pattern Density Effect on Characteristics of Spiral Inductor with Patterned Ground Shield." Japanese Journal of Applied Physics 47, no. 6 (June 13, 2008): 4454–60. http://dx.doi.org/10.1143/jjap.47.4454.

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4

Jinglin Shi, W. Y. Yin, Huailin Liao, and Jun-Fa Mao. "The enhancement of Q factor for patterned ground shield inductors at high temperatures." IEEE Transactions on Magnetics 42, no. 7 (July 2006): 1873–75. http://dx.doi.org/10.1109/tmag.2006.874186.

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5

Barakat, Adel, Muhammad Hanif, and Ramesh K. Pokharel. "Miniaturized low loss 60 GHz CMOS mixed coupled BPF with patterned ground shield." Microwave and Optical Technology Letters 58, no. 3 (January 27, 2016): 697–99. http://dx.doi.org/10.1002/mop.29650.

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6

Ichihashi, Masahiro, and Haruichi Kanaya. "A high-frequency, low-coupling 8-shaped differential inductor with patterned ground shield." Microwave and Optical Technology Letters 60, no. 11 (October 18, 2018): 2704–7. http://dx.doi.org/10.1002/mop.31469.

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7

Tiemeijer, Luuk F., Ralf M. T. Pijper, Ramon J. Havens, and Olivier Hubert. "Corrections on "Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes"." IEEE Transactions on Microwave Theory and Techniques 55, no. 8 (August 2007): 1811. http://dx.doi.org/10.1109/tmtt.2007.901593.

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8

Guan, X., Y. Jin, and C. Nguyen. "Design of high-performance compact CMOS distributed amplifiers with on-chip patterned ground shield inductors." Electronics Letters 45, no. 15 (2009): 791. http://dx.doi.org/10.1049/el.2009.1102.

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9

Wu, Rongxiang, Julong Chen, and Xiangming Fang. "A Novel On-Chip Transformer With Patterned Ground Shield for High Common-Mode Transient Immunity Isolated Signal Transfer." IEEE Electron Device Letters 39, no. 11 (November 2018): 1712–15. http://dx.doi.org/10.1109/led.2018.2871049.

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10

Lowther, R., and San-Gug Lee. "On-chip interconnect lines with patterned ground shields." IEEE Microwave and Guided Wave Letters 10, no. 2 (2000): 49–51. http://dx.doi.org/10.1109/75.843097.

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11

Shi, Jinglin, Wen-Yan Yin, Kai Kang, Jun-Fa Mao, and Le-Wei Li. "Frequency-Thermal Characterization of On-Chip Transformers With Patterned Ground Shields." IEEE Transactions on Microwave Theory and Techniques 55, no. 1 (January 2007): 1–12. http://dx.doi.org/10.1109/tmtt.2006.888934.

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12

Lin, Yo-Sheng, Chang-Zhi Chen, Hsiao-Bin Liang, and Chi-Chen Chen. "High-Performance On-Chip Transformers With Partial Polysilicon Patterned Ground Shields (PGS)." IEEE Transactions on Electron Devices 54, no. 1 (January 2007): 157–60. http://dx.doi.org/10.1109/ted.2006.887044.

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13

Yue, C. P., and S. S. Wong. "On-chip spiral inductors with patterned ground shields for Si-based RF ICs." IEEE Journal of Solid-State Circuits 33, no. 5 (May 1998): 743–52. http://dx.doi.org/10.1109/4.668989.

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14

Zhang, Zhiqiang, and Xiaoping Liao. "Micromachined GaAs MMIC-Based Spiral Inductors With Metal Shores and Patterned Ground Shields." IEEE Sensors Journal 12, no. 6 (June 2012): 1853–60. http://dx.doi.org/10.1109/jsen.2011.2178066.

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15

Karjalainen, Päivi H., and Pekka Heino. "Methods for Reducing Power Loss in On-Wafer Inductors." Journal of Microelectronics and Electronic Packaging 3, no. 4 (October 1, 2006): 194–200. http://dx.doi.org/10.4071/1551-4897-3.4.194.

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The easist way to improve the quality and decrease the size of the passive components is to improve their layout. On-wafer CMOS inductors with different patterned ground shields (PGS) and different layouts of metal coils aimed at reducing component power losses are presented in this work. Narrow extra wires at the edges of spirals and continuous via arrays in the spirals have been found to be effective. Moreover, the small n-well areas in the middle of a component and small polysilicon parts beside the coils do not harm the operation of the inductor. These results provide motivation for processing passive components stacked on top of each other.
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16

POKHAREL, Ramesh K., Xin LIU, Dayang A. A. MAT, Ruibing DONG, Haruichi KANAYA, and Keiji YOSHIDA. "60 GHz Millimeter-Wave CMOS Integrated On-Chip Open Loop Resonator Bandpass Filters on Patterned Ground Shields." IEICE Transactions on Electronics E96.C, no. 2 (2013): 270–76. http://dx.doi.org/10.1587/transele.e96.c.270.

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17

Zheng, Tao, Mei Han, Gaowei Xu, and Le Luo. "A NOVEL WL-INTEGRATED LOW-INSERTION-LOSS FILTER WITH SUSPENDED HIGH-Q SPIRAL INDUCTOR AND PATTERNED GROUND SHIELDS." Progress In Electromagnetics Research C 59 (2015): 41–49. http://dx.doi.org/10.2528/pierc15071101.

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18

Yusof, Nur S., Norlaili M. Noh, Jagadheswaran Rajendran, Asrulnizam A. Manaf, Yusman M. Yusof, Harikrishnan Ramiah, Shukri K. K. Mohd, and Mohamed F. P. Mohamed. "Patterned Ground Shield for Inductance Fine-tuning." IETE Journal of Research, February 26, 2020, 1–15. http://dx.doi.org/10.1080/03772063.2020.1726827.

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