Relevant bibliographies by topics / Patterned Ground Shield

Academic literature on the topic 'Patterned Ground Shield'

Author: Grafiati
Published: 10 December 2022
Last updated: 29 January 2023

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Journal articles on the topic "Patterned Ground Shield"

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Syahadah Yusof, Nur, Norlaili Mohd Noh, Jagadheswaran Rajendran, Asrulnizam Abd Manaf, Shukri Korakkottil Kunhi Mohd, Yusman Mohd. Yusof, Harikrishnan Ramiah, and Mohamed Fauzi Bin Packeer Mohamed. "Electronic controlled CMOS inductor with patterned metal ground shields for fine inductance tuning application." Indonesian Journal of Electrical Engineering and Computer Science 14, no. 2 (May 1, 2019): 937. http://dx.doi.org/10.11591/ijeecs.v14.i2.pp937-948.

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Abstract:
This paper is on an inductance fine tuning technique which benefits from the idea of varying the number of metal plates of an inductor’s pattern ground shield (PGS) shorted to ground to change its magnetic fields. This technique is unique because the geometry and physical shape of the inductor remains untouched from its form in the process design kit (PDK) while the inductance is being tuned. The number of metal shields shorted to ground was controlled by an electronic circuit which consists of analog-to-digital converters and active switches. Both Sonnet EM simulator and Cadence Virtuoso were used for the inductor and circuit simulations. From the simulation, it was found that the inductance increased while the Q-factor decreased as more metal shields were shorted to ground. For instance, at 1.6 GHz, the simulated inductance was 8.8 nH when all metals were floated and 9.4 nH when all metals were shorted to ground. On the other hand, the simulated Q-factor was 10.4 when all metals were floated and 9.8 when all metals were shorted to ground. From both simulation and measured results, both inductance and inductance tuning range increased with frequency. From the measured results too, the inductance observed was 9.4 nH at 1.6 GHz, 10.8 nH at 2 GHz, and 13.5 nH at 2.5 GHz when all the metal shields were shorted to ground. The inductance tuning range was 6.2% at 1.6 GHz, 12.5% at 2 GHz, and 20% at 2.5 GHz. The measured results showed good correlation with the simulated results trend, but with smaller value of inductance, inductance tuning range and Q-factor.
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Tiemeijer, Luuk F., Ralf M. T. Pijper, Ramon J. Havens, and Olivier Hubert. "Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes." IEEE Transactions on Microwave Theory and Techniques 55, no. 3 (March 2007): 561–70. http://dx.doi.org/10.1109/tmtt.2007.891691.

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Nishikawa, Kazuyasu, Kenji Shintani, and Satoshi Yamakawa. "Pattern Density Effect on Characteristics of Spiral Inductor with Patterned Ground Shield." Japanese Journal of Applied Physics 47, no. 6 (June 13, 2008): 4454–60. http://dx.doi.org/10.1143/jjap.47.4454.

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Jinglin Shi, W. Y. Yin, Huailin Liao, and Jun-Fa Mao. "The enhancement of Q factor for patterned ground shield inductors at high temperatures." IEEE Transactions on Magnetics 42, no. 7 (July 2006): 1873–75. http://dx.doi.org/10.1109/tmag.2006.874186.

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Barakat, Adel, Muhammad Hanif, and Ramesh K. Pokharel. "Miniaturized low loss 60 GHz CMOS mixed coupled BPF with patterned ground shield." Microwave and Optical Technology Letters 58, no. 3 (January 27, 2016): 697–99. http://dx.doi.org/10.1002/mop.29650.

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Ichihashi, Masahiro, and Haruichi Kanaya. "A high-frequency, low-coupling 8-shaped differential inductor with patterned ground shield." Microwave and Optical Technology Letters 60, no. 11 (October 18, 2018): 2704–7. http://dx.doi.org/10.1002/mop.31469.

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Tiemeijer, Luuk F., Ralf M. T. Pijper, Ramon J. Havens, and Olivier Hubert. "Corrections on "Low-Loss Patterned Ground Shield Interconnect Transmission Lines in Advanced IC Processes"." IEEE Transactions on Microwave Theory and Techniques 55, no. 8 (August 2007): 1811. http://dx.doi.org/10.1109/tmtt.2007.901593.

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Guan, X., Y. Jin, and C. Nguyen. "Design of high-performance compact CMOS distributed amplifiers with on-chip patterned ground shield inductors." Electronics Letters 45, no. 15 (2009): 791. http://dx.doi.org/10.1049/el.2009.1102.

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Wu, Rongxiang, Julong Chen, and Xiangming Fang. "A Novel On-Chip Transformer With Patterned Ground Shield for High Common-Mode Transient Immunity Isolated Signal Transfer." IEEE Electron Device Letters 39, no. 11 (November 2018): 1712–15. http://dx.doi.org/10.1109/led.2018.2871049.

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Lowther, R., and San-Gug Lee. "On-chip interconnect lines with patterned ground shields." IEEE Microwave and Guided Wave Letters 10, no. 2 (2000): 49–51. http://dx.doi.org/10.1109/75.843097.

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Book chapters on the topic "Patterned Ground Shield"

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"OnChip Spiral Inductors with Patterned Ground Shields for SiBased RF IC^apos;s." In Phase-Locking in High-Performance Systems. IEEE, 2009. http://dx.doi.org/10.1109/9780470545492.ch12.

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Conference papers on the topic "Patterned Ground Shield"

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Wang, Xin, Wen-Yan Yin, and Jun-Fa Mao. "Parameter Characterization of Silicon-Based Patterned Shield and Patterned Ground Shield Coplanar Waveguides." In 2008 Global Symposium on Millimeter Waves (GSMM 2008). IEEE, 2008. http://dx.doi.org/10.1109/gsmm.2008.4534581.

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Mat, D. A. A., R. K. Pokharel, R. Sapawi, H. Kanaya, and K. Yoshida. "Low-loss 60 GHz patterned ground shield CPW transmission line." In TENCON 2011 - 2011 IEEE Region 10 Conference. IEEE, 2011. http://dx.doi.org/10.1109/tencon.2011.6129285.

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Ondica, Robert, Martin Kovac, David Maljar, and Viera Stopjakova. "Fully Integrated Multi-layer Stacked Structure of Integrated Inductor with Patterned Ground Shield." In 2022 18th Biennial Baltic Electronics Conference (BEC). IEEE, 2022. http://dx.doi.org/10.1109/bec56180.2022.9935589.

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Wu, Jhen-Nong, Yan-Ming Chang, Zih-Yao Shen, and Hsiao-Chin Chen. "Investigation on CMOS on-Chip Inductors Using Various Patterned Ground/Floating Shield Techniques." In 2021 International Conference on Electronic Communications, Internet of Things and Big Data (ICEIB). IEEE, 2021. http://dx.doi.org/10.1109/iceib53692.2021.9686404.

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Jin, Xiangliang, Yongfeng Sun, and Xiao Xiao. "Modeling of Monolithic Spiral Inductors with Patterned Ground Shield for Si-Based RF IC's." In 2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM). IEEE, 2018. http://dx.doi.org/10.1109/icam.2018.8596564.

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Sun, X., G. Carchon, Y. Kita, K. Chiba, T. Tani, and W. De Raedt. "Experimental analysis of above-IC inductor performance with different patterned ground shield configurations and dummy metals." In Proceedings of the 36th European Microwave Conference. IEEE, 2006. http://dx.doi.org/10.1109/eumc.2006.281176.

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Rautio, James C., James D. Merrill, and Michael J. Kobasa. "Efficient electromagnetic analysis of spiral inductor patterned ground shields." In 2013 IEEE International Conference on Microwaves, Communications, Antennas and Electronic Systems (COMCAS). IEEE, 2013. http://dx.doi.org/10.1109/comcas.2013.6685228.

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Sahu, Abhishek, Bethany Grayczyk, Mohammad Almalkawi, Vijay Devabhaktuni, and Peter Aaen. "High-Q spiral inductors with multilayered split-ring resonator (SRR) patterned ground shields." In 2014 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting. IEEE, 2014. http://dx.doi.org/10.1109/aps.2014.6904505.

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Wen-Yan Yin. "On-chip EMC issue: the implementation of patterned ground shields for silicon devices." In 2007 18th International Zurich Symposium on Electromagnetic Compatibility. IEEE, 2007. http://dx.doi.org/10.1109/emczur.2007.4388183.

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Yue and Wong. "On-chip Spiral Inductors With Patterned Ground Shields For Si-based RF IC's." In 1993 Symposium on VLSI Circuits. IEEE, 1997. http://dx.doi.org/10.1109/vlsic.1997.623819.

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