Journal articles: 'Parity check decoder'

1

Zhang, Zhe, Liang Zhou, and Zhi Heng Zhou. "Design of A Parallel Decoding Method for LDPC Code Generated via Primitive Polynomial." Electronics 10, no. 4 (February 9, 2021): 425. http://dx.doi.org/10.3390/electronics10040425.

Full text

Abstract:

An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. In this method, the sub-decoders have two types. The first one contains only one decoding module using the original parity-check constraints to implement a belief propagation (BP) algorithm. The second one consists of a pre-decode module and a decoding module. The parity-check matrices for pre-decode modules are generated by the parity-check constraints of the sub-sequences sampled from an m-sequence. Then, the number of iterations of the BP process in each pre-decode module is set as half of the girth of the parity-check matrix, resulting in the elimination of the impact of short cycles. Using maximum a posterior (MAP), the least metric selector (LMS) finally picks out a codeword from the outputs of sub-decoders. Our simulation results show that the performance gain of the proposed parallel decoding method with five sub-decoders is about 0.4 dB, compared to the single-decoder decoding method at the bit error rate (BER) of 10−5.

APA, Harvard, Vancouver, ISO, and other styles

2

Jan, Qasim, Shahid Hussain, Muhammad Furqan, Zhiwen Pan, Nan Liu, and Xiaohu You. "Parity-Check-CRC Concatenated Polar Codes SSCFlip Decoder." Electronics 11, no. 23 (November 22, 2022): 3839. http://dx.doi.org/10.3390/electronics11233839.

Full text

Abstract:

Successive cancellation flip decoding requires a large number of extra successive cancellation decoding attempts at low signal-to-noise ratios (SNRs), resulting in high decoding complexity. In addition, it has a long decoding latency. Although modifications have been proposed in successive cancellation flip decoding, these still have high computational complexity at low SNRs due to a huge number of additional successive cancellation decoding attempts. It is desirable to detect the unsuccessful successive cancellation decoding process at an early stage in the additional successive cancellation flip attempts and stop it that can reduce the decoding complexity. This paper combines the parity-check-CRC concatenated polar codes with the low-latency simplified successive cancellation decoding and proposes a parity-check-CRC concatenated polar codes simplified successive cancellation flip (PC-CRC-SSCFlip) decoder. It further employs the parity-check vector to identify the unsuccessful simplified successive cancellation flip decoding at an early stage and terminates so that it can minimize the decoding complexity on average. Additionally, this work proposes an error-prone flipping list by incorporating the empirically observed indices based on channel-induced error distribution along with the first bit of each Rate-1 node. The proposed technique can identify more than one error-prone bit through a flipping list and correct them. In addition, the parity-check vector further narrows down the search space for the identification of erroneous decisions. Simulation results show that 60% of unsuccessful additional successive cancellation decoding attempts terminate early rather than decode the whole codeword. The proposed PC-CRC-SSCFlip decoder has approximately 0.7 dB and 0.3 dB gains over successive cancellation and successive cancellation flip decoders, respectively, at a fixed block error rate (BLER) = 10−3. Additionally, it reduces the average computational complexity and decoding latency of the successive cancellation flip decoder at low-to-medium SNRs while approaching successive cancellation decoding complexity at medium-to-high SNRs.

APA, Harvard, Vancouver, ISO, and other styles

3

Sułek, W. "Pipeline processing in low-density parity-check codes hardware decoder." Bulletin of the Polish Academy of Sciences: Technical Sciences 59, no. 2 (June 1, 2011): 149–55. http://dx.doi.org/10.2478/v10175-011-0019-9.

Full text

Abstract:

Pipeline processing in low-density parity-check codes hardware decoderLow-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.

APA, Harvard, Vancouver, ISO, and other styles

4

Arul Murugan, C., B. Banuselvasaraswathy, K. Gayathree, and M. Ishwarya Niranjana. "Efficient high throughput decoding architecture for non-binary LDPC codes." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 195. http://dx.doi.org/10.14419/ijet.v7i2.8.10407.

Full text

Abstract:

This article, deals with efficient trellis inbuilt decoding architecture for non-binary Linear Density Parity Check (LDPC) codes. In this decoder, a bidirectional recursion is embedded to enhance the layered scheduling and decoding latency, which in turn is used to minimize the number of iterations compared to existing techniques. Consequently, it is necessary to increase the throughput for improving the efficiency of the system. In addition, a compression technique is implemented for reducing the requirements of memory and the area. Trellis based decoder was used to reinforce the check node processing. The proposed decoder for LDPC codes yields high throughput when compared to other similar decoders presented in preceding works. The designed architecture was implemented using Cadence Virtuoso software. This decoder provides a throughput of about 39.21 Mb/s at clock frequency of 190MHz.

APA, Harvard, Vancouver, ISO, and other styles

5

Zhang, Chuan, Lulu Ge, Xingchi Zhang, Wei Wei, Jing Zhao, Zaichen Zhang, Zhongfeng Wang, and Xiaohu You. "A Uniform Molecular Low-Density Parity Check Decoder." ACS Synthetic Biology 8, no. 1 (December 4, 2018): 82–90. http://dx.doi.org/10.1021/acssynbio.8b00304.

Full text

APA, Harvard, Vancouver, ISO, and other styles

6

Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (May 31, 2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

Full text

Abstract:

Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.

APA, Harvard, Vancouver, ISO, and other styles

7

Revathy, M., and R. Saravanan. "A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/327357.

Full text

Abstract:

Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

APA, Harvard, Vancouver, ISO, and other styles

8

Baldi, Marco, Giovanni Cancellieri, and Franco Chiaraluce. "Iterative Soft-Decision Decoding of Binary Cyclic Codes." Journal of Communications Software and Systems 4, no. 2 (June 22, 2008): 142. http://dx.doi.org/10.24138/jcomss.v4i2.227.

Full text

Abstract:

Binary cyclic codes achieve good error correction performance and allow the implementation of very simpleencoder and decoder circuits. Among them, BCH codesrepresent a very important class of t-error correcting codes, with known structural properties and error correction capability. Decoding of binary cyclic codes is often accomplished through hard-decision decoders, although it is recognized that softdecision decoding algorithms can produce significant coding gain with respect to hard-decision techniques. Several approaches have been proposed to implement iterative soft-decision decoding of binary cyclic codes. We study the technique based on “extended parity-check matrices”, and show that such method is not suitable for high rates or long codes. We propose a new approach, based on “reduced parity-check matrices” and “spread parity-check matrices”, that can achieve better correction performance in many practical cases, without increasing the complexity.

APA, Harvard, Vancouver, ISO, and other styles

9

Yao, Chang-Kun, Yun-Ching Tang, and Hongchin Lin. "Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA." Journal of Circuits, Systems and Computers 24, no. 02 (November 27, 2014): 1550026. http://dx.doi.org/10.1142/s0218126615500267.

Full text

Abstract:

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

APA, Harvard, Vancouver, ISO, and other styles

10

Ismail, Mohamed, Imran Ahmed, and Justin Coon. "Low Power Decoding of LDPC Codes." ISRN Sensor Networks 2013 (January 17, 2013): 1–12. http://dx.doi.org/10.1155/2013/650740.

Full text

Abstract:

Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.

APA, Harvard, Vancouver, ISO, and other styles

11

Mao, Yun, Ying Guo, Jun Peng, Xueqin Jiang, and Moon Ho Lee. "Double-Layer Low-Density Parity-Check Codes over Multiple-Input Multiple-Output Channels." International Journal of Antennas and Propagation 2012 (2012): 1–6. http://dx.doi.org/10.1155/2012/716313.

Full text

Abstract:

We introduce a double-layer code based on the combination of a low-density parity-check (LDPC) code with the multiple-input multiple-output (MIMO) system, where the decoding can be done in both inner-iteration and outer-iteration manners. The present code, called low-density MIMO code (LDMC), has a double-layer structure, that is, one layer defines subcodes that are embedded in each transmission vector and another glues these subcodes together. It supports inner iterations inside the LDPC decoder and outeriterations between detectors and decoders, simultaneously. It can also achieve the desired design rates due to the full rank of the deployed parity-check matrix. Simulations show that the LDMC performs favorably over the MIMO systems.

APA, Harvard, Vancouver, ISO, and other styles

12

Lin, Cheng-Hung, Tzu-Hsuan Huang, Shu-Yen Lin, and Yu-Hsuan Lee. "Design and Implementation of Operation-Reduced LDPC Decoder Based on a Check Node Stopping Scheme." Journal of Circuits, Systems and Computers 26, no. 02 (November 3, 2016): 1750028. http://dx.doi.org/10.1142/s0218126617500281.

Full text

Abstract:

In this paper, we propose an operation-reduced low-density parity check (LDPC) decoder design and implementation by stopping reliable operation of check nodes of the iterative two-phase message passing (TPMP) min-sum algorithm (MSA). A check node stopping (CNS) scheme is used to tag reliability of check nodes by detecting the magnitudes of the check node belief messages with a threshold. The operation of reliable check nodes tagged by the CNS scheme can be stopped in the later iterations. The proposed LDPC decoder that employs the CNS scheme can significantly terminate the redundant operations of check nodes and efficiently reduce the power consumption of decoder. From the simulations under WiMAX QC LDPC decoding with high channel quality, the CNS scheme achieves up to 12% stopping rate of check nodes with a loss of coding gain less than 0.1 dB. The WiMAX QC LDPC decoder chip that employs the CNS scheme is implemented by a 90-nm CMOS process. Compared with the LDPC decoder that employs no CNS scheme, the overall power dissipation of the proposed LDPC decoder is decreased by 4.1% with 0.5% area overhead.

APA, Harvard, Vancouver, ISO, and other styles

13

Kuc, Mateusz, Wojciech Sułek, and Dariusz Kania. "Low Power QC-LDPC Decoder Based on Token Ring Architecture." Energies 13, no. 23 (November 30, 2020): 6310. http://dx.doi.org/10.3390/en13236310.

Full text

Abstract:

The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

APA, Harvard, Vancouver, ISO, and other styles

14

Khittiwitchayakul, Sirawit, Watid Phakphisut, and Pornchai Supnithi. "Associated Sectors of Magnetic Recording Systems Using Spatially Coupled LDPC Codes." ECTI Transactions on Electrical Engineering, Electronics, and Communications 20, no. 1 (February 18, 2022): 10–21. http://dx.doi.org/10.37936/ecti-eec.2022201.246094.

Full text

Abstract:

In traditional magnetic recording systems, non-associated sectors are mainly adopted, whereby two consecutive sectors are decoded independently by the low-density parity-check (LDPC) codes. In this paper, we propose a magnetic recording system with associated sectors, constructed using spatially coupled low-density parity-check (SC-LDPC) codes. If the SC-LDPC decoder cannot correct the erroneous bits in the current sector, it can request information stored in previous sectors to improve decoding performance. Moreover, we modify protograph-based extrinsic information transfer (P-EXIT) charts to examine the theoretical performance of SC-LDPC codes applied to both non-associated and associated sectors. Our theoretical results show that the associated sectors achieve significant performance gains compared to the traditional non-associated sectors.

APA, Harvard, Vancouver, ISO, and other styles

15

Anbuselvi, M., P. Saravanan, and S. Joseph Gladwin. "Analysis of a Code Construction Method for Non-Binary Quasi-Cyclic Irregular Low Density Parity Check Decoder." Journal of Computational and Theoretical Nanoscience 15, no. 2 (February 1, 2018): 719–24. http://dx.doi.org/10.1166/jctn.2018.7151.

Full text

Abstract:

Non-binary LDPC codes is a class of linear block code outperform in the short and moderate block length, closer to Shannon's limit. The numerical strength of the decoder is proportional to the sparsity of the parity check matrix. A Hierarchically Diagonal Parity Check Matrix (HDPCM) with better sparseness is constructed to optimize the computation complexity and decoding performance. The decoder based on the proposed matrix using FFT-SP decoding algorithm is analyzed, with different modulation schemes and channel environment. The positive impact of the constructed matrix is elaborated, concludes with the suitability of the HDPCM structure in AWGN channel and BPSK modulation environment.

APA, Harvard, Vancouver, ISO, and other styles

16

Thi Bao Nguyen, Tram, Tuy Nguyen Tan, and Hanho Lee. "Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication." Electronics 10, no. 4 (February 22, 2021): 516. http://dx.doi.org/10.3390/electronics10040516.

Full text

Abstract:

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

APA, Harvard, Vancouver, ISO, and other styles

17

Chaibi, Hasna. "Serial Genetic Algorithm Decoder for Low Density Parity Check Codes." International Journal of Communications, Network and System Sciences 08, no. 09 (2015): 358–66. http://dx.doi.org/10.4236/ijcns.2015.89034.

Full text

APA, Harvard, Vancouver, ISO, and other styles

18

Oh, Daesun, and Keshab K. Parhi. "Low Complexity Decoder Architecture for Low-Density Parity-Check Codes." Journal of Signal Processing Systems 56, no. 2-3 (May 30, 2008): 217–28. http://dx.doi.org/10.1007/s11265-008-0231-5.

Full text

APA, Harvard, Vancouver, ISO, and other styles

19

Awais, Muhammad, and Carlo Condo. "Flexible LDPC Decoder Architectures." VLSI Design 2012 (June 26, 2012): 1–16. http://dx.doi.org/10.1155/2012/730835.

Full text

Abstract:

Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.

APA, Harvard, Vancouver, ISO, and other styles

20

Beuschel, C., and H. J. Pfleiderer. "Hardwarearchitektur für einen universellen LDPC Decoder." Advances in Radio Science 7 (May 19, 2009): 213–18. http://dx.doi.org/10.5194/ars-7-213-2009.

Full text

Abstract:

Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.

APA, Harvard, Vancouver, ISO, and other styles

21

Wu, Xi, and Yafeng Wang. "Improving Polar-Coded SCMA System by Information Coupling and Parity Check." Sensors 20, no. 23 (November 25, 2020): 6740. http://dx.doi.org/10.3390/s20236740.

Full text

Abstract:

In this paper, the uplink information-coupled polar-coded sparse code multiple access (PC-SCMA) system is proposed. For this system, we first design the encoding method of systematic joint parity check and CRC-aided (PCCA) polar code. Using the systematic PCCA-polar code as base code, the partially information-coupled (PIC) polar code is constructed. Then, a joint iterative detection and successive cancellation list (SCL)-decoding receiver is proposed for the PC-SCMA system. For the receiver, the coupled polar decoder’s extrinsic messages are calculated by the Bayes rule and soft cancellation (SCAN) algorithm. Based on the extrinsic information transfer (EXIT) idea, the PIC PCCA-polar code is optimized. Simulation results demonstrate that the PIC PCCA-PC-SCMA system outperforms the other polar (or LDPC) coded SCMA systems at various code rates and channel configurations. Additionally, compared with an uncoupled PC-SCMA system with SCL decoder, the complexity of PIC PCCA-PC-SCMA is reduced at a high Eb/N0

APA, Harvard, Vancouver, ISO, and other styles

22

Hao, Ning, Yang An Zhang, Jin Nan Zhang, Ming Lun Zhang, and Xue Guang Yuan. "An Application of LDPC Code for Wireless Coherent-Light Commutation in Atmospheric Channel." Applied Mechanics and Materials 347-350 (August 2013): 1864–67. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1864.

Full text

Abstract:

Low Density Parity Check code is more and more taken seriously in high-speed transmission. In this article we represent a LDPC coder and decoder which based on IEEE802.16e and realize the coder and decoder with Virtex-5 FPGA. By using Matlab to make an off-line system simulation, we analyzed and compared the LDPC performance under the different length of code for LDPC coder then analyzed the influence of different iteration to the LDPC BER performance of decoder.

APA, Harvard, Vancouver, ISO, and other styles

23

Kuc, Mateusz, Wojciech Sułek, and Dariusz Kania. "FPGA-Oriented LDPC Decoder for Cyber-Physical Systems." Mathematics 8, no. 5 (May 4, 2020): 723. http://dx.doi.org/10.3390/math8050723.

Full text

Abstract:

A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

APA, Harvard, Vancouver, ISO, and other styles

24

Jiao, Xiaopeng, Haoyuan Wei, Jianjun Mu, and Chao Chen. "Improved ADMM Penalized Decoder for Irregular Low-Density Parity-Check Codes." IEEE Communications Letters 19, no. 6 (June 2015): 913–16. http://dx.doi.org/10.1109/lcomm.2015.2421445.

Full text

APA, Harvard, Vancouver, ISO, and other styles

25

Zhou, Hua, Erbao Li, and Jing Lei. "Serially concatenated belief propagation decoder for low-density parity-check codes." IET Communications 11, no. 14 (September 28, 2017): 2133–40. http://dx.doi.org/10.1049/iet-com.2016.1318.

Full text

APA, Harvard, Vancouver, ISO, and other styles

26

Grospellier, Antoine, Lucien Grouès, Anirudh Krishna, and Anthony Leverrier. "Combining hard and soft decoders for hypergraph product codes." Quantum 5 (April 15, 2021): 432. http://dx.doi.org/10.22331/q-2021-04-15-432.

Full text

Abstract:

Hypergraph product codes are a class of constant-rate quantum low-density parity-check (LDPC) codes equipped with a linear-time decoder called small-set-flip (SSF). This decoder displays sub-optimal performance in practice and requires very large error correcting codes to be effective. In this work, we present new hybrid decoders that combine the belief propagation (BP) algorithm with the SSF decoder. We present the results of numerical simulations when codes are subject to independent bit-flip and phase-flip errors. We provide evidence that the threshold of these codes is roughly 7.5% assuming an ideal syndrome extraction, and remains close to 3% in the presence of syndrome noise. This result subsumes and significantly improves upon an earlier work by Grospellier and Krishna (arXiv:1810.03681). The low-complexity high-performance of these heuristic decoders suggests that decoding should not be a substantial difficulty when moving from zero-rate surface codes to constant-rate LDPC codes and gives a further hint that such codes are well-worth investigating in the context of building large universal quantum computers.

APA, Harvard, Vancouver, ISO, and other styles

27

Raza, Hasnain, Syed Azhar Ali Zaidi, Aamir Rashid, and Shafiq Haider. "An area efficient and high throughput implementation of layered min-sum iterative construction a posteriori probability LDPC decoder." PLOS ONE 16, no. 3 (March 29, 2021): e0249269. http://dx.doi.org/10.1371/journal.pone.0249269.

Full text

Abstract:

Area efficient and high speed forward error correcting codes decoder are the demand of many high speed next generation communication standards. This paper explores a low complexity decoding algorithm of low density parity check codes, called the min-sum iterative construction a posteriori probability (MS-IC-APP), for this purpose. We performed the error performance analysis of MS-IC-APP for a (648,1296) regular QC-LDPC code and proposed an area and throughput optimized hardware implementation of MS-IC-APP. We proposed to use the layered scheduling of MS-IC-APP and performed other optimizations at architecture level to reduce the area and to increase the throughput of the decoder. Synthesis results show 6.95 times less area and 4 times high throughput as compared to the standard min-sum decoder. The area and throughput are also comparable to the improved variants of hard-decision bit-flipping (BF) decoders, whereas, the simulation results show a coding gain of 2.5 over the best implementation of BF decoder in terms of error performance.

APA, Harvard, Vancouver, ISO, and other styles

28

Gurskiy, S. S., and N. S. Mogilevskaya. "On the modification of bit-flipping decoder of LDPC-codes." Advanced Engineering Research 21, no. 1 (April 4, 2021): 96–104. http://dx.doi.org/10.23947/2687-1653-2021-21-1-96-104.

Full text

Abstract:

Introduction. In all types of digital communication, error control coding techniques are used. Many digital communication standards, such as Wi-Fi and 5G, use low density parity check (LDPC) codes. These codes are popular because they provide building encoders and decoders with low computational complexity. This work objective is to increase the error correcting capability of the well-known bit-flipping decoder (BF) of LDPC-codes. For this purpose, a modification of the decoder is built, which enables to dynamically control one of its main parameters whose choice affects significantly the quality of decoding.Materials and Methods. The well-known bit-flipping decoder of binary LDPC-codes is considered. This decoder has several parameters that are not rigidly bound with the code parameters. The dependence of the decoding quality on the selection of the output parameters of the bit-flipping decoder was investigated through simulation modeling. It is shown that the decoding results in this case are significantly affected by the input parameter of the decoder — threshold T. A modification of the BF-decoder of binary LDPC-codes has been developed, in which it is proposed to set the threshold dynamically during the execution of the algorithm depending on the error rate. A comparative analysis of the error- correcting capability of decoders is carried out by the simulation modeling method.Results. A lemma on the maximum value of the decoder threshold T is formulated and proved. Upper bounds for the number of operations are found for the original and modified decoders. A simulation model that implements a digital noise-immune communication channel has been built. In the model, the initial data is encoded with a given LDPC-code, then it is made noisy by additive uniformly distributed errors, and thereafter, it is decoded in turn by the bit-flipping algorithm with different threshold T parameters, as well as by a modified decoder. Based on the input and output data, the correction capacity of the decoders used is estimated. Experiments have shown that the error-correcting capability of the modified decoder in the range of the real error rate is higher than that of the original decoder, regardless of the selection of its parameters.Discussion and Conclusions. The lemma, proved in the paper, sets the upper bound on the threshold value in the original decoder, which simplifies its adjustment. The developed modification of the decoder has a better error- correcting capability compared to the original decoder. Nevertheless, the complexity of the modification is slightly increased compared to the original algorithm. It has been pointed out that the decoding quality of a modified decoder develops with a decrease in the number of cycles in the Tanner graph and an increase in the length of the code.Keywords: LDPC-codes, error-correcting capability, dynamic threshold, binary symmetric channel, experimental research.

APA, Harvard, Vancouver, ISO, and other styles

29

Li, Yunfeng, Yingchun Li, Nan Ye, Tianyang Chen, Zhijie Wang, and Junjie Zhang. "High Throughput Priority-Based Layered QC-LDPC Decoder with Double Update Queues for Mitigating Pipeline Conflicts." Sensors 22, no. 9 (May 5, 2022): 3508. http://dx.doi.org/10.3390/s22093508.

Full text

Abstract:

A high-throughput layered decoder for quasi-cyclic (QC) low-density parity-check (LDPC) codes is required for communication systems. The preferred way to improve the throughput is to insert pipeline stages and increase the operating frequency, which suffers from pipeline conflicts at the same time. A priority-based layered schedule is proposed to keep the updates of log-likelihood ratios (LLRs) as frequent as possible when pipeline conflicts happen. To reduce pipeline conflicts, we also propose double update queues for layered decoders. The proposed double update queues improve the percentage of updated LLRs per iteration. Benefitting from these, the performance loss of the proposed decoder for the fifth generation (5G) new radio (NR) is reduced from 0.6 dB to 0.2 dB using the same quantization compared with the state-of-the-art work. As a result, the throughput of the proposed decoder improved up to 2.85 times when the signal-to-noise ratio (SNR) was equal to 5.9 dB.

APA, Harvard, Vancouver, ISO, and other styles

30

Raveendran, Nithin, and Bane Vasić. "Trapping Sets of Quantum LDPC Codes." Quantum 5 (October 14, 2021): 562. http://dx.doi.org/10.22331/q-2021-10-14-562.

Full text

Abstract:

Iterative decoders for finite length quantum low-density parity-check (QLDPC) codes are attractive because their hardware complexity scales only linearly with the number of physical qubits. However, they are impacted by short cycles, detrimental graphical configurations known as trapping sets (TSs) present in a code graph as well as symmetric degeneracy of errors. These factors significantly degrade the decoder decoding probability performance and cause so-called error floor. In this paper, we establish a systematic methodology by which one can identify and classify quantum trapping sets (QTSs) according to their topological structure and decoder used. The conventional definition of a TS from classical error correction is generalized to address the syndrome decoding scenario for QLDPC codes. We show that the knowledge of QTSs can be used to design better QLDPC codes and decoders. Frame error rate improvements of two orders of magnitude in the error floor regime are demonstrated for some practical finite-length QLDPC codes without requiring any post-processing.

APA, Harvard, Vancouver, ISO, and other styles

31

Raveendran, Nithin, and Bane Vasić. "Trapping Sets of Quantum LDPC Codes." Quantum 5 (October 14, 2021): 562. http://dx.doi.org/10.22331/q-2021-10-14-562.

Full text

Abstract:

Iterative decoders for finite length quantum low-density parity-check (QLDPC) codes are attractive because their hardware complexity scales only linearly with the number of physical qubits. However, they are impacted by short cycles, detrimental graphical configurations known as trapping sets (TSs) present in a code graph as well as symmetric degeneracy of errors. These factors significantly degrade the decoder decoding probability performance and cause so-called error floor. In this paper, we establish a systematic methodology by which one can identify and classify quantum trapping sets (QTSs) according to their topological structure and decoder used. The conventional definition of a TS from classical error correction is generalized to address the syndrome decoding scenario for QLDPC codes. We show that the knowledge of QTSs can be used to design better QLDPC codes and decoders. Frame error rate improvements of two orders of magnitude in the error floor regime are demonstrated for some practical finite-length QLDPC codes without requiring any post-processing.

APA, Harvard, Vancouver, ISO, and other styles

32

Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (January 5, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.1.

Full text

Abstract:

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

APA, Harvard, Vancouver, ISO, and other styles

33

Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (November 14, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.2.

Full text

Abstract:

Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

APA, Harvard, Vancouver, ISO, and other styles

34

Lin, Cheng-Hung, Hsin-Hao Su, Tang-Syun Chen, and Cheng-Kai Lu. "Reconfigurable Low-Density Parity-Check (LDPC) Decoder for Multi-Standard 60 GHz Wireless Local Area Networks." Electronics 11, no. 5 (February 26, 2022): 733. http://dx.doi.org/10.3390/electronics11050733.

Full text

Abstract:

In this study, a reconfigurable low-density parity-check (LDPC) decoder is designed with good hardware sharing for IEEE 802.15.3c, 802.11ad, and 802.11ay standards. This architecture flexibly supports 12 types of parity-check matrix. The switching network adopts an architecture that can flexibly switch between different inputs and achieves a low hardware complexity. The check node unit adopts a switchable 8/16/32 reconfigurable structure to match different row weights at different code rates and uses the normalised probability min-sum algorithm to simplify the structure of searching for the minimum value. Finally, the chip is implemented using the TSMC 40 nm CMOS process, based on the IEEE 802.11ad standard decoder, extended to support the IEEE 802.15.3c standard, and upwardly compatible with the next-generation advanced standard IEEE 802.11ay. The chip core size was 1.312 mm × 1.312 mm, the operating frequency was 117 MHz when the maximum number of iterations was five with the power consumption of 57.1 mW, and the throughput of 5.24 Gbps and 3.90 Gbsp was in the IEEE 802.11ad and 802.5.3c standards, respectively.

APA, Harvard, Vancouver, ISO, and other styles

35

Thuan. "IMPLEMENTATION OF SOME DECODING ALGORITHMS FOR NB-LDPC CODES ON FPGA." Journal of Military Science and Technology, no. 69A (November 16, 2020): 1–10. http://dx.doi.org/10.54939/1859-1043.j.mst.69a.2020.1-10.

Full text

Abstract:

Non-binary low-density parity-check codes (NB-LDPC) provide better error correction performance in comparison with their counterparts. However, the NB-LDPC decoder has a very high complexity, especially the processing of the check node unit. This paper evaluates the error correction performance of some decoding algorithms for NB-LDPC codes in different fields with different codeword lengths. The paper also presents the results of the implementation a decoder structure for the NB-LDPC (35,23) over GF(8) on the Spartan 6 board. Analysis and evaluation results show that decoding quality on hardware is equivalent to simulation results on software, demonstrating high feasibility in implementing decoder on a hardware platform, capable of application in devices of the advanced communication systems or high-speed read-and-write data storages.

APA, Harvard, Vancouver, ISO, and other styles

36

Han, Ji Qu, and Li Liu. "Implementation of Decoder for Effective Quasi-Cyclic LDPC Codes Based on FPGA." Advanced Materials Research 791-793 (September 2013): 1867–71. http://dx.doi.org/10.4028/www.scientific.net/amr.791-793.1867.

Full text

Abstract:

Designers are increasingly relying on FPGA-based emulation to evaluate the performance of LDPC codes. In this paper, we propose a novel approximate lower triangular structure for the parity part of the parity-check matrix of QC-LDPC codes. Next, a high speed partially parallel decoder architecture which based on the Offset BP-based decoding algorithm is proposed. The results indicate that the frequency can reach 100MHz and its throughput rate can reach 113Mbps.

APA, Harvard, Vancouver, ISO, and other styles

37

Wang, Biao. "Novel Early Termination Method of an ADMM-Penalized Decoder for LDPC Codes in the IoT." Security and Communication Networks 2022 (October 14, 2022): 1–13. http://dx.doi.org/10.1155/2022/4599105.

Full text

Abstract:

As a critical communication technology, low-density parity-check (LDPC) codes are widely concerned with the Internet of things (IoT). To increase the convergence rate of the alternating direction method of multiplier (ADMM)-penalized decoder for LDPC codes, a novel early termination (ET) method is presented by computing the average sum of the hard decision (ASHD) during each ADMM iteration. In terms of the flooding scheduling and layered scheduling ADMM-penalized decoders, the simulation results show that the proposed ET method can significantly reduce the average number of iterations at low signal-to-noise ratios (SNRs) with negligible decoding performance loss.

APA, Harvard, Vancouver, ISO, and other styles

38

Le, Khoa, Fakhreddine Ghaffari, Lounis Kessal, David Declercq, Emmanuel Boutillon, Chris Winstead, and Bane Vasic. "A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes." IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 1 (January 2019): 403–16. http://dx.doi.org/10.1109/tcsi.2018.2849679.

Full text

APA, Harvard, Vancouver, ISO, and other styles

39

Zheng, Hao, Zhe Zhao, Xiangming Li, and Hangcheng Han. "Design of a (480, 240) CMOS analog low-density parity-check decoder." China Communications 14, no. 8 (August 2017): 41–53. http://dx.doi.org/10.1109/cc.2017.8014346.

Full text

APA, Harvard, Vancouver, ISO, and other styles

40

Chung, Biwoong, Pilsang Yoon, Haksun Kim, Jooyoun Park, Jongyong Park, and Euiseok Hwang. "A Modified Low-Density Parity-Check Decoder for Holographic Data Storage System." Japanese Journal of Applied Physics 46, no. 6B (June 22, 2007): 3812–15. http://dx.doi.org/10.1143/jjap.46.3812.

Full text

APA, Harvard, Vancouver, ISO, and other styles

41

Declercq, David. "Non-Binary Decoder Diversity for Dense or Locally-Dense Parity-Check Codes." IEEE Transactions on Communications 59, no. 3 (March 2011): 729–39. http://dx.doi.org/10.1109/tcomm.2011.010411.080527.

Full text

APA, Harvard, Vancouver, ISO, and other styles

42

Cai, Fang, and Xinmiao Zhang. "Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 11 (November 2013): 2010–23. http://dx.doi.org/10.1109/tvlsi.2012.2226920.

Full text

APA, Harvard, Vancouver, ISO, and other styles

43

Dai, Jingxin, Hang Yin, Yansong Lv, Weizhang Xu, and Zhanxin Yang. "Multi-Gbps LDPC Decoder on GPU Devices." Electronics 11, no. 21 (October 25, 2022): 3447. http://dx.doi.org/10.3390/electronics11213447.

Full text

Abstract:

To meet the high throughput requirement of communication systems, the design of high-throughput low-density parity-check (LDPC) decoders has attracted significant attention. This paper proposes a high-throughput GPU-based LDPC decoder, aiming at the large-scale data process scenario, which optimizes the decoder from the perspectives of the decoding parallelism and data scheduling strategy, respectively. For decoding parallelism, the intra-codeword parallelism is fully exploited by combining the characteristics of the flooding-based decoding algorithm and GPU programming model, and the inter-codeword parallelism is improved using the single-instruction multiple-data (SIMD) instructions. For the data scheduling strategy, the utilization of off-chip memory is optimized to satisfy the demands of large-scale data processing. The experimental results demonstrate that the decoder achieves 10 Gbps throughput by incorporating the early termination mechanism on general-purpose GPU (GPGPU) devices and can also achieve a high-throughput and high-power-efficiency performance on low-power embedded GPU (EGPU) devices. Compared with the state-of-the-art work, the proposed decoder had a × 1.787 normalized throughput speedup at the same error correcting performance.

APA, Harvard, Vancouver, ISO, and other styles

44

Stark, Maximilian, Jan Lewandowsky, and Gerhard Bauch. "Information-Bottleneck Decoding of High-Rate Irregular LDPC Codes for Optical Communication Using Message Alignment." Applied Sciences 8, no. 10 (October 11, 2018): 1884. http://dx.doi.org/10.3390/app8101884.

Full text

Abstract:

In high-throughput applications, low-complexity and low-latency channel decoders are inevitable. Hence, for low-density parity-check (LDPC) codes, message passing decoding has to be implemented with coarse quantization—that is, the exchanged beliefs are quantized with a small number of bits. This can result in a significant performance degradation with respect to decoding with high-precision messages. Recently, so-called information-bottleneck decoders were proposed which leverage a machine learning framework (i.e., the information bottleneck method) to design coarse-precision decoders with error-correction performance close to high-precision belief-propagation decoding. In these decoders, all conventional arithmetic operations are replaced by look-up operations. Irregular LDPC codes for next-generation fiber optical communication systems are characterized by high code rates and large maximum node degrees. Consequently, the implementation complexity is mainly influenced by the memory required to store the look-up tables. In this paper, we show that the complexity of information-bottleneck decoders remains manageable for irregular LDPC codes if our proposed construction approach is deployed. Furthermore, we reveal that in order to design information bottleneck decoders for arbitrary degree distributions, an intermediate construction step which we call message alignment has to be included. Exemplary numerical simulations show that incorporating message alignment in the construction yields a 4-bit information bottleneck decoder which performs only 0.15 dB worse than a double-precision belief propagation decoder and outperforms a min-sum decoder.

APA, Harvard, Vancouver, ISO, and other styles

45

El habti El idrissi, Anas, Rachid El Gouri, and Hlou Laamari. "Conception of a new LDPC decoder with hardware implementation on FPGA card." International Journal of Engineering & Technology 3, no. 4 (September 18, 2014): 451. http://dx.doi.org/10.14419/ijet.v3i4.3185.

Full text

Abstract:

Low Density Parity-Check codes are one of the hottest topics in coding theory nowadays. Equipped with very fast encoding and decoding algorithms, LDPC codes are very attractive both theoretically and practically. In this paper, A simplified algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity, this algorithm is based on a simple matrix equation which must be resolved in order to calculate all possible solutions of this equation, and then a simple circuit will be used to determine the errors produced during the transmission channel. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of LDPC codes on FPGA card. Keywords: Bit-Flipping Algorithm, Error Detection, FPGA Card, LDPC Decoder, Matrix Equation.

APA, Harvard, Vancouver, ISO, and other styles

46

Ganin, Dmitriy V., Mokhammed A. Y. Damdam, and Aleksandr L. Savkin. "PERMUTATION DECODING IN LOW-POWER WIRELESS SENSOR NETWORKS." Автоматизация процессов управления 2, no. 68 (2022): 37–44. http://dx.doi.org/10.35752/1991-2927-2022-2-68-37-44.

Full text

Abstract:

Wireless sensor networks are currently considered for many subject areas as effective communication systems, including, for example, industrial and agricultural facilities and enterprises, monitoring of sensors of transport security systems, medicine applications, environmental and weather monitoring, etc. In such systems, the correction code (CC) is a classic approach used to increase the reliability of the data transmission channel while simultaneously reducing the required transmitted signal power, called the energy gain code. At the same time, the power of the transmitter is reduced due to additional power consumption in the receiver decoder. Stronger codes provide better performance with lower power requirements, but have more complex decoders with higher power consumption than relatively simple error control systems. If the additional power consumption at the output of the decoder exceeds the savings in transmitted power due to the use of CC, then such a code will not be energy efficient compared to a system with a non-redundant code. Various codes can be used to protect data, while the best codes for which the critical distance turns out to be large according to a number of studies are codes with a low parity check density. The paper proposes an alternative variant based on the synthesis of a permutation decoding system using the method of localization of a limited number of permutations and the organization of additional parity checks exclusively for the verification bits of the CC using the Bayesian approach to iterative transformations of integer soft solutions of symbols.

APA, Harvard, Vancouver, ISO, and other styles

47

Xie, TianJiao, Bo Li, Mao Yang, and Zhongjiang Yan. "LDPC Decoder of High Speed Multi-Rate DVB-S2 Based on FPGA." Xibei Gongye Daxue Xuebao/Journal of Northwestern Polytechnical University 37, no. 2 (April 2019): 299–307. http://dx.doi.org/10.1051/jnwpu/20193720299.

Full text

Abstract:

A multi-rate LDPC decoder architecture for DVB-S2 codes based on FPGA is proposed. Through elementary transformation on the parity check matrices of DVB-S2 LDPC codes, a new matrix whose left is a QC sub-matrix and right is Transformation of Staircase lower triangular (TST) sub-matrix is obtained. The QC and TST are designed separately, therefore the successful experience of the most popular Quasi-Cyclic (QC) LDPC decoder architecture can be drawn on. While for TST sub-matrix, the variable nodes updating only need to be considered and the check nodes updating is realized compatibility with QC sub-matrix. Based on the proposed architectures, a multi-rate LDPC decoder implemented on Xilinx XC7VX485T FPGA can achieve the maximum decoding throughput of 2.5 Gbit/s at the 20 iterations when the operating frequency is 250 MHz, which demonstrates the highest throughput compared with the state-of-the-art works.

APA, Harvard, Vancouver, ISO, and other styles

48

Zuo, Yun Hua, Jun Yang, and Xiao Yu Cheng. "Design and Implementation of Manchester CODEC Based on FPGA." Applied Mechanics and Materials 273 (January 2013): 805–9. http://dx.doi.org/10.4028/www.scientific.net/amm.273.805.

Full text

Abstract:

This paper designed and realized Manchester encoder and decoder based on FPGA. The M sequence generator produced input baseband signal, Manchester CODEC possessed parity check function, and the output signals of encoding and decoding were stable. This design used VHDL language programme, encoder and decoder used modular design, simulated and tested in Altera development software Quartus II 8.0, and downloaded to FPGA chip Cyclone II EP2C35F672C6 for verification. The results showed that the design scheme is good to realize Manchester CODEC, and possesses good stability and reliability.

APA, Harvard, Vancouver, ISO, and other styles

49

Panteleev, Pavel, and Gleb Kalachev. "Degenerate Quantum LDPC Codes With Good Finite Length Performance." Quantum 5 (November 22, 2021): 585. http://dx.doi.org/10.22331/q-2021-11-22-585.

Full text

Abstract:

We study the performance of medium-length quantum LDPC (QLDPC) codes in the depolarizing channel. Only degenerate codes with the maximal stabilizer weight much smaller than their minimum distance are considered. It is shown that with the help of OSD-like post-processing the performance of the standard belief propagation (BP) decoder on many QLDPC codes can be improved by several orders of magnitude. Using this new BP-OSD decoder we study the performance of several known classes of degenerate QLDPC codes including hypergraph product codes, hyperbicycle codes, homological product codes, and Haah's cubic codes. We also construct several interesting examples of short generalized bicycle codes. Some of them have an additional property that their syndromes are protected by small BCH codes, which may be useful for the fault-tolerant syndrome measurement. We also propose a new large family of QLDPC codes that contains the class of hypergraph product codes, where one of the used parity-check matrices is square. It is shown that in some cases such codes have better performance than hypergraph product codes. Finally, we demonstrate that the performance of the proposed BP-OSD decoder for some of the constructed codes is better than for a relatively large surface code decoded by a near-optimal decoder.

APA, Harvard, Vancouver, ISO, and other styles

50

TSANG, TONY. "A METHOD FOR PERFORMANCE MODELING AND EVALUATION OF LDPC DECODER ARCHITECTURE." International Journal of Modeling, Simulation, and Scientific Computing 04, no. 02 (June 2013): 1350003. http://dx.doi.org/10.1142/s1793962313500037.

Full text

Abstract:

This paper presents a high-throughput memory efficient decoder for low density parity check (LDPC) codes in the high-rate wireless personal area network application. The novel techniques which can apply to our selected LDPC code is proposed, including parallel blocked layered decoding architecture and simplification of the WiGig networks. State-of-the-art flexible LDPC decoders cannot simultaneously achieve the high throughput mandated by these standards and the low power needed for mobile applications. This work develops a flexible, fully pipelined architecture for the IEEE 802.11ad standard capable of achieving both goals. We use Real Time–Performance Evaluation Process Algebra (RT-PEPA) to evaluate a typical LDPC Decoder system's performance. The approach is more convenient, flexible, and lower cost than the former simulation method which needs to develop special hardware and software tools. Moreover, we can easily analyze how changes in performance depend on changes in a particular mode by supplying ranges for parameter values.

APA, Harvard, Vancouver, ISO, and other styles

Journal articles on the topic 'Parity check decoder'

Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles