Academic literature on the topic 'Parity check decoder'
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Journal articles on the topic "Parity check decoder"
Zhang, Zhe, Liang Zhou, and Zhi Heng Zhou. "Design of A Parallel Decoding Method for LDPC Code Generated via Primitive Polynomial." Electronics 10, no. 4 (February 9, 2021): 425. http://dx.doi.org/10.3390/electronics10040425.
Full textJan, Qasim, Shahid Hussain, Muhammad Furqan, Zhiwen Pan, Nan Liu, and Xiaohu You. "Parity-Check-CRC Concatenated Polar Codes SSCFlip Decoder." Electronics 11, no. 23 (November 22, 2022): 3839. http://dx.doi.org/10.3390/electronics11233839.
Full textSułek, W. "Pipeline processing in low-density parity-check codes hardware decoder." Bulletin of the Polish Academy of Sciences: Technical Sciences 59, no. 2 (June 1, 2011): 149–55. http://dx.doi.org/10.2478/v10175-011-0019-9.
Full textArul Murugan, C., B. Banuselvasaraswathy, K. Gayathree, and M. Ishwarya Niranjana. "Efficient high throughput decoding architecture for non-binary LDPC codes." International Journal of Engineering & Technology 7, no. 2.8 (March 19, 2018): 195. http://dx.doi.org/10.14419/ijet.v7i2.8.10407.
Full textZhang, Chuan, Lulu Ge, Xingchi Zhang, Wei Wei, Jing Zhao, Zaichen Zhang, Zhongfeng Wang, and Xiaohu You. "A Uniform Molecular Low-Density Parity Check Decoder." ACS Synthetic Biology 8, no. 1 (December 4, 2018): 82–90. http://dx.doi.org/10.1021/acssynbio.8b00304.
Full textDinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (May 31, 2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.
Full textRevathy, M., and R. Saravanan. "A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/327357.
Full textBaldi, Marco, Giovanni Cancellieri, and Franco Chiaraluce. "Iterative Soft-Decision Decoding of Binary Cyclic Codes." Journal of Communications Software and Systems 4, no. 2 (June 22, 2008): 142. http://dx.doi.org/10.24138/jcomss.v4i2.227.
Full textYao, Chang-Kun, Yun-Ching Tang, and Hongchin Lin. "Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA." Journal of Circuits, Systems and Computers 24, no. 02 (November 27, 2014): 1550026. http://dx.doi.org/10.1142/s0218126615500267.
Full textIsmail, Mohamed, Imran Ahmed, and Justin Coon. "Low Power Decoding of LDPC Codes." ISRN Sensor Networks 2013 (January 17, 2013): 1–12. http://dx.doi.org/10.1155/2013/650740.
Full textDissertations / Theses on the topic "Parity check decoder"
Vijayakumar, Suresh Mikler Armin. "FPGA implementation of low density parity check codes decoder." [Denton, Tex.] : University of North Texas, 2009. http://digital.library.unt.edu/permalink/meta-dc-11003.
Full textZhang, Kai. "High-Performance Decoder Architectures For Low-Density Parity-Check Codes." Digital WPI, 2012. https://digitalcommons.wpi.edu/etd-dissertations/17.
Full textKopparthi, Sunitha. "Flexible encoder and decoder designs for low-density parity-check codes." Diss., Manhattan, Kan. : Kansas State University, 2010. http://hdl.handle.net/2097/4190.
Full textHussein, Ahmed Refaey Ahmed. "Universal Decoder for Low Density Parity Check, Turbo and Convolutional Codes." Thesis, Université Laval, 2011. http://www.theses.ulaval.ca/2011/28154/28154.pdf.
Full textSelvarathinam, Anand Manivannan. "High throughput low power decoder architectures for low density parity check codes." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2529.
Full textCai, Fang. "Efficient VLSI Architectures for Non-binary Low Density Parity Check Decoding." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300821245.
Full textShadab, Rakin Muhammad. "Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7582.
Full textYang, Lei. "VLSI implementation of low-error-floor multi-rate capacity-approaching low-density parity-check code decoder /." Thesis, Connect to this title online; UW restricted, 2006. http://hdl.handle.net/1773/5966.
Full textVon, Leipzig Mirko. "Code generation and simulation of an automatic, flexible QC-LDPC hardware decoder." Thesis, Stellenbosch : Stellenbosch University, 2015. http://hdl.handle.net/10019.1/96835.
Full textENGLISH ABSTRACT: Iterative error correcting codes such as LDPC codes have become prominent in modern forward error correction systems. A particular subclass of LDPC codes known as quasicyclic LDPC codes has been incorporated in numerous high speed wireless communication and video broadcasting standards. These standards feature multiple codes with varying codeword lengths and code rates and require a high throughput. Flexible hardware that is capable of decoding multiple quasi-cyclic LDPC codes is therefore desirable. This thesis investigates binary quasi-cyclic LDPC codes and designs a generic, flexible VHDL decoder. The decoder is further enhanced to automatically select the most likely decoder based on the initial a posterior probability of the parity-check equation syndromes. A software system is developed that generates hardware code for such a decoder based on a small user specification. The system is extended to provide performance simulations for this generated decoder.
AFRIKAANSE OPSOMMING: Iteratiewe foutkorreksiekodes soos LDPC-kodes word wyd gebruik in moderne voorwaartse foutkorreksiestelsels. ’n Subklas van LDPC-kodes, bekend as kwasisikliese LDPC-kodes, word in verskeie hoëspoed-kommunikasie- en video-uitsaaistelselstandaarde gebruik. Hierdie standaarde inkorporeer verskeie kodes van wisselende lengtes en kodetempos, en vereis hoë deurset. Buigsame apparatuur, wat die vermoë het om ’n verskeidenheid kwasisikliese LDPC-kodes te dekodeer, is gevolglik van belang. Hierdie tesis ondersoek binêre kwasisikliese LDPC-kodes, en ontwerp ’n generiese, buigsame VHDL-dekodeerder. Die dekodeerder word verder verbeter om outomaties die mees waarskynlike dekodeerder te selekteer, gebaseer op die aanvanklike a posteriori-waarskynlikheid van die pariteitstoetsvergelykings se sindrome. ’n Programmatuurstelsel word ontwikkel wat die fermware-kode vir so ’n dekodeerder genereer, gebaseer op ’n beknopte gebruikerspesifikasie. Die stelsel word uitgebrei om werksverrigting te simuleer vir die gegenereerde dekodeerder.
Yang, Lan. "An Area-Efficient Architecture for the Implementation of LDPC Decoder." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576.
Full textBook chapters on the topic "Parity check decoder"
Benhayoun, Mhammed, Mouhcine Razi, Anas Mansouri, and Ali Ahaitouf. "Efficient Memory Parity Check Matrix Optimization for Low Latency Quasi Cyclic LDPC Decoder." In Lecture Notes in Electrical Engineering, 71–79. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6259-4_5.
Full textLou, Der-Chyuan, Jiang-Lung Liu, and Hao-Kuan Tso. "Evolution of Information-Hiding Technology." In Information Security and Ethics, 144–54. IGI Global, 2008. http://dx.doi.org/10.4018/978-1-59904-937-3.ch010.
Full textConference papers on the topic "Parity check decoder"
Praveena, H., and K. Kalyani. "FPGA implementation of Parity Check Matrix based Low Density Parity Check Decoder." In 2018 2nd International Conference on Inventive Systems and Control (ICISC). IEEE, 2018. http://dx.doi.org/10.1109/icisc.2018.8398997.
Full textIshikawa, Tatsuyuki, Kazunori Shimizu, Takeshi Ikenaga, and Satoshi Goto. "High-throughput decoder for low-density parity-check code." In the 2006 conference. New York, New York, USA: ACM Press, 2006. http://dx.doi.org/10.1145/1118299.1118332.
Full textPhillips, Braden J., Daniel R. Kelly, and Brian W. Ng. "Estimating adders for a low density parity check decoder." In SPIE Optics + Photonics, edited by Franklin T. Luk. SPIE, 2006. http://dx.doi.org/10.1117/12.680199.
Full textTong, Jiajie, Huazi Zhang, Xianbin Wang, Shengchen Dai, Rong Li, and Jun Wang. "A Soft Cancellation Decoder for Parity-Check Polar Codes." In 2020 IEEE 31st Annual International Symposium on Personal, Indoor and Mobile Radio Communications. IEEE, 2020. http://dx.doi.org/10.1109/pimrc48278.2020.9217144.
Full textAlleyne, Damien, and Janak Sodha. "Pseudo-ARQ for a Low Density Parity Check Code Decoder." In Third IEEE International Conference on Wireless and Mobile Computing, Networking and Communications (WiMob 2007). IEEE, 2007. http://dx.doi.org/10.1109/wimob.2007.4390813.
Full textPetrovic, Vladimir L. "Flexible Encoder and Decoder of Low-Density Parity-Check Codes." In 2022 30th Telecommunications Forum (TELFOR). IEEE, 2022. http://dx.doi.org/10.1109/telfor56187.2022.9983744.
Full textKanur, Sudeep, Georgios Georgakarakos, Antti Siirila, Jeremie Lagraviere, Kristian Nybom, Sebastien Lafond, and Johan Lilius. "Parallel decoder for low density parity check codes: A MPSoC study." In 2013 International Conference on High Performance Computing & Simulation (HPCS). IEEE, 2013. http://dx.doi.org/10.1109/hpcsim.2013.6641414.
Full textZarubica, Radivoje, Stephen G. Wilson, and Eric Hall. "Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design." In IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference. IEEE, 2007. http://dx.doi.org/10.1109/glocom.2007.108.
Full textZarubica, Radivoje, and Stephen Wilson. "A Wiring-Efficient, High-Throughput Low Density Parity Check Decoder Design." In 2006 40th Annual Conference on Information Sciences and Systems. IEEE, 2006. http://dx.doi.org/10.1109/ciss.2006.286580.
Full textChoi, Eun-A., N. Kim, I. Lee, and J. Jung. "Optimal Structure of Decoder Design for Low Density Parity Check Codes." In 22nd AIAA International Communications Satellite Systems Conference & Exhibit 2004 (ICSSC). Reston, Virigina: American Institute of Aeronautics and Astronautics, 2004. http://dx.doi.org/10.2514/6.2004-3110.
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