Relevant bibliographies by topics / Parity-check codes

Academic literature on the topic 'Parity-check codes'

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Published: 4 June 2021
Last updated: 3 February 2022

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Journal articles on the topic "Parity-check codes"

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Heegard, C., and A. J. King. "FIR parity check codes." IEEE Transactions on Communications 48, no. 7 (July 2000): 1108–13. http://dx.doi.org/10.1109/26.855518.

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UCHIKAWA, Hironori. "Low-Density Parity-Check Codes." IEICE ESS Fundamentals Review 14, no. 3 (January 1, 2021): 217–28. http://dx.doi.org/10.1587/essfr.14.3_217.

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Fuja, T., C. Heegard, and M. Blaum. "Cross parity check convolutional codes." IEEE Transactions on Information Theory 35, no. 6 (1989): 1264–76. http://dx.doi.org/10.1109/18.45283.

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Wang, Tao, Daiming Qu, and Tao Jiang. "Parity-Check-Concatenated Polar Codes." IEEE Communications Letters 20, no. 12 (December 2016): 2342–45. http://dx.doi.org/10.1109/lcomm.2016.2607169.

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Rankin, D. M., and T. A. Gulliver. "Single parity check product codes." IEEE Transactions on Communications 49, no. 8 (2001): 1354–62. http://dx.doi.org/10.1109/26.939851.

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Li Ping, W. K. Leung, and Nam Phamdo. "Low density parity check codes with semi-random parity check matrix." Electronics Letters 35, no. 1 (1999): 38. http://dx.doi.org/10.1049/el:19990065.

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Olaya, Wilson. "The parity check codes through geometric Goppa codes." IEEE Latin America Transactions 5, no. 1 (March 2007): 38–40. http://dx.doi.org/10.1109/t-la.2007.4444531.

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Ward, R. K. "Parity Check Codes for Logic Processors." Computer Journal 29, no. 1 (January 1, 1986): 12–16. http://dx.doi.org/10.1093/comjnl/29.1.12.

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Kanter, Ido, and David Saad. "Cascading parity-check error-correcting codes." Physical Review E 61, no. 2 (February 1, 2000): 2137–40. http://dx.doi.org/10.1103/physreve.61.2137.

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Haley, David, and Alex Grant. "Reversible Low-Density Parity-Check Codes." IEEE Transactions on Information Theory 55, no. 5 (May 2009): 2016–36. http://dx.doi.org/10.1109/tit.2009.2016025.

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Dissertations / Theses on the topic "Parity-check codes"

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Adhikari, Dikshya. "The Role of Eigenvalues of Parity Check Matrix in Low-Density Parity Check Codes." Thesis, University of North Texas, 2020. https://digital.library.unt.edu/ark:/67531/metadc1707297/.

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The new developments in coding theory research have revolutionized the application of coding to practical systems. Low-Density Parity Check (LDPC) codes form a class of Shannon limit approaching codes opted for digital communication systems that require high reliability. This thesis investigates the underlying relationship between the spectral properties of the parity check matrix and LDPC decoding convergence. The bit error rate of an LDPC code is plotted for the parity check matrix that has different Second Smallest Eigenvalue Modulus (SSEM) of its corresponding Laplacian matrix. It is found that for a given (n,k) LDPC code, large SSEM has better error floor performance than low SSEM. The value of SSEM decreases as the sparseness in a parity-check matrix is increased. It was also found from the simulation that long LDPC codes have better error floor performance than short codes. This thesis outlines an approach to analyze LDPC decoding based on the eigenvalue analysis of the corresponding parity check matrix.
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Hayes, Bob. "LOW DENSITY PARITY CHECK CODES FOR TELEMETRY APPLICATIONS." International Foundation for Telemetering, 2007. http://hdl.handle.net/10150/604497.

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ITC/USA 2007 Conference Proceedings / The Forty-Third Annual International Telemetering Conference and Technical Exhibition / October 22-25, 2007 / Riviera Hotel & Convention Center, Las Vegas, Nevada
Next generation satellite communication systems require efficient coding schemes that enable high data rates, require low overhead, and have excellent bit error rate performance. A newly rediscovered class of block codes called Low Density Parity Check (LDPC) codes has the potential to revolutionize forward error correction (FEC) because of the very high coding rates. This paper presents a brief overview of LDPC coding and decoding. An LDPC algorithm developed by Goddard Space Flight Center is discussed, and an overview of an accompanying VHDL development by L-3 Communications Cincinnati Electronics is presented.
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Tee, James Seng Khien. "On concatenated single parity check codes and bit interleaved coded modulation." Thesis, University of Canterbury. Electrical and Electronic Engineering, 2001. http://hdl.handle.net/10092/5463.

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In recent years, the invention of Turbo codes has spurred much interest in the coding community. Turbo codes are capable of approaching channel capacity closely at a decoding complexity much lower than previously thought possible. Although decoding complexity is relatively low, Turbo codes are still too complex to implement for many practical systems. This work is focused on low complexity channel coding schemes with Turbo-like performance. The issue of complexity is tackled by using single parity check (SPC) codes, arguably the simplest codes known. The SPC codes are used as component codes in multiple parallel and multiple serial concatenated structures to achieve high performance. An elegant technique for improving error performance by increasing the dimensionality of the code without changing the block length and code rate is presented. For high bandwidth efficiency applications, concatenated SPC codes are combined with 16-QAM Bit Interleaved Coded Modulation (BICM) to achieve excellent performance. Analytical and simulation results show that concatenated SPC codes are capable of achieving Turbo-like performances at a complexity which is approximately 10 times less than that of a 16-state Turbo code. A simple yet accurate generalised bounding method is derived for BICM systems employing large signal constellations. This bound works well over a wide range of SNRs for common signal constellations in the independent Rayleigh fading channel. Moreover, the bounding method is independent of the type and code rate of channel coding scheme. In addition to the primary aim of the research, an improved decoder structure for serially concatenated codes has been designed, and a sub-optimal, soft-in-soft-out iterative technique for decoding systematic binary algebraic block codes has been developed.
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Sharifi, Tehrani Saeed. "Stochastic decoding of low-density parity-check codes." Thesis, McGill University, 2011. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=97010.

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Low-Density Parity-Check (LDPC) codes are one of the most powerful classes of error-control codes known to date. These codes have been considered for many recent digital communication applications. In this dissertation, we propose stochastic decoding of state-of-the-art LDPC codes and demonstrate it as a competitive approach to practical LDPC decoding algorithms.In stochastic decoding, probabilities are represented as streams of random bits using Bernoulli sequences in which the information is contained in the statistics of the bit stream. This representation results in low hardware-complexity processing nodes that perform computationally-intensive operations. However, stochastic decoding is prone to the acute problem of latching. This problem is caused by correlated bit streams within cycles in the code's factor graph, and significantly deteriorates the performance of stochastic LDPC decoders.We propose edge memories, tracking forecast memories, and majority-based tracking forecast memories to address the latching problem. These units efficiently extract the evolving statistics of stochastic bit streams and rerandomize them to disrupt latching. To the best of our knowledge, these methods are the first successful methods for stochastic decoding of state-of-the-art LDPC codes.We present novel decoder architectures and report on several hardware implementations. The most advanced reported implementation is a stochastic decoder that decodes the (2048,1723) LDPC code from the IEEE 802.3an standard. To the best of our knowledge, this decoder is the most silicon area-efficient and, with a maximum core throughput of 61.3 Gb/s, is one of the fastest fully parallel soft-decision LDPC decoders reported in the literature. We demonstrate the performance of this decoder in low bit-error-rate regimes.In addition to stochastic LDPC decoding, we propose the novel application of the stochastic approach for joint decoding of LDPC codes and partial-response channels that are considered in practical magnetic recording applications. Finally, we investigate the application of the stochastic approach for decoding linear block codes with high-density parity-check matrices on factor graphs. We consider Reed-Solomon, Bose-Chaudhuri-Hocquenghem, and block turbo codes.
À ce jour, les codes Low-Density Parity-Check (LDPC) font partie des codes correcteurs d'erreurs les plus performants. Ces codes sont inclus dans différents standards de communications numériques. Dans ce manuscrit, nous proposons d'utiliser le décodage stochastique pour les codes LDPC. D'autre part, nous démontrons que pour les codes LDPC, le décodage stochastique représente une alternative réaliste aux algorithmes de décodage existants.Dans le processus de décodage stochastique, les probabilités sont représentées sous forme de séquences de Bernoulli. L'information est contenue dans la statistique de ces flux binaires aléatoires. Cette représentation particulière permet d'exécuter des calculs intensifs avec une faible complexité matérielle. Cependant le décodage stochastique est enclin au problème du verrouillage ("latching"). La corrélation entre les bits des différents flux au sein des cycles du graphe biparti dégrade les performances du décodage stochastique des codes LDPC. Pour résoudre le problème du verrouillage, nous proposons trois solutions: les mémoires de branche, les mémoires de suivi, et les mémoires de suivi à majorité. Ces différents composants permettent de suivre l'évolution de la statistique des flux binaires et de réintroduire des éléments aléatoires au sein des séquences observées, minimisant ainsi le phénomène de verrouillage. À notre connaissance, il s'agit là des premiers résultats probants permettant un décodage stochastique efficace des codes LDPC. Nous proposons de nouvelles architectures de décodeurs associées à leurs implantations matérielles respectives. La plus perfectionnée des architectures présentée ici est celle d'un décodeur stochastique pour le code LDPC (2048,1723) associé au standard IEEE 802.3an. À notre connaissance, en comparaison avec l'état de l'art actuel, ce décodeur dispose du meilleur rapport vitesse/complexité. Le débit maximum (au niveau du coeur), est de 61.3 Gb/s, il s'agit là du plus rapide des décodeurs de codes LDPC à décisions souples connu à ce jour. Nous présentons par ailleurs les performances de ce décodeur à très faible taux d'erreurs binaire. De plus, nous proposons d'appliquer le calcul stochastique au décodage conjoint des codes LDPC et des canaux à réponse partielle qui est utilisé dans les applications d'enregistrement magnétique. Enfin, nous étudions l'extension du décodage stochastique au décodage des codes en blocs ayant une matrice de parité à forte densité. Nous appliquons le décodage stochastique sur des graphes biparti aux codes Reed-Solomon, Bose-Chaudhuri-Hocquenghem, et aux turbocodes en blocs.
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Meidan, Amir. "Linear-time encodable low-density parity-check codes." Thesis, National Library of Canada = Bibliothèque nationale du Canada, 1998. http://www.collectionscanada.ca/obj/s4/f2/dsk1/tape11/PQDD_0006/MQ40942.pdf.

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Davey, M. C. "Error-correction using low-density parity-check codes." Thesis, University of Cambridge, 2000. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.598305.

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Gallager's low-density parity-check codes are defined by sparse parity-check matrices, usually with a random contruction. Such codes have near Shannon limit performance when decoded using an iterative probabilistic decoding algorithm. We report two advances that improve the error-correction performance of these codes. First, defining the codes over non-binary fields we can obtain a 0.6 dB improvement in signal to noise ratio for a given bit error rate. Second, using irregular parity-check matrices with non-uniform row and column weights we obtain gains of up to 0.5 dB. The empirical error-correction performance of irregular low-density parity-check codes is unbeaten for the additive white Gaussian noise channel. Low-density parity-check codes are also shown to be useful for communicating over channels which make insertions and deletions as well as additive (substitution) errors. Error-correction for such channels has not been widely studied, but is of importance whenever synchronisation of sender and receiver is imperfect. We introduce concatenated codes using novel non-linear inner codes which we call 'watermark' codes, and low-density parity-check codes over non-binary fields as outer codes. The inner code allows resynchronisation using a probabilistic decoder, providing soft outputs for the outer low-density parity-check decoder. Error-correction performance using watermark codes is several orders of magnitude better than any comparable results in the literature.
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Rankin, David Michael. "Single parity check product codes and iterative decoding." Thesis, University of Canterbury. Electrical and Computer Engineering, 2001. http://hdl.handle.net/10092/1084.

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The aim of coding theory is to design codes which can achieve the fundamental limits of communication [52] and yet are simple to implement. On average randomly constructed codes can achieve this goal, but with a decoding complexity that is impractical. Consequently, highly structured codes with practical decoding algorithms have been extensively studied. Unfortunately the vast majority of these codes do not approach capacity. Recent advances involving simple 'random like' codes with practical iterative decoding algorithms have closely approached capacity as the blocklength increases. This thesis investigates single parity check (SPC) product codes and introduces the class of randomly interleaved (RI) SPC product codes. It will be shown that RI SPC product codes can asymptotically force the probability of error to zero, at code rates up to capacity, for almost all codewords. Furthermore the structure of these codes allows a very simple, sub-optimal, iterative decoding algorithm to be used. This thesis also derives an asymptotic analysis on SPC product codes from the decoding point of view. It is shown that the probability of error can be driven to zero, as the blocklength increases, for signal to noise ratios within 2dB of capacity on the additive white Gaussian noise (AWGN) channel. Simulation results for both SPC and RI SPC product codes in an AWGN channel are presented. These results indicate that RI SPC product codes perform very well, typically within 1.5dB of capacity over a wide range of blocklengths and code rates. Further analysis on the weight enumerator of finite length RI SPC product codes is used to confirm the error floor of these codes. Extensions to parallel and serially concatenated SPC product codes are also investigated. Simulation results show an advantageous trade-off between code rate, blocklength and performance for three dimensional parallel concatenated SPC product codes. The design of irregular SPC product codes is also considered, and some simulation results are presented.
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Anitei, Irina. "Circular Trellis based Low Density Parity Check Codes." Ohio University / OhioLINK, 2008. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1226513009.

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Moon, Todd K., and Jacob H. Gunther. "AN INTRODUCTION TO LOW-DENSITY PARITY-CHECK CODES." International Foundation for Telemetering, 2003. http://hdl.handle.net/10150/607470.

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International Telemetering Conference Proceedings / October 20-23, 2003 / Riviera Hotel and Convention Center, Las Vegas, Nevada
Low-Density Parity-Check (LDPC) codes are powerful codes capable of nearly achieving the Shannon channel capacity. This paper presents a tutorial introduction to LDPC codes, with a detailed description of the decoding algorithm. The algorithm propagates information about bit and check probabilities through a tree obtained from the Tanner graph for the code. This paper may be useful as a supplement in a course on error-control coding or digital communication.
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Ha, Jeongseok Ha. "Low-Density Parity-Check Codes with Erasures and Puncturing." Diss., Georgia Institute of Technology, 2003. http://hdl.handle.net/1853/5296.

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In this thesis, we extend applications of Low-Density Parity-Check (LDPC) codes to a combination of constituent sub-channels, which is a mixture of Gaussian channels with erasures. This model, for example, represents a common channel in magnetic recordings where thermal asperities in the system are detected and represented at the decoder as erasures. Although this channel is practically useful, we cannot find any previous work that evaluates performance of LDPC codes over this channel. We are also interested in practical issues such as designing robust LDPC codes for the mixture channel and predicting performance variations due to erasure patterns (random and burst), and finite block lengths. On time varying channels, a common error control strategy is to adapt the coding rate according to available channel state information (CSI). An effective way to realize this coding strategy is to use a single code and puncture it in a rate-compatible fashion, a so-called rate-compatible punctured code (RCPC). We are interested in the existence of good puncturing patterns for rate-changes that minimize performance loss. We show the existence of good puncturing patterns with analysis and verify the results with simulations. Universality of a channel code across a broad range of coding rates is a theoretically interesting topic. We are interested in the possibility of using the puncturing technique proposed in this thesis for designing universal LDPC codes. We also consider how to design high rate LDPC codes by puncturing low rate LDPC codes. The new design method can take advantage of longer effect block lengths, sparser parity-check matrices, and larger minimum distances of low rate LDPC codes.
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Books on the topic "Parity-check codes"

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Gallagher, Robert G. Low-density parity-check codes. Cambridge, Mass: MIT-Press, 2003.

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Gallager, Robert G. Low-density parity-check codes. Cambridge: M.I.T. Press, 2005.

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Rovini, Massimo. Low-density parity-check codes: A tutorial. Noordwijk: ESA Publications Division, 2004.

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Meidan, Amir. Linear-time encodable low-density parity-check codes. Ottawa: National Library of Canada, 1998.

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Park, Eun-Young Christina. New decoding algorithms for regular low-density parity-check codes. Ottawa: National Library of Canada, 2002.

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Mantha, Ramesh. Hybrid automatic repeat request schemes using turbo codes and low density parity check codes. Ottawa: National Library of Canada, 1999.

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Johnson, Sarah J. Iterative error correction: Turbo, low-density parity-check and repeat-accumulate codes. New York: Cambridge University Press, 2009.

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Gallagher, Robert G. Low-Density Parity-Check Codes. MIT Press, 2003.

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Benjamin, Smith. Low-density parity-check codes with reduced decoding complexity. 2007.

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Ardakani, Masoud. Efficient analysis, design and decoding of low-density parity-check codes. 2004.

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Book chapters on the topic "Parity-check codes"

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Baldi, Marco. "Low-Density Parity-Check Codes." In SpringerBriefs in Electrical and Computer Engineering, 5–21. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-02556-8_2.

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Cancellieri, Giovanni. "Low Density Parity Check Codes." In Polynomial Theory of Error Correcting Codes, 503–43. Cham: Springer International Publishing, 2014. http://dx.doi.org/10.1007/978-3-319-01727-3_10.

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Deergha Rao, K. "Low Density Parity Check Codes." In Channel Coding Techniques for Wireless Communications, 251–303. New Delhi: Springer India, 2015. http://dx.doi.org/10.1007/978-81-322-2292-7_8.

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Ball, Simeon. "Low Density Parity Check Codes." In A Course in Algebraic Error-Correcting Codes, 123–32. Cham: Springer International Publishing, 2020. http://dx.doi.org/10.1007/978-3-030-41153-4_8.

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Wu, Zining. "Low-Density Parity-Check Codes." In Coding and Iterative Detection for Magnetic Recording Channels, 47–69. Boston, MA: Springer US, 2000. http://dx.doi.org/10.1007/978-1-4615-4565-1_3.

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Ivaniš, Predrag, and Dušan Drajić. "Low Density Parity Check Codes." In Information Theory and Coding - Solved Problems, 447–507. Cham: Springer International Publishing, 2016. http://dx.doi.org/10.1007/978-3-319-49370-1_9.

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Rao, K. Deergha. "Low Density Parity Check Codes." In Channel Coding Techniques for Wireless Communications, 273–329. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0561-4_8.

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Kienle, Frank. "Low-Density Parity-Check Codes." In Architectures for Baseband Signal Processing, 147–83. New York, NY: Springer New York, 2013. http://dx.doi.org/10.1007/978-1-4614-8030-3_7.

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Paolini, E. "Low-Density Parity-Check (LDPC) Codes." In Inside Solid State Drives (SSDs), 293–331. Dordrecht: Springer Netherlands, 2012. http://dx.doi.org/10.1007/978-94-007-5146-0_11.

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Paolini, E. "Low-Density Parity-Check (LDPC) Codes." In Inside Solid State Drives (SSDs), 407–53. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-13-0599-3_12.

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Conference papers on the topic "Parity-check codes"

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MacKay, D. J. C. "Fountain codes." In IEE Seminar on Sparse-Graph Codes (Turbo Codes, Low Density Parity-Check Codes and Fountain Codes). IEE, 2004. http://dx.doi.org/10.1049/ic:20040504.

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Pyndiah, R. "Block turbo codes: ten years later." In IEE Seminar on Sparse-Graph Codes (Turbo Codes, Low Density Parity-Check Codes and Fountain Codes). IEE, 2004. http://dx.doi.org/10.1049/ic:20040505.

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Urbanke, R. "The quest for capacity-achieving codes." In IEE Seminar on Sparse-Graph Codes (Turbo Codes, Low Density Parity-Check Codes and Fountain Codes). IEE, 2004. http://dx.doi.org/10.1049/ic:20040506.

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Ng, S. X. "Integrated wireless multimedia turbo-transceiver design approaching the Rayleigh channel's capacity: interpreting Shannon's lessons in the turbo-era." In IEE Seminar on Sparse-Graph Codes (Turbo Codes, Low Density Parity-Check Codes and Fountain Codes). IEE, 2004. http://dx.doi.org/10.1049/ic:20040507.

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Peng, X. H. "Coding for distributed networks." In IEE Seminar on Sparse-Graph Codes (Turbo Codes, Low Density Parity-Check Codes and Fountain Codes). IEE, 2004. http://dx.doi.org/10.1049/ic:20040508.

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Markarian, G. "Hierarchical modulation and DVB-S2." In IEE Seminar on Sparse-Graph Codes (Turbo Codes, Low Density Parity-Check Codes and Fountain Codes). IEE, 2004. http://dx.doi.org/10.1049/ic:20040509.

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Fossorier, M. "Quasicyclic low density parity check codes." In IEEE International Symposium on Information Theory, 2003. Proceedings. IEEE, 2003. http://dx.doi.org/10.1109/isit.2003.1228164.

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Wang, Chung-Li, and Shu Lin. "Low-density parity-check accumulate codes." In Its Applications (Isita2010). IEEE, 2010. http://dx.doi.org/10.1109/isita.2010.5650090.

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Santini, Paolo, Massimo Battaglioni, Franco Chiaraluce, Marco Baldi, and Edoardo Persichetti. "Low-Lee-Density Parity-Check Codes." In ICC 2020 - 2020 IEEE International Conference on Communications (ICC). IEEE, 2020. http://dx.doi.org/10.1109/icc40277.2020.9148812.

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Wang, Zhifeng, Peng Zhang, Changyin Liu, Yuanzhi Chen, and Jianhe Du. "Parity check for decoding QC-LDPC codes with all-diagonal parity-check structure." In 2019 IEEE 3rd Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC). IEEE, 2019. http://dx.doi.org/10.1109/imcec46724.2019.8984145.

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