Relevant bibliographies by topics / Parallelising architecture

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Conference papers

Academic literature on the topic 'Parallelising architecture'

Author: Grafiati
Published: 25 January 2025

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Journal articles on the topic "Parallelising architecture"

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Keane, J. A. "Parallelising a financial system." Future Generation Computer Systems 9, no. 1 (May 1993): 41–51. http://dx.doi.org/10.1016/0167-739x(93)90025-k.

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Lam, Yuet Ming, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, and Wayne Luk. "Multiloop Parallelisation Using Unrolling and Fission." International Journal of Reconfigurable Computing 2010 (2010): 1–10. http://dx.doi.org/10.1155/2010/475620.

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A technique for parallelising multiple loops in a heterogeneous computing system is presented. Loops are first unrolled and then broken up into multiple tasks which are mapped to reconfigurable hardware. A performance-driven optimisation is applied to find the best unrolling factor for each loop under hardware size constraints. The approach is demonstrated using three applications: speech recognition, image processing, and the N-Body problem. Experimental results show that a maximum speedup of 34 is achieved on a 274 MHz FPGA for the N-Body over a 2.6 GHz microprocessor, which is 4.1 times higher than that of an approach without unrolling.
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Stewart, Robert, Andrew Nowlan, Pascal Bacchus, Quentin Ducasse, and Ekaterina Komendantskaya. "Optimising Hardware Accelerated Neural Networks with Quantisation and a Knowledge Distillation Evolutionary Algorithm." Electronics 10, no. 4 (February 5, 2021): 396. http://dx.doi.org/10.3390/electronics10040396.

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This paper compares the latency, accuracy, training time and hardware costs of neural networks compressed with our new multi-objective evolutionary algorithm called NEMOKD, and with quantisation. We evaluate NEMOKD on Intel’s Movidius Myriad X VPU processor, and quantisation on Xilinx’s programmable Z7020 FPGA hardware. Evolving models with NEMOKD increases inference accuracy by up to 82% at the cost of 38% increased latency, with throughput performance of 100–590 image frames-per-second (FPS). Quantisation identifies a sweet spot of 3 bit precision in the trade-off between latency, hardware requirements, training time and accuracy. Parallelising FPGA implementations of 2 and 3 bit quantised neural networks increases throughput from 6 k FPS to 373 k FPS, a 62× speedup.
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Rinberg, Arik, Alexander Spiegelman, Edward Bortnikov, Eshcar Hillel, Idit Keidar, Lee Rhodes, and Hadar Serviansky. "Fast Concurrent Data Sketches." ACM Transactions on Parallel Computing 9, no. 2 (June 30, 2022): 1–35. http://dx.doi.org/10.1145/3512758.

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Data sketches are approximate succinct summaries of long data streams. They are widely used for processing massive amounts of data and answering statistical queries about it. Existing libraries producing sketches are very fast, but do not allow parallelism for creating sketches using multiple threads or querying them while they are being built. We present a generic approach to parallelising data sketches efficiently and allowing them to be queried in real time, while bounding the error that such parallelism introduces. Utilising relaxed semantics and the notion of strong linearisability, we prove our algorithm’s correctness and analyse the error it induces in some specific sketches. Our implementation achieves high scalability while keeping the error small. We have contributed one of our concurrent sketches to the open-source data sketches library.
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Ete, Remi, Frank Gaede, Julian Benda, and Hadrian Grasland. "MarlinMT - parallelising the Marlin framework." EPJ Web of Conferences 245 (2020): 05022. http://dx.doi.org/10.1051/epjconf/202024505022.

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Marlin is the event processing framework of the iLCSoft [1] ecosystem. Originally developed for the ILC more than 15 years ago, it is now widely used also by other communities, such as CLICdp, CEPC and many test beam projects such as CALICE, LCTPC and EU-Telescope. While Marlin is lightweight and flexible it was originally designed for sequential processing only. With MarlinMT we have now evolved Marlin for parallel processing of events on multi-core architectures based on multi-threading. We report on the necessary developments and issues encountered, within Marlin as well as with the underlying LCIO [4] event data model (EDM). A focus will be put on the new parallel event processing (PEP) scheduler. We conclude with first performance estimates, like the application speedup and a discussion on histogram handling in parallel applications.
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Arbelaez, Alejandro, and Luis Quesada. "Parallelising the k-Medoids Clustering Problem Using Space-Partitioning." Proceedings of the International Symposium on Combinatorial Search 4, no. 1 (August 20, 2021): 20–28. http://dx.doi.org/10.1609/socs.v4i1.18282.

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The k-medoids problem is a combinatorial optimisation problem with multiples applications in Resource Allocation, Mobile Computing, Sensor Networks and Telecommunications.Real instances of this problem involve hundreds of thousands of points and thousands of medoids.Despite the proliferation of parallel architectures, this problem has been mostly tackled using sequential approaches.In this paper, we study the impact of space-partitioning techniques on the performance of parallel local search algorithms to tackle the k-medoids clustering problem, and compare these results with the ones obtained using sampling.Our experiments suggest that approaches relying on partitioning scale more while preserving the quality of the solution.
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Haveraaen, Magne. "Case Study on Algebraic Software Methodologies for Scientific Computing." Scientific Programming 8, no. 4 (2000): 261–73. http://dx.doi.org/10.1155/2000/482042.

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The use of domain specific languages and appropriate software architectures are currently seen as the way to enhance reusability and improve software productivity. Here we outline a use of algebraic software methodologies and advanced program constructors to improve the abstraction level of software for scientific computing. This leads us to the language of coordinate free numerics as an alternative to the traditional coordinate dependent array notation. This provides the backdrop for the three accompanying papers:Coordinate Free Programming of Computational Fluid Dynamics Problems, centered around an example of using coordinate free numerics,Machine and Collection Abstractions for User-Implemented Data-Parallel Programming, exploiting the higher abstraction level when parallelising code, andAn Algebraic Programming Style for Numerical Software and its Optimization, looking at high-level transformations enabled by the domain specific programming style.
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Grote-Ramm, Wolfgang, Felix Schönig, Peter Schwarzbözl, Maximilian Drexelius, Daniel Maldonado Quinto, and Matthias Binder. "Model Predictive Control and Service Life Monitoring for Molten Salt Solar Power Towers." SolarPACES Conference Proceedings 2 (October 15, 2024). http://dx.doi.org/10.52825/solarpaces.v2i.774.

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A two-component system for control and monitoring of solar power towers with molten salt receivers is proposed. The control component consists of a model predictive control application (MPC) with a flexible objective function and on-line tunable weights, which runs on a Industrial PC and uses a reduced order dynamic model of the receiver’s thermal and flow dynamics. The second component consists of a service-life monitoring unit, which estimates the service-life consumption of the absorber tubes depending on the current mode of operation based on thermal stresses and creep fatigue in the high temperature regime. The calculation of stresses is done based on a detailed finite element study, in which a digital twin of the receiver was developed. By parallelising the model solver, the estimation of service-life consumption became capable of real-time operation. The system has been implemented at a test facility in Jülich, Germany, and awaits field experiments. In this paper, the modeling and architecture are presented along simulation results, which were validated on a hardware-in-the-loop test bench. The MPC showed good disturbance rejection while respecting process variable constraints during the simulation studies.
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Padulano, Vincenzo Eduardo, Ivan Donchev Kabadzhov, Enric Tejedor Saavedra, Enrico Guiraud, and Pedro Alonso-Jordá. "Leveraging State-of-the-Art Engines for Large-Scale Data Analysis in High Energy Physics." Journal of Grid Computing 21, no. 1 (February 10, 2023). http://dx.doi.org/10.1007/s10723-023-09645-2.

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AbstractThe Large Hadron Collider (LHC) at CERN has generated a vast amount of information from physics events, reaching peaks of TB of data per day which are then sent to large storage facilities. Traditionally, data processing workflows in the High Energy Physics (HEP) field have leveraged grid computing resources. In this context, users have been responsible for manually parallelising the analysis, sending tasks to computing nodes and aggregating the partial results. Analysis environments in this field have had a common building block in the ROOT software framework. This is the de facto standard tool for storing, processing and visualising HEP data. ROOT offers a modern analysis tool called RDataFrame, which can parallelise computations from a single machine to a distributed cluster while hiding most of the scheduling and result aggregation complexity from users. This is currently done by leveraging Apache Spark as the distributed execution engine, but other alternatives are being explored by HEP research groups. Notably, Dask has rapidly gained popularity thanks to its ability to interface with batch queuing systems, widespread in HEP grid computing facilities. Furthermore, future upgrades of the LHC are expected to bring a dramatic increase in data volumes. This paper presents a novel implementation of the Dask backend for the distributed RDataFrame tool in order to address the aforementioned future trends. The scalability of the tool with both the new backend and the already available Spark backend is demonstrated for the first time on more than two thousand cores, testing a real HEP analysis.
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Dissertations / Theses on the topic "Parallelising architecture"

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Louetsi, Kenelm. "Un environnement de développement d'applications sur un processeur à beaucoup de cœurs parallélisant." Electronic Thesis or Diss., Perpignan, 2024. http://www.theses.fr/2024PERP0024.

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Les objets numériques du futur (robots domestiques, véhicules autonomes, engins spatiaux automatiques,...) auront besoin à la fois de puissance de calcul et de sûreté. Le Little Big Processor (LBP) est adapté à ce défi : il a une approche novatriced u parallélisme qui offre l'avantage de la puissance en garantissant un certain déterminisme de l'exécution. Ce déterminisme d'exécution donne une sûreté de fonctionnement indispensable dans la plupart des dispositifs interagissant avec le monde et l'humain. Dans cette thèse, nous avons réalisé un environnement de développement pour LBP, avec un compilateur, un « bootloader » et un débogueur. Ces outils sont classiques, mais en l'occurrence, ils devront être adaptés à la mise en oeuvre d'applications parallélisées avec OpenMP pour LBP. Suite à la réalisation de l'environnement de développement, nous avons défini un modèle de parallélisme déterministe pour de l'embarqué « bareme-tal ». Ce modèle a été évalué sur une plateforme embarquée « baremetal » et nous a permis de confirmer qu'il était possible d'avoir une exécution parallèle déterministe qui conserve les gains en performance du parallélisme
Digital objects of the future (domestic robots, autonomous vehicles, automatic spacecraft, ...) will need both computing power and safety. The Little Big Processor (LBP) is suitable for this challenge: it has an innovative approach to parallelism which offers the advantages of computing power while guaranteeing a certain determinism of execution. This execution determinism brings a level of operational safety essential in most devices interacting with the world and humans. In the present thesis we created a development environment for LBP, with a compiler, a loader and a debugger. These tools are classic but in this case, they will have to be adapted to the implementation of parallelized OpenMP applications for LBP. Following the creation of the development environment, we defined a deterministic parallel model for embedded bare-metal. This model has been evaluated on a embedded bare-metal platform, and this allowed us to confirm that it is possible to have a deterministic parallel execution which keeps the performance speedups from parallelism
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Books on the topic "Parallelising architecture"

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Baxter, M. J. Parallelising and developing control algorithms for heterogeneous architectures. Sheffield: University of Sheffield, Dept. of Automatic Control and Systems Engineering, 1995.

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Conference papers on the topic "Parallelising architecture"

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Song, Meishu, Emilia Parada-Cabaleiro, Zijiang Yang, Xin Jing, Kazumasa Togami, Kun Qian*, Björn W. Schuller, and Yoshiharu Yamamoto. "Parallelising 2D-CNNs and Transformers: A Cognitive-based approach for Automatic Recognition of Learners’ English Proficiency." In Intelligent Human Systems Integration (IHSI 2022) Integrating People and Intelligent Systems. AHFE International, 2022. http://dx.doi.org/10.54941/ahfe1001000.

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Learning English as a foreign language requires an extensive use of cognitive capacity, memory, and motor skills in order to orally express one’s thoughts in a clear manner. Current speech recognition intelligence focuses on recognising learners’ oral proficiency from fluency, prosody, pronunciation, and grammar’s perspectives. However, the capacity of clearly and naturally expressing an idea is a high-level cognitive behaviour which can hardly be represented by these detailed and segmental dimensions, which indeed do not fulfil English learners and teachers’ requirements. This work aims to utilise the state-of-the-art deep learning techniques to recognise English speaking proficiency at a cognitive level, i. e., a learner’s ability to clearly organise their own thoughts when expressing an idea in English as a foreign language. For this, we collected the “Oral English for Japanese Learners” Dataset (OEJL-DB), a corpus of recordings by 82 students of a Japanese high school expressing their ideas in English towards 5 different topics. Annotations concerning the clarity of learners’ thoughts are given by 5 English teachers according to 2 classes: clear and unclear. In total, the dataset includes 7.6 hours of audio data with an average length for each oral English presentation of66 seconds. As initial cognitive-based method to identify learners’ speaking proficiency, we propose an architecture based on the parallelization of CNNs and Transformers. With the strengthening of the CNNs in spatial feature representation and the Transformer in sequence encoding, we achieve a 89.4% accuracy and 87.6%. Unweighted Average Recall (UAR), results which outperform those from the ResNet architectures (89.2 % accuracy and 86.3 % UAR). Our promising outcomes reveal that speech intelligence can be efficiently applied to “grasp” high level cognitive behaviours, a new area of research which seems to have a great potential for further investigation.
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Baxter, M. J. "Parallelising algorithms to exploit heterogeneous architectures for real-time control systems." In International Conference on Control '94. IEE, 1994. http://dx.doi.org/10.1049/cp:19940319.

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