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Journal articles on the topic 'Parallel processing (Electronic computers)'

Author: Grafiati

Published: 4 June 2021

Last updated: 31 July 2024

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1

Arthurs, E., J. M. Cooper, M. S. Goodman, H. Kobrinski, M. Tur, and M. P. Vecchi. "Multiwavelength optical crossconnect for parallel-processing computers." Electronics Letters 24, no. 2 (1988): 119. http://dx.doi.org/10.1049/el:19880079.

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2

Kai Hwang and Zhiwei Xu. "Scalable parallel computers for real-time signal processing." IEEE Signal Processing Magazine 13, no. 4 (July 1996): 50–66. http://dx.doi.org/10.1109/79.526898.

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3

Moulin, P., A. T. Ogielski, G. Lilienfeld, and J. W. Woods. "Video Signal Processing and Coding on Data-Parallel Computers." Digital Signal Processing 5, no. 2 (April 1995): 118–29. http://dx.doi.org/10.1006/dspr.1995.1011.

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4

Buchanan, W. J., and N. K. Gupta. "Maxwell's Equations in the 21st Century." International Journal of Electrical Engineering & Education 30, no. 4 (October 1993): 343–53. http://dx.doi.org/10.1177/002072099303000408.

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Maxwell's equations in the 21st Century The finite-difference time-domain method is a novel method for solving Maxwell's curl equations, especially when parallel-processing techniques are applied. The next generation of computers will bring a revolution by exploiting the use of parallel processing in computation to the maximum.

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5

Ishikawa, Masatoshi. "Optical Neuron Computers - Associative Memory and Learning by Optical Parallel Processing -." Journal of Robotics and Mechatronics 2, no. 4 (August 20, 1990): 322–23. http://dx.doi.org/10.20965/jrm.1990.p0322.

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6

El-Seoud, Samir Abou, Reham Fouad Mohamed, and Samy Ghoneimy. "DNA Computing: Challenges and Application." International Journal of Interactive Mobile Technologies (iJIM) 11, no. 2 (April 11, 2017): 74. http://dx.doi.org/10.3991/ijim.v11i2.6564.

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<p class="Abstract">Much of our scientific, technological, and economic future depends on the availability of an ever-increasing supply of computational power. However, the increasing demand for such power has pushed electronic technology to the limit of physical feasibility and has raised the concern that this technology may not be able to sustain our growth in the near future. It became important to consider an alternative means of achieving computational power. In this regard, DNA computing was introduced based on the usage of DNA and molecular biology hardware instead of the typical silicon based technology. The molecular computers could take advantage of DNA's physical properties to store information and perform calculations. These include extremely dense information storage, enormous parallelism and extraordinary energy efficiency. One of the main advantages that DNA computations would add to computation is its self - parallel processing while most of the electronic computers now use linear processing. In this paper, the DNA computation is reviewed and its state of the art challenges and applications are presented. Some of these applications are those require fast processing, at which DNA computers would be able to solve the hardest problems faster than the traditional ones. For example, 10 trillion DNA molecules can fit in one cubic centimeter that would result in a computer that holds 10 terabytes of data. Moreover, this work focuses on whether a large scale molecular computer can be built.</p>

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7

Pissaloux, Edwige E., and Patrick Bonnin. "On the Evolution of Parallel Computers Dedicated to Image Processing through Examples of Some French Computers." Digital Signal Processing 7, no. 1 (January 1997): 13–27. http://dx.doi.org/10.1006/dspr.1997.0274.

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8

Hayat, L. "Two-dimensional median filter algorithm for parallel reconfigurable computers." IEE Proceedings - Vision, Image, and Signal Processing 142, no. 6 (1995): 345. http://dx.doi.org/10.1049/ip-vis:19952273.

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9

Niewiadomska-Szynkiewicz, Ewa, Michał Marks, Jarosław Jantura, and Mikołaj Podbielski. "A Hybrid CPU/GPU Cluster for Encryption and Decryption of Large Amounts of Data." Journal of Telecommunications and Information Technology, no. 3 (September 30, 2012): 32–39. http://dx.doi.org/10.26636/jtit.2012.3.1276.

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The main advantage of a distributed computing system over standalone computer is an ability to share the workload between cores, processors and computers. In our paper we present a hybrid cluster system – a novel computing architecture with multi-core CPUs working together with many-core GPUs. It integrates two types of CPU, i.e., Intel and AMD processor with advanced graphics processing units, adequately, Nvidia Tesla and AMD FirePro (formerly ATI). Our CPU/GPU cluster is dedicated to perform massive parallel computations which is a common approach in cryptanalysis and cryptography. The efficiency of parallel implementations of selected data encryption and decryption algorithms are presented to illustrate the performance of our system.

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10

Song, Zhe, Xing Mu, and Hou-Xing Zhou. "High Performance Computing of Complex Electromagnetic Algorithms Based on GPU/CPU Heterogeneous Platform and Its Applications to EM Scattering and Multilayered Medium Structure." International Journal of Antennas and Propagation 2017 (2017): 1–12. http://dx.doi.org/10.1155/2017/9173062.

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The fast and accurate numerical analysis for large-scale objects and complex structures is essential to electromagnetic simulation and design. Comparing to the exploration in EM algorithms from mathematical point of view, the computer programming realization is coordinately significant while keeping up with the development of hardware architectures. Unlike the previous parallel algorithms or those implemented by means of parallel programming on multicore CPU with OpenMP or on a cluster of computers with MPI, the new type of large-scale parallel processor based on graphics processing unit (GPU) has shown impressive ability in various scenarios of supercomputing, while its application in computational electromagnetics is especially expected. This paper introduces our recent work on high performance computing based on GPU/CPU heterogeneous platform and its application to EM scattering problems and planar multilayered medium structure, including a novel realization of OpenMP-CUDA-MLFMM, a developed ACA method and a deeply optimized CG-FFT method. With fruitful numerical examples and their obvious enhancement in efficiencies, it is convincing to keep on deeply investigating and understanding the computer hardware and their operating mechanism in the future.

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11

Seo, Jung-hyun, and HyeongOk Lee. "Petersen-star networks modeled by optical transpose interconnection system." International Journal of Distributed Sensor Networks 17, no. 11 (November 2021): 155014772110331. http://dx.doi.org/10.1177/15501477211033115.

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One method to create a high-performance computer is to use parallel processing to connect multiple computers. The structure of the parallel processing system is represented as an interconnection network. Traditionally, the communication links that connect the nodes in the interconnection network use electricity. With the advent of optical communication, however, optical transpose interconnection system networks have emerged, which combine the advantages of electronic communication and optical communication. Optical transpose interconnection system networks use electronic communication for relatively short distances and optical communication for long distances. Regardless of whether the interconnection network uses electronic communication or optical communication, network cost is an important factor among the various measures used for the evaluation of networks. In this article, we first propose a novel optical transpose interconnection system–Petersen-star network with a small network cost and analyze its basic topological properties. Optical transpose interconnection system–Petersen-star network is an undirected graph where the factor graph is Petersen-star network. OTIS–PSN n has the number of nodes 102n, degree n+3, and diameter 6 n − 1. Second, we compare the network cost between optical transpose interconnection system–Petersen-star network and other optical transpose interconnection system networks. Finally, we propose a routing algorithm with a time complexity of 6 n − 1 and a one-to-all broadcasting algorithm with a time complexity of 2 n − 1.

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12

Jang, Keon Woo, Woo Jae Jeong, and Yeonsik Kang. "Development of a GPU-Accelerated NDT Localization Algorithm for GNSS-Denied Urban Areas." Sensors 22, no. 5 (March 1, 2022): 1913. http://dx.doi.org/10.3390/s22051913.

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There are numerous global navigation satellite system-denied regions in urban areas, where the localization of autonomous driving remains a challenge. To address this problem, a high-resolution light detection and ranging (LiDAR) sensor was recently developed. Various methods have been proposed to improve the accuracy of localization using precise distance measurements derived from LiDAR sensors. This study proposes an algorithm to accelerate the computational speed of LiDAR localization while maintaining the original accuracy of lightweight map-matching algorithms. To this end, first, a point cloud map was transformed into a normal distribution (ND) map. During this process, vector-based normal distribution transform, suitable for graphics processing unit (GPU) parallel processing, was used. In this study, we introduce an algorithm that enabled GPU parallel processing of an existing ND map-matching process. The performance of the proposed algorithm was verified using an open dataset and simulations. To verify the practical performance of the proposed algorithm, the real-time serial and parallel processing performances of the localization were compared using high-performance and embedded computers, respectively. The distance root-mean-square error and computational time of the proposed algorithm were compared. The algorithm increased the computational speed of the embedded computer almost 100-fold while maintaining high localization precision.

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13

Curiel, Mariela, David F. Calle, Alfredo S. Santamaría, David F. Suarez, and Leonardo Flórez. "Parallel Processing of Images in Mobile Devices using BOINC." Open Engineering 8, no. 1 (April 19, 2018): 87–101. http://dx.doi.org/10.1515/eng-2018-0012.

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Abstract Medical image processing helps health professionals make decisions for the diagnosis and treatment of patients. Since some algorithms for processing images require substantial amounts of resources, one could take advantage of distributed or parallel computing. A mobile grid can be an adequate computing infrastructure for this problem. A mobile grid is a grid that includes mobile devices as resource providers. In a previous step of this research, we selected BOINC as the infrastructure to build our mobile grid. However, parallel processing of images in mobile devices poses at least two important challenges: the execution of standard libraries for processing images and obtaining adequate performance when compared to desktop computers grids. By the time we started our research, the use of BOINC in mobile devices also involved two issues: a) the execution of programs in mobile devices required to modify the code to insert calls to the BOINC API, and b) the division of the image among the mobile devices as well as its merging required additional code in some BOINC components. This article presents answers to these four challenges.

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14

Inkinen, Sami J. "Parallel image processing." Signal Processing 35, no. 1 (January 1994): 97–98. http://dx.doi.org/10.1016/0165-1684(94)90197-x.

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15

Aspinall, D. "Structures for parallel processing." Computing & Control Engineering Journal 1, no. 1 (1990): 15. http://dx.doi.org/10.1049/cce:19900005.

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16

Khudhair, Muslim Mohsin, Adil AL-Rammahi, and Furkan Rabee. "An innovativefractal architecture model for implementing MapReduce in an open multiprocessing parallel environment." Indonesian Journal of Electrical Engineering and Computer Science 30, no. 2 (May 1, 2023): 1059. http://dx.doi.org/10.11591/ijeecs.v30.i2.pp1059-1067.

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One of the infrastructure applications that cloud computing offers as a service is parallel data processing. MapReduce is a type of parallel processing used more and more by data-intensive applications in cloud computing environments. MapReduce is based on a strategy called "divide and conquer," which uses regular computers, also called "nodes," to do processing in parallel. This paper looks at how open multiprocessing (OpenMP), the best shared-memory parallel programming model for high-performance computing, can be used with the proposed fractal network model in the MapReduce application. A well-known model, the cube, is used to compare the fractal network model and its work. Where experiments demonstrated that the fractal model is preferable to the cube model. The fractal model achieved an average speedup of 2.7 and an efficiency rate of 67.7%. In contrast, the cube model could only reach an average speedup of 2.5 and an efficiency rate of 60.4%.

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17

Xing, Junjie, Shixian Qin, Binglin Lai, Bowen Li, Zhida Li, and Guocheng Zhang. "Top-Gate Transparent Organic Synaptic Transistors Based on Co-Mingled Heterojunctions." Electronics 12, no. 7 (March 29, 2023): 1596. http://dx.doi.org/10.3390/electronics12071596.

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The rapid development of electronics and materials science has driven the progress of various electronic devices, and the new generation of electronic devices, represented by wearable smart products, has introduced transparent new demands on the devices. The ability of biological synapses to enhance or inhibit information when it is transmitted is thought to be the biological mechanism of artificial synaptic devices. The advantage of the human brain over conventional computers is the ability to perform efficient parallel operations when dealing with unstructured and complex problems. Inspired by biologically powerful neural networks, it is important to simulate biological synaptic functions on a single electronic device, and organic artificial synaptic transistors are artificially intelligent and very suitable artificial synaptic devices. Therefore, this paper proposes an organic artificial synaptic transistor with transparency (≥75%), provides a new solution for transparent top-gate synapses, and shows their promise for the next generation of organic electronics.

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18

Downton, A., and D. Crookes. "Parallel architectures for image processing." Electronics & Communication Engineering Journal 10, no. 3 (June 1, 1998): 139–51. http://dx.doi.org/10.1049/ecej:19980307.

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19

Kohata, Naoki, Toru Yamaguchi, Takanobu Baba, and Hideki Hashimoto. "Chaotic Evolutionary Parallel Computation on Intelligent Agents." Journal of Robotics and Mechatronics 10, no. 5 (October 20, 1998): 424–30. http://dx.doi.org/10.20965/jrm.1998.p0424.

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This paper proposes evolutionary computation using chaotic dynamics rather than the conventional genetic algorithm (GA) for such intelligent agents as welfare robots. Proposed evolutionary computation applies chaotic retrieval to associative memory. We applied evolutionary computation to multiagent robots moving side by side in step. Evolutionary computation is basically parallel processing, so we implement its parallel processing algorithm on A-NET (Actors NETwork) parallel objectoriented computer to show usefulness of parallel processing in evolutionary computation.

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20

Khudhair, Muslim Mohsin, Furkan Rabee, and Adil AL_Rammahi. "New efficient fractal models for MapReduce in OpenMP parallel environment." Bulletin of Electrical Engineering and Informatics 12, no. 4 (August 1, 2023): 2313–27. http://dx.doi.org/10.11591/beei.v12i4.4977.

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Parallel data processing is one of the specific infrastructure applications categorized as a service provided by cloud computing. In cloud computing environments, data-intensive applications increasingly use the parallel processing paradigm known as MapReduce. MapReduce is based on a strategy called "divide and conquer," which uses ordinary computers, also called "nodes," to do processing in parallel. This paper looks at how open multiprocessing (OpenMP), the best shared-memory parallel programming model for high-performance computing, can be used in the MapReduce application using proposed fractal network models. Two fractal network models are offered, and their work is compared with a well-known network model, the hypercube. The first fractal network model achieved an average speedup of 3.239 times while an efficiency ranged from 73-95%. In the second model of the network, the speedup got to 3.236 times while keeping an efficiency of 70-92%. Furthermore, the path-finding algorithm employed in the recommended fractal network models remarkably identified all paths and calculated the shortest and longest routes.

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21

Khudhair, Muslim Mohsin, Furkan Rabee, and Adil AL_Rammahi. "New efficient fractal models for MapReduce in OpenMP parallel environment." Bulletin of Electrical Engineering and Informatics 12, no. 4 (August 1, 2023): 2313–27. http://dx.doi.org/10.11591/eei.v12i4.4977.

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Parallel data processing is one of the specific infrastructure applications categorized as a service provided by cloud computing. In cloud computing environments, data-intensive applications increasingly use the parallel processing paradigm known as MapReduce. MapReduce is based on a strategy called "divide and conquer," which uses ordinary computers, also called "nodes," to do processing in parallel. This paper looks at how open multiprocessing (OpenMP), the best shared-memory parallel programming model for high-performance computing, can be used in the MapReduce application using proposed fractal network models. Two fractal network models are offered, and their work is compared with a well-known network model, the hypercube. The first fractal network model achieved an average speedup of 3.239 times while an efficiency ranged from 73-95%. In the second model of the network, the speedup got to 3.236 times while keeping an efficiency of 70-92%. Furthermore, the path-finding algorithm employed in the recommended fractal network models remarkably identified all paths and calculated the shortest and longest routes.

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22

Kokaji, Shigeru. "Parallel Processing Systems for Robot Control." Journal of Robotics and Mechatronics 2, no. 6 (December 20, 1990): 479–84. http://dx.doi.org/10.20965/jrm.1990.p0479.

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23

Marchant, John. "Parallel processing for produce inspection." Computing & Control Engineering Journal 2, no. 5 (1991): 241. http://dx.doi.org/10.1049/cce:19910065.

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24

Wey, Chin-Long. "Parallel processing for analogue fault diagnosis." International Journal of Circuit Theory and Applications 16, no. 3 (July 1988): 303–16. http://dx.doi.org/10.1002/cta.4490160303.

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25

Zalewski, Janusz. "Parallel processing in digital control." Control Engineering Practice 2, no. 6 (December 1994): 1095–96. http://dx.doi.org/10.1016/0967-0661(94)91886-4.

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26

Cucchiara, Rita, Luigi Di Stefano, Massimo Piccardi, and Tullio Salmon Cinotti. "The GIOTTO System: a Parallel Computer for Image Processing." Real-Time Imaging 3, no. 5 (October 1997): 343–53. http://dx.doi.org/10.1006/rtim.1996.0069.

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27

Yoshikawa, Masaya, and Hidekazu Terai. "Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption." Journal of Advanced Computational Intelligence and Intelligent Informatics 11, no. 2 (February 20, 2007): 168–75. http://dx.doi.org/10.20965/jaciii.2007.p0168.

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With portable information devices now widely disseminated, low power consumption LSIs are increasingly needed in battery, implementation, and heat generation applications. We propose parallel placement to realize low power consumption and confirm its effectiveness in experiments with a commercial electronic design automation (EDA) tool for designing LSIs. Our proposal hierarchically combines outline and detail placement based on genetic algorithm. In selection operators, new evaluation functions are introduced for realizing the reduction of power consumption focusing on the signal transition probability. Considering a parallel processing, in which a processing speed has a scalable relation with the number of processors, and by implementing it in a parallel computer, its effect is demonstrated.

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28

Yetiş, Hasan, and Mehmet Karaköse. "A New Framework Containing Convolution and Pooling Circuits for Image Processing and Deep Learning Applications with Quantum Computing Implementation." Traitement du Signal 39, no. 2 (April 30, 2022): 501–12. http://dx.doi.org/10.18280/ts.390212.

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The resource need for deep learning and quantum computers' high computing power potential encourage collaboration between the two fields. Today, variational quantum circuits are used to perform the convolution operation with quantum computing. However, the results produced by variational circuits do not show a direct resemblance to the classical convolution operation. Because classical data is encoded into quantum data with their exact values in value-encoded methods, in contrast to variational quantum circuits, arithmetical operations can be applied with high accuracy. In this study, value-encoded quantum circuits for convolution and pooling operations are proposed to apply deep learning in quantum computers in a traditional and proven way. To construct the convolution and pooling operations, some modules such as addition, multiplication, division, and comparison are created. In addition, a window-based framework for quantum image processing applications is proposed. The generated convolution and pooling circuits are simulated on the IBM QISKIT simulator in parallel thanks to the proposed framework. The obtained results are verified by the expected results. Due to the limitations of quantum simulators and computers in the NISQ era, the used grayscale images are resized to 8x8 and the resolution of the images is reduced to 3 qubits. With developing the quantum technologies, the proposed approach can be applied for bigger and higher resolution images. Although the proposed method causes more qubit usage and circuit depth compared to variational convolutional circuits, the results they produce are exactly the same as the classical convolution process.

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29

Ishikawa, Masatoshi. "Active Sensor System Using Parallel Processing Circuits." Journal of Robotics and Mechatronics 5, no. 1 (February 20, 1993): 31–37. http://dx.doi.org/10.20965/jrm.1993.p0031.

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In this paper, an active sensor system using parallel processing circuits is proposed and its characteristics are discussed. From the perspective of a model of active touch sensory processing mechanism, the system uses information of efferent copy and internal actuator model in order to generate active motions from the local pattern information detected by local pattern sensors, such as tactile sensors. In addition, an experimental system and its basic experimental results are described. The experimental system is a sensor system for active perception of the shape of two-dimensional objects by tracing the edge of the objects. The system realizes both high speed processing of the local pattern and real-time control of the actuator.

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30

Glivenko, E. V., S. А. Sorokin, and G. N. Petrovа. "IDEA OF ARCHITECTURE OF A MULTIPROCESSOR COMPUTER M-10 AND THEIR IMPLEMENTATION IN MODERN COMPUTING PLATFORMS (IN SMALL FORMS)." Issues of radio electronics, no. 5 (June 8, 2019): 28–31. http://dx.doi.org/10.21778/2218-5453-2019-5-28-31.

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The article is devoted to the design of high‑performance computing devices for parallel processing of information. The problem of increasing the productivity of computing facilities by one or several orders of magnitude is considered on the example of the high‑ performance electronic computer M‑10, which was created in the 1970s at the NIIVK. If in a conventional computer, the method of processing numbers is given by commands, then in M‑10, the methods for processing a function were specified by operators taken from functional analysis. At the same time, the possibility of parallel processing of an entire information line appeared. Such systems began to be called «functional operator type machines». The main ideas presented in the article may be of interest to developers of specialized machines of the new generation, as well as engineers involved in the creation of high‑performance computing devices using technologies of computing platforms.

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31

Barkovska, Olesia, Viktor Khomych, and Oleksandr Nastenko. "RESEARCH OF THE TEXT PROCESSING METHODS IN ORGANIZATION OF ELECTRONIC STORAGES OF INFORMATION OBJECTS." Innovative Technologies and Scientific Solutions for Industries, no. 1 (19) (April 26, 2022): 5–12. http://dx.doi.org/10.30837/itssi.2022.19.005.

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The subject matter of the article is electronic storage of information objects (IO) ordered by specified rules at the stage of accumulation of qualification thesis and scientific work of the contributors of the offered knowledge exchange system provided to the system in different formats (text, graphic, audio). Classified works of contributors of the system are the ground for organization of thematic rooms for discussion to spread scientific achievements, to adopt new ideas, to exchange knowledge and to look for employers or mentors in different countries. The goal of the work is to study the libraries of text processing and analysis to speed-up and increase accuracy of the scanned text documents classification in the process of serialized electronic storage of information objects organization. The following tasks are: to study the text processing methods on the basis of the proposed generalized model of the system of classification of scanned documents with the specified location of the block of text processing and analysis; to investigate the statistics of change in the execution time of the developed parallel modification of the methods of the word processing module for the system with shared memory for collections of text documents of different sizes; analyze the results. The methods used are the following: parallel digital sorting methods, methods of mathematical statistics, linguistic methods of text analysis. The following results were obtained: in the course of the research fulfillment the generalized model of the scanned documents classification system that consist of image processing unit and text processing unit that include unit of the scanned image previous processing; text detection unit; previous text processing; compiling of the frequency dictionary; text proximity detection was offered. Conclusions: the proposed parallel modification of the previous text processing unit gives acceleration up to 3,998 times. But, at a very high computational load (collection of 18144 files, about 1100 MB), the resources of an ordinary multiprocessor-based computer with the shared memory obviously is not enough to solve such problems in the mode close to real time.

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32

Glass, A. M. "Materials for Photonic Switching and Information Processing." MRS Bulletin 13, no. 8 (August 1988): 16–20. http://dx.doi.org/10.1557/s0883769400064629.

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In electronic processors, heat dissipation and interconnection delay are serious design and performance limiting factors. Why then consider photonic components where both the energy and size of the photon are large (˜1 eV and ˜1 μm, respectively) and the required nonlinear interactions between electric or magnetic fields and photons for switching or modulation are small? There are several answers to this question. First, the wide bandwidth of optical communications systems is taxing the current capabilities of electronic switching technologies. Even a slow optical switch can switch a very wide bandwidth optical signal from one fiber to another. External optical modulators will likely be required in ultrawide bandwidth communications because of basic limitations on direct modulation of lasers. Because of the weak electromagnetic interaction and low dispersion, optical interconnection of electronic circuits offers considerable advantages in high speed computer architectures. Some of these applications would appear to be relatively near term since they build on current capabilities of optical communication.Longer term and more speculative are applications of photonics to computation and image processing — areas where electronics technology is already mature. Current research can be divided into two groups — ultrafast processing and parallel processing. The first group concentrates on processing with ultra-fast optical pulses. Optical pulses as short as 6 fs — orders of magnitude shorter than any electronic pulses — have been generated in the research laboratory. High processing rates are achievable by serial processing of high repetition rate ultrashort pulses. This approach requires ultrafast switches, which in turn requires materials with ultrafast nonlinear optical response time. Indeed, the shortest electrical signals are now measured by optical sampling techniques.

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33

Quintuna Rodriguez, Veronica, and Fabrice Guillemin. "Cloud-RAN Modeling Based on Parallel Processing." IEEE Journal on Selected Areas in Communications 36, no. 3 (March 2018): 457–68. http://dx.doi.org/10.1109/jsac.2018.2815378.

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34

Thompson, H. A. "Parallel processing architectures for aerospace applications." Control Engineering Practice 2, no. 3 (June 1994): 509–20. http://dx.doi.org/10.1016/0967-0661(94)90789-7.

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35

D'Autrechy, C. Lynne, and James A. Reggia. "Parallel plan execution with self-processing networks." Telematics and Informatics 6, no. 3-4 (January 1989): 145–57. http://dx.doi.org/10.1016/s0736-5853(89)80012-7.

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36

O.Pandithurai, Et al. "Dual-Step Parallel Approach for Network Flow Restoration to File." International Journal on Recent and Innovation Trends in Computing and Communication 11, no. 3 (March 31, 2023): 319–22. http://dx.doi.org/10.17762/ijritcc.v11i3.9860.

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This paper presents a network flow recovery method that focuses on recovering network flow to a file. The proposed method utilizes a two-stage parallel strategy to maximize the processing efficiency of multi-core computers. It involves acquiring high-speed flow, splitting the flow using Mac address xor and IP address xor methods, and resolving the initial flow into multiple thin flows. The method employs a 'producer-consumer model' loose coupling multithreading framework for data transfer within the thin flow recovery flow path, achieving parallelism at the threading level. Load balancing is implemented on each thin flow, and support for both IPv4 and IPv6 protocols is provided. The objective of this research is to address the challenge of converting "invisible" network flow into computationally processable information under high-speed network bandwidth. By doing so, this method offers technical support for identifying and blocking illegal network information transmission.

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37

Szczepankiewicz, Karolina, Mateusz Malanowski, and Michał Szczepankiewicz. "Passive Radar Parallel Processing Using General-Purpose Computing on Graphics Processing Units." International Journal of Electronics and Telecommunications 61, no. 4 (December 1, 2015): 357–63. http://dx.doi.org/10.1515/eletel-2015-0047.

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Abstract In the paper an implementation of signal processing chain for a passive radar is presented. The passive radar which was developed at the Warsaw University of Technology, uses FM radio and DVB-T television transmitters as ”illuminators of opportunity”. As the computational load associated with passive radar processing is very high, NVIDIA CUDA technology has been employed for effective implementation using parallel processing. The paper contains the description of the algorithms implementation and the performance results analysis.

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38

ROSENDAHL, G. K., R. D. MCLEOD, and H. C. CARD. "A DSP–FPGA-BASED RECONFIGURABLE COMPUTER." Journal of Circuits, Systems and Computers 08, no. 04 (August 1998): 453–59. http://dx.doi.org/10.1142/s0218126698000250.

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In order to exploit architectural advantages associated with specific computations while at the same time having flexibility in those computations, we have designed a reconfigurable parallel machine architecture. A prototype reconfigurable computer has been constructed based on digital signal processing (DSP) chips and field-programmable gate arrays (FPGAs). Communications are based upon a broadcast network that employs FPGA-based message pre-processing and post-processing. Tradeoffs between computational and communication performance are made possible by software reconfiguration of the FPGAs. The system has been successfully tested on several applications in signal processing.

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Erenyi, I., and Z. Fazekas. "Image processing applications and their parallel aspects." Computing & Control Engineering Journal 5, no. 2 (April 1, 1994): 71–74. http://dx.doi.org/10.1049/cce:19940207.

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Mertzios, B. G. "Block parallel processing of 2-D digital signals." International Journal of Circuit Theory and Applications 14, no. 3 (July 1986): 211–28. http://dx.doi.org/10.1002/cta.4490140304.

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ZIPPEL, RICHARD. "THE DATA STRUCTURE ACCELERATOR ARCHITECTURE." International Journal of High Speed Electronics and Systems 07, no. 04 (December 1996): 533–71. http://dx.doi.org/10.1142/s012915649600030x.

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We present a heterogeneous architecture that contains a fine grained, massively parallel SIMD component called the data structure accelerator and demonstrate its use in a number of problems in computational geometry including polygon filling and convex hull. The data structure accelerator is extremely dense and highly scalable. Systems of 106 processing elements can be embedded in workstations and personal computers, without dramatically changing their cost. These components are intended for use in tandem with conventional single sequence machines and with small scale, shared memory multiprocessors. A language for programming these heterogeneous systems is presented that smoothly incorporates the SIMD instructions of the data structure accelerator with conventional single sequence code. We then demonstrate how to construct a number of higher level primitives such as maximum and minimum, and apply these tools to problems in logic and computational geometry. For computational geometry problems, we demonstrate that simple algorithms that take advantage of the parallelism available on a data structure accelerator perform as well or better than the far more complex algorithms which are needed for comparable efficiency on single sequence computers.

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Zalewski, Janusz. "Parallel processing in industrial real-time applications." Control Engineering Practice 2, no. 5 (October 1994): 924–25. http://dx.doi.org/10.1016/0967-0661(94)90564-9.

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Zalewski, Janusz. "Parallel processing in a control systems environment." Control Engineering Practice 2, no. 5 (October 1994): 925–26. http://dx.doi.org/10.1016/0967-0661(94)90565-7.

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Marsh, Shaun. "Recognizing the parallelism of data-flow: Many computer architectures expedite parallel processing." IEEE Potentials 6, no. 1 (February 1987): 28–31. http://dx.doi.org/10.1109/mp.1987.6500906.

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Engel, Alejandro B. "True parallel processing in artificial neural networks." Kybernetes 30, no. 9/10 (December 2001): 1192–98. http://dx.doi.org/10.1108/03684920110405764.

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Paprzycki, M. "Portability and performance for parallel processing [Book Reviews]." IEEE Parallel & Distributed Technology: Systems & Applications 3, no. 3 (1995): 72. http://dx.doi.org/10.1109/m-pdt.1995.414848.

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Cai, Jun, Zhongwei Huang, Liping Liao, Jianzhen Luo, and Wai-Xi Liu. "APPM: Adaptive Parallel Processing Mechanism for Service Function Chains." IEEE Transactions on Network and Service Management 18, no. 2 (June 2021): 1540–55. http://dx.doi.org/10.1109/tnsm.2021.3052223.

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Ishikawa, Masatoshi. "High-Speed Vision and its Applications Toward High-Speed Intelligent Systems." Journal of Robotics and Mechatronics 34, no. 5 (October 20, 2022): 912–35. http://dx.doi.org/10.20965/jrm.2022.p0912.

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Currently, high-speed vision based on parallel processing exists, and its various applications as high-speed intelligent systems have been proposed and implemented. The basic goal of high-speed vision is to realize vision capabilities and systems that operate at speeds necessary for intelligent systems, in which intelligence operating at the speed inherently required by the application system is achieved. This paper described the vision chip and parallel image processing architectures, presented outlines of system architectures, image-processing algorithms, and related peripheral technologies; described the concepts required to configure high-speed intelligent systems, such as hierarchical parallel distributed architecture, parallel decomposition, orthogonal decomposition, dynamics matching, latency minimization, high-speed 3D shape measurement, active vision, tracking vision, dynamic compensation, and dynamic projection mapping; and discussed a wide range of application systems in a systematic manner.

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Tooyama, Osamu, Shinji Takase, Akira Watanabe, and Junichi Akita. "Fast coordinates generating circuit for pixel parallel processing." Electronics and Communications in Japan (Part II: Electronics) 85, no. 6 (June 2002): 27–32. http://dx.doi.org/10.1002/ecjb.1109.

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AbdulRazzaq, Atheer Akram, Mohammed A. Fadhel, Laith Alzubaidi, and Omran Al-Shamma. "Parallel processing of E-Atheer algorithm using pthread paradigm." Indonesian Journal of Electrical Engineering and Computer Science 30, no. 3 (June 1, 2023): 1624. http://dx.doi.org/10.11591/ijeecs.v30.i3.pp1624-1633.

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The development in the field of computer technology, and the increase in the growth rate of database, alongside the extraction of certain data from a huge pool of database involve intricate and complex processes. The processes comprise text mining, pattern recognition, retrieval of information and text processing. Thus, the need for enhancing the performance of string matching algorithms is required, which is considered as one of the challenges to the researchers. Consequently, one of the resolution to address this problem is the parallelization for exact string matching algorithms. In this study, we implemented the parallel exact string matching algorithm termed as E-Atheer with multi-core processing utilizing Pthread (POSIX) for the reduction of time consumption. The Pitch, XML, Protein, and DNA database types are utilized to test the impact of the proposed parallel algorithm. The parallelization algorithm obtained positive results in the parallel execution time, and a more superior expediting capabilities, in comparison to the sequential result. The Pitch database indicated optimal results in parallel execution time, and when utilizing long and short pattern lengths. The DNA database indicated optimal speedup performance when utilizing short and long pattern length, meanwhile the XML and Protein on the other hand indicated the worst results.

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