Dissertations / Theses on the topic 'Packard Band'
To see the other types of publications on this topic, follow the link: Packard Band.
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 26 dissertations / theses for your research on the topic 'Packard Band.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Duo, Xinzhong. "System-on-package solutions for multi-band RF front end." Doctoral thesis, Stockholm, 2005. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-482.
Full text
2
Bapu, Vijay Madhukar. "Eliminating package resonances in printed circuit boards over wide frequency band." Diss., Online access via UMI:, 2004. http://wwwlib.umi.com/dissertations/fullcit/1424171.
Full text
3
Liu, Zhengyang. "Characterization and Application of Wide-Band-Gap Devices for High Frequency Power Conversion." Diss., Virginia Tech, 2017. http://hdl.handle.net/10919/77959.
Full textAbstract:
Advanced power semiconductor devices have consistently proven to be a major force in pushing the progressive development of power conversion technology. The emerging wide-band-gap (WBG) material based power semiconductor devices are considered as gaming changing devices which can exceed the limit of silicon (Si) and be used to pursue groundbreaking high-frequency, high-efficiency, and high-power-density power conversion.
The switching performance of cascode GaN HEMT is studied at first. An accurate behavior-level simulation model is developed with comprehensive consideration of the impacts of parasitics. Then based on the simulation model, detailed loss breakdown and loss mechanism analysis are studied. The cascode GaN HEMT has high turn-on loss due to the reverse recovery charge and junction capacitor charge, and the common source inductance (CSI) of the package; while the turn-off loss is extremely small attributing to unique current source turn off mechanism of the cascode structure.
With this unique feature, the critical conduction mode (CRM) soft switching technique is applied to reduce the dominant turn on loss and significantly increase converter efficiency. The switching frequency is successfully pushed to 5MHz while maintaining high efficiency and good thermal performance.
Traditional packaging method is becoming a bottle neck to fully utilize the advantages of GaN HEMT. So an investigation of the package influence on the cascode GaN HEMT is also conducted. Several critical parasitic inductance are identified, which cause high turn on loss and high parasitic ringing that may lead to device failure. To solve the issue, the stack-die package is proposed to eliminate all critical parasitic inductance, and as a result, reducing turn on loss by half and avoiding potential failure mode of the cascode GaN device effectively.
Utilizing soft switching and enhanced packaging, a GaN-based MHz totem-pole PFC rectifier is demonstrated with 99% peak efficiency and 700 W/in3 power density. The switching frequency of the PFC is more than ten times higher than the state-of-the-art industry product while it achieves best possible efficiency and power density. Integrated power module and integrated PCB winding coupled inductor are all studied and applied in this PFC.
Furthermore, the technology of soft switching totem-pole PFC is extended to a bidirectional rectifier/inverter design. By using SiC MOSFETs, both operating voltage and power are dramatically increased so that it is successfully applied into a bidirectional on-board charger (OBC) which achieves significantly improved efficiency and power density comparing to the best of industrial practice. In addition, a novel 2-stage system architecture and control strategy are proposed and demonstrated in the OBC system.
As a continued extension, the critical mode based soft switching rectifier/inverter technology is applied to three-phase AC/DC converter. The inherent drawback of critical mode due to variable frequency operation is overcome by the proposed new modulation method with the idea of frequency synchronization. It is the first time that a critical mode based modulation is demonstrated in the most conventional three phase H-bridge AC/DC converter, and with 99% plus efficiency at above 300 kHz switching frequency.Ph. D.
4
Fourquin, Olivier. "Conception et intégration en technologie "System in Package" d'émetteurs récepteurs ultra large bande pour communications ULB impulsionnelles dans la bande de fréquence 3.1 - 10.6 GHz." Thesis, Aix-Marseille 1, 2011. http://www.theses.fr/2011AIX10133/document.
Full textAbstract:
Les systèmes radio impulsionnelle Ultra large bande (IR-ULB), de part la nature de leurs signaux et de leurs architectures, montrent des caractéristiques intéressantes pour concurrencer les technologies existantes (Zigbee, Bluetooth et RFID) pour certaines applications nécessitant un faible coût et une faible consommation de puissance. Dans ce contexte cette thèse évalue les potentialités des systèmes IR-ULB pour la réalisation d’objets communicants miniatures.En utilisant une technologie "System In Package" (SiP), des objets communicants ULB prototype intégrant une ou plusieurs puces CMOS et une antenne ULB directement réalisée sur le boîtier sont présentés dans la thèse. Les transitions entre le circuit imprimé et les puces sont réalisées avec des fils d'interconnexion ("wirebonding"). Les points d'étude de la thèse se focalisent particulièrement sur la mise en boîtier d'une puce ULB et sur la conception sur silicium de la tête radio fréquence d'un système ULB. La réalisation d'une interconnexion faible cout par "wirebonding" entre un circuit intégré ULB et son support est problématique aux fréquences utilisées en ULB (3-10 GHz) en raison des éléments parasites importants limitant sa bande passante. Pour obtenir une transition ne dégradant pas les signaux ULB, plusieurs méthodologies d’interfaçage sont proposées permettant de réaliser sans augmentation notable de cout une transition large bande entre le circuit intégré et le circuit imprimé du boîtier. L'intégration en technologie CMOS standard des éléments principaux constituant la tête radio fréquence d'un système ULB impulsionnel (LNA, détecteur d'impulsions et générateurs d'impulsions) est étudiée. L'intérêt d'un co-design entre le silicium et le circuit imprimé lors de la conception de ces éléments est mis en avant. L'intégration ainsi que la miniaturisation du système final dans une technologie SIP sont également présentéesDue to the nature of their signals and their architectures, Impulse Radio Ultra Wide Band (IR-UWB) systems show interesting features to compete with existing technologies (Zigbee, Bluetooth and RFID UHF) for low cost and low power applications. In this context, this thesis evaluates the potential of UWB systems for the realization of miniature communication devices.The thesis presents UWB communicating devices realized with a System in Package (SiP) technology. Devices incorporate one or several CMOS chips and an antenna directly printed on the board (PCB). Transitions between the PCB and the chips are made with standard wire bonds. The thesis especially focuses on packaging of UWB dice and on the design of UWB front end radio frequency.Due to important parasitic elements limiting its bandwidth, wire bonds transition is problematic for UWB applications (3-10 GHz). This thesis proposes several methodologies to interface integrated circuit and PCB to obtain a broadband transition without increasing cost production. The integration in standard CMOS technology of main components comprising the UWB radio frequency front end (LNA, pulse detector and pulse generator) is studied. The interest of a co-design between silicon and PCB to design these elements is pointed up. Integration and miniaturization of the final system in a SIP technology are also presented
5
Morton, Matthew Allan. "Development of Monolithic SiGe and Packaged RF MEMS High-Linearity Five-bit High-Low Pass Phase Shifters for SoC X-band T/R Modules." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/16190.
Full textAbstract:
A comprehensive study of the High-pass/Low-pass topology has been performed, increasing the understanding of error sources arising from bit layout issues and fabrication tolerances. This included a detailed analysis of error sources in monolithic microwave phase shifters due to device size limitations, inductor parasitics, loading effects, and non-ideal switches. Each component utilized in the implementation of a monolithic high-low pass phase shifter was analyzed, with its influence on phase behavior shown in detail. An emphasis was placed on the net impact on absolute phase variation, which is critical to the system performance of a phased array radar system. The design of the individual phase shifter filter sections, and the influence of bit ordering on overall performance was also addressed.
A variety of X-band four- and five-bit phase shifters were fabricated in a 200 GHz SiGe HBT BiCMOS technology platform, and further served to validate the analysis and design methodology. The SiGe phase shifter can be successfully incorporated into a single-chip T/R module forming a system-on-a-chip (SoC).
Reduction in the physical size of transmission lines was shown to be a possibility with spinel magnetic nanoparticle films. The signal transmission properties of phase lines treated with nanoparticle thin films were examined, showing the potential for significant size reduction in both delay line and High-pass/Low-pass phase topologies.
Wide-band, low-loss, and near-hermetic packaging techniques for RF MEMS devices were presented. A thermal compression bonding technique compatible with standard IC fabrication techniques was shown, that uses a low temperature thermal compression bonding method that avoids plastic deformations of the MEMS membrane.
Ultimately, a system-on-a-package (SoP) approach was demonstrated that utilized packaged RF MEMS switches to maintain the performance of the SiGe phase shifter with much lower loss. The extremely competitive performance of the MEMS-based High-pass/Low-pass phase shifter, despite the lack of the extensive toolkits and commercial fabrication facilities employed with the active-based SiGe phase shifters, confirms both the effectiveness of the detailed phase error analysis presented in this work and the robust nature of the High-pass/Low-pass topology.
6
Bourgeois, Edouard, and Fatmir Stublla. "How is remuneration used in Bank, Financial, and Insurance companies to retain employees in France and Kosovo?" Thesis, Växjö University, School of Management and Economics, 2008. http://urn.kb.se/resolve?urn=urn:nbn:se:vxu:diva-2219.
Full text
7
Borsatto, João Victor Basolli. "Colunas empacotadas em cromatografia líquida capilar: desenvolvimento de hardwares e avaliação de suas contribuições no desempenho cromatográfico." Universidade de São Paulo, 2018. http://www.teses.usp.br/teses/disponiveis/75/75135/tde-23102018-170956/.
Full textAbstract:
Essa dissertação de mestrado descreve o desenvolvimento de hardwares de colunas para cromatografia líquida capilar. O processo de desenvolvimentos desses dispositivos é descrito gradativamente e os pontos fortes e as limitações de cada modelo de hardware são discutidos. O melhor modelo de hardware desenvolvido apresentou produção simples, fácil conexão ao sistema cromatográfico e resistência a pressões superiores a 900 bar. Sucessivamente ao estabelecimento de um modelo de hardware apropriado, os efeitos dos materiais do hardware na eficiência das colunas foram avaliados. Poucos estudos relatam a influência do hardware nas separações em escala capilar, de forma que essa dissertação contribui para o preenchimento dessa lacuna. Capilares de aço inoxidável e sílica fundida e frits de aço inoxidável e fibra de vidro foram avaliados. Colunas com eficiências superiores a 100.000 pratos por metro foram produzidas.This master\'s dissertation describes the development of hardware for capillary liquid chromatography columns. The development process of the devices is described gradually and the strengths and limitations of each model of hardware are discussed. The best-developed hardware model presented easy production, practice connection to the chromatographic system and resistance to pressures greater than 900 bar. After the establishment of an appropriate hardware model, the effects of hardware materials on the efficiency of the columns were evaluated. Few studies report the influence of the hardware on capillary scale separations; therefore, this dissertation contributes to fill this gap. Capillaries of stainless steel and fused silica and frits of stainless steel and glass fiber were evaluated. Columns with efficiencies greater than 100,000 plates per meter were produced.
8
Govind, Vinu. "Design of Baluns and Low Noise Amplifiers in Integrated Mixed-Signal Organic Substrates." Diss., Georgia Institute of Technology, 2005. http://hdl.handle.net/1853/7208.
Full textAbstract:
The integration of mixed-signal systems has long been a problem in the semiconductor industry. CMOS System-on-Chip (SOC), the traditional means for integration, fails mixed-signal systems on two fronts; the lack of on-chip passives with high quality (Q) factors inhibits the design of completely integrated wireless circuits, and the noise coupling from digital to analog circuitry through the conductive silicon substrate degrades the performance of the analog circuits. Advancements in semiconductor packaging have resulted in a second option for integration, the System-On-Package (SOP) approach. Unlike SOC where the package exists just for the thermal and mechanical protection of the ICs, SOP provides for an increase in the functionality of the IC package by supporting multiple chips and embedded passives. However, integration at the package level also comes with its set of hurdles, with significant research required in areas like design of circuits using embedded passives and isolation of noise between analog and digital sub-systems.
A novel multiband balun topology has been developed, providing concurrent operation at multiple frequency bands. The design of compact wideband baluns has been proposed as an extension of this theory. As proof-of-concept devices, both singleband and wideband baluns have been fabricated on Liquid Crystalline Polymer (LCP) based organic substrates. A novel passive-Q based optimization methodology has been developed for chip-package co-design of CMOS Low Noise Amplifiers (LNA). To implement these LNAs in a mixed-signal environment, a novel Electromagnetic Band Gap (EBG) based isolation scheme has also been employed.
The key contributions of this work are thus the development of novel RF circuit topologies utilizing embedded passives, and an advancement in the understanding and suppression of signal coupling mechanisms in mixed-signal SOP-based systems. The former will result in compact and highly integrated solutions for RF front-ends, while the latter is expected to have a significant impact in the integration of these communication devices with high performance computing.
9
Sankaran, Nithya. "Electromagnetic coupling in multilayer thin-film organic packages with chip-last embedded actives." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/43621.
Full textAbstract:
The demands of consumer electronic products to support multi-functionality such as computing, communication and multimedia applications with reduced form factor and low cost is the driving force behind packaging technologies such as System on Package (SOP). SOP aims to enhance the functionality of the package while providing form factor reduction by the integration of active and passive components. However, embedding components within mixed signal packages causes unwanted interferences across the digital and analog-radio frequency (RF) sections of the package, which is a major challenge yet to be addressed. This dissertation focused on the chip-last method of embedding chips within cavities in organic packages and addressed the challenges for preserving power integrity in such packages. The challenges associated with electromagnetic coupling in packages when chips are embedded within the substrate layers are identified, analyzed and demonstrated. The presence of the chip embedded within the package introduces new interaction mechanisms between the chip and package that have not been encountered in conventional packages with surface mounted chips. It is of significant importance to understand the chip-package interaction mechanisms, for ensuring satisfactory design of systems with embedded actives. The influence of the electromagnetic coupling from the package on the bulk substrate and bond-pads of the embedded chip are demonstrated. Solutions that remedy the noise coupling using Electromagnetic Band-Gap structures (EBGs) along with design methodologies for their efficient implementation in multilayer packages are proposed. This dissertation presents guidelines for designing efficient power distribution networks in multilayer packages with embedded chips.
10
Thursby, William R. Jr, and Benjamin M. Shirley. "LOW COST SUBMINIATURE TELEMETRY SPREAD SPECTRUM TECHNOLOGY DEMONSTRATION/VALIDATION." International Foundation for Telemetering, 1995. http://hdl.handle.net/10150/608417.
Full textAbstract:
International Telemetering Conference Proceedings / October 30-November 02, 1995 / Riviera Hotel, Las Vegas, NevadaEglin Air Force Base (AFB) plans to demonstrate subminiature telemetry (SMT) spread spectrum technology, via an upgraded prototype SMT system, to validate its cost-effectiveness for both Department of Defense (DoD) and commercial use. The goal is to develop new and/or modify current SMT instrumentation using existing production methods to provide increased capabilities at lower costs and reduced size. The transmitter is to require less than 2 cubic inches of space and have a cost goal of $500/unit "in quantity." The cost goal of a ground-based, 24-channel capable ground receiver is $4000/unit "in quantity". The SMT project as well as its schedule, flight and ground demonstrations, validation criteria and goals, and various benefits are discussed.
11
Gattoni, Giacomo. "Improving the reliability of recurrent neural networks while dealing with bad data." Master's thesis, Alma Mater Studiorum - Università di Bologna, 2021.
Find full textAbstract:
In practical applications, machine learning and deep learning models can have difficulty in achieving generalization, especially when dealing with training samples that are either noisy or limited in quantity.
Standard neural networks do not guarantee the monotonicity of the input features with respect to the output, therefore they lack interpretability and predictability when it is known a priori that the input-output relationship should be monotonic. This problem can be encountered in the CPG industry, where it is not possible to ensure that a deep learning model will learn the increasing monotonic relationship between promotional mechanics and sales. To overcome this issue, it is proposed the combined usage of recurrent neural networks, a type of artificial neural networks specifically designed to deal with data structured as sequences, with lattice networks, conceived to guarantee monotonicity of the desired input features with respect to the output. The proposed architecture has proven to be more reliable when new samples are fed to the neural network, demonstrating its ability to infer the evolution of the sales depending on the promotions, even when it is trained on bad data.
12
Letowski, Bastien. "Intégration technologique alternative pour l'élaboration de modules électroniques de puissance." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAT114.
Full textAbstract:
Les performances, l’encombrement, l’efficacité et la fiabilité des dispositifs sont parmi les enjeux majeurs de l’électronique de puissance. Ils se traduisent sur la conception, la fabrication et le packaging des semiconducteurs. Aujourd’hui, le packaging 3D apporte des réponses concrètes à ces problématiques en regard de l’approche standard (2D). Malgré les excellentes propriétés de ces modules 3D au niveau de la réduction de la signature CEM et du refroidissement, la réalisation, notamment les interconnexions, est complexe. Une approche globale prenant en compte un maximum de paramètres a été développée dans cette thèse. L’ensemble de ce travail s’appuie sur deux propositions que sont la conception couplée entre les composants et le packaging ainsi qu’une fabrication collective à l’échelle de la plaque des modules de puissance. Elles se combinent par la mise en place d’une filière d’étapes technologiques appuyée sur une boite à outils de procédés génériques. Cette approche est concrétisée par la réalisation d’un module de puissance 3D performant et robuste adressant des convertisseurs polyphasés avec des gains aussi bien sur les procédés de fabrication que le module lui-même ainsi que sur le système final.Ce travail offre une nouvelle vision alternative pour l’élaboration des modules électroniques de puissance. Il ouvre également des opportunités pour une fabrication et un packaging plus performants pour les nouveaux semiconducteurs grand gapPerformances, efficiency and reliability are among the main issues in power electronics. Nowadays, 3D packaging solutions increase standard planar module (2D) performances, for instance EMC. However such integrations are based on complex manufacturing, especially concerning interconnections. Improvements require global and advanced solutions. This work depends on two proposed concepts: a coupled design of the power devices and their associated package and a collective wafer-level process fabrication. A technological offer is proposed based on an innovative power packaging toolbox. Our approach is materialized by the fabrication of a 3D polyphase power module which proved to be more efficient and reliable. The benefits are more precise process manufacturing, lower EMI generation and lower inductive interconnections.As a matter of fact, this work offers a new and advanced technological integration for future power electronics modules, perfectly suitable for the wide bandgap semiconductors
13
Ranaivoniarivo, Manohiaina. "Modélisation, caractérisation et analyse de systèmes de PLL intégrés, utilisant une approche globale puce-boîtier-circuit imprimé." Thesis, Paris Est, 2011. http://www.theses.fr/2011PEST1045/document.
Full textAbstract:
Cette thèse porte sur la caractérisation, la modélisation et l'analyse des phénomènes de «Pulling» et de «Pushing» dans les systèmes de boucles à verrouillage de phase (PLL), utilisant une approche globale où les effets de couplages électromagnétiques aux différents niveaux d'intégration (niveau puce, niveau assemblage, niveau report sur PCB) sont pris en compte de manière distribuée. L'approche de modélisation adopte une méthodologie hybride où l'analyse des couplages électromagnétiques combinée à des schémas équivalents large-bande (compatibles avec les modèles de composants actifs disponibles dans les librairies) est couplée à des représentations comportementales dynamiques. Les représentations comportementales développées permettent de capturer des effets de non-linéarités tant au niveau composant (caractéristique non-linéaire des Varicap en fonction des tensions de contrôle) qu'au niveau block de fonction (gain KVCO non uniforme de l'oscillateur contrôlé en tension (VCO) en fonction de la fréquence).Cette méthodologie hybride permet l'évaluation d'effets compétitifs résultant de phénomènes de «pulling» et de «Pushing» au niveau de la puce (influence de la PLL, effets de l'amplificateur de puissance, intégrité des alimentations ou distribution des références de masse, etc.) , et des distorsions induites par des éléments extérieurs à la puce (exemple de composants sur PCB : Filtre SAW, capacités de découplages, réseaux d'adaptation).L'approche proposée est utilisée pour l'étude et la conception de deux types de circuits développés par NXP-semi-conducteurs pour des applications liées à la sécurité automobile (PLL fonctionnant aux alentours de 1.736GHz) et à la réception satellitaire (PLL de faible consommation fonctionnant à 9.75/10.6 GHz pour les circuits LNB).Les résultats de modélisation obtenus sont validés par corrélations avec les données expérimentales et par comparaison avec les résultats obtenus de différents outils (ADS Harmonic- Balance/Transient de Agilent, Spectre de CadenceThis thesis work focuses on characterization, modeling and analysis of «Pulling» and «Pushing» phenomena in Phase Locked Loops (PLL) based on a global approach where distributed effects of electromagnetic couplings at different integration levels (chip-level, assembly-level, board or PCB-level) are taken into account. The modeling approach adopts a hybrid methodology where the analysis of electromagnetic couplings combined with broadband equivalent circuit synthesis (compatible with library models of active components) is coupled with dynamic behavioral representations. The derived behavioral representations properly capture the effects of nonlinearities both at component scale (non-linear characteristic of varicap as function of control voltages) and at function block level (non-uniform gain KVCO of VCO circuits depending on frequency).The hybrid methodology renders possible the assessment of competitive effects resulting from «Pulling» and «Pushing» phenomena at chip level (influence of the PLL, effects of the power amplifier, power integrity, or ground reference distribution, etc..), and the distortions induced by components external to the chip at package and board levels (such as components on PCB: SAW filters, decoupling capacitors, matching networks).The proposed approach is used for the study and design of two types of circuits developed by NXP- Semiconductors, for applications related to automotive security and immobilization (an RF low power transceiver Integrated Circuit (PLL running around 1.763GHz), and to satellite receiver (PLL operating at low power for LNB circuits working at 9.75/10.6 GHz).The obtained modeling results are validated by correlation with experimental data and by comparison with different time-domain and frequency-domain simulation tools results (ADS-Harmonic Balance, ADS-Shooting solutions, Cadence-Spectre)
14
Tecklenburg, Gerhard. "Design of body assemblies with distributed tasks under the support of parametric associative design (PAD)." Thesis, University of Hertfordshire, 2011. http://hdl.handle.net/2299/5809.
Full textAbstract:
This investigation identifies how CAD models of typical automotive body assemblies could be defined to allow a continuous optimisation of the number of iterations required for the final design and the number of variants on the basis of Parametric Associative Design (PAD) and how methodologies for the development of surfaces, parts and assemblies of the automotive body can be represented and structured for a multiple re-use in a collaborative environment of concept phase of a Product Evolution (Formation) Process (PEP). The standardisation of optimised processes and methodologies and the enhanced interaction between all parties involved in product development could lead to improve product quality and reduce development time and hence expenses. The fundamental principles of PAD, the particular methodologies used in automotive body design and the principles of methodical development and design in general are investigated. The role which automotive body engineers play throughout the activities of the PEP is also investigated. The distribution of design work in concept teams of automotive body development and important methodologies for the design of prismatic profile areas is critically analysed. To address the role and distribution of work, 25 group work projects were carried out in cooperation with the automotive industry. Large assemblies of the automotive bodies were developed. The requirements for distributed design work have been identified and improved. The results of the investigation point towards a file based, well structured administration of a concept design, with a zone based approach. The investigation was extended to the process chain of sections, which are used for development of surfaces, parts and assemblies. Important methods were developed, optimised and validated with regard to an update safe re-use of 3D zone based CAD models instead of 2D sections. The thesis presents a thorough description of the research undertaken, details the experimental results and provides a comprehensive analysis of them. Finally it proposes a unique methodology to a zone based approach with a clearly defined process chain of sections for an update-safe re-use of design models.
15
Su, Jen-Yi, and 蘇珍儀. "C band RF circuit and package design." Thesis, 2003. http://ndltd.ncl.edu.tw/handle/96609221318259006565.
Full text
16
Wang, To-Po, and 王多柏. "Ka-band Oscillator Design Applying Packaged Transistor." Thesis, 2000. http://ndltd.ncl.edu.tw/handle/81810757121526343878.
Full textAbstract:
碩士國立交通大學
電信工程系
88
In this thesis, a hybrid MIC Ka band oscillator has been developed and tested successfully employing the advanced SMT (surface mount technique) packaged PHEMT (pseudomorphic high electron mobility transistor). The simulated results based on SeriesIV and measured oscillator frequency agrees excellently. Also, it is feasible to product large volume, low cost Ka band integrated circuits. The measured oscillation frequency is 27.33 GHz, and the output power is —9.83dBm. The oscillator is biased at VDS=2 volt, VGS=-0.2 volt and the current IDS=32 mA.
17
Chen, Kuan-Yu, and 陳冠宇. "QFN-Packaged X-/Ku-Band LNA Design for Satellite Communication Applications." Thesis, 2019. http://ndltd.ncl.edu.tw/handle/wnemyp.
Full textAbstract:
碩士國立中央大學
電機工程學系
107
In this thesis, three high-gain, low-noise, and compact X-/Ku-Band low-noise amplifiers (LNA) for the satellite communication application are proposed. These LNAs are realized in a 90-nm CMOS technology combined with GIPD process and 0.15-μm GaAs pHEMT technology with Quad Flat no-Leads (QFN) packaging. Replacing the discrete amplifiers in the Low Noise Block Downconverter (LNB) is to make the system more compact. The first LNA design is realized in a 90-nm CMOS technology combined with GIPD process. Some of the passive components are designed on the GIPD process. Using the low metal loss substrate is to realize high quality factor of the passive components. Combining the 90-nm CMOS and GIPD process by using flip chip technique is to minimize the noise figure. The proposed LNA can provide power gain of 18.8 dB at 9.8 GHz and the minimum NF of 3.5 dB in the measurement. The IIP3 is -7 dBm. The power consumption is only 17.5 mW from a 1.2-V supply. The second LNA design is realized in a 0.15-μm GaAs pHEMT technology with Quad Flat no-Leads (QFN) packaging. This is a low-noise, low-power consumption, high-gain, and compact LNA. This packaged LNA can be directly welded on the print circuit board (PCB) and be able to work with other circuits. The parasitic effect of the QFN packaging is completely characterized by using a 3D electromagnetic simulator and then is co-designed with the LNA to ensure simultaneous noise and impedance matching at the desired frequency band. The proposed packaged LNA exhibits measured power gain of 22.4 dB at 9.7 GHz while having 3-dB bandwidth from 8.5 to 12.5 GHz. The minimum NF is 1.5 dB at 10.7 GHz. The power consumption is only 68.5 mW from a 1.1-V supply. The third LNA design is realized in a 0.15-μm GaAs pHEMT technology with Quad Flat no-Leads (QFN) packaging. The LNA is able to support the reception of dual horizontally (H) and vertically (V) polarized signals, increasing the channel capacity. This is a low-noise, low-power consumption, high-gain, and compact LNA. This packaged LNA can be directly welded on the print circuit board (PCB) and be able to work with other circuits. The proposed QFN-packaged LNA can provide power gain of 20.8 and 21.5 dB while having 3-dB bandwidth from 10.7 to 13.2 GHz and minimum NF of 1.35 dB for the H- and V-polarization channels respectively. The IIP3 is -11 dBm and -10 dBm for the H- and V-polarization channels respectively. The power consumption is only 32.8 mW from a 1-V and 0.8-V supply.
18
Lee, Ming-Chou, and 李明洲. "Design of RF System on Package (SOP) and Miniaturized Dual-Band Printed Antenna." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/xahs72.
Full textAbstract:
碩士國立交通大學
電信工程系所
92
In front of this thesis, three RF front end-module (FEM) based on LTCC (low temperature co-fire ceramics) under 802.11b specification is designed. The first FEM contains a diversity switch, a T/R switch and a band-pass filter in both receive and transmit path. The second FEM changes the band-pass filter in the first FEM into low-pass filter in transmit path to improve the total insertion loss. The third FEM includes a power amplifier than the first FEM. They put power amplifier, diversity switch and T/R switch on the top layer of LTCC substrate and band-pass filter, capacitors and inductors of the matching circuit in it. The second part of this thesis, two different inverted F antenna structure are proposed. The first antenna uses spiral line, and the second utilizes couple line as its feed. They are both with miniaturized size, operated in dual frequencies, and implemented by printed circuit board and LTCC. The measured results also reveal that they which have less size than the conventional inverted F antenna and omni-directional pattern can easily operated in the designed frequency.
19
Tsai, Chih-Chun, and 蔡智鈞. "A Wide-Band Millimeter-Wave Transition Design Using Multi-layered LTCC Package Technology." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/43193564852594385750.
Full textAbstract:
碩士國立臺灣大學
電信工程學研究所
98
A wide-band microstrip-to-microstrip via transition used for connecting an integrated circuit chip and an antenna array on the opposite sides of a multi-layer low-temperature co-fired ceramic substrate is investigated in this paper. The via transition is decomposed into external and internal segments to facilitate the design. The equivalent impedance of the internal segment, consisting of a multi-layered through-hole via with four ground vias, is calculated from the lump-circuit model generated by Ansoft Q3D Extractor. The electrical performances of the external segments, consisting of via to microstrip line transitions, are evaluated as microstrip-to-coax transitions for choosing appropriate physical parameters. Finally, the geometrical parameters of entire transition are obtained by combining the results of the external and internal segments. It has been demonstrated, through the simulation results by commercial software Ansoft HFSS, that the return loss is better than 19dB over a band from DC up to 70GHz with an in-band insertion loss better than 0.48dB. Coherent results between simulation and measurement are also obtained with a back-to-back transition structure. Additionally, based on the design guideline of equal line length and same number of corners, the layout of microstrip lines between integrated circuit chip and antenna array is also proposed. Finally the simulation result shows the phase difference is in two degrees and near-end crosstalk and far-end crosstalk are both better than 26dB between each microstrip line up to 70GHz.
20
Wang, Ting-Kuang, and 王挺光. "A Package-level Power Plane with Ultra-wide band Ground Bounce Noise Rejection." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/62919600743374771861.
Full textAbstract:
碩士國立中山大學
電機工程學系研究所
93
Transient current surges resulted from the simultaneous switching of output buffers in the high-speed digital circuits can induce significant ground bounce noise (GBN) on the chip, package, and printed circuit board (PCB). The GBN not only causes the signal integrity (SI) problems, such as glitches or timing push-out of signal traces, but also increases the electromagnetic interference (EMI) in the high-speed digital circuits. With the design trends of digital circuits toward higher speed, low voltage level, smaller volume, the impact of GBN has become one of the most important issues that determine the performance of electronic products. Adding decoupling capacitors between the power and ground planes is a typical way to suppress the GBN. However, they are not effective at the frequencies higher than 600MHz due to their inherent lead inductance. Recently, a new idea for eliminating the GBN is proposed by designing electromagnetic bandgap (EBG) structure with high impedance surface (HIS) on the ground or power plane. Several new EBG power/ground plane designs have been proposed to broaden the stopband bandwidth for suppressing the GBN. However there are some drawbacks, such as high cost, large area occupation and complicated fabrication process. In this paper, we propose a novel Hybrid EBG power planes for PCB or package to suppress the GBN. Its extinctive behavior of broadband suppression of GBN (over 10GHz) is demonstrated experientially and numerically. Finally, we combine the periodic high-low dielectric material with the EBG power plane to control the position and bandwidth of stopband.
21
Raimundo, Filipa Gomes. "Antena em "package" para radares em automóveis na banda W." Master's thesis, 2019. https://hdl.handle.net/10216/124768.
Full textAbstract:
A miniaturização do hardware tem-se revelado cada vez mais um processocrítico no que que diz respeito às telecomunicações. Isto deve-se à crescente necessidade de os integrar com os objetos do quotidiano.Em resposta a essa necessidade, uma preocupação atual é a integração dosmecanismos de radiação no próprio chip ou no encapsulamento, isto porque as antenas são atualmente o componente mais volumoso que se encontra presente nos dispositivos sem fios. Quando se fala em elevadas frequências como é o caso das da banda W (75 a 115GHz), a necessidade do seu encapsulamento é ainda maior, dado que nesta banda de frequências as pequenas interconexões apresentam fenómenos parasíticos elevados.Utilizando softwares como o ADS(Advanced Design System), começou por ser desenvolvida uma antena single ended, mas cujos resultados não foram os mais satisfatórios, tendo por isso sido posteriormente desenvolvida uma patch antena com um feed diferencial. Ao longo do trabalho foi notória a interferência que os circuitos de adaptação tinham relativamente à antena, tendo-se optado no final por usar uma blindagem nesses circuitos de forma a que a antena continuasse a ficar perfeitamnte adaptada na banda de frequências desejada.
22
"A survival kit for a credit card package." Chinese University of Hong Kong, 1986. http://library.cuhk.edu.hk/record=b5885616.
Full text
23
Liao, Shan-Yi, and 廖伸憶. "Design of Novel Dual-Band Printed Antennas and Simulation for GPS System-on Package (SOP)." Thesis, 2004. http://ndltd.ncl.edu.tw/handle/4s4pe4.
Full textAbstract:
碩士國立交通大學
電信工程系所
92
This thesis is divided into two parts. The first part is the design of dual-band printed antennas. This design utilizes the theory of pliers, which can reduce the size, to propose a dual-pliers structure. By simulation and measurement, the advantages of structure miniaturization and dual-band characteristics are demonstrated with the dual-pliers structure. The antenna is more wideband if one of the dual-pliers is properly arranged. The two operating bands of this antenna meet the standards of IEEE 802.11a and 802.11b. The second part is the design of GPS system-on-package module by LTCC. This module integrates LNA, SAW filter, 1st IF filter, and RF front-end IC. Furthermore, the 1st IF filter and LNA consisting of buried components and surface-mounted devices are designed by simulation.
24
Chin, Ta-Cheng, and 金大正. "Study of Wide Band Electromagnetic Bandgap Structure for Ground Bounce Noise Suppression in Package-level." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/90823759742734513380.
Full textAbstract:
碩士國立中山大學
通訊工程研究所
99
With electronic devices trending toward higher clock rates, lower voltage levels, and smaller form factors, the simultaneously switching noise (SSN), which is induced in package and printed circuit board, is one of the major factors affecting the performance and design of the high speed digital circuits. This noise will lead to false switching and malfunctioning in digital and/or analog circuits, and causes serious signal integrity (SI) and electromagnetic interference (EMI) problems for the high speed digital systems. Therefore, mitigating the SSN becomes a major challenge for the high speed circuits design. In this thesis, first of all, we introduce and discuss previously proposed solutions to suppress the SSN. These solutions include the use of decoupling capacitors, isolation moats, and electromagnetic bnadgap (EBG) structures. We analyzed the EBG structures and generated some EBG design rules. As the speed of digital circuits moving toward higher frequencies, the Double L-bridge EBG structure can be used to improve the performance of Hybrid EBG structure by employing the EBG design rules that were generated. The Double L-bridge EBG structure design improved the behavior at the high frequencies, which also maintained the low frequency performance. It is demonstrated numerically and experimentally. For fast estimating the stopband, we use one-dimensional lump circuit model. Then, we propose another structure, named Double Cross EBG structure. This design, compared to the Double L-bridge EBG structure, not only maintained the high frequency performance, but also improved the low frequency behavior. It is also both experimentally and numerically validated.
25
Tsai, Guo-Ding, and 蔡國鼎. "X-band Three-stub Filter Embedded SPDT/SP4T Switches Using Packaged PIN Diodes and Novel Resonators." Thesis, 2015. http://ndltd.ncl.edu.tw/handle/jdk45j.
Full textAbstract:
碩士國立交通大學
電信工程研究所
103
A single pole double throw (SPDT) and single pole four throw (SP4T) switch using the packaged PIN diodes for X-band application is proposed. At first, the S domain synthesis method is applied to design a Chebyshev three-stub filter. Next, the center stub of the filter is substituted by a PIN diode incorporation with the peripheral circuits to implement a single pole single throw (SPST) switch. Finally, two of the SPST switches can be merged as a SPDT switch. The SPDT switch is embedded in two Chebyshev three-stub filters where the center one of the three stubs is substituted by the PIN diode and peripheral circuits. The high value of parasitic inductance in the package is absorbed by the filter with a proposed novel resonator structure. As result, the designing procedures of SP4T switch are similar to that of the SPDT switch.
26
Li, Dian-Chi, and 李典錡. "Implementation of the Ka Band Receiver Front-End Circuits with Flip-Chip Package Technology and Distributed Amplifier Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/36573920761580617507.
Full textAbstract:
碩士國立中央大學
通訊工程研究所
93
Title：Implementation of the Ka Band Receiver Front-End Circuits with Flip-Chip Package Technology and Distributed Amplifier Design School：National Central University Department of Communication Engineering Student：Dian-Chi Li Advisor：Dr. Hwann-Kaeo Chiou Abstract As the wireless multi-media services become more and more popular, therefore broadband wireless access techniques are developed to satisfy these demands. The millimeter wave system takes advantages in the wide frequency range, and matches the trend of high data rate and wide-bandwidth in modern wireless communication system. The millimeter wave system, such as LMDS (Local Multipoint Distribution Service), plays an important role in the wireless-broadband technologies. The receiver circuits include low noise amplifiers, broadband low noise amplifier, and distributed amplifier, which are the key components in LMDS system. The thesis focuses on the millimeter wave receiver front-end circuit designed, which include the low noise amplifiers in Ka band and V band. The circuits are implemented with WIN 0.15mm pHEMT technology, and then apply the filp-chip package technology to investigate the issues of high frequency interconnects. The integrated millimeter wave front end by flip-chip package will be developed in the next study phase. The measured and simulated results of the designed circuits are illustrated as followings; for the coplanar waveguide 28GHz LNA, the obtained gain is 28.6 dB, input power at the 1-dB gain compression point is -15 dBm, noise figure is 3.5 dB; for 10-30GHz wideband LNA, the gain is 14.5 dB, output power at the 1-dB gain compression point is 10 dBm, noise figure is 6dB; for the coplanar waveguide distributed amplifier, gain is more than 5 dB within 32GHz bandwidth, output power at the 1-dB gain compression point is more than 5 dBm; for the coplanar waveguide Darlington distributed amplifier, the gain is more than 5 dB in within 35GHz bandwidth, output power at the 1-dB gain impression point is more than 5 dBm. The V-band LNA has 18dB gain and the bandwidth is 10GHz, and noise figure is 4.84 dB.