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Journal articles on the topic 'Oxide nitride stacks'

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Author: Grafiati

Published: 4 June 2021

Last updated: 28 January 2023

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1

Levin, Igor. "Nanoscale Compositional Characterization of Silicon Oxide-Nitride-Oxide Stacks." Microscopy and Microanalysis 8, S02 (August 2002): 1178–79. http://dx.doi.org/10.1017/s1431927602107768.

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2

Huang, Tiao‐Yuan, Donald J. Coleman, and James L. Paterson. "LPCVD Oxide/LPCVD Nitride Stacks for Interpoly Dielectrics." Journal of The Electrochemical Society 132, no. 6 (June 1, 1985): 1406–9. http://dx.doi.org/10.1149/1.2114133.

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3

Mao, L. F., and Z. O. Wang. "Tunneling currents through lightly nitride silicon dioxide/oxide stacks." physica status solidi (a) 204, no. 3 (March 2007): 784–90. http://dx.doi.org/10.1002/pssa.200622325.

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4

Ioannou-Sougleridis, V., P. Dimitrakis, V. Em Vamvakas, P. Normand, C. Bonafos, S. Schamm, N. Cherkashin, G. Ben Assayag, M. Perego, and M. Fanciulli. "Oxide-nitride-oxide memory stacks formed by low-energy Si ion implantation into nitride and wet oxidation." Microelectronic Engineering 84, no. 9-10 (September 2007): 1986–89. http://dx.doi.org/10.1016/j.mee.2007.04.068.

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5

Levin, Igor, Mark Kovler, Yakov Roizin, Menachem Vofsi, Richard D. Leapman, Gary Goodman, Norio Kawada, and Munabu Funahashi. "Structure, Chemistry, and Electrical Performance of Silicon Oxide-Nitride-Oxide Stacks on Silicon." Journal of The Electrochemical Society 151, no. 12 (2004): G833. http://dx.doi.org/10.1149/1.1811594.

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6

Ioannou-Sougleridis, V., P. Dimitrakis, V. Em Vamvakas, P. Normand, C. Bonafos, S. Schamm, N. Cherkashin, G. Ben Assayag, M. Perego, and M. Fanciulli. "Wet oxidation of nitride layer implanted with low-energy Si ions for improved oxide-nitride-oxide memory stacks." Applied Physics Letters 90, no. 26 (June 25, 2007): 263513. http://dx.doi.org/10.1063/1.2752769.

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7

Drown, J. L., S. M. Merchant, M. E. Gross, D. Eaglesham, L. A. Giannuzzi, and R. B. Irwin. "Comparison of Sputtered Titanium Nitride on Silicon Dioxide and Aluminum-Alloy Thin Films." Microscopy and Microanalysis 3, S2 (August 1997): 469–70. http://dx.doi.org/10.1017/s1431927600009235.

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Titanium nitride (TiN) films are used as anti-reflection coatings (ARC) on aluminum (Al) films to facilitate lithography processes during multilevel metallization for the manufacture of integrated circuits on silicon-based (Si) semiconductor devices. It is generally accepted in the literature that the microstructure of multilevel metal stacks is influenced by the texture of the substrate. For the case of interconnect materials used in the semiconductor industry, a typical metal stack is as follows: Titanium/Titanium Nitride/Al-alloy/ARC-Titanium Nitride. The Ti/TiN layer underneath the Al-alloy film is used as a barrier stack to prevent junction spiking. The Ti/TiN underlayer also determines the growth conditions (crystallography and orientation relationships) of the subsequent Al-alloy film.This study focuses on the microstructural characterization of the ARC-TiN layer on Si-oxide and Ti/TiN/Al-alloy substrates that are fabricated under similar conditions using conventional physical vapor deposition (PVD - sputtering) techniques. The ARC-TiN microstructure was investigated by transmission electron microscopy (TEM) using a Philips EM430 operating at 300 kV.

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8

Habermehl, S., R. D. Nasby, and M. J. Rightley. "Cycling endurance of silicon–oxide–nitride–oxide–silicon nonvolatile memory stacks prepared with nitrided SiO2/Si(100) interfaces." Applied Physics Letters 75, no. 8 (August 23, 1999): 1122–24. http://dx.doi.org/10.1063/1.124616.

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9

Rosenman, G., M. Naich, Ya Roizin, and Rob van Schaijk. "Deep traps in oxide-nitride-oxide stacks fabricated from hydrogen and deuterium containing precursors." Journal of Applied Physics 99, no. 2 (January 15, 2006): 023702. http://dx.doi.org/10.1063/1.2161416.

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10

El Amrani, A., R. Si-Kaddour, M. Maoudj, and C. Nasraoui. "SiN/SiO2 passivation stack of n-type silicon surface." Materials Science-Poland 37, no. 3 (September 1, 2019): 482–87. http://dx.doi.org/10.2478/msp-2019-0065.

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AbstractThe SiN/SiO2 stack is widely used to passivate the surface of n-type monocrystalline silicon solar cells. In this work, we have undertaken a study to compare the stack layer obtained with SiO2 grown by both rapid thermal and chemical ways to passivate n-type monocrystalline silicon surface. By varying the plateau time and the plateau temperature of the rapid thermal oxidation, we determined the parameters to grow 10 nm thick oxide. Two-step nitric acid oxidation was used to grow 2 nm thick silicon oxide. Silicon nitride films with three refractive indices were used to produce the SiN/SiO2 stack. Regarding this parameter, the minority carrier lifetime measured by means of QSSPC revealed that the refractive index of 1.9 ensured the best passivation quality of silicon wafer surface. We also found that stacks with nitric acid oxidation showed definitely the best passivation quality. In addition to produce the most efficient passivation, this technique has the lowest thermal budget.

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11

Landheer, D., P. Ma, W. N. Lennard, I. V. Mitchell, and C. McNorgan. "Analysis of silicon–oxide–silicon nitride stacks by medium-energy ion scattering." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 18, no. 5 (2000): 2503. http://dx.doi.org/10.1116/1.1285991.

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12

Levin, Igor, Richard D. Leapman, Mark Kovler, and Yakov Roizin. "Radiation-induced nitrogen segregation during electron energy loss spectroscopy of silicon oxide–nitride-oxide stacks." Applied Physics Letters 83, no. 8 (August 25, 2003): 1548–50. http://dx.doi.org/10.1063/1.1604182.

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13

Ioannou-Sougleridis, V., P. Dimitrakis, V. Em Vamvakas, P. Normand, C. Bonafos, S. Schamm, A. Mouti, G. Ben Assayag, and V. Paillard. "Oxide–nitride–oxide dielectric stacks with Si nanoparticles obtained by low-energy ion beam synthesis." Nanotechnology 18, no. 21 (April 27, 2007): 215204. http://dx.doi.org/10.1088/0957-4484/18/21/215204.

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14

Liu, Po-Tsun, C. S. Huang, and C. W. Chen. "Nonvolatile low-temperature polycrystalline silicon thin-film-transistor memory devices with oxide-nitride-oxide stacks." Applied Physics Letters 90, no. 18 (April 30, 2007): 182115. http://dx.doi.org/10.1063/1.2736293.

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15

Nikolaou, Nikolaos, Panagiotis Dimitrakis, Pascal Normand, Vassilios Ioannou-Sougleridis, Konstantinos Giannakopoulos, Konstantina Mergia, Kaupo Kukli, Jaakko Niinisto, Mikko Ritala, and Markku Leskela. "Influence of HfO₂ Control Oxide ALD Precursor Chemistry for Nitride Memories." Advanced Materials Research 324 (August 2011): 42–45. http://dx.doi.org/10.4028/www.scientific.net/amr.324.42.

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In this work we report on the structural and electrical properties of SiO2/Si3N4/HfO2memory stacks with emphasis upon the influence of Atomic Layer Deposition chemistry used for forming the HfO2blocking layer. Two HfO2precursor chemistries were employed, the tetrakis- (ethylmethylamino)hafnium (TEMAH) and the bis(methylcyclopentadienyl)methoxymethylhafnium (HfD-04). Ozone was used as the oxygen source. The structural characteristics of the stacks were examined by means of TEM and GIXRD. Comparative studies conducted with the use of platinum gated capacitors showed that the samples grown using TEMAH have an increased electron trapping ability in comparison to the HfD-04 ones. While the two structures exhibit similar Write/Erase and retention characteristics, The samples grown from TEMAH can sustain more repeated W/E cycles (> 3×105in the 10V/-11V, 10 ms regime) compared to the samples grown from HfD-04 (< 104W/E cycles). This difference in endurance characteristics is attributed mainly to the different deposition temperatures used with these two precursors and the nature of the interfacial layer they produce between the Si3N4and the HfO2layers.

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16

Nikolaou, N., P. Dimitrakis, P. Normand, S. Schamm, C. Bonafos, G. Ben Assayag, A. Mouti, and V. Ioannou-Sougleridis. "Temperature-dependent low electric field charging of Si nanocrystals embedded within oxide–nitride–oxide dielectric stacks." Nanotechnology 20, no. 30 (July 8, 2009): 305704. http://dx.doi.org/10.1088/0957-4484/20/30/305704.

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17

Kerber, A., and E. A. Cartier. "Reliability Challenges for CMOS Technology Qualifications With Hafnium Oxide/Titanium Nitride Gate Stacks." IEEE Transactions on Device and Materials Reliability 9, no. 2 (June 2009): 147–62. http://dx.doi.org/10.1109/tdmr.2009.2016954.

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18

Kim, Kyoung H., Roy G. Gordon, Andrew Ritenour, and Dimitri A. Antoniadis. "Atomic layer deposition of insulating nitride interfacial layers for germanium metal oxide semiconductor field effect transistors with high-κ oxide/tungsten nitride gate stacks." Applied Physics Letters 90, no. 21 (May 21, 2007): 212104. http://dx.doi.org/10.1063/1.2741609.

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19

Perálvarez, M., Josep Carreras, J. Barreto, A. Morales, C. Domínguez, and B. Garrido. "Efficiency and reliability enhancement of silicon nanocrystal field-effect luminescence from nitride-oxide gate stacks." Applied Physics Letters 92, no. 24 (June 16, 2008): 241104. http://dx.doi.org/10.1063/1.2939562.

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20

Cassan, E., P. Dollfus, S. Galdin, and P. Hesto. "Calculation of direct tunneling gate current through ultra-thin oxide and oxide/nitride stacks in MOSFETs and H-MOSFETs." Microelectronics Reliability 40, no. 4-5 (April 2000): 585–88. http://dx.doi.org/10.1016/s0026-2714(99)00265-6.

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21

Zhigang Wang, C. G. Parker, D. W. Hodge, R. T. Croswell, Nian Yang, V. Misra, and J. R. Hauser. "Effect of polysilicon gate type on the flatband voltage shift for ultrathin oxide-nitride gate stacks." IEEE Electron Device Letters 21, no. 4 (April 2000): 170–72. http://dx.doi.org/10.1109/55.830971.

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22

Chein-Hao Chen, Yean-Kuen Fang, Chih-Wei Yang, Shyh-Fann Ting, Yong-Shiuan Tsair, Ming-Fang Wang, Tuo-Hong Hou, et al. "To optimize electrical properties of the ultrathin (1.6 nm) nitride/oxide gate stacks with bottom oxide materials and post-deposition treatment." IEEE Transactions on Electron Devices 48, no. 12 (2001): 2769–76. http://dx.doi.org/10.1109/16.974702.

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23

Mauersberger, Tom, Jens Trommer, Saurabh Sharma, Martin Knaut, Darius Pohl, Bernd Rellinghaus, Thomas Mikolajick, and André Heinzig. "Single-step reactive ion etching process for device integration of hafnium-zirconium-oxide (HZO)/titanium nitride (TiN) stacks." Semiconductor Science and Technology 36, no. 9 (August 11, 2021): 095025. http://dx.doi.org/10.1088/1361-6641/ac1827.

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24

García, H., S. Dueñas, H. Castán, A. Gómez, L. Bailón, M. Toledano-Luque, A. del Prado, I. Mártil, and G. González-Díaz. "Influence of interlayer trapping and detrapping mechanisms on the electrical characterization of hafnium oxide/silicon nitride stacks on silicon." Journal of Applied Physics 104, no. 9 (November 2008): 094107. http://dx.doi.org/10.1063/1.3013441.

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25

Verma, Ram Mohan, Ashwath Rao, and B. R. Singh. "Electrical characterization of the metal ferroelectric oxide semiconductor and metal ferroelectric nitride semiconductor gate stacks for ferroelectric field effect transistors." Applied Physics Letters 104, no. 9 (March 3, 2014): 092907. http://dx.doi.org/10.1063/1.4866655.

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26

Joonwichien, Supawan, Shalamujiang Simayi, Katsuhiko Shirasawa, Katsuto Tanahashi, and Hidetaka Takato. "Thermal Treatment Effects on Flat-band Voltage Shift in Atomic-layer-deposited Alumina or Aluminum Oxide/Silicon Nitride Passivation Stacks." Energy Procedia 92 (August 2016): 353–58. http://dx.doi.org/10.1016/j.egypro.2016.07.112.

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27

Mukherjee, Kalparupa, Carlo De Santi, Matteo Borga, Karen Geens, Shuzhen You, Benoit Bakeroot, Stefaan Decoutere, et al. "Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization." Materials 14, no. 9 (April 29, 2021): 2316. http://dx.doi.org/10.3390/ma14092316.

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The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

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28

Suvorova, Elena I., Oleg V. Uvarov, Kirill V. Chizh, Alexey A. Klimenko, and Philippe A. Buffat. "Structure, Oxygen Content and Electric Properties of Titanium Nitride Electrodes in TiNx/La:HfO2/TiNx Stacks Grown by PEALD on SiO2/Si." Nanomaterials 12, no. 20 (October 14, 2022): 3608. http://dx.doi.org/10.3390/nano12203608.

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This work reports experimental results of the quantitative determination of oxygen and band gap measurement in the TiNx electrodes in planar TiNx top/La:HfO2/TiNx bottom MIM stacks obtained by plasma enhanced atomic layer deposition on SiO2. Methodological aspects of extracting structural and chemical information from (scanning) transmission electron microscopy imaging (bright field and high angular annular dark field), energy dispersive X-ray spectrometry and electron energy loss spectroscopy are thoroughly considered. The study shows that the oxygen concentration is higher in the TiNxOy bottom electrode (about 14.2 ± 0.1 at. %) compared to the TiNxOy top electrode (about 11.4 ± 0.5 at. %). The following average stoichiometric formulas are TiN0.52O0.20 top and TiN0.54O0.26 bottom for top and bottom electrodes, respectively. The amount of oxygen incorporated into TiNx during PEALD because of oxygen impurities in the plasma is minor compared to that because of diffusion from SiO2 and HfO2. This asymmetry, together with results on a sample grown on a Si substrate, shows that incorporating oxygen impurity from the plasma itself is a minor part compared to diffusion from the SiO2 substrate and HfO2 dielectric during the PEALD growth. We observe the presence of TiO2 at the interface between the Hf oxide layer and the Ti nitride electrodes as well as at the SiO2 interface. EELS analysis led to a band gap ranging from 2.2 to 2.5 eV for the bottom TiNxOy and 1.7–2.2 eV for the top TiNxOy, which is in fair agreement with results obtained on the top TiNx electrode (1.6 ± 01 eV) using optical absorption spectra. Measurement of sheet resistance, resistivity and temperature coefficient of resistance by a four-point probe on the top TiNxOy electrode from 20 to 100 °C corresponds to the typical values for semiconductors.

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29

Smith, Jeffrey A., Kai Ni, Hideki Takeuchi, Robert J. Stephenson, Yi-Ann Chen, Marek Hytha, Shuyi Li, Paul E. Nicollian, Robert J. Mears, and Suman Datta. "Intermixing reduction in ultra-thin titanium nitride/hafnium oxide film stacks grown on oxygen-inserted silicon and associated reduction of the interface charge dipole." Journal of Applied Physics 130, no. 18 (November 14, 2021): 185303. http://dx.doi.org/10.1063/5.0068002.

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30

Lucovsky, G., Y. Wu, H. Niimi, H. Yang, J. Keister, and J. E. Rowe. "Separate and independent reductions in direct tunneling in oxide/nitride stacks with monolayer interface nitridation associated with the (i) interface nitridation and (ii) increased physical thickness." Journal of Vacuum Science & Technology A: Vacuum, Surfaces, and Films 18, no. 4 (July 2000): 1163–68. http://dx.doi.org/10.1116/1.582318.

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31

Salim, Kashmala, Muhammad Asif, Farman Ali, Ammar Armghan, Nasim Ullah, Al-Sharef Mohammad, and Ahmad Aziz Al Ahmadi. "Low-Stress and Optimum Design of Boost Converter for Renewable Energy Systems." Micromachines 13, no. 7 (July 8, 2022): 1085. http://dx.doi.org/10.3390/mi13071085.

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This paper examines the design and analysis of DC–DC converters for high-power and low-voltage applications such as renewable energy sources (RESs) and comparisons between converters based on switch stresses and efficiency. The RESs including photovoltaic arrays and fuel cell stacks must have enhanced output voltages, such as 380 V DC in the case of a full bridge inverter or 760 V DC in the case of a half bridge inverter, in order to interface with the 220 V AC grid-connected power system. One of the primary difficulties in developing renewable energy systems is enhancing DC–DC converters’ efficiency to enable high step-up voltage conversion with high efficiency and low voltage stress. In the present work, the efficiency, current, and voltage stress of switches of an isolated Flyback boost converter, simple DC–DC Boost converter, and an Interleaved boost converter, are explored and studied relatively. The most suitable and optimized options with a high efficiency and low switching stress are investigated. The more suitable topology is designed and analyzed for the switch technology based on the Silicon-Metal Oxide Semiconductor Field Effect Transistor (Si-MOSFET) and the Gallium Nitride-High Electron Mobility Transistor (GaN-HEMT). The Analytical approach is analyzed in this paper based on efficiency and switching stress. It is explored that GaN HEMT based Flyback boost converter is the best. Finally, the future direction for further improving the efficiency of the proposed boost converter is investigated.

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32

Xu, Li Jun, He Ming Zhang, Hui Yong Hu, Xiao Bo Xu, and Jian Li Ma. "The Study of Direct Tunneling Current in Strained MOS Device with Silicon Nitride Stack Gate Dielectric." Applied Mechanics and Materials 110-116 (October 2011): 5442–46. http://dx.doi.org/10.4028/www.scientific.net/amm.110-116.5442.

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As the size of MOS device scaled down to sub 100nm, the direct tunneling current of gate oxide increases more and more. Using silicon nitride as gate dielectric can solve this problem effectively in some time due to the dielectric constant of silicon nitride is larger than silica’s.This paper derived the dielectric constant of silicon nitride stack gate dielectric,and simulated the direct tunneling current of strained MOS device with silica and silicon nitride gate dielectric through device simulation software ISE TCAD10.0,studied the direct tunneling current of strained MOS device with silicon nitride stack gate dielectric change with the variation of some parameters and the application limit of silicon nitride material.

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33

Ramkumar, K., V. Prabhakar, Ali Keshavarzi, Igor Kouznetsov, and Sam Geha. "SONOS Memories: Advances in Materials and Devices." MRS Advances 2, no. 4 (2017): 209–21. http://dx.doi.org/10.1557/adv.2017.144.

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AbstractSilicon Nitride based charge trap devices have been studied since the 1980s for applications in non-volatile memories. Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) stack as the non-volatile memory gate stack has been the focus since the 1990s. Several enhancements in SONOS layer materials have been invented to reduce the programming voltage and improve the reliability of the SONOS memory. SONOS memories are a widely used class of non-volatile memories today. This paper will review the history of SONOS and highlight the various innovations that have enhanced SONOS memory performance, reliability and low cost of manufacture. Topics covered include various improvements in the SONOS stack such as Band gap engineering, High K–Metal Gate for SONOS, 3D SONOS, SONOS FinFETs (Field Effect Transistor) and embedded SONOS.

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34

Tezcan, Deniz Sabuncuoglu, Bivragh Majeed, Yann Civale, Philippe Soussan, and Eric Beyne. "Via Last using Polymer Liners and their Reliability." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2010, DPC (January 1, 2010): 000831–58. http://dx.doi.org/10.4071/2010dpc-tp15.

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This paper discusses the use of polymer dielectrics as insulating liner for realizing two types of 3D-WLP through Si vias (TSV's) in Si wafers with a thickness of respectively 50 and 100μm. These TSV technologies are based on thinning first, via last approach where 3D interconnects are implemented on the backside of thinned IC fabricated device wafers. Key aspects of the TSV processes are: i) fabricating the TSV from the backside of the wafer and contacting to BEOL M1, hence it is independent of the BEOL interconnect stack. ii) use of thick polymer as via isolation is a differentiator from most classical approaches using thin CVD oxide or nitride. The result is a significantly reduced capacitance, and hence, improvement of electrical performance. Another advantage of using thick polymer is that it can absorb some of the stress induced by CTE mismatch between the Cu in via and surrounding Si. This paper presents IMEC's 3D-WLP TSV flavors developed using spin-on dielectric polymers as isolation layer and the reliability of these TSVs' while undergoing thermal cycle tests. For each wafer thickness a 3-mask process sequence is implemented to fabricate the TSVs. Different process flows are used for the different Si thicknesses. For the 100μm thick substrate, a low aspect ratio TSV is used. A Si-via is etched from the wafer backside with a bottom diameter of about 70μm. The top side of the via is chamfered and has a top diameter of about 100μm. As a dielectric liner, a photo-sensitive spin-on polymer is conformally coated on the wafer. At the via bottom, a contact hole with approximately 30μm diameter is realized by photo patterning. Next, conformal Cu plating is used as TSV metallization. For the 50μm thick substrates, a different approach is used enabling a higher aspect ratio TSV. First, a 5μm wide ring trench is etched in the Si. Subsequently, these trenches are filled with a spin-on polymer. After filling the ring trenches, the central Si pillar is etched out of the via (second litho step) and the oxide at the via bottom is removed to provide access to the lowest chip metal level. Next, bottom-up Cu via fill is used to form the TSV metallization. This via has a Cu TSV diameter of 25μm, and an overall diameter with isolation of 35μm [1]. All processes employed in the fabrication of the TSVs are performed at low temperature (<200°C) for maximum post CMOS compatibility The test vehicle used to develop the TSV technologies include TSV daisy chains of various lengths connecting different number of vias to determine the TSV yield and resistance. For both TSV approaches, yielding electrical measurements are done on fabricated TSV wafers. For 50μm thick silicon, up to 95% electrical yield is achieved and the single TSV resistance is measured to be ~10–15mΩ on bonded stacks through Kelvin structures. Thermal cycling from −40 to +125°C of TSV dies are also done, and after 1000 thermal cycles no electrical failure is observed. For 100μm thick silicon TSV approach, single TSV resistance is measured to be ~4–20mΩ with good yield. Test die are subjected to 1000 thermal cycles and results show limited yield loss.

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35

Barreto, J., M. Perálvarez, A. Morales, B. Garrido, J. Montserrat, and C. Domínguez. "Broad range adjustable emission of stacked SiNx/SiOy layers." Journal of Materials Research 23, no. 6 (June 2008): 1513–16. http://dx.doi.org/10.1557/jmr.2008.0189.

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Structures containing stacked layers of silicon-rich silicon nitride (green-blue luminescence) and oxide (red luminescence) fabricated by ion implantation are reported, and it is shown how a Si-based material can be engineered to emit over a broad range. To study in depth the emission from implanted SiNx matrices, single nitride layers have been also fabricated by the first time. Si excess variation and the relative thickness of nitride and oxide provide the intensity and position variation of the peaks, and thus open the way to engineer a stack with desired emission properties over the whole visible spectrum.

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36

Chen, Christopher, Jeong-Mo Hwang, Young-Woo Ok, Wook-Jin Choi, Vijaykumar Upadhyaya, Brian Rounsaville, and Ajeet Rohatgi. "Investigation of long-term light stability of negative charge injected into oxide-nitride-oxide passivation stack of crystalline silicon solar cells." Journal of Applied Physics 132, no. 21 (December 7, 2022): 213302. http://dx.doi.org/10.1063/5.0111681.

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A negatively charged oxide-nitride-oxide stack for field-effect passivation of crystalline silicon solar cells is discussed. The negative charge was injected into the stack by a plasma charge injection technology. Charge stability was studied by exposing samples to AM1.5 simulation visible light and full-spectrum light at temperatures ranging from 55 to 78 °C for up to 300 h. Charge injection and loss were quantified based on shifts in the flatband voltage of capacitance–voltage curves measured with a mercury probe. The most probable mechanism of charge loss was found to be diffusion of negative charged hydrogen atoms through nitride and bottom oxide. The optimum recipe for each layer of the stack was investigated to minimize the loss of injected charge. The flatband voltage decay of the optimized stack was found to fit a power-law trend, suggesting the dispersive transport of hydrogen atoms with a dispersion parameter of ∼0.06–0.07. The optimized stack is projected to maintain a negative charge density of about 3.6 × 1012 cm−2 or more after 25 years of field operation in an environment such as Arizona, which would be sufficient for field-effect passivation under one-sun illumination. The high stability of the negative injected charge makes the plasma charging technology a safer and lower cost alternative to Al2O3-passivation technology commonly used to passivate p-type surfaces.

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37

Chang, T. C., S. T. Yan, P. T. Liu, M. C. Wang, and S. M. Sze. "A Method for Fabricating a Superior Oxide/Nitride /Oxide Gate Stack." Electrochemical and Solid-State Letters 7, no. 7 (2004): G138. http://dx.doi.org/10.1149/1.1738473.

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38

Ying Shi, Xiewen Wang, and Tso-Ping Ma. "Electrical properties of high-quality ultrathin nitride/oxide stack dielectrics." IEEE Transactions on Electron Devices 46, no. 2 (1999): 362–68. http://dx.doi.org/10.1109/16.740903.

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39

Hong, Peizhen, Qiang Xu, Jingwen Hou, Mingkai Bai, Zhiguo Zhao, Lei Jin, Zongliang Huo, and Chunlong Li. "Pre-metal dielectric PE TEOS oxide pitting in 3D NAND: mechanism and solutions." Semiconductor Science and Technology 37, no. 2 (December 21, 2021): 025007. http://dx.doi.org/10.1088/1361-6641/ac419e.

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Abstract In 3D NAND, as the stack number increases, the process cost becomes higher and higher, and the stress problem becomes more and more serious. Therefore, the low cost and low stress plasma enhanced tetraethyl orthosilicate (PE TEOS), compared to high density plasma (HDP) oxide, shows its superiority as pre-metal dielectric (PMD) oxide layer in 3D NAND. This paper explores the challenges in the application of PE TEOS in 3D NAND PMD oxide layer. In our experiment both PE TEOS and HDP are employed as the PMD oxide for 3D NAND staircase protection. There is not any void found in the two oxide structures. However, oxide pitting is spotted in the subsequent diluted hydrofluoric acid wet etching in the PE TEOS split. Moreover, we observe that the top silicon nitride corrodes in hot phosphoric acid. We study the mechanism of PE TEOS oxide pitting and silicon nitride corroding, propose two solutions: (1) HDP oxide + PE TEOS, and (2) PE TEOS + dry etching. Experimental results demonstrate that our solutions can well address the issue of PE TEOS oxide pitting and effectively protect the staircase structure. This work extends the application of PE TEOS oxide of which the cost and the stress are both low in 3D NAND.

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Song, S. C., H. F. Luan, C. H. Lee, A. Y. Mao, S. J. Lee, J. Gelpey, S. Marcus, and D. L. Kwong. "Ultra thin high quality stack nitride/oxide gate dielectrics prepared by in-situ rapid thermal N2O oxidation of NH3-nitrided Si." Microelectronic Engineering 48, no. 1-4 (September 1999): 55–58. http://dx.doi.org/10.1016/s0167-9317(99)00337-8.

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Ying Shi, Xiewen Wang, and T. P. Ma. "Tunneling leakage current in ultrathin (<4 nm) nitride/oxide stack dielectrics." IEEE Electron Device Letters 19, no. 10 (October 1998): 388–90. http://dx.doi.org/10.1109/55.720195.

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El Amrani, A., R. Si Kaddour, M. Maoudj, A. El Kechai, and S. Mezghiche. "Investigation of rapid thermal oxide/ silicon nitride passivation stack of n+ emitter." Current Applied Physics 15, no. 12 (December 2015): 1563–67. http://dx.doi.org/10.1016/j.cap.2015.10.002.

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Jang, Dong Beom, and Sang Jeen Hong. "In-Situ Monitoring of Multiple Oxide/Nitride Dielectric Stack PECVD Deposition Process." Transactions on Electrical and Electronic Materials 19, no. 1 (January 29, 2018): 21–26. http://dx.doi.org/10.1007/s42341-018-0005-0.

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Rambeloson, Jafetra, Qiliang Li, and Dimitris E. Ioannou. "(Invited, Digital Presentation) Photoactivated In₂O₃/GaN NW Sensors for Monitoring NO₂ with High Sensitivity and Low Power." ECS Meeting Abstracts MA2022-02, no. 36 (October 9, 2022): 1324. http://dx.doi.org/10.1149/ma2022-02361324mtgabs.

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We report and discuss our results on the performance of our photoactivated In3O2/GaN NW sensors, for monitoring NO2 at various levels of relative humidity and operating power. A 1ppm sensitivity as high as 29% was demonstrated at operating power of 5 mW and relative humidity 40%. Nanostructure-based semiconductor gas sensors such as nanowires, nanotubes or nanorods have seen significant progress in recent years, owning to their large surface-to-volume ratio proprieties, which lead to considerably increased sensitivity and improve the time response to analyte gases. In particular, Gallium Nitride (GaN) nanostructure-based gas sensors have generated a lot of interest due to its unique combination of sensor “friendly” properties such as, direct bandgap, excellent carrier mobility, high heat capacity and high breakdown voltage. These properties combined with suitable surface engineering make GaN and GaN-based nanostructures an excellent candidate for portable gas sensors. In this work, Gallium Nitride (GaN) nanowire (NW)-based NO2 sensors, functionalized with either pure In2O3 or In2O3 covered with an evaporated Au nanolayer, were developed for low operating power and high sensitivity. An AlGaN buffer layer was first deposited on a Si substrate to minimize lattice mismatch and improve adhesion between the Si substrate and the GaN NWs. Then the GaN NWs were patterned by stepper lithography-assisted dry-etching, followed by Induced Coupled Plasma etching using a metal hard mask to protect the GaN NW. The nanowire width target ranged between 200-600nm. Subsequently, electrodes composed of Ti/Al/Ti/Au metal stacks were deposited on top of the GaN to form Ohmic contacts. A thin In2O3 layer metal oxide receptor was deposited on all devices, using RF magnetron sputtering on top of the exposed GaN NW and this was followed for a subgroup of devices by coating the In2O3 with an evaporated Au nanolayer. Finally, rapid thermal annealing (RTA) at 700 0C was performed to crystalize the receptor layers and improve the ohmic contact. The surface quality of the resulting sensors was inspected with the help of Scanning Electron Microscope (SEM) micrographs. Several devices of each group (In2O3 and In2O3/Au ) were wire bonded and mounted onto an array board chamber. The devices were biased under 5V DC. Photoconductivity measurements, humidity testing and NO2 gas testing (1ppm and 10ppm concentration) were conducted. The sensors were illuminated under constant UV LED illumination throughout the duration of the testing at two wavelengths, 265 nm and 365 nm and three irradiance levels, 5mW, 30mW and 60mW. In general, the In3O2 GaN NW sensors where characterized by low sensitivity levels, whereas the In3O2/Au GaN NW sensors achieved excellent sensitivity levels. Fig.1 shows typical dynamic responses to 1ppm NO2 of the In3O2/Au GaN NW sensors under illumination at 265 nm and 365 nm, respectively, and Fig.2 the response at various relative humidity (RH) levels. An increase in resistance upon exposure to NO2 is observed, confirming the oxidizing nature of the NO2 gas. At this NO2 concentration level, the highest response value (29%) was obtained under (5mW, 265 nm) illumination, whereas the sensitivity under (5mW, 365nm) illumination was lower. For (30mW, 265nm) illumination, the sensitivity was 23% and for (30mW, 365nm) illumination it dropped to 15%. This phenomenon has been observed in the past by other authors also, and although its origins are not yet understood unambiguously, it may be caused by a higher rate of phonon energy relaxation at the surface at higher wavelengths, thereby reducing the effectiveness of chemisorption at the surface. In conclusion, room-temperature low-power photoactivated In3O2/Au GaN NW sensors with excellent levels of sensitivity at elevated relative humidity were designed, fabricated and tested. Figure 1

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Nguyen, Hong Hanh, Ngoc Son Dang, Van Duy Nguyen, Kyungsoo Jang, Kyunghyun Baek, Woojin Choi, Jayapal Raja, and Junsin Yi. "Charge Storage Characteristics of Si-Rich Silicon Nitride and the Effect of Tunneling Thickness on Nonvolatile Memory Performance." Solid State Phenomena 181-182 (November 2011): 307–11. http://dx.doi.org/10.4028/www.scientific.net/ssp.181-182.307.

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Nonvolatile memory (NVM) devices with nitride-nitride-oxynitride (NNO) stack structure using Si-rich silicon nitride (SiNx) as charge trapping layer on glass substrate were fabricated. Amorphous silicon clusters existing in the Si-rich SiNxlayer enhance the charge storage capacity of the devices. Low temperature poly-silicon (LTPS) technology, plasma-assisted oxidation/nitridation method to form a uniform ultra-thin tunneling layer, and an optimal Si-rich SiNxcharge trapping layer were used to fabricate NNO NVM devices with different tunneling thickness 2.3, 2.6 and 2.9 nm. The increase memory window, lower voltage operation but little scarifying in retention characteristics of nitride trap NVM devices had been accomplished by reducing the tunnel oxide thickness. The fabricated NVM devices with 2.9 nm tunneling thickness shows excellent electrical properties, such as a low threshold voltage, a high ON/OFF current ratio, a low operating voltage of less than ±9 V and a large memory window of 2.7 V, which remained greater than 72% over a period of 10 years.

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Eom, Dail, Cheol Seong Hwang, and Hyeong Joon Kim. "Thermal Stability of Stack Structures of Aluminum Nitride and Lanthanum Oxide Thin Films." ECS Transactions 3, no. 3 (December 21, 2019): 121–27. http://dx.doi.org/10.1149/1.2355704.

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Chen, Shih-Ching, Ting-Chang Chang, Po-Tsun Liu, Yung-Chun Wu, Ping-Hung Yeh, Chi-Feng Weng, S. M. Sze, Chun-Yen Chang, and Chen-Hsin Lien. "Nonvolatile polycrystalline silicon thin-film-transistor memory with oxide/nitride/oxide stack gate dielectrics and nanowire channels." Applied Physics Letters 90, no. 12 (March 19, 2007): 122111. http://dx.doi.org/10.1063/1.2715443.

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Chen, Yung Yu, Chih Ren Hsieh, and Fang Yu Chiu. "Characteristics of the SiN Uniaxial Strained NMOSFET with Channel Fluorine Implantation." Advanced Materials Research 383-390 (November 2011): 3178–82. http://dx.doi.org/10.4028/www.scientific.net/amr.383-390.3178.

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Channel fluorine implantation (CFI) has been successfully integrated with silicon nitride contact etch stop layer (SiN CESL) to further improve the channel hot electron stress (CHES) and constant voltage stress (CVS) reliability of n-channel metal-oxide-semiconductor field-effect-transistor with HfO2/SiON gate stack. Although the improvement of transconductance, drain current and subthreshold swing due to the fluorine passivation is screened out by the effect of uniaxial tensile strain, the result clearly demonstrates that integrating the CFI process in the SiN CESL-strained device can further suppress the CHES- and CVS-induced threshold voltage shift.

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Sahu, B. S., A. Kapoor, P. Srivastava, O. P. Agnihotri, and S. M. Shivaprasad. "Study of thermally grown and photo-CVD deposited silicon oxide–silicon nitride stack layers." Semiconductor Science and Technology 18, no. 7 (June 11, 2003): 670–75. http://dx.doi.org/10.1088/0268-1242/18/7/312.

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Wan, Yimao, James Bullock, and Andres Cuevas. "Tantalum oxide/silicon nitride: A negatively charged surface passivation stack for silicon solar cells." Applied Physics Letters 106, no. 20 (May 18, 2015): 201601. http://dx.doi.org/10.1063/1.4921416.

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