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1
Biswas, Shampa. "Integrated CMOS Doppler Radar : System Specification & Oscillator Design." Thesis, Linköpings universitet, Elektroniska Kretsar och System, 2016. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-129222.
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This thesis report presents system specification, such as frequency and output power level, and selection topology of an oscillator circuit suitable for a CMOS Integrated Doppler radar application, in order to facilitate short range target detection within 5-15 m range, using a 0.35 μm CMOS process. With this selected CMOS process, the frequency band at 2.45 GHz or 5 GHz, with a maximum output power level of 25 mW (e.i.r.p), is found to be appropriate for the whole system to obtain a good performance. In this thesis work, a Ring VCO with pseudo-differential architecture has been designed and optimised for 2.45 GHz application. However, for 5 GHz application, a differential cross-coupled LC VCO oscillator topology has been suggested and it is so designed that it can be further scaled down to operate at a frequency of 2.45 GHz. The performance of the oscillator circuits has been tested at circuit level and has been presented as simulation results in this report.
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Bosley, Ryan Travis. "A VHF/UHF Voltage Controlled Oscillator in 0.5um BiCMOS." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/31452.
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The dramatic increase in market demand for wireless products has inspired a trend for new designs. These designs are smaller, less expensive, and consume less power. A natural result of this trend has been the push for components that are more highly integrated and take up less real estate on the printed circuit board (PCB). Major efforts are underway to reduce the number of integrated circuits (ICs) in newer designs by incorporating several functions into a single chip. Availability of newer technologies such as silicon bipolar with complementary metal oxide semiconductor (BiCMOS) has helped facilitate this move toward more complex circuit topologies onto one die. BiCMOS achieves efficient chip area utilization by combining bipolar transistors, suited for higher frequency analog circuits with CMOS transistors that are useful for digital functions and lower frequency analog circuits. A voltage controlled oscillator (VCO) is just one radio frequency (RF) circuit block that can benefit from a more complex semiconductor process like BiCMOS.
This thesis presents the design and evaluation of an integrated VCO in the IBM 5S BiCMOS process. IBM 5S is a 0.5 um, single poly, five-metal process with surface channel PFETs and NFETs. The process also features self-aligned extrinsic base NPN bipolar devices exhibiting ft of up to 24 GHz.
The objective of this work is to obtain a VCO design that provides a high degree of functionality while maximizing performance over environmental conditions. It is shown that an external feedback and resonator network as well as a bandgap voltage referenced bias circuit help to achieve these goals. An additional objective for this work is to highlight several pragmatic issues associated with designing an integrated VCO capable of high volume production.
The Clapp variant of the Colpitts topology is selected for this application for reasons of robust operation, frequency stability, and ease of implementing in integrated form. Design is performed at 560 MHz using the negative resistance concept. Simulation results from Pspice and the Agilent ADS are presented. Implementation related issues such as bondwire inductances and layout details are covered. The VCO characterization is shown over several environmental conditions. The final nominal design is capable of: tuning over 150 MHz (22%) and delivering â 4.2 dBm into a 50 Ohm load while consuming only 9mA from a 3.0V supply. The phase noise at these conditions is
-92.5 dBc/Hz at a frequency offset of 10 kHz from the carrier. Finally, the conclusion of this work lists some suggestions for potential future research.Master of Science
3
Yu, Chuanzhao. "STUDY OF NANOSCALE CMOS DEVICE AND CIRCUIT RELIABILITY." Doctoral diss., University of Central Florida, 2006. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/3551.
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The development of semiconductor technology has led to the significant scaling of the transistor dimensions -The transistor gate length drops down to tens of nanometers and the gate oxide thickness to 1 nm. In the future several years, the deep submicron devices will dominate the semiconductor industry for the high transistor density and the corresponding performance enhancement. For these devices, the reliability issues are the first concern for the commercialization. The major reliability issues caused by voltage and/or temperature stress are gate oxide breakdown (BD), hot carrier effects (HCs), and negative bias temperature instability (NBTI). They become even more important for the nanoscale CMOS devices, because of the high electrical field due to the small device size and high temperature due to the high transistor densities and high-speed performances. This dissertation focuses on the study of voltage and temperature stress-induced reliability issues in nanoscale CMOS devices and circuits. The physical mechanisms for BD, HCs, and NBTI have been presented. A practical and accurate equivalent circuit model for nanoscale devices was employed to simulate the RF performance degradation in circuit level. The parameter measurement and model extraction have been addressed. Furthermore, a methodology was developed to predict the HC, TDDB, and NBTI effects on the RF circuits with the nanoscale CMOS. It provides guidance for the reliability considerations of the RF circuit design. The BD, HC, and NBTI effects on digital gates and RF building blocks with the nanoscale devices – low noise amplifier, oscillator, mixer, and power amplifier, have been investigated systematically. The contributions of this dissertation include: It provides a thorough study of the reliability issues caused by voltage and/or temperature stresses on nanoscale devices – from device level to circuit level; The more real voltage stress case – high frequency (900 MHz) dynamic stress, has been first explored and compared with the traditional DC stress; A simple and practical analytical method to predict RF performance degradation due to voltage stress in the nanoscale devices and RF circuits was given based on the normalized parameter degradations in device models. It provides a quick way for the designers to evaluate the performance degradations; Measurement and model extraction technologies, special for the nanoscale MOSFETs with ultra-thin, ultra-leaky gate oxide, were addressed and employed for the model establishments; Using the present existing computer-aided design tools (Cadence, Agilent ADS) with the developed models for performance degradation evaluation due to voltage or/and temperature stress by simulations provides a potential way that industry could use to save tens of millions of dollars annually in testing costs. The world now stands at the threshold of the age of nanotechnology, and scientists and engineers have been exploring here for years. The reliability is the first challenge for the commercialization of the nanoscale CMOS devices, which will be further downscaling into several tens or ten nanometers. The reliability is no longer the post-design evaluation, but the pre-design consideration. The successful and fruitful results of this dissertation, from device level to circuit level, provide not only an insight on how the voltage and/or temperature stress effects on the performances, but also methods and guidance for the designers to achieve more reliable circuits with nanoscale MOSFETs in the future.Ph.D.
Department of Electrical and Computer Engineering
Engineering and Computer Science
Electrical Engineering
4
Chen, Tingsu. "CMOS High Frequency Circuits for Spin Torque Oscillator Technology." Licentiate thesis, KTH, Integrerade komponenter och kretsar, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-139588.
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Spin torque oscillator (STO) technology has a unique blend of features, including but not limited to octave tunability, GHz operating frequency, and nanoscaled size, which makes it highly suitable for microwave and radar applications. This thesis studies the fundamentals of STOs, utilizes the state-of-art STO's advantages, and proposes two STO-based microwave systems targeting its microwave applications and measurement setup, respectively. First, based on an investigation of possible STO applications, the magnetic tunnel junction (MTJ) STO shows a great suitability for microwave oscillator in multi-standard multi-band radios. Yet, it also imposes a large challenge due to its low output power, which limits it from being used as a microwave oscillator. In this regard, different power enhancement approaches are investigated to achieve an MTJ STO-based microwave oscillator. The only possible approach is to use a dedicated CMOS wideband amplifier to boost the output power of the MTJ STO. The dedicated wideband amplifier, containing a novel Balun-LNA, an amplification stage and an output buffer, is proposed, analyzed, implemented, measured and used to achieve the MTJ STO-based microwave oscillator. The proposed amplifier core consumes 25.44 mW from a 1.2 V power supply and occupies an area of 0.16 mm2 in a 65 nm CMOS process. The measurement results show a S21 of 35 dB, maximum NF of 5 dB, bandwidth of 2 GHz - 7 GHz. This performance, as well as the measurement results of the proposed MTJ STO-based microwave oscillator, show that this microwave oscillator has a highly-tunable range and is able to drive a PLL. The second aspect of this thesis, firstly identifies the major difficulties in measuring the giant magnetoresistance (GMR) STO, and hence studying its dynamic properties. Thereafter, the system architecture of a reliable GMR STO measurement setup, which integrates the GMR STO with a dedicated CMOS high frequency IC to overcome these difficulties in precise characterization of GMR STOs, is proposed. An analysis of integration methods is given and the integration method based on wire bonding is evaluated and employed, as a first integration attempt of STO and CMOS technologies. Moreover, a dedicated high frequency CMOS IC, which is composed of a dedicated on-chip bias-tee, ESD diodes, input and output networks, and an amplification stage for amplifying the weak signal generated by the GMR STO, is proposed, analyzed, developed, implemented and measured. The proposed dedicated high frequency circuits for GMR STO consumes 14.3 mW from a 1.2 V power supply and takes a total area of 0.329 mm2 in a 65 nm CMOS process. The proposed on-chip bias-tee presents a maximum measured S12 of -20 dB and a current handling of about 25 mA. Additionally, the proposed dedicated IC gives a measured gain of 13 dB with a bandwidth of 12.5 GHz - 14.5 GHz. The first attempt to measure the (GMR STO+IC) pair presents no RF signal at the output. The possible cause and other identified issues are given.QC 20140114
5
Van, der Merwe John. "An experimental investigation into the validity of Leeson's equation for low phase noise oscillator design." Thesis, Stellenbosch : University of Stellenbosch, 2010. http://hdl.handle.net/10019.1/5424.
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Thesis (MScEng (Electrical and Electronic Engineering))--University of Stellenbosch, 2010.Thesis presented in partial fulfilment of the requirements for the degree Master of Science in Engineering at the University of Stellenbosch
ENGLISH ABSTRACT: In 1966, D.B. Leeson presented his model on phase noise in a letter entitled A Simple Model of Feedback Oscillator Noise Spectrum. This model usually requires an additional e ffective noise figure in order to conform with measured results. (This e ffective noise fi gure has to be determined by means of curve-fi tting Leeson's model with the measured results.) The model is, however, relatively simple to use, compared with other more accurate phase noise models that have since been developed and which can only be solved numerically with the aid of computers. It also gives great insight regarding component choices during the design process. Therefore several experiments were conducted in order to determine conditions under which Leeson's model may be considered valid and accurate. These experiments, as well as the conclusions drawn from their results, are discussed in this document.
AFRIKAANSE OPSOMMING: In 1966 stel D.B. Leeson sy faseruis model bekend in 'n brief getiteld A Simple Model of Feedback Oscillator Noise Spectrum. Hierdie model vereis gewoonlik die gebruik van 'n bykomende e ektiewe ruissyfer, sodat die model ooreenstem met die gemete resultate. (Hierdie e ektiewe ruissyfer kan slegs bepaal word deur middel van krommepassings tussen Leeson se model en die gemete resultate.) Die model is egter relatief eenvoudig om te gebruik in teenstelling met ander, meer akkurate, faseruis modelle wat sedertdien ontwikkel is en slegs met behulp van rekenaars opgelos kan word. Dit bied ook onoortre ike insig ten opsigte van komponent keuses tydens die ontwerpsproses. Om hierdie rede is verskeie eksperimente uitgevoer met die doel om toestande te identi seer waaronder Leeson se model as geldig en akkuraat geag kan word. Hierdie eksperimente, asook die gevolgtrekkings wat van hul resultate gemaak is, word in hierdie dokument behandel.
6
Wang, Shen. "Design and Analysis of a Low-Power Low-Voltage Quadrature LO Generation Circuit for Wireless Applications." Diss., Virginia Tech, 2012. http://hdl.handle.net/10919/39301.
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The competitive market of wireless communication devices demands low power and low cost RF solutions. A quadrature local oscillator (LO) is an essential building block for most transceivers. As the CMOS technology scales deeper into the nanometer regime, design of a low-power low-voltage quadrature LO still poses a challenge for RF designers.
This dissertation investigates a new quadrature LO topology featuring a transformer-based voltage controlled oscillator (VCO) stacked with a divide-by-two for low-power low-voltage wireless applications. The transformer-based VCO core adopts the Armstrong VCO configuration to mitigate the small voltage headroom and the noise coupling. The LO operating conditions, including the start-up condition, the oscillation frequency, the voltage swing and the current consumption are derived based upon a linearized small-signal model. Both linear time-invariant (LTI) and linear time-variant (LTV) models are utilized to analyze the phase noise of the proposed LO. The results indicate that the quality factor of the primary coil and the mutual inductance between the primary and the secondary coils play an important role in the trade-off between power and noise. The guidelines for determining the parameters of a transformer are developed.
The proposed LO was fabricated in 65 nm CMOS technology and its die size is about 0.28 mm2. The measurement results show that the LO can work at 1 V supply voltage, and its operation is robust to process and temperature variations. In high linearity mode, the LO consumes about 2.6 mW of power typically, and the measured phase noise is -140.3 dBc/Hz at 10 MHz offset frequency. The LO frequency is tunable from 1.35 GHz to 1.75 GHz through a combination of a varactor and an 8-bit switched capacitor bank. The proposed LO compares favorably to the existing reported LOs in terms of the figure of merit (FoM). More importantly, high start-up gain, low power consumption and low voltage operation are achieved simultaneously in the proposed topology. However, it also leads to higher design complexity.
The contributions of this work can be summarized as 1) proposal of a new quadrature LO topology that is suitable for low-power low-voltage wireless applications, 2) an in-depth circuit analysis as well as design method development, 3) implementation of a fully integrated LO in 65 nm CMOS technology for GPS applications, 4) demonstration of high performance for the design through measurement results. The possible future improvements include the transformer optimization and the method of circuit analysis.Ph. D.
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Arndt, Grégory. "System architecture and circuit design for micro and nanoresonators-based mass sensing arrays." Thesis, Paris 11, 2011. http://www.theses.fr/2011PA112358/document.
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Le sujet de thèse porte sur des micro/nanorésonateurs ainsi que leurs électroniques de lecture. Les composants mécaniques sont utilisés pour mesurer des masses inférieures à l'attogramme (10-18 g) ou de très faibles concentrations de gaz. Ces composants peuvent ensuite être mis en réseau afin de réaliser des spectromètres de masse ou des détecteurs de gaz. Afin d'atteindre les résolutions nécessaires, il a été choisi d'utiliser une détection harmonique de résonance détectant les variations de la fréquence de résonance d'une nanostructure mécanique. Les dimensions du résonateur sont réduites afin d'augmenter sensibilité en masse, cependant le niveau du signal électrique en sortie du composant est également réduit. Ce faible signal nécessite donc de concevoir de nouvelles transductions électromécaniques ainsi que des architectures électroniques qui minimisent le bruit, les couplages parasites et qui peuvent être mise en réseauThe PhD project focuses on micro or nanomechanical resonators and their surrounding electronics environment. Mechanical components are employed to sense masses in the attogram range (10−18 g) or extremely low gas concentrations. The components can then be implemented in arrays in order to construct cutting-edge mass spectrometers or gas chromatographs. To reach the necessary resolutions, a harmonic detection of resonance technique is employed that measures the shift of the resonant frequency of a tiny mechanical structure due to an added mass or a gas adsorption. The need of shrinking the resonator's dimensions to enhance the sensitivity also reduces the signal delivered by the component. The resonator low output signal requires employing new electromechanical resonator topologies and electronic architectures that minimize the noise, the parasitic couplings and that can be implemented in arrays
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Fitzpatrick, Justin Jennings. "Analysis and Design of Low-Jitter Oscillators." Diss., CLICK HERE for online access, 2004. http://contentdm.lib.byu.edu/ETD/image/etd369.pdf.
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Kellum, Reginald 1963. "Analysis and design of a regenerative differential voltage-controlled oscillator for high frequency integrated circuit applications." Thesis, The University of Arizona, 1991. http://hdl.handle.net/10150/278040.
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An investigation into the feasibility of designing a monolithic high frequency voltage controlled oscillator is performed. With design constraints of an oscillator Q between 5 and 10 and minimal chip area, the resonant LC tank and negative resistive cross coupled differential amplifier circuit is analyzed and design guidelines are developed. Analysis of the circuit encompasses both linear and non-linear modes of operation of the circuit, predicts the fundamental frequency of oscillation, and highlights design limitations for the resonant elements in terms of meeting the Q specifications at higher frequencies. Experimental results on a fixed frequency version of the VCO circuit yielded good agreement with theoretical analysis. For the parameters tested, the error was on the order of 10% in most cases.
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Bunch, Ryan Lee. "A Fully Monolithic 2.5 GHz LC Voltage Controlled Oscillator in 0.35 um CMOS Technology." Thesis, Virginia Tech, 2001. http://hdl.handle.net/10919/32287.
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The explosive growth in wireless communications has led to an increased
demand for wireless products that are cheaper, smaller, and lower
power. Recently there has been an increased interest in using CMOS, a
traditional digital and low frequency analog IC technology, to implement
RF components such as mixers, voltage controlled oscillators (VCOs), and
low noise amplifiers (LNAs). Future mass-market RF links, such as
BlueTooth, will require the potentially low-cost single-chip solutions
that CMOS can provide. In order for such single-chip solutions to be
realized, RF circuits must be designed that can operate in the presence
of noisy digital circuitry. The voltage controlled oscillator (VCO), an
important building block for RF systems, is particularly sensitive when
exposed to an electrically noisy environment. In addition, CMOS
implementations of VCOs have been hampered by the lack of high-quality
integrated inductors.
This thesis focuses on the design of a fully integrated 2.5 GHz LC CMOS
VCO. The circuit is intended as a vehicle for future mixed RF/digital
noise characterization. The circuit was implemented in a 0.35 um single
poly, 4 metal, 3.3 V, CMOS process available through MOSIS. The
oscillator uses a complementary negative transconductance topology.
This oscillator circuit is analyzed as a negative-resistance
oscillator. Monolithic inductors are designed using full-wave
electromagnetic field solver software. The design of an
"inversion-mode" MOS (I-MOS) tuning varactor is presented, along with a
discussion of the effects of varactor nonlinearity on VCO performance.
I-MOS varactors are shown to have substantially improved tuning range
(and tuning curve linearity) over conventional MOS varactors. Practical
issues pertaining to CMOS VCO circuit design, layout, and testing are
also discussed. The characterization of the VCO and the integrated
passives is presented. The VCO achieves a best-case phase noise of
-106.7 dBc/Hz at 100 kHz offset from a center frequency of 2.73 GHz. The
tuning range is 425 MHz (17%). The circuit consumes 9 mA from a 3.3 V
supply. This represents excellent performance for CMOS oscillator
designs reported at this frequency. Finally, several recommendations for
improvements in oscillator performance and characterization are
discussed.Master of Science
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Narayanaswamy, Anand Subramanian. "A Non-Contact Sensor Interface for High-Temperature, MEMS Capacitive Sensors." Case Western Reserve University School of Graduate Studies / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=case1275675071.
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Yu, Yixin. "Negative bias temperature instability and charge trapping effects on analog and digital circuit reliability." Master's thesis, University of Central Florida, 2007. http://digital.library.ucf.edu/cdm/ref/collection/ETD/id/4056.
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Nanoscale p-channel transistors under negative gate bias at an elevated temperature show threshold voltage degradation after a short period of stress time. In addition, nanoscale (45 nm) n-channel transistors using high-k (HfO2) dielectrics to reduce gate leakage power for advanced microprocessors exhibit fast transient charge trapping effect leading to threshold voltage instability and mobility reduction. A simulation methodology to quantify the circuit level degradation subjected to negative bias temperature instability (NBTI) and fast transient charge trapping effect has been developed in this thesis work. Different current mirror and two-stage operation amplifier structures are studied to evaluate the impact of NBTI on CMOS analog circuit performances for nanoscale applications. Fundamental digital circuit such as an eleven-stage ring oscillator has also been evaluated to examine the fast transient charge transient effect of HfO2 high-k transistors on the propagation delay of ring oscillator performance. The preliminary results show that the negative bias temperature instability reduces the bandwidth of CMOS operating amplifiers, but increases the amplifier's voltage gain at mid-frequency range. The transient charge trapping effect increases the propagation delay of ring oscillator. The evaluation methodology developed in this thesis could be extended to study other CMOS device and circuit reliability issues subjected to electrical and temperature stresses.M.S.E.E.
School of Electrical Engineering and Computer Science
Engineering and Computer Science
Electrical Engineering MSEE
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Scardelletti, Maximilian C. "DEVELOPMENT OF A HIGH TEMPERATURE SILICON CARBIDE CAPACITIVE PRESSURE SENSOR SYSTEM BASED ON A CLAPP-TYPE OSCILLATOR CIRCUIT." Case Western Reserve University School of Graduate Studies / OhioLINK, 2016. http://rave.ohiolink.edu/etdc/view?acc_num=case1467112012.
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Muhr, Eloi. "Conception de générateurs d'impulsions et des circuits de mise en forme reconfigurables associés." Thesis, Aix-Marseille, 2016. http://www.theses.fr/2016AIXM4346.
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Depuis 2002, différentes bandes de fréquences de plusieurs GHz dites « Ultra-Large Bande » (ULB), généralement comprises entre 3,1GHz et 10,6GHz, ont été libérées de par le monde pour la transmission d’informations sans fil. La largeur de ces bandes est telle qu’il devient envisageable d’utiliser des impulsions comme support de l’information en lieu et place d’une porteuse modulée comme cela est le cas habituellement. En effet, le spectre d’une impulsion étant inversement proportionnel à sa durée, une large plage de fréquences est requise pour la transmission d’informations via des impulsions. Cependant, il devient possible d’accroitre les débits en rapprochant les impulsions émises lorsque ceci est nécessaire, tout en offrant la possibilité d’éteindre les circuits et donc réduire la consommation lorsque deux impulsions sont suffisamment éloignées dans le temps.Le travail de recherche de cette thèse est dans ce contexte de proposer une structure d’émetteur impulsionnel reconfigurable disposant d’un contrôle suffisamment fin pour s’adapter aux différents canaux des standards IEEE 802.15.4 et 802.15.6 et ce, en n’utilisant que des circuits numériques pour les besoins des applications faibles coût. Pour cela, une étude théorique sur la mise en forme des impulsions requises est faite. Puis, il est question de la conception des différentes fonctions nécessaires à la mise en œuvre d’un émetteur impulsionnel reconfigurable, telles qu’un oscillateur contrôlé en tension pour la bande 3,1GHz-10,6GHz à démarrage rapide et que le circuit de mise en forme des oscillations associéSince 2002, various frequency bands of several GHz called "Ultra-WideBand" (UWB), generally between 3,1GHz and 10,6GHz, were liberalized in the world for wireless data transmission. The width of these bands is that it becomes possible to use pulses instead of a modulated carrier to transmit data. Indeed, as the spectrum of a pulse is inversely proportional to its duration, a wide range of frequencies is required for the transmission of information via pulses. However, it becomes possible to increase the rates by moving closer the emitted pulses when this is necessary, while providing the ability to switch off the circuits and thus reduce power consumption when two pulses are sufficiently far in time.To standardize the use of UWB frequency bands, standards such as IEEE 802.15.4 and 802.15.6 standards have emerged and have chosen to cut these frequency bands in channels of 500MHz and more. The aim of this thesis is also to propose a reconfigurable pulse transmitter structure with a fine enough control to address the different channels of IEEE 802.15.4 and 802.15.6 standard and, using only digital circuits to target low cost applications. For this, a theoretical study on the shaping of pulses required is made. Then it comes to the design of the various functions necessary for the implementation of a reconfigurable pulse transmitter, such as the implementation of a voltage controlled oscillator for 3,1GHz band-10,6GHz with quick start ability and the required oscillations shaping circuit
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Carroll, Matthew J. "First Order Self-Oscillating Class-D Circuit with Triangular Wave Injection." DigitalCommons@CalPoly, 2021. https://digitalcommons.calpoly.edu/theses/2303.
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An investigation into performance improvements to the modulator stage of a class-D amplifier is conducted in this thesis. Two of the standard topologies, namely class-D open-loop pulse-width modulation (PWM), and the improved self-oscillating feedback system are benchmarked against a topology which includes both a hysteretic comparator in a feedback loop and triangle wave injection. Circuit performance is analyzed by comparing how the triangle injection circuit handles known issues with open-loop and self-oscillating circuits. Using this analysis, it is shown that the triangle injection topology offers an improved power supply rejection ratio relative to open-loop PWM and reduces distortion generated by frequency modulation characteristic of the self-oscillating topology.
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Bořecký, Tomáš. "ARC oscilátor s bloky s řiditelným parametrem." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-217807.
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Within the master’s thesis there is comparison of different structures of ARC oscillators with respect to their harmonic distortion. Individual blocks of oscillator are analyzed. Attention is paid to choosing and design of suitable ARC filter structure and possibilities of its tuning. Also possibilities of stabilization of amplitude are analyzed. Different types of controlled amplifiers and circuits for controlling of their amplification are discussed. Next captures are focused to designing and simulation of the ARC oscillator. The oscillator can be tuned in the frequency range from 100 Hz to 20 kHz with harmonic distortion smaller than 1%. At the end of the thesis, practical realization of the proposed circuit is described. Also results of the measurement of parameters of the oscillator are given.
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Gomez, gomez Ricardo. "Design of innovative solutions to improve the variability and reliability of CMOS circuits on thin film technologies." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALT023.
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La sensibilité accrue aux variations des procedés de fabrication, de tension, de température et de vieillissement (PVTA) dans les nœuds technologiques avancés d'integration est responsable d'une dégradation significative des spécifications des circuits integrés lors de la fabrication à grand volume. Celle-ci est devenue une préoccupation croissante dans la conception de circuits numériques, qui doit faire face aux exigences de plus en plus strictes des applications modernes en termes d'efficacité énergétique, de fiabilité et de sécurité. Dans ce travail de thèse, les techniques de surveillance de timing intégrée et de compensation sont explorées pour répondre efficacement à ces exigences contradictoires. Dans ce travail de thèse, les techniques proposées ont été étudiés séparément puis combinées dans 3 démonstrateurs SoC numériques fabriqués en technologie 28nm FD-SOI CMOS, dont l'un a été mesuré au moment de la rédaction de ce manuscrit.La surveillance de timing intégrée est proposée comme solution de conception pour permettre la compensation des variations PVTA, la surveillance de la sécurité en operation et la protection contre les attaques hardware en timing. Les moniteurs de timing de l'état de l'art ont été évalués dans la perspective d'une intégration dans des produits industriels, ce qui privilégie des caractéristiques telles que la reusabilité et les faibles coûts d'intégration. Les avantages identifiés de la surveillance de timing de registre à registre ont conduit à la mise en œuvre d'un circuit témoin reconfigurable (Tunable Replica Circuit en langue anglaise) avec une sensibilité de 3 mV/bit en 28nm FD-SOI CMOS, qui démontre un suivi rapide et précis des variations PVTA d'un SoC basé sur un ARM Cortex-R4F à travers des corners lent / typique / rapide, une plage de tension 0.5/1.2 V, une gamme de temperature -40/150°C, et de vieillissement jusqu'a fin de vie. Enfin, ce travail propose un nouveau moniteur de timing qui permet de surmonter les faiblesses des solutions existantes, en obtenant simultanément la reutilisabilité élevée et la large plage de surveillance des oscillateurs en anneau et l'acquisition rapide et précise des circuits témoins reconfigurables.L'exploration des techniques d'adaptation et de compensation commence par la détermination de leur champ d'application dans les produits industriels: l'amélioration des pires cas qui définissent les limites de spécifications du produit lors de la fabrication à grand volume. Dans cette perspective, la région d'application optimale des techniques de voltage scaling et de body biasing a été déterminée et leur impact sur les pires cas des SoC numériques a été évalué. Enfin, ces travaux montrent comment la surconsommation induite par l'application séparée de voltage scaling ou body biasing peut être atténuée par la combinaison des deux, en particulier dans les circuits avec une variété de points de performance opérationnelle (OPPs).Les avantages des techniques proposées ont été démontrés dans un SoC numérique qui optimise son énergie à travers d'une largeur de fréquence de 11X en combinant le voltage scaling adaptatif, body biasing adaptatif et le bias-in-memory-array avec un tunable replica circuit pour la sécurité, la régulation de puissance intégrée et la compensation. Grâce à l'application de ces techniques, le circuit proposé permet de surmonter les limites précédemment signalées et démontre une amélioration des performances de 21X, une Vmin inférieure de 120 mV et une durée de vie de 8X, pour les OPP de faible puissance, de moyenne et de haute performance respectivement.Les études présentées ici ont été incluses dans plusieurs chapitres d'un livre scientifique qui sera publié cette année. En outre, elles ont contribué à une nouvelle plateforme de technologie et de conception. Enfin, 3 publications dans des conférences de l'IEEE et 3 demandes de brevet ont résulté de ce travail de thèseThe increased sensitivity to Process, Voltage, Temperature, and Aging (PVTA) variations in scaled integrated circuits' technology nodes is responsible for a significant degradation in the products' specifications during high volume manufacturing. This has become a growing concern in digital circuit design, which has to cope with the increasingly stringent requirements of modern applications in terms of energy efficiency, reliability, and safety. In this thesis work, embedded timing monitoring and compensation techniques are explored to efficiently address these conflicting requirements. The proposed techniques are studied separately and then combined in 3 digital SoC demonstrators manufactured in 28nm FD-SOI CMOS technology, one of which has been measured at the time of this manuscript's writing.Embedded timing monitoring is proposed as a design solution to enable PVTA compensation, in-field safety monitoring and security protection against hardware timing attacks. The state-of-the-art timing monitors are evaluated from the perspective of an integration into industrial products, emphasizing features such as high reusability and low integration costs. The identified advantages of register-to-register timing monitoring have led to the implementation of a 3mV/bit tunable replica circuit in 28nm FD-SOI CMOS, which demonstrates a fast and accurate PVTA tracking of an ARM Cortex-R4F based SoC across slow/typical/fast process, 0.5/1.2V, -40/150ºC, and End Of Life (EOL) aging. Finally, this work proposes a novel timing monitor that overcomes the weaknesses of existing solutions, simultaneously achieving the high reusability and wide monitoring range of ring oscillators and the fast and accurate timing acquisition of tunable replica circuits.The exploration of adaptive and compensation techniques begins with the determination of their application scope in industrial designs: the improvement of the worst-case limiting corners that set the product's specifications during high volume manufacturing. Following this perspective, the optimal region of application of voltage scaling and body biasing techniques has been determined and their impact on the worst-case specifications of digital SoCs has been assessed. Finally, this work demonstrates how the power overhead induced by the separate application of voltage scaling or body biasing can be mitigated through the combination of both, specially in circuits with a variety of Operational Performance Points (OPPs).The benefits of the proposed techniques have been demonstrated in a digital SoC that optimizes its energy across 11X frequency-wide OPPs by combining adaptive voltage scaling, adaptive body biasing, and bias-in-memory-array with a tunable replica circuit for safety, embedded power regulation and compensation. Through the application of these techniques the proposed design overcomes previously reported limitations and demonstrates an improvement by 21X performance, 120mV lower Vmin, and 8X lifetime, the low-power, mid-, and high-performance OPPs respectively.The studies reported here have been included in several chapters of a scientific book to be published this year. Furthermore, they have contributed to a new technology and design platform. Finally, 3 IEEE conference publications and 3 patent applications have resulted from this thesis' work
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Ameziane, El Hassani Chama. "Contribution à la réalisation d’un oscillateur push-push 80GHz synchronisé par un signal subharmonique pour des applications radars anticollisions." Thesis, Bordeaux 1, 2010. http://www.theses.fr/2010BOR14025/document.
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Ce travail de thèse s’inscrit dans le cadre d’un projet Français « VéLo » qui est une collaboration entre l’industriel STMicroelectronics et plusieurs laboratoires dont les laboratoires IMS-bordeaux et LAAS. Le but du projet est de concevoir un prototype de radar anticollision millimétrique. Dans ce travail un synthétiseur de fréquence est implémenté. Ce dernier sera intégré dans la chaine de réception du démonstrateur. Une étude bibliographique des architectures classiques de système de radiocommunication a été réalisée. Des exemples d’architectures rencontrées dans le domaine millimétrique ont été étudiés.L’objet principal de cette thèse est l’étude des oscillateurs synchronisés par injection ILO. L’objectif est de réaliser un oscillateur verrouillé par injection qui sera piloté par un oscillateur de fréquence plus basse possédant des caractéristiques de stabilité et de bruit meilleures.Dans ce travail de thèse, le mécanisme de verrouillage des oscillateurs par injection a été décrit. Un modèle de synchronisation par injection série, basé sur la théorie de Huntoon Weiss et inspiré du travail de Badets réalisé sur les oscillateurs synchrones verrouillés par injection parallèle, est proposé. La théorie établie a permis d’exprimer la plage de synchronisation en fonction de la topologie utilisée et des composants de la structure. La validité de la théorie a été évaluée par la simulation de la structure. Les résultats présentés montrent une bonne concordance entre la simulation et la théorie et permettent de valider le principe de synchronisation par injection. La faisabilité de l’intégration d’un ILO millimétrique synchronisé par l’harmonique d’un signal de référence de fréquence plus basse a été démontrée expérimentalement. Le synthétiseur de fréquence est réalisé en technologie BiCMOS 130nm pour des applications millimétriques de STMicroelectronics. Ce dernier opère dans une plage de 2GHz autour de la fréquence 82,5GHz. Les performances en bruit du synthétiseur sont satisfaisantes. Le bruit de phase de l’ILO recopie celui du signal injecté. Les équipements de mesures utilisés, le bruit de phase de l’oscillateur atteint des valeurs inférieures à -110dBc/Hz à 1MHz de la porteuseThis thesis is a part of a French project "VELO". The project is collaboration between STMicroelectronics and several laboratories including IMS-Bordeaux and LAAS laboratories. The aim of this project is to achieve a prototype of millimeter anti-collision radar. In this work a frequency synthesizer is implemented. This circuit will be incorporated in the reception chain of the demonstrator. A bibliographical study of classical architecture was completed. Examples of architectures encountered in the millimeter frequency range have been studied. The purpose of this thesis is to study the phenomena of synchronization in oscillators. The objective is to design an injection locked oscillator ILO driven by another oscillator, the second oscillator operates at lower frequency and offers better stability and noise characteristics.In this thesis, the injection locking mechanism of the oscillators has been described. A model of synchronization by series injection is proposed. The model is based on the theory of Huntoon and Weiss and inspired by Badets’ work performed on parallel injection. The theory expresses the synchronized frequency range depending on the used topology and the values of the components. The validity of the theory was evaluated by simulation. The results show good agreement between simulation and theory and validate the principle of synchronization by injection.The feasibility of a millimeter ILO synchronized by the harmonic of a reference signal operating at lower frequency has been demonstrated experimentally. The synthesizer was implemented in BiCMOS technology for 130nm applications millimeter of STMicroelectronics. The oscillator operates at 82.5 GHz and performs a frequency range of 2GHz. The noise performance of the synthesizer is satisfactory. The phase noise of the ILO depends on the reference phase noise, and reaches values of -110dBc/Hz at 1MHz from the carrier frequency
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Laporte, Christophe. "Conception en technologie intégrée de circuits hyperfréquences pour la télémesure image d'un instrument spatial." Phd thesis, Université Paul Sabatier - Toulouse III, 1995. http://tel.archives-ouvertes.fr/tel-00144088.
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L'objectif de cette étude est la réalisation en technologie monolithique intégrée de circuits hyperfréquences pour la télémesure d'un instrument spatial. L'étude a plus particulièrement porté sur la conception d'oscillateurs à fréquences fixes et d'oscillateurs contrôlés en tension entièrement intégrés dans la bande de fréquence 8-8,4 GHz. Une nouvelle méthode de conception des oscillateurs hyperfréquences, basée sur le calcul analytique des conditions d'oscillations de l'oscillateur, est présentée. Le calcul formel est utilisé pour accéder au rôle de chacun des éléments du circuit ainsi qu'à leur sensibilité sur les performances électriques. Les résultats théoriques et expérimentaux sont en très bon accord et démontrent la faisabilité d'oscillateurs à fréquences fixes et d'oscillateurs contrôlés en tension à résonateurs intégrés sur une puce. Cette méthode est également appliquée avec succès pour la réalisation d'un oscillateur intégré à 2 GHz. Une autre partie du travail a porté sur la réalisation de modulateurs biphases et quadriphases monolithiques. Les résultats de mesure sont conformes aux simulations et répondent aux spécifications de la télémesure
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Tinguy, Pierre. "Etude et développement d’un oscillateur à quartz intégré." Thesis, Besançon, 2011. http://www.theses.fr/2011BESA2017/document.
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Le besoin croissant de réduction du volume, de la masse et de la consommation des dispositifs électroniques sans pertes deperformances concerne aussi les oscillateurs à quartz utilisés dans les applications métrologiques (bases de temps, capteurs),la téléphonie, la navigation... Dans le cadre de cette problématique, nous avons développé un ASIC (Application SpecificIntegrated Circuit) en technologie 0,35 μm SiGe BiCMOS (Austriamicrosystems®) fonctionnant sous 3,3 V (±10%) pourréaliser un oscillateur à quartz miniature opérationnel sur une gamme en fréquence allant de 10 MHz à 100 MHz. Ce circuitdont la surface ne dépasse pas les 4 mm2 est composé de diverses cellules RF, depuis le système d’entretien de type Colpitts,la mise en forme et jusqu’à l’adaptation du signal à sa charge d’utilisation (50 W ou HCMOS). Ces cellules sont toutespolarisées par une référence de tension interne de type bandgap CMOS. La consommation totale du circuit en charge resteinférieure à 100 mW pour un bruit blanc de phase visé de −150 dBc/Hz à 40 MHz. Pour minimiser la sensibilité thermiquedu résonateur et ainsi pouvoir s’orienter également vers des applications OCXO (Oven Controlled Crystal Oscillator),nous avons partiellement intégré une régulation de température dans notre ASIC. Cette régulation fortement dépendante del’architecture thermo-mécanique a été dimensionnée puis validée au travers de modélisations par analogie sous Spectre®.Notre électronique intégrée nécessite peu de composants externes et nous l’avons reportée par flip chip sur une interfacespécifique pourThe increasing demand for high-performance devices featuring compact, lighter-weight designs with low-power consumptionalso impacts quartz crystal oscillators used in metrological applications (time bases, sensors), telephony or navigation. Inthis context, we have developed an ASIC (Application Specific Integrated Circuit) in 0.35 μm SiGe BiCMOS technology(Austriamicrosystems®) supplied by 3.3 V (±10%) to realize a miniaturized quartz crystal oscillator operating in the 10 MHzto 100 MHz frequency range. The fabricated die hosts several RF cells in a 4 mm2 area, including a sustaining amplifier(Colpitts topology), a signal shaping circuit and an output buffer dedicated to a specific load (50 W or HCMOS). These cellsare biased by a fully integrated CMOS bandgap voltage reference. The die power consumption remains lower than 100 mWfor a targeted phase noise floor as low as −150 dBc/Hz at a 40 MHz carrier frequency. A thermal control loop has in additionbeen partially integrated to the ASIC, in order to reduce the quartz resonator thermal sensitivity as well as to extend thepotential application field of the developed die to oven applications (OCXO). The thermal control, that is strongly dependanton the mechanical design, has been designed and tested by using electrical analogy modeling on Spectre® simulator. Finallyour integrated circuit has been connected to a specific substrate using flip chip technology to realize a miniaturized quartzcrystal oscillator packaged on a TO-8 enclosure (Ø15.2 mm)
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Zheng, Yi. "Biological Agent Sensing Integrated Circuit (BASIC): A New Complementary Metal-oxide-semiconductor (CMOS) Magnetic Biosensor System." Diss., Virginia Tech, 2014. http://hdl.handle.net/10919/48892.
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Fast and accurate diagnosis is always in demand by modern medical professionals and in the area of national defense. At present, limitations of testing speed, sample conditions, and levels of precision exist under current technologies, which are usually slow and involve testing the specimen under laboratory conditions. Typically, these methods also involve several biochemical processing steps and subsequent detection of low energy luminescence or electrical changes, all of which reduce the speed of the test as well as limit the precision. In order to solve these problems and improve the sensing performance, this project proposes an innovative CMOS magnetic biological sensor system for rapidly testing the presence of potential pathogens and bioterrorism agents (zoonotic microorganisms) both in specimens and especially in the environment. The sensor uses an electromagnetic detection mechanism to measure changes in the number of microorganisms--tagged by iron nanoparticles--that are placed on the surface of an integrated circuit (IC) chip. Measured magnetic effects are transformed into electronic signals that count the number and type of organisms present. This biosensor introduces a novel design of a conical-shaped inductor, which achieves ultra-accuracy of sensing biological pathogens. The whole system is integrated on a single chip based on the fabrication process of IBM 180 nm (CMOS_IBM_7RF), which makes the sensor small-sized, portable, high speed, and low cost. The results of designing, simulating, and fabricating the sensor are reported in this dissertation.Ph. D.
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CARUSO, Marco. "Computationally Efficient Innovative Techniques for the Design-Oriented Simulation of Free-Running and Driven Microwave Oscillators." Doctoral thesis, Università degli Studi di Palermo, 2014. http://hdl.handle.net/10447/90792.
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Analysis techniques for injection-locked oscillators/amplifiers (ILO) can be broadly divided into two classes. To the first class belong methods with a strong and rigorous theoretical basis, that can be applied to rather general circuits/systems but which are very cumbersome and/or time-consuming to apply. To the second class belong methods which are very simple and fast to apply, but either lack of validity/accuracy or are applicable only to very simple or particular cases.
In this thesis, a novel method is proposed which aims at combining the rigorousness and broad applicability characterizing the first class of analysis techniques above cited with the simplicity and computational efficiency of the second class. The method relies in the combination of perturbation-refined techniques with a fundamental frequency system approach in the dynamical complex envelope domain. This permits to derive an approximate, but first-order exact, differential model of the phase-locked system useable for the steady-state, transient and stability analysis of ILOs belonging to the rather broad (and rigorously identified) class of nonlinear oscillators considered.
The hybrid (analytical-numerical) nature of the formulation developed is suited for coping with all ILO design steps, from initial dimensioning (exploiting, e.g., the simplified semi-analytical expressions stemming from a low-level injection operation assumption) to accurate prediction (and fine-tuning, if required) of critical performances under high-injection signal operation.
The proposed application examples, covering realistically modeled low- and high-order ILOs of both reflection and transmission type, illustrate the importance of having at one's disposal a simulation/design tool fully accounting for the deviation observed, appreciable for instance in the locking bandwidth of high-frequency circuits with respect to the simplified treatments usually applied, for a quick arrangement, in ILO design optimization procedures.Analysis techniques for injection-locked oscillators/amplifiers (ILO) can be broadly divided into two classes. To the first class belong methods with a strong and rigorous theoretical basis, that can be applied to rather general circuits/systems but which are very cumbersome and/or time-consuming to apply. To the second class belong methods which are very simple and fast to apply, but either lack of validity/accuracy or are applicable only to very simple or particular cases. In this thesis, a novel method is proposed which aims at combining the rigorousness and broad applicability characterizing the first class of analysis techniques above cited with the simplicity and computational efficiency of the second class. The method relies in the combination of perturbation-refined techniques with a fundamental frequency system approach in the dynamical complex envelope domain. This permits to derive an approximate, but first-order exact, differential model of the phase-locked system useable for the steady-state, transient and stability analysis of ILOs belonging to the rather broad (and rigorously identified) class of nonlinear oscillators considered. The hybrid (analytical-numerical) nature of the formulation developed is suited for coping with all ILO design steps, from initial dimensioning (exploiting, e.g., the simplified semi-analytical expressions stemming from a low-level injection operation assumption) to accurate prediction (and fine-tuning, if required) of critical performances under high-injection signal operation. The proposed application examples, covering realistically modeled low- and high-order ILOs of both reflection and transmission type, illustrate the importance of having at one's disposal a simulation/design tool fully accounting for the deviation observed, appreciable for instance in the locking bandwidth of high-frequency circuits with respect to the simplified treatments usually applied, for a quick arrangement, in ILO design optimization procedures.
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Huan, Junjun. "Wafer-Level Vacuum-Encapsulated Ultra-Low Voltage Tuning Fork MEMS Resonator." University of Dayton / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=dayton1493253273171541.
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Sanderson, David Ivan. "A 5-6 Ghz Silicon-Germanium Vco With Tunable Polyphase Outputs." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/32623.
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In-phase and quadrature (I/Q) signal generation is often required in modern transceiver architectures, such as direct conversion or low-IF, either for vector modulation and demodulation, negative frequency recovery in direct conversion receivers, or image rejection. If imbalance between the I and Q channels exists, the bit-error-rate (BER) of the transceiver and/or the image rejection ratio (IRR) will quickly deteriorate. Methods for correcting I/Q imbalance are desirable and necessary to improve the performance of quadrature transceiver architectures and modulation schemes.
This thesis presents the design and characterization of a monolithic 5-6 GHz Silicon Germanium (SiGe) inductor-capacitor (LC) tank voltage controlled oscillator (VCO) with tunable polyphase outputs. Circuits were designed and fabricated using the Motorola 0.4 ìm CDR1 SiGe BiCMOS process, which has four interconnect metal layers and a thick copper uppermost bump layer for high-quality radio frequency (RF) passives.
The VCO design includes full-wave electromagnetic characterization of an electrically symmetric differential inductor and a traditional dual inductor. Differential effective inductance and Q factor are extracted and compared for simulated and measured inductors. At 5.25 GHz, the measured Q factors of the electrically symmetric and dual inductors are 15.4 and 10.4, respectively. The electrically symmetric inductor provides a measured 48% percent improvement in Q factor over the traditional dual inductor.
Two VCOs were designed and fabricated; one uses the electrically symmetric inductor in the LC tank circuit while the other uses the dual inductor. Both VCOs are based on an identical cross-coupled, differential pair negative transconductance -GM oscillator topology. Analysis and design considerations of this topology are presented with a particular emphasis on designing for low phase noise and low-power consumption. The fabricated VCO with an electrically symmetric inductor in the tank circuit tunes from 4.19 to 5.45 GHz (26% tuning range) for control voltages from 1.7 to 4.0 V. This circuit consumes 3.81 mA from a 3.3 V supply for the VCO core and 14.1 mA from a 2.5 V supply for the output buffer. The measured phase noise is -115.5 dBc/Hz at a 1 MHz offset and a tank varactor control voltage of 1.0 V. The VCO figure-of-merit (FOM) for the symmetric inductor VCO is -179.2 dBc/Hz, which is within 4 dBc/Hz of the best reported VCO in the 5 GHz frequency regime. The die area including pads for the symmetric inductor VCO is 1 mm x 0.76 mm. In comparison, the dual inductor VCO tunes from 3.50 to 4.58 GHz (27% tuning range) for control voltages from 1.7 to 4.0 V. DC power consumption of this circuit consists of 3.75 mA from a 3.3 V supply for the VCO and 13.3 mA from a 2.5 V supply for the buffer. At 1 MHz from the carrier and a control voltage of 0 V, the dual inductor VCO has a phase noise of -104 dBc/Hz. The advantage of the higher Q symmetric inductor is apparent by comparing the FOM of the two VCO designs at the same varactor control voltage of 0 V. At this tuning voltage, the dual inductor VCO FOM is -166.3 dBc/Hz compared to -175.7 dBc/Hz for the symmetric inductor VCO -- an improvement of about 10 dBc/Hz. The die area including pads for the dual inductor VCO is 1.2 mm x 0.76 mm.
In addition to these VCOs, a tunable polyphase filter with integrated input and output buffers was designed and fabricated for a bandwidth of 5.15 to 5.825 GHz. Series tunable capacitors (varactors) provide phase tunability for the quadrature outputs of the polyphase filter. The die area of the tunable polyphase with pads is 920 ìm x 755 ìm. The stand-alone polyphase filter consumes 13.74 mA in the input buffer and 6.29 mA in the two output buffers from a 2.5 V supply. Based on measurements, approximately 15° of I/Q phase imbalance can be tuned out using the fabricated polyphase filter, proving the concept of tunable phase. The output varactor control voltages can be used to achieve a potential ±5° phase flatness bandwidth of 700 MHz. To the author's knowledge, this is the first reported I/Q balance tunable polyphase network.
The tunable polyphase filter can be integrated with the VCO designs described above to yield a quadrature VCO with phase tunable outputs. Based on the above designs I/Q tunability can be added to VCO at the expense of about 6 mA. Future work includes testing of a fabricated version of this combined polyphase VCO circuit.Master of Science
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Klein, Adam Sherman. "Design and Characterization of RFIC Voltage Controlled Oscillators in Silicon Germanium HBT and Submicron MOS Technologies." Thesis, Virginia Tech, 2003. http://hdl.handle.net/10919/34435.
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Advances in wireless technology have recently led to the potential for higher data rates and greater functionality. Wireless home and business networks and 3G and 4G cellular phone systems are promising technologies striving for market acceptance, requiring low-cost, low-power, and compact solutions. One approach to meet these demands is system-on-a-chip (SoC) integration, where RF/analog and digital circuitry reside on the same chip, creating a mixed-signal environment. Concurrently, there is tremendous incentive to utilize Si-based technologies to leverage existing fabrication and design infrastructure and the corresponding economies of scale. While the SoC approach is attractive, it presents major challenges for circuit designers, particularly in the design of monolithic voltage controlled oscillators (VCOs). VCOs are important components in the up or downconversion of RF signals in wireless transceivers. VCOs must have very low phase noise and spurious emissions, and be extremely power efficient to meet system requirements. To meet these specifications, VCOs require high-quality factor (Q) tank circuits and reduction of noise from active devices; however, the lack of high-quality monolithic inductors, along with low noise transistors in traditional Si technologies, has been a limiting factor.
This thesis presents the design, characterization, and comparison of three monolithic 3-4 GHz VCOs and an integrated 5-6 GHz VCO with tunable polyphase outputs. Each VCO is designed around a differential -G_{M} core with an LC tank circuit. The circuits exploit two Si-based device technologies: Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) for a cross-coupled collectors circuit and Graded-Channel MOS (GC-MOS) transistors for a complementary (CMOS) implementation. The circuits were fabricated using the Motorola 0.4 μm CDR1 SiGe BiCMOS process, which consists of four interconnected metal layers and a thick copper (10 μm) metal bump layer for improved inductive components.
The VCO implementations are targeted to meet the stringent phase noise specifications for the GSM/EGSM 3G cellular standard. The specifications state that the VCO output cannot exceed -162 dBc/Hz sideband noise at 20 MHz offset from the carrier. Simultaneously, oscillators must be designed to address other system level effects, such as feed-through of the local oscillator (LO). LO feed-through directly results in self-mixing in direct conversion receivers, which gives rise to unwanted corrupting DC offsets. Therefore, a system-level strategy is employed to avoid such issues. For example, multiplying the oscillator frequency by two or four times can help avoid self-mixing during downconversion by moving the LO out of the bandwidth of the RF front-end.
Meanwhile, direct conversion or low-IF (intermediate frequency) receiver architectures utilize in-phase and quadrature (I/Q) downconversion signal recovery and image rejection. Any imbalance between the I and Q channels can result in an increase in bit-error-rate (BER) and/or decrease in the image rejection ratio (IRR). To compensate for such an imbalance, an integrated tunable polyphase filter is implemented with a VCO. Control voltages between the differential I and Q channels can be individually controlled to help compensate for I/Q mismatches.
This thesis includes an introduction to design flow and layout strategies for oscillator implementations. A detailed comparison of the advantages and disadvantages of the SiGe HBTs and GC-MOS device in 3-4 GHz VCOs is presented. In addition, an overview of full-wave electromagnetic characterization of differential dual inductors is given. The oscillators are characterized for tuning range, output power, and phase noise. Finally, new measurement techniques for the 5-6 GHz VCO with a tunable polyphase filter are explored. A comparison between the time and frequency approaches is also offered.Master of Science
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Vencálek, Roman. "Univerzální aktivní prvky a jejich využití v kmitočtových filtrech." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2009. http://www.nusl.cz/ntk/nusl-218092.
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This master’s thesis deals with the advanced universal modern active elements, such as the current and voltage conveyors. The problem with small bandwidth has been fixed due to the quick development in recent years. Current and voltage conveyors are still being researched. The good properties of conveyors promise their possible commercial usage in the future. For the research of current conveyors we can use parts of other integrated circuits and thus get elements with similar properties. This thesis suggests how to make an active filter using the DBTA and FDBTA elements which were created by “combination” of the universal current and voltage conveyor. Simulations were carried out on selected circuits containing the DBTA to verify their properties. It was for finding out about their behaviour in real applications that the circuits were constructed. This enabled the comparison of the results acquired from the simulation programs with the ideal behaviour of the elements and with the models simulating real properties against the values acquired by measurements of the circuits.
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Enchelmaier, David Samuel. "A miniaturised wideband frequency synthesiser." Thesis, Queensland University of Technology, 2009. https://eprints.qut.edu.au/31851/1/David_Enchelmaier_Thesis.pdf.
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Wideband frequency synthesisers have application in many areas, including test instrumentation and defence electronics. Miniaturisation of these devices provides many advantages to system designers, particularly in applications where extra space and weight are expensive.
The purpose of this project was to miniaturise a wideband frequency synthesiser and package it for operation in several different environmental conditions while satisfying demanding technical specifications. The four primary and secondary goals to be achieved were:
1. an operating frequency range from low MHz to greater than 40 GHz, with resolution better than 1 MHz,
2. typical RF output power of +10 dBm, with maximum DC supply of 15 W,
3. synthesiser package of only 150 100 30 mm, and
4. operating temperatures from 20C to +71C, and vibration levels over 7 grms.
This task was approached from multiple angles. Electrically, the system is designed to have as few functional blocks as possible. Off the shelf components are used for active functions instead of customised circuits. Mechanically, the synthesiser package is designed for efficient use of the available space. Two identical prototype synthesisers were manufactured to evaluate the design methodology and to show the repeatability of the design.
Although further engineering development will improve the synthesiser’s performance, this project has successfully demonstrated a level of miniaturisation which sets a new benchmark for wideband synthesiser design. These synthesisers will meet the demands for smaller, lighter wideband sources. Potential applications include portable test equipment, radar and electronic surveillance systems on unmanned aerial vehicles. They are also useful for reducing the overall weight and power consumption of other systems, even if small dimensions are not essential.
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Weisz, Mario. "Electrothermal device-to-circuit interactions for half THz SiGe∶C HBT technologies." Thesis, Bordeaux 1, 2013. http://www.theses.fr/2013BOR14909/document.
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Ce travail concerne les transistors bipolaires à hétérogène TBH SiGe. En particulier, l'auto-échauffement des transistors unitaires et le couplage thermique avec leurs plus proches voisins périphériques sont caractérisés et modélisés. La rétroaction électrothermique intra- et inter-transistor est largement étudiée. En outre, l’impact des effets thermiques sur la performance de deux circuits analogiques est évalué. L'effet d'autoéchauffement est évalué par des mesures à basse fréquence et des mesures impulsionnelles DC et AC. L'auto-échauffement est diminué de manière significative en utilisant des petites largeurs d'impulsion. Ainsi la dépendance fréquentielle de l’autoéchauffementa été étudiée en utilisant les paramètres H et Y. De nouvelles structures de test ont été fabriqués pour mesurer l'effet de couplage. Les facteurs de couplage thermique ont été extraits à partir de mesures ainsi que par simulations thermiques 3D. Les résultats montrent que le couplage des dispositifs intra est très prononcé. Un nouvel élément du modèle de résistance thermique récursive ainsi que le modèle de couplage thermique a été inclus dans un simulateur de circuit commercial. Une simulation transitoire entièrement couplée d'un oscillateur en anneau de 218 transistors a été effectuée. Ainsi, un retard de porte record de 1.65ps est démontré. À la connaissance des auteurs, c'est le résultat le plus rapide pour une technologie bipolaire. Le rendement thermique d'un amplificateur de puissance à 60GHz réalisé avec un réseau multi-transistor ou avec un transistor à plusieurs doigts est évalué. La performance électrique du transistor multidoigt est dégradée en raison de l'effet de couplage thermique important entre les doigts de l'émetteur. Un bon accord est constaté entre les mesures et les simulations des circuits en utilisant des modèles de transistors avec le réseau de couplage thermique. Enfin, les perspectives sur l'utilisation des résultats sont donnéesThe power generate by modern silicon germanium (SiGe) heterojunction bipolar transistors (HBTs) can produce large thermal gradients across the silicon substrate. The device opering temperature modifies model parameters and can significantly affect circuit operation. This work characterizes and models self-heating and thermal coupling in SiGe HBTs. The self-heating effect is evaluated with low frequency and pulsed measurements. A novel pulse measurement system is presented that allows isothermal DC and RF measurements with 100ns pulses. Electrothermal intra- and inter-device feedback is extensively studied and the impact on the performance of two analog circuits is evaluated. Novel test structures are designed and fabricated to measure thermal coupling between single transistors (inter-device) as well as between the emitter stripes of a multi-finger transistor (intra-device). Thermal coupling factors are extracted from measurements and from 3D thermal simulations. Thermally coupled simulations of a ring oscillator (RO) with 218 transistors and of a 60GHz power amplifier (PA) are carried out. Current mode logic (CML) ROs are designed and measured. Layout optimizations lead to record gate delay of 1.65ps. The thermal performance of a 60GHz power amplifier is compared when realized with a multi-transistor array (MTA) and with a multi-finger trasistor (MFT). Finally, perspectives of this work within a CAD based circuit design environment are discussed
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Veillette, Benoît R. "A study of delta-sigma oscillator circuits." Thesis, McGill University, 1995. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=22837.
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The generation of spectrally pure analog sinewave with predictable characteristics is an important issue of mixed-signal testing. Digital frequency synthesizers exhibit many good features but current implementations are area expensive. This dissertation will study a novel digital frequency synthesizer approach based on digital resonators and delta-sigma modulation. Except for a 1-bit digital-to-analog converter, the analog signal generator implementation is entirely digital allowing precise control over the amplitude and frequency of oscillation. It may therefore be tested using digital methods, making this signal generator attractive for analog built-in self-test (BIST) implementations. Furthermore, this signal generation method is area efficient as it does not require a ROM or a multiplier. However the presence of a delta-sigma modulator in a feedback loop make these circuits non-linear. The limitations of the linear model will therefore be addressed. We envision that this signal generator can be used in communication or for analog testing. One such application, wireless communication system BIST will be presented.
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Gray, Peter. "Phase-locked cellular oscillators." Thesis, University of Aberdeen, 1996. http://digitool.abdn.ac.uk/R?func=search-advanced-go&find_code1=WSN&request1=AAIU089854.
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Biological oscillators occur frequently in nature---and many systems, such as the growth of certain bacteria, are governed by the 24-hour circadian clock. Furthermore biological phase-locked oscillators, as identified by researchers, are clearly an integral part of the structure of the brain in humans, and in animals in general. Such systems are most conveniently investigated via computer models. This thesis describes the computer-modelling of phase-locked systems in which the oscillator is a cellular automaton---a device often used by scientists to model the growth or decay of populations within biological and other systems. The latter part of the thesis shows how these computer models have been implemented in a two-dimensional form using gate array technology, and results are presented to demonstrate the overall loop performance. It is not suggested that the phase-locked loops described in this thesis should be translated directly into practical commercial products---the primary objective of the research described being to originate a new type of phase-locked loop based around a novel variable frequency oscillator. However, the summary at the end of the thesis indicates how the designs might be modified so as to allow a direct silicon implementation.
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Sharapov, V. M., and K. V. Bazilo. "Piezoelectric transformer with parallel oscillatiry circuit." Thesis, Sumy State University, 2014. http://essuir.sumdu.edu.ua/handle/123456789/39938.
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Piezoelectric transducers are widely used in electroacoustics, hydroacoustics, in ultrasound, medical, measurement technique, in scanning probe nanomicroscopes, piezoengines and in other fields of science and technology. To create transducers with necessary characteristics the technology of additional elements can be used.
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Sehmbi, Jatinder Singh. "The dynamics of friction oscillators." Thesis, University College London (University of London), 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.248042.
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Lang, Radek. "Vysokofrekvenční oscilátor v technologii CMOS." Master's thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2015. http://www.nusl.cz/ntk/nusl-221110.
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This project focus to desing an on-chip oscillator in function as a clock generator. Frequency stability of the oscillator is affected by supply voltage, temperature and process variations. The aim is to propose a clock generator with sufficient frequency stability, low power consumption and a small chip area. This work deals with the types of oscillators and their basic building blocks suitable for our application. It also deals with the study and design options of temperature and process compensation circuit generating the current control, which provides the frequency stabilization of the output signal.
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Tasselli, Josiane. "Etude et realisation de structures bipolaires particulieres a heterojonction gaas-gaaias : application aux circuits integres de type ecl." Toulouse 3, 1986. http://www.theses.fr/1986TOU30019.
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Ce memoire presente l'etude et la realisation d'un circuit integre bipolaire de type ecl sur arseniure de gallium. Une etude theorique de transistors bipolaires a double heterojonction a montre l'influence determinante de la jonction collecteur-base, notamment de sa gradualite, sur leur comportement electrique. Ces resultats ont pu etre confirmes par une analyse experimentale a partir de structures realisees par epitaxie en phase liquide. La simulation et l'optimisation d'un oscillateur en anneau a base de simples heterotransistors et mettant en oeuvre le logiciel astec iii, ont permis de calculer des temps de propagation par porte de 20 ps pour une puissance consommee de 4 mw; ceci confirme les potentialites de la filiere logique bipolaire sur asga. Enfin, un oscillateur en anneau a 3 portes ecl a ete concu et realise par les technologies d'epitaxie en phase liquide et d'attaques mesas, a partir d'un processus nouveau sur substrat semi-isolant. La faisabilite d'un circuit integre bipolaire asga a ainsi ete montree
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Opperman, Tjaart Adriaan Kruger. "A 5 GHz BiCMOS I/Q VCO with 360° variable phase outputs using the vector sum method." Diss., Pretoria : [s.n.], 2009. http://upetd.up.ac.za/thesis/available/etd-04082009-171225/.
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Thesis (M.Eng.(Microelectronic Engineering))--University of Pretoria, 2009.Includes summaries in Afrikaans and English. Includes bibliographical references (leaves [74]-78). Mode of access: World Wide Web.
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Wilson, Martin Paul. "Synthesised local oscillator design considerations for satellite data communications systems." Thesis, University of York, 1992. http://etheses.whiterose.ac.uk/2489/.
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Laha, Soumyasanta. "Analysis & Design of Radio Frequency Wireless Communication Integrated Circuits with Nanoscale Double Gate MOSFETs." Ohio University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1418730974.
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Madureira, Heider Marconi Guedes. "Study and design of CMOS RF power circuits and modulation capabilities for communication applications." Thesis, reponame:Repositório Institucional da UnB, 2015. http://www.theses.fr/2015BORD0093/document.
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Dans l’ère des systèmes de communication multi-standards, le besoin des circuits en radio fréquence (RF) flexibles et reconfigurables pousse l´industrie et le monde académique vers la recherche d´architectures alternatives d’émetteurs et de récepteurs RF. Dans cette thèse, nous nous intéressons aux émetteurs RF flexibles. Nous présentons une architecture basée sur l’utilisation d’un oscillateur de puissance composé d´un amplificateur de puissance dans une boucle de rétroaction positive. Pour des raisons de compatibilité avec des circuit numériques et dans le but de minimiser les coûts de fabrication, nous avons choisi la technologie CMOS. Ce choix génère des difficultés de conception des circuits en RF à cause des faibles tensions de claquage. Cette contrainte de conception a motivé le choix de la classe EF2 pour l’amplificateur de puissance afin de réduire le stress en tension sur les transistors. Nous présentons la conception de cet amplificateur de puissance de classe EF2, ainsi que la conception de l’oscillateur de puissance. Nous validons cette architecture avec une implémentation en technologie CMOS 0.13um de STMicroelectronics. Nous démontrons le bon comportement par une campagne de mesures des circuits fabriqués. Ce circuit répond aux contraintes de flexibilité de modulation et de puissance de sortie. Il peut donc être utilisé pour différents standards de communications. Les limitations inhérentes de cette architecture sont discutées et une modélisation mathématique est présentéeThis work presents the study, design and measurement of RF circuits aiming communication applications. The need for flexible and reconfigurable RF hardware leads to the need of alternative transmitter architectures. In the center of this innovative architecture, there is thepower oscillator. This circuit is composed of a power amplifier in a positive feedback loop soit oscillates. As the circuit under study is mainly composed of a power amplifier, a study on power amplifier is mandatory. Modern CMOS technologies impose difficulties in the efficient RF generation due to low breakdown voltages. In order to reduce the voltage stress on the transistors, wave form-engineering techniques are used leading to the use of class EF2. Thedesign and measurement of a class EF2 power amplifier and power oscillator are shown. Thecircuits were implemented in standard STMicroelectronics 0.13um CMOS. Correct behaviorfor the circuits was obtained in measurement, leading to a first implementation of class EF2 inRF frequencies. From a system perspective, the proposed architecture is shown to be flexible and able to generate different modulations without change in the hardware. Reconfigurability is shown not only in modulation but also in output power level. The limitations of this architecture are discussed and some mathematical modeling is presented
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Foale, Stephen. "Bifurcations in impact oscillators : theoretical and experimental studies." Thesis, University College London (University of London), 1993. http://discovery.ucl.ac.uk/1381753/.
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One of the most important features of nonlinear dynamicai systems is that, as system parameters are varied, qualitative changes in the overall behaviour of the system can occur at a bifurcation . For smooth systems, the local bifurcations which occur under the change of one parameter are well understood. Non-smooth dynamical systems, which frequently arise due to the way certain physical processes are modelled, undergo bifurcations which have not been widely studied. We examine a particular type of bifurcation arising in a commonly occurring class of non-smooth dynamical system, combining theoretical and experimental results. In this thesis we are concerned with the study of the important class of dynamical system we call impact oscillators, which undergo oscillations under the influence of some forcing, and additionally can undergo impacts at rigid stops. Such systems are of interest because a large number of physical and engineering systems display behaviour which can be classified as impacting, where it is important to use a dynamical analysis to identify and thus avoid the noise, wear or failure which could be caused by repeated impacts producing unacceptably large loads. Recent interest in such systems has concentrated on the unusual bifurcational behaviour which occurs when part of an orbit begins to undergo low velocity impacts. Using analytical methods to locate particular simple steady state solutions of an impact oscillator these grazing bjfurcations are investigated. Comparisons are made between the behaviour of these special bifurcations, which arise because of the instantaneous reversal of velocity in the mathematical model of the impact process, and the standard bifurcations of smooth dynamical systems. An experimental study of an electromagnetically forced metal beam impacting against a stop is used to show that the overall qualitative behaviour displayed by a simple theoretical model is also displayed in a physical impact oscillator. Finally the theoretical studies are related to a particular problem of offshore engineering and it is shown how a very simple model can be used to explain some unusual observed behaviour.
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Pache, Denis. "Étude de nouvelles architectures pour l'intégration de fonctions radio fréquence en technologie BiCMOS." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0079.
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Ce travail est consacre a l'integration des fonctions radio frequence (rf) de la partie reception d'un terminal mobile 2ghz en technologie silicium bicmos. Dans une premiere partie, les differentes caracteristiques des systemes rf sont rappelees. Ces systemes sont particulierement complexes (architecture, fiabilite) et les problemes lies a leur integration sont mis en evidence. Dans la partie suivante les principes de base et les proprietes des modulations analogiques et numeriques sont donnes. Dans une troisieme partie les composants silicium sont analyses. En particulier, une comparaison entre les transistors bipolaire et mos montre leurs limitations respectives et leur complementarite. Les systemes rf utilisent des inductances ; une modelisation de ce composant passif est proposee pour son integration sur silicium. Dans la derniere partie, quatre architectures pour une integration complete des quatre fonctions principales d'un recepteur (lna, filtre de frequence image et melangeur, filtre de frequence intermediaire, synthetiseur de frequence) sont proposees. Ces architectures ont ete validees par des mesures sur circuit. Leurs performances et leur souplesse permettent d'envisager maintenant la conception d'un recepteur rf totalement integre et adaptable a la plupart des normes des systemes rf (actuels ou futurs)
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Lauterbach, Adam Peter. "Low-cost SiGe circuits for frequency synthesis in millimeter-wave devices." Australia : Macquarie University, 2010. http://hdl.handle.net/1959.14/76626.
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"2009"Thesis (MSc (Hons))--Macquarie University, Faculty of Science, Dept. of Physics and Engineering, 2010.
Bibliography: p. 163-166.
Introduction -- Design theory and process technology -- 15GHz oscillator implementations -- 24GHz oscillator implementation -- Frequency prescaler implementation -- MMIC fabrication and measurement -- Conclusion.
Advances in Silicon Germanium (SiGe) Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) technology has caused a recent revolution in low-cost Monolithic Microwave Integrated Circuit (MMIC) design. -- This thesis presents the design, fabrication and measurement of four MMICs for frequency synthesis, manufactured in a commercially available IBM 0.18μm SiGe BiCMOS technology with ft = 60GHz. The high speed and low-cost features of SiGe Heterojunction Bipolar Transistors (HBTs) were exploited to successfully develop two single-ended injection-lockable 15GHz Voltage Controlled Oscillators (VCOs) for application in an active Ka-Band antenna beam-forming network, and a 24GHz differential cross-coupled VCO and 1/6 synchronous static frequency prescaler for emerging Ultra Wideband (UWB) automotive Short Range Radar (SRR) applications. -- On-wafer measurement techniques were used to precisely characterise the performance of each circuit and compare against expected simulation results and state-of-the-art performance reported in the literature. -- The original contributions of this thesis include the application of negative resistance theory to single-ended and differential SiGe VCO design at 15-24GHz, consideration of manufacturing process variation on 24GHz VCO and prescaler performance, implementation of a fully static multi-stage synchronous divider topology at 24GHz and the use of differential on-wafer measurement techniques. -- Finally, this thesis has llustrated the excellent practicability of SiGe BiCMOS technology in the engineering of high performance, low-cost MMICs for frequency synthesis in millimeterwave (mm-wave) devices.
Mode of access: World Wide Web.
xxii, 166 p. : ill (some col.)
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Conti, Riccardo. "Studio e realizzazione di un "timing circuit" e "output circuit" per pacemaker." Bachelor's thesis, Alma Mater Studiorum - Università di Bologna, 2015. http://amslaurea.unibo.it/9264/.
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Nell'elaborato è stato svolto uno studio su più livelli degli elementi essenziali del pacemaker asincrono secondo la realizzazione circuitale proposta da Wilson Greatbatch nel 1960. Un primo livello ha riguardato l’analisi teorica del circuito. Un secondo livello ha riguardato un’analisi svolta con LTSPICE. Con questo stesso programma, si è analizzato il segnale di temporizzazione e la forma d’onda sul carico al variare del valore di alcuni componenti chiave del circuito. Infine, si è proceduto alla sua realizzazione su breadboard.
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Crouch, David Andrew. "Gallium arsenide field effect transistors microstrip integrated circuit dielectric resonator oscillators." Master's thesis, University of Cape Town, 1988. http://hdl.handle.net/11427/8329.
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Bibliography: leaves 175-177.This thesis is concerned with Gallium Arsenide Metal Semiconductor Field Effect Transistor Microstrip Integrated Circuit Dielectric Resonator Oscillators (GaAs MESFET MIC DROs) - the different types, their design and their performance compared to other high Q factor (ie narrowband) microwave oscillators. The thesis has three major objectives. The first is to collate the information required to build microwave DROs. The second is to present the practical results obtained from Dielectric Resonator Bandreject and Bandpass filters (DR BRFs and DR BPFs). The last is to present and compare results from a DR stabilised microstrip oscillator and three types of series feedback DROs. Narrowband oscillators are usually evaluated in terms of their frequency stability, reliability, size, cost, efficiency and output power characteristics. In terms of these parameters DROs outperform Gunn cavity oscillators and are only bettered by crystal locked sources in terms of frequency temperature stability and long-term stability. The components of a GaAs MESFET MIC DRO possess ideal properties for the construction of a narrowband source with the exception of the long term stability of the GaAs MESFET. GaAs MESFET•DROs have the best published DRO results for efficiency, output power, power temperature stability and external Q factor. Basic oscillator theory derived by Kurokawa can be applied to both negative resistance and feedback oscillators. Impedance locus, device-line and operating point concepts provide a convenient framework for understanding hysteresis in microwave oscillators. The work by Kurokawa can also be translated into the S-parameter domain which has proved convenient for the design of microwave oscillators.
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Li, Jih-Shui, and 李日舜. "11.492GHz Local Oscillator Circuit Design." Thesis, 2005. http://ndltd.ncl.edu.tw/handle/65800913454844139310.
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碩士逢甲大學
電子工程所
93
Abstract In this thesis we design a 11.492GHz local oscillator circuit. This text was described a circuit which includes several important parts TCXO IC, RF synthesizer IC, Frequency control IC, loop filter, VCO(voltage control oscillator) IC, feedback loop, multiple, micro-strip band-pass filter, amplifier, and micro-strip low-pass filter. The local oscillator is a very important component in the RF/microwave system. It serves as the signal generator in a transmitter and in a receiver, and the local oscillator is used together with a mixer to convert the received RF signal to an IF signal. The oscillator signal also can serve as a carrier, and the modulating low frequency signal to be transmitted like up-converter or down-converter. The oscillators used in RF transceivers are usually embedded in a synthesizer environment so as to achieve a precise definition of the output frequency. Nevertheless synthesizer design still remains one of the challenging tasks in RF systems because it must meet very stringent requirement. The flourish development designing the industry IC in recent years makes us be able to use existing IC directly in the circuit design.
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AN, CHUU FU, and 褚福安. "Steady-state Nonlinear Circuit and Oscillator Circuit Analysis Using Chebyshev series." Thesis, 1995. http://ndltd.ncl.edu.tw/handle/51157577152677376983.
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碩士國立臺灣科技大學
工程技術研究所
83
PSPICE是廣被運用於電子電路模擬設計的主要工具之一,對於振盪器電路 之高Q值線路,使用暫態分析時,經常會碰到準確性與收斂性的問題使得結 果並不正確,並且暫態分析可能因電路中各節點之時間常數之大小,可能相 差太遠,而使得到達穩態之時間很大,因此使用PSPICE並不方便,所以需要 一種穩態分析方法。本文提出一種時域方法,來計算非線性電路與振盪器 電路的穩態響應。此方法以電路中元件或埠的電壓或電流為電路狀態變 數,並以柴比雪夫級數(Chebyshev Series)來代表。根據網路方程式可建 立目標函數,再代入最佳化程式中,以求得柴比雪夫級數的係數,進而求得 各分支的電壓與電流。文中舉出四個例子,分別利用本文之方法及PSPICE 做分析,發現兩者結果相近,根據目標函數值,可驗証本文之方法。本文不 僅提出了一種穩態分析電路的方法,並實做出一微波振盪器,隨後對實做結 果做一討論。歷年來有許多非線性電路的研究,對於有關本文的參考文獻, 有些文獻有缺點,本文將其缺點處指出,並加以修正。
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Yao, Chi-Ping, and 姚啟平. "The Circuit Design of Dual-Band Voltage-Controlled Oscillator." Thesis, 2002. http://ndltd.ncl.edu.tw/handle/54154547643571076574.
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碩士國立清華大學
電子工程研究所
90
When the device technology improves, the power supply vdd become lower,the voltage used to bias the varactor reduced consequently. As a result, the tuning range of vco reduces.This thesis use CMOS technology to simulate specification of GSM900 and DCS1800 which dual-band voltage-controlled oscillator,and can be used in RF transceiver.So,it introduce mulity channel and wide channel form the design of circuit.Beside, using switch resonator to meet the requirement of dual-band range and using the varactor to tune frequency slightly.
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Chang, Chun Yi, and 張淳毅. "10~30GHz Voltage Control Oscillator Circuit Design and Implementation." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/86914430990435582586.
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碩士長庚大學
電子工程學研究所
96
This thesis presents the development of a 10~30GHz UWB voltage-controlled oscillator with standard CMOS technology. There are two groups of voltage-controlled oscillators (VCO) to be implemented. One is tuning range of around 7.5GHz to 10GHz and another is around 10GHz to 15GHz. Via the operation mechanism, we can switch on the special voltage-controlled oscillator. Then, it provides the frequency bandwidth of 20GHz. Furthermore, ADS (Advanced Design System) software is also used to design the whole circuit with the RF circuit simulation. The contents are divided into the following three parts. The first part presents the design of 15~20GHz UWB VCO. The simulation results are shown as follows: frequency range from 14.39 to 20.32GHz, phase noise from -100.6 to -109.5dBc/Hz@1MHz, output power from -1.1 to -5.2dBm and power dissipation of about 27.32mW. The second part is a design of 10~15GHz UWB VCO. The simulation result shows：frequency range from 10.26 to 14.41GHz, phase noise from -104 to -109.5dBc/Hz@1MHz, output power from -5.3 to -9.5dBm and power dissipation of around 29mW to 39.9mW. Finally, a 10~30 GHz integrated modules in advance is presented. The simulation result shows：frequency range from 10.38 to 29.49GHz, phase noise below -100dBc/Hz@1MHz, output power around -1.4 to -9.9dBm and power dissipation of around 68.72mW to 65.77mW (in total).
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Bai, Hong-bin, and 白宏彬. "A Design of Optical-Current-Controlled Oscillator Integrated Circuit." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/25311381628234849161.
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碩士國立臺灣科技大學
電子工程系
95
In this thesis, a study of optical-current-controlled oscillator is presented. The CMOS process provided by CIC (Chip Implement Center) is used. Here, we study three ICs: the transimpedance amplifier and the ring-type voltage-controlled oscillator and LC-type voltage-controlled oscillator. The first part deals with three types of transimpedance amplifiers. That are linear type, and RGC type, RGC linear type. The amplifiers we designed have 81.9dBΩ,49dBΩ and 74.7dBΩ gains, respectively. Their bandwidths are 257MHz,2.73GHz and 522MHz, respectively. In the second part, the designs of ring and LC voltage-controlled oscillators are presented. The frequency tuning range of ring VCO is 1.09GHz∼1.55GHz in our design. The frequency tuning range of LC VCO is 3.15GHz∼3.82GHz in our design. The range of controlled voltage is 0V∼3.3V. The measured result of frequency tuning range of our ring VCO is 676MHz∼906.3MHz. Finally, the combination of the above mentioned two building blocks can be applied to optical-intensity controlled electrical oscillators. It has potential applications to the radio over fiber in the monitoring of carrier frequency, or to the optical control systems.
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Chen, Nai-Ching, and 陳乃慶. "TE01 Gyrotron Backward-Wave Oscillator with Mode Selective Circuit." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/70691579161214911386.
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JARWAL, VIKASH. "AN INVESTIGATING ON CDBA BASED CONTINOUS TIME CIRCUITS." Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/15114.
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Over the year of time, the evolution of modern application of signal processing has
followed the trends of so called current mode, when signals, representing the information being
processed, are in the form of current. In contrast to the conventional mode which utilized electric
voltage, the current mode circuit can exhibit higher bandwidth, better signal linearity, higher
slew rate and lower power consumption. Since they are designed for lower voltage swings,
smaller supply voltage can be used. The current differencing buffered (CDBA) amplifier can
operate in both current mode and voltage mode, which provides flexibility.
This project discusses implementation of lossless grounded negative inductor circuits
(and application thereof), and oscillator circuit, using single CDBA. CDBA is designed using
AD844 IC.