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Rozanov, V. V., and E. A. Suvorova. "VLSI AND SYSTEM-ON-CHIP REDUNDANT COMPONENTS SYNTHESIS." Issues of radio electronics, no. 8 (August 20, 2018): 33–39. http://dx.doi.org/10.21778/2218-5453-2018-8-33-39.
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Redundancy - mostly used method to increase fault tolerance of the system. Fault tolerance in modern embedded systems is important feature due to accelerating aging and manufacturing defects, which diagnosis during the chip testing at fabric is impossible. In addition, different ways of system using may need different degree of fault tolerance. From Application Specified Integrated Circuit (ASIC) design point of view redundancy means area and power increasing. On early design stages, it is necessary to see the correlation between the components hardware description and its synthesized equivalent. The article considers several variants of synthesized redundant components that show the effect on area and power regarding to their architecture. The main goal of presented research is to describe RTL and Synthesis correlation.
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Zhou, Xiaofeng, Lu Liu, and Zhangming Zhu. "A Fault-Tolerant Deflection Routing for Network-on-Chip." Journal of Circuits, Systems and Computers 26, no. 03 (November 21, 2016): 1750037. http://dx.doi.org/10.1142/s0218126617500372.
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Network-on-Chip (NoC) has become a promising design methodology for the modern on-chip communication infrastructure of many-core system. To guarantee the reliability of traffic, effective fault-tolerant scheme is critical to NoC systems. In this paper, we propose a fault-tolerant deflection routing (FTDR) to address faults on links and router by redundancy technique. The proposed FTDR employs backup links and a redundant fault-tolerant unit (FTU) at router-level to sustain the traffic reliability of NoC. Experimental results show that the proposed FTDR yields an improvement of routing performance and fault-tolerant capability over the reported fault-tolerant routing schemes in average flit deflection rate, average packet latency, saturation throughput and reliability by up to 13.5%, 9.8%, 10.6% and 17.5%, respectively. The layout area and power consumption are increased merely 3.5% and 2.6%.
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Yu, Qiaoyan, Meilin Zhang, and Paul Ampadu. "Addressing network-on-chip router transient errors with inherent information redundancy." ACM Transactions on Embedded Computing Systems 12, no. 4 (June 2013): 1–21. http://dx.doi.org/10.1145/2485984.2485993.
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Li, Ran, Rui Ding, Zi Jian Min, and Hui Mei Yuan. "Design of Redundant Parallel Power Supply Based on Integrated DC/DC Modules." Applied Mechanics and Materials 229-231 (November 2012): 1568–71. http://dx.doi.org/10.4028/www.scientific.net/amm.229-231.1568.
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Taking into account the efficiency, cost-effectiveness and reliability of power supply, redundant parallel power supply controlled by microcontroller could be a good solution for us. This paper analyzes principles and traits of parallel current sharing structure. Then a design of redundancy parallel current sharing structure is introduced, which is based on integrated buck chip LM2678 and microcontroller MSP430. The design has good fault-tolerant ability, and its output voltage can be adjusted easily. The capability and feasibility of this design has been verified by the simulation and experiment.
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Cai, Bai-gen, Cheng-ming Jin, Lian-chuan Ma, Yuan Cao, and Hideo Nakamura. "Analysis on the application of on-chip redundancy in the safety-critical system." IEICE Electronics Express 11, no. 9 (2014): 20140153. http://dx.doi.org/10.1587/elex.11.20140153.
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Mohammed, Hala, Wameedh Flayyih, and Fakhrul Rokhani. "Tolerating Permanent Faults in the Input Port of the Network on Chip Router." Journal of Low Power Electronics and Applications 9, no. 1 (February 27, 2019): 11. http://dx.doi.org/10.3390/jlpea9010011.
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Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.
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UPADHYAYA, SHAMBHU J., and I.-SHYAN HWANG. "DESIGN OF A MULTI-LEVEL FAULT-TOLERANT MESH (MFTM) FOR HIGH RELIABILITY APPLICATIONS." International Journal of Reliability, Quality and Safety Engineering 02, no. 04 (December 1995): 419–29. http://dx.doi.org/10.1142/s0218539395000290.
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This paper presents a novel technique for the enhancement of operational reliability of processor arrays by a multi-level fault-tolerant design approach. The key idea of the design is based on the well known hierarchical design paradigm. The proposed fault-tolerant architecture uses a flexible reconfiguration of redundant nodes, thereby offering a better spare utilization than existing two-level redundancy schemes. A variable number of spares is provided at each level of redundancy which enables a flexible reconfiguration as well as area efficient layouts and better spare utilization. The spare nodes at each level can replace any of the failed primary nodes, not only at the same level but also those at the lower levels. The architecture can be adopted to increase the system reliability in Multi Chip Modules (MCMs). The main contributions of our work are the higher degree of fault tolerance, higher overall reliability, flexibility, and a better spare utilization.
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Nasimi, Fahimeh, Mohammad Reza Khayyambashi, and Naser Movahhedinia. "Redundancy cancellation of compressed measurements by QRS complex alignment." PLOS ONE 17, no. 2 (February 8, 2022): e0262219. http://dx.doi.org/10.1371/journal.pone.0262219.
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The demand for long-term continuous care has led healthcare experts to focus on development challenges. On-chip energy consumption as a key challenge can be addressed by data reduction techniques. In this paper, the pseudo periodic nature of ElectroCardioGram(ECG) signals has been used to completely remove redundancy from frames. Compressing aligned QRS complexes by Compressed Sensing (CS), result in highly redundant measurement vectors. By removing this redundancy, a high cluster of near zero samples is gained. The efficiency of the proposed algorithm is assessed using the standard MIT-BIH database. The results indicate that by aligning ECG frames, the proposed technique can achieve superior reconstruction quality compared to state-of-the-art techniques for all compression ratios. This study proves that by aligning ECG frames with a 0.05% unaligned frame rate(R-peak detection error), more compression could be gained for PRD > 5% when 5-bit non-uniform quantizer is used. Furthermore, analysis done on power consumption of the proposed technique, indicates that a very good recovery performance can be gained by only consuming 4.9μW more energy per frame compared to traditional CS.
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Sun, H., Q. Sun, S. Biereigel, R. Francisco, D. Gong, G. Huang, X. Huang, et al. "A radiation tolerant clock generator for the CMS endcap timing layer readout chip." Journal of Instrumentation 17, no. 03 (March 1, 2022): C03038. http://dx.doi.org/10.1088/1748-0221/17/03/c03038.
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Abstract We present the test results of a low jitter Phase Locked Loop (PLL) prototype chip for the CMS Endcap Timing Layer readout chip (ETROC). This chip is based on the improved version of a clock synthesis circuit named ljCDR from the Low Power Gigabit Transceiver (lpGBT) project. The ljCDR is tested in its PLL mode. An automatic frequency calibration (AFC) block with the Triple Modular Redundancy (TMR) register is developed for the LC-oscillator calibration. The chip was manufactured in a 65 nm CMOS process with 10 metal layers. The chip has been extensively tested, including Total Ionizing Dose (TID) testing up to 300 Mrad and Single Event Upset (SEU) testing with heavy ions possessing a Linear Energy Transfer (LET) from 1.3 to 62.5 MeV × cm2/mg.
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Fei, Ji You, Hua Li, and Bin Gao. "Based on the Single Chip Microcomputer Atmega168 Robot Control System Design." Applied Mechanics and Materials 341-342 (July 2013): 700–703. http://dx.doi.org/10.4028/www.scientific.net/amm.341-342.700.
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based on the single chip microcomputer atmega168 robot control system design This paper introduces using micro controller, many sensors, such as ultrasonic distance measuring sensor, infrared range sensor, infrared obstacle avoidance sensor, and also using motor driving module and dc motor design a robot which can operate independently, The robot can detect its own attitude, obstacles, competition venues edge automatically, then according to signal which the sensor feedback to micro controller controlling the motor produce pushing or avoid action. In the design of the robot, we using the sensor redundancy design positioning obstacles in front of robot, we take full advantage of the proximity detector features in order to make the robot highly efficient and stable operation. The robot in the experiment operating in good condition, and it has reference significance for robot design.
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Hernandez Herrera, H. D., M. Bregant, B. Sanchez, and W. Van Noije. "Onchip digital calibrated 2 mW 12-bit 25 MS/s SAR ADC with reduced input capacitance." Journal of Instrumentation 17, no. 04 (April 1, 2022): C04013. http://dx.doi.org/10.1088/1748-0221/17/04/c04013.
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Abstract We present a 12-bits asynchronous SAR ADC with a low complexity digital on-chip calibration and just 2 pF of total array capacitance. The ADC architecture utilizes a redundant weighting switching of 2 fF MOM capacitors consuming 14 clock-cycles to complete the conversion. Taking advantage of redundancy, the weights of the MSB capacitors are estimated using the LSB array, thus it is possible to digitally compensate for the mismatch non-linearity directly over the ADC output. The circuit consumes 2 mW at 25 MS/s on a core area of 300 μm × 500 μm in 180 nm CMOS technology. ENOB improvements of 0.85 bits were post-layout simulated after calibration. Sample characterization is ongoing.
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Zhou, Zi Guan, Xiao Shan Pan, Shu Gang Yin, Wei Li Ren, Sheng Bo Sun, and Yang Wang. "Research on Variable-Frequency-Point Variable-Bandwidth Wireless Broadband Radio Frequency Chip and its Application in the Smart Grid." Advanced Materials Research 347-353 (October 2011): 3107–15. http://dx.doi.org/10.4028/www.scientific.net/amr.347-353.3107.
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With the development of the smart grid, residential electricity services have a higher bandwidth and frequency requirement to the power system communication , the existing power 230MHz narrow-band data transmission communication has been unable to meet the needs of the two-way interaction between the users and the smart grid. In terms of current communication technology in the power system, this paper introduces a wireless broadband radio frequency chip ,which supports 100MHz to 1.2GHz frequency range, and 5KHz to 2MHz tunable bandwidth.With the chip embedded in intelligent electricity interactive terminals, distribution monitoring terminals and other devices, it can achieve flexible and intelligent electricity services. This paper describes the architecture of the RF chip,and gives key technology solutions such as broadband matching, adjustable IF bandwidth of the channel, sums up the advantages of the chip,presents the application in the smart grid. The analysis finds that the chip has a variety of charateristics such as high integration, good redundancy, versatility, flexibility and so on, and can satisfy the growing application needs of power speacial network,and has an extremely promising market .
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Shafique, Muhammad Akmal, Naveed Khan Baloch, Muhammad Iram Baig, Fawad Hussain, Yousaf Bin Zikria, and Sung Won Kim. "NoCGuard: A Reliable Network-on-Chip Router Architecture." Electronics 9, no. 2 (February 17, 2020): 342. http://dx.doi.org/10.3390/electronics9020342.
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Aggressive scaling in deep nanometer technology enables chip multiprocessor design facilitated by the communication-centric architecture provided by Network-on-Chip (NoC). At the same time, it brings considerable challenges in reliability because a fault in the network architecture severely impacts the performance of a system. To deal with these reliability challenges, this research proposed NoCGuard, a reconfigurable architecture designed to tolerate multiple permanent faults in each pipeline stage of the generic router. NoCGuard router architecture uses four highly reliable and low-cost fault-tolerant strategies. We exploited resource borrowing and double routing strategy for the routing computation stage, default winner strategy for the virtual channel allocation stage, runtime arbiter selection and default winner strategy for the switch allocation stage and multiple secondary bypass paths strategy for the crossbar stage. Unlike existing reliable router architectures, our architecture features less redundancy, more fault tolerance, and high reliability. Reliability comparison using Mean Time to Failure (MTTF) metric shows 5.53-time improvement in a lifetime and using Silicon Protection Factor (SPF), 22-time improvement, which is better than state-of-the-art reliable router architectures. Synthesis results using 15 nm and 45 nm technology library show that additional circuitry incurs an area overhead of 28.7% and 28% respectively. Latency analysis using synthetic, PARSEC and SPLASH-2 traffic shows minor increase in performance by 3.41%, 12% and 15% respectively while providing high reliability.
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Najeeb, K., Vishal Gupta, V. Kamakoti, and Madhu Mutyam. "Temporal Redundancy Based Encoding Technique for Peak Power and Delay Reduction of On-Chip Buses." Journal of Low Power Electronics 2, no. 3 (December 1, 2006): 425–36. http://dx.doi.org/10.1166/jolpe.2006.099.
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Arya, Namita, and Amit Prakash Singh. "Comparative Analysis of Time and Physical Redundancy Techniques for Fault Detection." Indonesian Journal of Electrical Engineering and Computer Science 6, no. 1 (April 1, 2017): 66. http://dx.doi.org/10.11591/ijeecs.v6.i1.pp66-71.
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<p>The integration level in today’s world is continuously increasing in VLSI chips. VLSI circuit verification is a major challenge in these days. Integration capacity of VLSI circuits mimics the testing complexity of circuits. There is a significant chunk of the testing cost with respect to the whole fabrication prices. Hence it is important to cut down the verification cost. Time required during testing is a main factor for the cost of a chip. This time is directly proportional to the number of testing in the circuitry. So the test set should be very small. There is one way to generate a small test set is to compact a large test set parameters. The main drawback of the compaction results on the quality of the original test set. This aspect of compaction has motivated the work present here with some methods of fault detection and avoidance techniques via redundancy logic as Time redundancy and physical redundancy.</p>
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Rashid, Muhammad, Naveed Khan Baloch, Muhammad Akmal Shafique, Fawad Hussain, Shahroon Saleem, Yousaf Bin Zikria, and Heejung Yu. "Fault-Tolerant Network-On-Chip Router Architecture Design for Heterogeneous Computing Systems in the Context of Internet of Things." Sensors 20, no. 18 (September 18, 2020): 5355. http://dx.doi.org/10.3390/s20185355.
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Network-on-chip (NoC) architectures have become a popular communication platform for heterogeneous computing systems owing to their scalability and high performance. Aggressive technology scaling makes these architectures prone to both permanent and transient faults. This study focuses on the tolerance of a NoC router to permanent faults. A permanent fault in a NoC router severely impacts the performance of the entire network. Thus, it is necessary to incorporate component-level protection techniques in a router. In the proposed scheme, the input port utilizes a bypass path, virtual channel (VC) queuing, and VC closing strategies. Moreover, the routing computation stage utilizes spatial redundancy and double routing strategies, and the VC allocation stage utilizes spatial redundancy. The switch allocation stage utilizes run-time arbiter selection. The crossbar stage utilizes a triple bypass bus. The proposed router is highly fault-tolerant compared with the existing state-of-the-art fault-tolerant routers. The reliability of the proposed router is 7.98 times higher than that of the unprotected baseline router in terms of the mean-time-to-failure metric. The silicon protection factor metric is used to calculate the protection ability of the proposed router. Consequently, it is confirmed that the proposed router has a greater protection ability than the conventional fault-tolerant routers.
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Gonzalez, Carlos J., Diego Machado, Rafael G. Vaz, Alexis C. Vilas Bôas, Odair L. Gonçalez, Helmut Puchner, Nemitala Added, et al. "Testing a Fault Tolerant Mixed-Signal Design Under TID and Heavy Ions." Journal of Integrated Circuits and Systems 16, no. 3 (December 31, 2021): 1–11. http://dx.doi.org/10.29292/jics.v16i3.567.
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This work presents results of three distinct radiation tests performed upon a fault-tolerant data acquisition system comprising a design diversity redundancy technique. The first and second experiments are Total Ionizing Dose (TID) essays, comprising gamma and X-ray irradiations. The last experiment considers single event effects, in which two heavy ion irradiation campaigns are carried out. The case study system comprises three analog-to-digital converters and two software-based voters, besides additional software and hardware resources used for controlling, monitoring and memory management. The applied Diversity Triple Modular Redundancy (DTMR) technique, comprises different levels of diversity (temporal and architectural). The circuit was designed in a programmable System-on-Chip (PSoC), fabricated in a 130nm CMOS technology process. Results show that the technique may increase the lifetime of the system under TID if comparing with a non-redundant implementation. Considering the heavy ions experiments the system was proved effective to tolerate 100% of the observed errors originated in the converters, while errors in the processing unit present a higher criticality. Critical errors occurring in one of the voters were also observed. A second heavy-ion campaign was then carried out to investigate the voters reliability, comparing the dynamic cross-section of three different software-based voter schemes implemented in the considered PSoC.
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Park, Daejin. "Low-Power Code Memory Integrity Verification Using Background Cyclic Redundancy Check Calculator Based on Binary Code Inversion Method." Journal of Circuits, Systems and Computers 25, no. 07 (April 22, 2016): 1650068. http://dx.doi.org/10.1142/s0218126616500687.
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The integrity verification of on-chip flash memory data as code memory is becoming important in microcontroller-based applications such as automotive systems. On-the-fly memory fail-detection requires a fast detection method in the seamless background mode without any interruption of CPU operation and low-power flash access hardware to provide safety-conscious execution of the user-programmed firmware during system operations. In this paper, newly-designed read-path architecture based on the binary inversion techniques is proposed for on-chip flash-embedded microcontrollers. The proposed binary inversion method also enables fail-safe, low-power memory access with zero hardware overhead by embedding the scramble flags on the cyclic redundancy check (CRC) protection code. Time-multiplexed CRC calculation for bit-inversion binary code is automatically executed with the silent background mode during CPU idle time without any CPU wait cost. The implementation result shows that the de-inversion procedure could be achieved with just an additional 1,024 bits CRC data in the case of 64 sectors for 4 KB flash memory by reducing 75% of the area of the previous work. The code memory integrity verification time in the seamless background mode is about 30% of the conventional foreground method. The total average current during the code execution for DhrystoneTM benchmark uses just 15% of the basement.
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Omar, Hamza, and Omer Khan. "PRISM." ACM Transactions on Architecture and Code Optimization 18, no. 3 (June 2021): 1–25. http://dx.doi.org/10.1145/3450523.
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Multicores increasingly deploy safety-critical parallel applications that demand resiliency against soft-errors to satisfy the safety standards. However, protection against these errors is challenging due to complex communication and data access protocols that aggressively share on-chip hardware resources. Research has explored various temporal and spatial redundancy-based resiliency schemes that provide multicores with high soft-error coverage. However, redundant execution incurs performance overheads due to interference effects induced by aggressive resource sharing. Moreover, these schemes require intrusive hardware modifications and fall short in providing efficient system availability guarantees. This article proposes PRISM, a resilient multicore architecture that incorporates strong hardware isolation to form redundant clusters of cores, ensuring a non-interference-based redundant execution environment. A soft error in one cluster does not effect the execution of the other cluster, resulting in high system availability. Implementing strong isolation for shared hardware resources, such as queues, caches, and networks requires logic for partitioning. However, it is less intrusive as complex hardware modifications to protocols, such as hardware cache coherence, are avoided. The PRISM approach is prototyped on a real Tilera Tile-Gx72 processor that enables primitives to implement the proposed cluster-level hardware resource isolation. The evaluation shows performance benefits from avoiding destructive hardware interference effects with redundant execution, while delivering superior system availability.
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Das, Abhishek, and Nur A. Touba. "A Single Error Correcting Code with One-Step Group Partitioned Decoding Based on Shared Majority-Vote." Electronics 9, no. 5 (April 26, 2020): 709. http://dx.doi.org/10.3390/electronics9050709.
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Technology scaling has led to an increase in density and capacity of on-chip caches. This has enabled higher throughput by enabling more low latency memory transfers. With the reduction in size of SRAMs and development of emerging technologies, e.g., STT-MRAM, for on-chip cache memories, reliability of such memories becomes a major concern. Traditional error correcting codes, e.g., Hamming codes and orthogonal Latin square codes, either suffer from high decoding latency, which leads to lower overall throughput, or high memory overhead. In this paper, a new single error correcting code based on a shared majority voting logic is presented. The proposed codes trade off decoding latency in order to improve the memory overhead posed by orthogonal Latin square codes. A latency optimization technique is also proposed which lowers the decoding latency by incurring a slight memory overhead. It is shown that the proposed codes achieve better redundancy compared to orthogonal Latin square codes. The proposed codes are also shown to achieve lower decoding latency compared to Hamming codes. Thus, the proposed codes achieve a balanced trade-off between memory overhead and decoding latency, which makes them highly suitable for on-chip cache memories which have stringent throughput and memory overhead constraints.
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Melo, Douglas R., Cesar A. Zeferino, Luigi Dilillo, and Eduardo A. Bezerra. "Maximizing the Inner Resilience of a Network-on-Chip through Router Controllers Design." Sensors 19, no. 24 (December 9, 2019): 5416. http://dx.doi.org/10.3390/s19245416.
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Reducing component size and increasing the operating frequency of integrated circuits makes the Systems-on-Chip (SoCs) more susceptible to faults. Faults can cause errors, and errors can be propagated and lead to a system failure. SoCs employing many cores rely on a Network-on-Chip (NoC) as the interconnect architecture. In this context, this study explores alternatives to implement the flow regulation, routing, and arbitration controllers of an NoC router aiming at minimizing error propagation. For this purpose, a router with Finite-State Machine (FSM)-based controllers was developed targeting low use of logical resources and design flexibility for implementation in FPGA devices. We elaborated and compared the synthesis and simulation results of architectures that vary their controllers on Moore and Mealy FSMs, as well as the Triple Modular Redundancy (TMR) hardening application. Experimental results showed that the routing controller was the most critical one and that migrating a Moore to a Mealy controller offered a lower error propagation rate and higher performance than the application of TMR. We intended to use the proposed router architecture to integrate cores in a fault-tolerant NoC-based system for data processing in harsh environments, such as in space applications.
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Nguyen, Hai T., Giao N. Pham, Anh N. Bui, Binh A. Nguyen, Ngoc T. Le, and Hanh T. Pham. "Linear Feedback Shift Register and its Applications in Digital System Design." International Journal of Emerging Technology and Advanced Engineering 11, no. 11 (November 13, 2021): 204–8. http://dx.doi.org/10.46338/ijetae1121_24.
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In digital system design, the Linear Feedback Shift Register (LFSR) is the queen of logic functions, and the design engineers can use LFSR in both hardware (HW) or software (SW) implementation. In this paper, LFSR will be discussed in its HW implementation via Hardware description language. In addition, the application of LFSR in of pseudorandom number generator (PRNG), direct sequence spread spectrum (DSSS), cyclic redundancy check (CRC) is also given. Keywords-- Digital system design, System on chip, ASIC digital design, Linear feedback shift register
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Kurata, Kazuhiko, Luca Giorgi, Fabio Cavaliere, Liam O’Faolain, Sebastian A. Schulz, Kohei Nishiyama, Yasuhiko Hagihara, et al. "Silicon Photonic Micro-Transceivers for Beyond 5G Environments." Applied Sciences 11, no. 22 (November 19, 2021): 10955. http://dx.doi.org/10.3390/app112210955.
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Here, we report on the design and performance of a silicon photonic micro-transceiver required to operate in 5G and 6G environments at high ambient temperatures above 105 °C. The four-channel “IOCore” micro-transceiver incorporates a 1310 nm quantum dot laser system and operates at a data rate of 25 Gbps and higher. The 5 × 5 mm micro-transceiver chip benefits from a multimode coupling interface for low-cost assembly and robust connectivity at high temperatures as well as an optical redundancy scheme, which increases reliability by over an order of magnitude.
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KANEKAWA, Nobuyasu. "Potential of Fault-Detection Coverage by means of On-Chip Redundancy - IEC61508: Are There Royal Roads to SIL 4?" IEICE Transactions on Information and Systems E96.D, no. 9 (2013): 1907–13. http://dx.doi.org/10.1587/transinf.e96.d.1907.
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Li, Shuai, Kuangyuan Sun, Yukui Luo, Nandakishor Yadav, and Ken Choi. "Novel CNN-Based AP2D-Net Accelerator: An Area and Power Efficient Solution for Real-Time Applications on Mobile FPGA." Electronics 9, no. 5 (May 18, 2020): 832. http://dx.doi.org/10.3390/electronics9050832.
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Standard convolutional neural networks (CNNs) have large amounts of data redundancy, and the same accuracy can be obtained even in lower bit weights instead of floating-point representation. Most CNNs have to be developed and executed on high-end GPU-based workstations, for which it is hard to transplant the existing implementations onto portable edge FPGAs because of the limitation of on-chip block memory storage size and battery capacity. In this paper, we present adaptive pointwise convolution and 2D convolution joint network (AP2D-Net), an ultra-low power and relatively high throughput system combined with dynamic precision weights and activation. Our system has high performance, and we make a trade-off between accuracy and power efficiency by adopting unmanned aerial vehicle (UAV) object detection scenarios. We evaluate our system on the Zynq UltraScale+ MPSoC Ultra96 mobile FPGA platform. The target board can get the real-time speed of 30 fps under 5.6 W, and the FPGA on-chip power is only 0.6 W. The power efficiency of our system is 2.8× better than the best system design on a Jetson TX2 GPU and 1.9× better than the design on a PYNQ-Z1 SoC FPGA.
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Paul, Priyanka, Sanjay Joshi, Ran Tian, Rubens Diogo Junior, Manohar Chakrabarti, and Sharyn E. Perry. "The MADS-domain factor AGAMOUS-Like18 promotes somatic embryogenesis." Plant Physiology 188, no. 3 (November 25, 2021): 1617–31. http://dx.doi.org/10.1093/plphys/kiab553.
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Abstract AGAMOUS-Like 18 (AGL18) is a MADS domain transcription factor (TF) that is structurally related to AGL15. Here we show that, like AGL15, AGL18 can promote somatic embryogenesis (SE) when ectopically expressed in Arabidopsis (Arabidopsis thaliana). Based on loss-of-function mutants, AGL15 and AGL18 have redundant functions in developmental processes such as SE. To understand the nature of this redundancy, we undertook a number of studies to look at the interaction between these factors. We studied the genome-wide direct targets of AGL18 to characterize its roles at the molecular level using chromatin immunoprecipitation (ChIP)-SEQ combined with RNA-SEQ. The results demonstrated that AGL18 binds to thousands of sites in the genome. Comparison of ChIP-SEQ data for AGL15 and AGL18 revealed substantial numbers of genes bound by both AGL15 and AGL18, but there were also differences. Gene ontology analysis revealed that target genes were enriched for seed, embryo, and reproductive development as well as hormone and stress responses. The results also demonstrated that AGL15 and AGL18 interact in a complex regulatory loop, where AGL15 inhibited transcript accumulation of AGL18, while AGL18 increased AGL15 transcript accumulation. Co-immunoprecipitation revealed an interaction between AGL18 and AGL15 in somatic embryo tissue. The binding and expression analyses revealed a complex crosstalk and interactions among embryo TFs and their target genes. In addition, our study also revealed that phosphorylation of AGL18 and AGL15 was crucial for the promotion of SE.
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Youplao, Phichai, Nithiroth Pornsuwancharoen, and Preecha P. Yupapin. "High capacity terahertz frequency combs generated by small scale optical mesh network." Journal of Nonlinear Optical Physics & Materials 23, no. 01 (March 2014): 1450003. http://dx.doi.org/10.1142/s0218863514500039.
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A novel design of mesh ring resonator system is proposed and simulated to obtain the multi frequency comb bands, in which the frequency band less than 10 GHz (about 0.084 nm) of comb lines spacing with commercialized ring parameters is achieved. The proposed system is used to enhance the capacity of optical frequency comb for redundancy networks against the network element failures and to increase the survivability of the communication systems. The dependence of the mesh ring transmission characteristics with coupling coefficients of directional couplers is analyzed and studied. In application, such a system can be employed as an on-chip optical device for redundancy networks against the network element failures and to increase the survivability of the communication systems. The potential for improving the reliability and availability of the optical networks is discussed. Moreover, the proposed system can also be employed as multi sensing devices, where the microscale, for instance, as an atom/molecule force sensor can be measured by the shifted parameters of the Vernier filters.
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Alnatheer, Suleman, and Mohammed Altaf Ahmed. "Optimal Method for Test and Repair Memories Using Redundancy Mechanism for SoC." Micromachines 12, no. 7 (July 10, 2021): 811. http://dx.doi.org/10.3390/mi12070811.
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The current system-on-chip (SoC)-based devices uses embedded memories of enormous size. Most of these systems’ area is dense with memories and promotes different types of faults appearance in memory. The memory faults become a severe issue when they affect the yield of the product. A memory-test and -repair scheme is an attractive solution to tackle this kind of problem. The built-in self-repair (BISR) scheme is a prominent method to handle this issue. The BISR scheme is widely used to repair the defective memories for an SoC-based system. It uses a built-in redundancy analysis (BIRA) circuit to allocate the redundancy when defects appear in the memory. The data are accessed from the redundancy allocation when the faulty memory is operative. Thus, this BIRA scheme affects the area overhead for the BISR circuit when it integrates to the SoC. The spare row and spare column–based BISR method is proposed to receive the optimal repair rate with a low area overhead. It tests the memories for almost all the fault types and repairs the memory by using spare rows and columns. The proposed BISR block’s performance was measured for the optimal repair rate and the area overhead. The area overhead, timing, and repair rate were compared with the other approaches. Furthermore, the study noticed that the repair rate and area overhead would increase by increasing the spare-row/column allocation.
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Ji, Ling. "Software Anti-Interference Design of SCM Control System." Applied Mechanics and Materials 644-650 (September 2014): 667–69. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.667.
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SCM control system requires high reliability and security, the entire control system to operate safely and reliably only when a strong anti-interference capability. In switch input and output, the use of the instruction redundancy methods to achieve the switch signal input and output filtering; in data collection, based on the hardware anti-interference taken arithmetic average filtering method, in order to strengthen its anti-jamming capability. In the system status monitoring, watchdog feature is enabled with the MSP430F449 microcontroller, when the watchdog timer overflows, the system automatically reset, the experiment proved that this method can save hardware resources, flexible design, low cost, single-chip control, it can guarantee the smooth operation of the system.
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Hosseini, Fateme S., Fanruo Meng, Chengmo Yang, Wujie Wen, and Rosario Cammarota. "Tolerating Defects in Low-Power Neural Network Accelerators Via Retraining-Free Weight Approximation." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–21. http://dx.doi.org/10.1145/3477016.
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Hardware accelerators are essential to the accommodation of ever-increasing Deep Neural Network (DNN) workloads on the resource-constrained embedded devices. While accelerators facilitate fast and energy-efficient DNN operations, their accuracy is threatened by faults in their on-chip and off-chip memories, where millions of DNN weights are held. The use of emerging Non-Volatile Memories (NVM) further exposes DNN accelerators to a non-negligible rate of permanent defects due to immature fabrication, limited endurance, and aging. To tolerate defects in NVM-based DNN accelerators, previous work either requires extra redundancy in hardware or performs defect-aware retraining, imposing significant overhead. In comparison, this paper proposes a set of algorithms that exploit the flexibility in setting the fault-free bits in weight memory to effectively approximate weight values, so as to mitigate defect-induced accuracy drop. These algorithms can be applied as a one-step solution when loading the weights to embedded devices. They only require trivial hardware support and impose negligible run-time overhead. Experiments on popular DNN models show that the proposed techniques successfully boost inference accuracy even in the face of elevated defect rates in the weight memory.
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Huang, Feng Ying, Jun Wang, Yu Sen Xu, and Ji Wei Huang. "A Novel Design of PIE Decoding with Multiple CRC Circuit for RFID Tag." Advanced Materials Research 816-817 (September 2013): 957–61. http://dx.doi.org/10.4028/www.scientific.net/amr.816-817.957.
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This paper proposes a new synchronized serial-parallel CRC(Cycle Redundancy Check) with PIE(Pulse Interval Encoding) decoding circuit for the UHF(Ultra-High Frequency) RFID(Radio Frequency Identification), which is based on the ISO/IEC 18000-6C standards protocol. The parallel algorithm of CRC circuit is derived, and the serial or parallel CRC circuit on RFID tag chip is evaluated in this paper. Finally, the designed circuit is simulated and analyzed on the FPGA platform. Simulation results show that the proposed circuit meets the communication requirement of the protocol and addresses the problem of low data processing rate of conventional serial CRC circuit, as well as implements 1 to 8 degree of parallelism of the parallel CRC circuit for UHF RFID.
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van Roermund, Arthur H. M. "Shifting the Frontiers of Analog and Mixed-Signal Electronics." Advances in Electronics 2014 (December 16, 2014): 1–16. http://dx.doi.org/10.1155/2014/590970.
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Nowadays, analog and mixed-signal (AMS) IC designs, mainly found in the frontends of large ICs, are highly dedicated, complex, and costly. They form a bottleneck in the communication with the outside world, determine an upper bound in quality, yield, and flexibility for the IC, and require a significant part of the power dissipation. Operating very close to physical limits, serious boundaries are faced. This paper relates, from a high-level point of view, these boundaries to the Shannon channel capacity and shows how the AMS circuitry forms a matching link in transforming the external analog signals, optimized for the communication medium, to the optimal on-chip signal representation, the digital one, for the IC medium. The signals in the AMS part itself are consequently not optimally matched to the IC medium. To further shift the frontiers of AMS design, a matching-driven design approach is crucial for AMS. Four levels will be addressed: technology-driven, states-driven, redundancy-driven, and nature-driven design. This is done based on an analysis of the various classes of AMS signals and their specific properties, seen from the angle of redundancy. This generic, but abstract way of looking at the design process will be substantiated with many specific examples.
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Cheng, Xingguo, and Chaomeng Chen. "Vehicle Detection System with Statistical Functions Based on 3-Axis Anisotropic Magnetoresistive Using Wireless Communication Technology." Journal of Computational and Theoretical Nanoscience 17, no. 7 (July 1, 2020): 2876–81. http://dx.doi.org/10.1166/jctn.2020.6749.
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In terms of current issues that the sensor’s output signal drifts along with the surrounding strong magnetic field by using the single or dual-axis analog anisotropic magnetoresistive (AMR) sensor in the traffic flow detection, a traffic flow detection system based on ZigBee wireless sensor network is developed and a novel approach by exercising the new digital three-axis AMR sensor to detect the traffic flow is proposed to solve these issues as mentioned above. Using Single Chip Microcomputer (SCM) control technique and utilizing wireless transmitting, an effective algorithm is designed. The algorithm makes it possible to classify vehicle, calculate vehicle speed and count vehicle, in the meantime it provides a reliable and efficient method to collect intelligent transportation data. Even more important, the algorithm has a statistical functions based on MATLAB. The experimental result shows that the novel method has much better measurement accuracy, reliability and redundancy than single or dual-axis method.
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Zhange, Zhi, Liwei Wang, Ruiying Liu, and Jinghang Fan. "Development of Cloud Computing Platform Based on Neural Network." Mathematical Problems in Engineering 2022 (March 7, 2022): 1–9. http://dx.doi.org/10.1155/2022/1513081.
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Aiming at the problems of small data storage, small platform throughput, and high energy consumption in the development of existing cloud computing platforms, this paper develops a cloud computing platform based on neural networks. In the design of the platform, firstly, the functions of the cloud computing platform are determined. Based on the function design, the hardware and software of the cloud computing platform are designed. In the hardware design, the topology of cloud computing platform, data acquisition module, single-chip microcomputer, node deployment, and other types of functional hardware are designed. In the software design, the neural network is mainly used to remove the redundancy of data stored in a cloud computing platform, design the data processing flow of cloud computing platform, and complete the development of cloud computing platform based on neural network. The experimental results show that the cloud computing platform based on the neural network designed in this paper runs faster, the throughput of platform data has been significantly improved, and the operating energy consumption of the platform is low.
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Mestice, Marco, Bruno Neri, Gabriele Ciarpi, and Sergio Saponara. "Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL." Sensors 20, no. 14 (July 19, 2020): 4013. http://dx.doi.org/10.3390/s20144013.
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The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board satellite communications. Taking as a starting point a rad-hard 6.25 GHz Voltage Controlled Oscillator in 65 nm technology, this work presents the design of the key blocks for an integrated PLL: a Triple Modular Redundancy Phase/Frequency Detector, a Charge Pump, and a passive Loop Filter. The modeling activities carried out in an Advanced Design System have proven that the proposed PLL can be completely integrated on-chip, with a Loop Filter area consumption of only 6000 µm2 (considering the 65 nm technology). The design of active circuits has been carried out at the transistor level in a Cadence Virtuoso environment, implementing both system and layout rad-hard techniques, and different solutions are discussed in this paper. As a result, a compact (0.09 mm2), low power (10.24 mW), dead zone free and rad-hard PLL is obtained with a Phase Noise below −80 dBc/Hz @ 1 MHz. A preliminary block view and floor plan of the test chip is also proposed.
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Nourmandi-Pour, Reza. "A Programmable IEEE 1500-Compliant Wrapper for Testing of Word-Oriented Memory Cores." Journal of Circuits, Systems and Computers 27, no. 09 (April 26, 2018): 1850134. http://dx.doi.org/10.1142/s0218126618501347.
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In today’s embedded technology, memories are the universal components. With the onset of the deep-submicron VLSI technology, the density and capacity of the memory are growing. However, providing a cost-effective test solution for these on-chip memories is becoming a challenging task. As memory and other processing cores have been embedded deeply in system chips, the IEEE std 1500 has been suggested to facilitate the test of these core types. Whereas up to now this standard has not presented a definite solution for testing of memory cores, in this paper, we proposed a programmable IEEE 1500-compliant wrapper for applying several Mach algorithms on word-oriented memory cores to reach the desired fault coverage. The proposed wrapper is without finite-state-machine controller, and as a result, the complexity of wrapper circuitry is low and hardware redundancy is acceptable as well.
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Perepelitsyn, A., O. Illiashenko, V. Duzhyi, and V. Kharchenko. "Application of the FPGA Technology for the Development of Multi-Version Safety-Critical NPP Instrumentation and Control Systems." Nuclear and Radiation Safety, no. 2(86) (June 12, 2020): 52–61. http://dx.doi.org/10.32918/nrs.2020.2(86).07.
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The paper overviews the requirements of international standards on application of diversity in safety-critical NPP instrumentation and control (I&C) systems. The NUREG7007 classification of version redundancy and the method for diversity assessment are described. The paper presents results from the analysis of instruments and design tools for FPGA-based embedded digital devices from leading manufacturers of programmable logics using the Xilinx and Altera (Intel) chips, which are used in NPP I&C systems, as an example. The most effective integrated development environments are analyzed and the results of comparing the functions and capabilities of using the Xilinx and Altera (Intel) tools are described. The analysis of single failures and fault tolerance using diversity in chip designs based on the SRAM technology is presented. The results from assessment of diversity metrics for RadICS platform-based multi-version I&C systems are discussed.
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Murali, Srinivasan, David Atienza, Luca Benini, and Giovanni De Micheli. "A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees." VLSI Design 2007 (April 5, 2007): 1–11. http://dx.doi.org/10.1155/2007/37627.
Full textAbstract:
Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today's NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.
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Park, John. "Path Finding for Multiple Platforms." Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT) 2014, DPC (January 1, 2014): 002036–56. http://dx.doi.org/10.4071/2014dpc-tha24.
Full textAbstract:
With the increasing complexity of today's SOCs and the growth in multi-die packaging, companies are recognizing the value of cross-domain collaboration between the IC, package substrate and PCB design groups. High pin count devices coupled with cost sensitivity drive engineers to reconsider how they plan, optimize and automate the I/O placement on their chips, while targeting multiple packaging variables, which have direct impact on how the PCB will be designed. In some instances, informal design flows based on multiple EDA design tools have been pieced together. This is a step in the right direction; however, without a central repository for the data or accurate device modeling and rule-based optimization, design intent is often misinterpreted or lost and redundancy is often introduced into the flow. This presentation outlines a co-design methodology that allows design teams the ability to easily plan and optimize I/O and connectivity from a chip(s), through multiple packaging variables while targeting multiple different system platforms (PCBs). Using this planning, optimization and design methodology, engineering teams for the IC, the Package and the PCB would drive rule-based I/O level optimization and perform ball-out studies from their respective domains, all while visualizing the impact across the complete system. Key features and advantages of this methodology are:Multi-mode connectivity management for cross-domain pin/signal mapping/shortingUser definable rules for I/O and ball-out assignmentsRobust support for feasibility analysis and rapid prototypingFully automated library developmentDirect integration to multi-mode physical layout toolSeamless interface to 2D and 3D EM analysis enginesTight interface with CFD based thermal analysis solutionEDA vendor neutral flow The result of implementing this methodology will be a chip(s) that is fully optimized for its package(s) and PCB(s). This solution drives down the cost of the package and PCB through layer reduction and tighter control of the design process without impacting the cost of the chip.
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Y. N., Sharath Kumar, and Dinesha P. "TFI-FTS: An efficient transient fault injection and fault-tolerant system for asynchronous circuits on FPGA platform." International Journal of Electrical and Computer Engineering (IJECE) 11, no. 3 (June 1, 2021): 2704. http://dx.doi.org/10.11591/ijece.v11i3.pp2704-2710.
Full textAbstract:
Designing VLSI digital circuits is challenging tasks because of testing the circuits concerning design time. The reliability and productivity of digital integrated circuits are primarily affected by the defects in the manufacturing process or systems. If the defects are more in the systems, which leads the fault in the systems. The fault tolerant systems are necessary to overcome the faults in the VLSI digital circuits. In this research article, an asynchronous circuits based an effective transient fault injection (TFI) and fault tolerant system (FTS) are modelled. The TFI system generates the faults based on BMA based LFSR with faulty logic insertion and one hot encoded register. The BMA based LFSR reduces the hardware complexity with less power consumption on-chip than standard LFSR method. The FTS uses triple mode redundancy (TMR) based majority voter logic (MVL) to tolerant the faults for asynchronous circuits. The benchmarked 74X-series circuits are considered as an asynchronous circuit for TMR logic. The TFI-FTS module is modeled using Verilog-HDL on Xilinx-ISE and synthesized on hardware platform. The Performance parameters are tabulated for TFI-FTS based asynchronous circuits. The performance of TFI-FTS Module is analyzed with 100% fault coverage. The fault coverage is validated using functional simulation of each asynchronous circuit with fault injection in TFI-FTS Module.
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Wang, Hongsheng, Shweta Jain, Peng Li, Jian-Xin Lin, Jangsuk Oh, Chenfeng Qi, Yuanyuan Gao, et al. "Transcription factors IRF8 and PU.1 are required for follicular B cell development and BCL6-driven germinal center responses." Proceedings of the National Academy of Sciences 116, no. 19 (April 18, 2019): 9511–20. http://dx.doi.org/10.1073/pnas.1901258116.
Full textAbstract:
The IRF and Ets families of transcription factors regulate the expression of a range of genes involved in immune cell development and function. However, the understanding of the molecular mechanisms of each family member has been limited due to their redundancy and broad effects on multiple lineages of cells. Here, we report that double deletion of floxed Irf8 and Spi1 (encoding PU.1) by Mb1-Cre (designated DKO mice) in the B cell lineage resulted in severe defects in the development of follicular and germinal center (GC) B cells. Class-switch recombination and antibody affinity maturation were also compromised in DKO mice. RNA-seq (sequencing) and ChIP-seq analyses revealed distinct IRF8 and PU.1 target genes in follicular and activated B cells. DKO B cells had diminished expression of target genes vital for maintaining follicular B cell identity and GC development. Moreover, our findings reveal that expression of B-cell lymphoma protein 6 (BCL6), which is critical for development of germinal center B cells, is dependent on IRF8 and PU.1 in vivo, providing a mechanism for the critical role for IRF8 and PU.1 in the development of GC B cells.
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Sari, Aitzan, and Mihalis Psarakis. "A Flexible Fault Injection Platform for the Analysis of the Symptoms of Soft Errors in FPGA Soft Processors." Journal of Circuits, Systems and Computers 26, no. 08 (April 11, 2017): 1740009. http://dx.doi.org/10.1142/s0218126617400096.
Full textAbstract:
Due to the high vulnerability of SRAM-based FPGAs in single-event upsets (SEUs), effective fault tolerant soft processor architectures must be considered when we use FPGAs to build embedded systems for critical applications. In the past, the detection of symptoms of soft errors in the behavior of microprocessors has been used for the implementation of low-budget error detection techniques, instead of costly hardware redundancy techniques. To enable the development of such low-cost error detection techniques for FPGA soft processors, we propose an in-depth analysis of the symptoms of SEUs in the FPGA configuration memory. To this end, we present a flexible fault injection platform based on an open-source CAD framework (RapidSmith) for the soft error sensitivity analysis of soft processors in Xilinx SRAM-based FPGAs. Our platform supports the estimation of soft error sensitivity per configuration bit/frame, processor component and benchmark. The fault injection is performed on-chip by a dedicated microcontroller which also monitors processor behavior to identify specific symptoms as consequences of soft errors. The performed analysis showed that these symptoms can be used to build an efficient, low-cost error detection scheme. The proposed platform is demonstrated through an extensive fault injection campaign in the Leon3 soft processor.
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Coertze, R. D., and C. C. Bezuidenhout. "Detection and quantification of clinically relevant plasmid-mediated AmpC beta-lactamase genes in aquatic systems." Water Supply 20, no. 5 (May 7, 2020): 1745–56. http://dx.doi.org/10.2166/ws.2020.085.
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Abstract The extent and impact of plasmid-mediated AmpC beta-lactamase genes (pAmpCs) prevalence in aquatic environments is poorly understood. The aim of this study was to detect and quantify pAmpCs from the aquatic environment. The following pAmpCs were analysed with clinical TaqMan assays from isolated plasmids: ACC, ACT/MIR, BIL/LAT/CMY, DHA, FOX and MOX/CMY. Quantification was conducted using quantitative PCR (qPCR) and 3D chip-based digital PCR. The results of qPCR yielded 4,875.27 copies/ng DNA and dPCR, 1,640.58 copies/ng (Mann–Whitney U Test, p= 0.868). Redundancy analysis indicated that land coverage explains 90.49% (ANOVA, p= 0.601) of pAmpC variance. There was a correlation between the frequency and quantities of pAmpCs detected in each river and this could be related to anthropogenic influence. Frequencies of detection for pAmpCs were 25/36 for the Crocodile West River and 13/36 for the Marico River. Quantification resulted in higher copy numbers for the Crocodile West River and high copies in only two sites of the Marico River, thus reflecting degrees of anthropogenic influences on both rivers. The presence of these clinically relevant pAmpCs in aquatic systems are cause for concern, considering their potential impact if these genes are harboured by pathogens and become dispersed to human populations.
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Quezada, María Josefina, María Elisa Picco, María Belén Villanueva, María Victoria Castro, Gastón Barbero, Natalia Brenda Fernández, Edith Illescas, and Pablo Lopez-Bergami. "BCL2L10 Is Overexpressed in Melanoma Downstream of STAT3 and Promotes Cisplatin and ABT-737 Resistance." Cancers 13, no. 1 (December 30, 2020): 78. http://dx.doi.org/10.3390/cancers13010078.
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The anti-apoptotic proteins from the Bcl-2 family are important therapeutic targets since they convey resistance to anticancer regimens. Despite the suspected functional redundancy among the six proteins of this subfamily, both basic studies and therapeutic approaches have focused mainly on BCL2, Bcl-xL, and MCL1. The role of BCL2L10, another member of this group, has been poorly studied in cancer and never has been in melanoma. We describe here that BCL2L10 is abundantly and frequently expressed both in melanoma cell lines and tumor samples. We established that BCL2L10 expression is driven by STAT3-mediated transcription, and by using reporter assays, site-directed mutagenesis, and ChIP analysis, we identified the functional STAT3 responsive elements in the BCL2L10 promoter. BCL2L10 is a pro-survival factor in melanoma since its expression reduced the cytotoxic effects of cisplatin, dacarbazine, and ABT-737 (a BCL2, Bcl-xL, and Bcl-w inhibitor). Meanwhile, both genetic and pharmacological inhibition of BCL2L10 sensitized melanoma cells to cisplatin and ABT-737. Finally, BCL2L10 inhibited the cell death upon combination treatments of PLX-4032, a BRAF inhibitor, with ABT-737 or cisplatin. In summary, we determined that BCL2L10 is expressed in melanoma and contributes to cell survival. Hence, targeting BCL2L10 may enhance the clinical efficacy of other therapies for malignant melanoma.
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Tormo, Daniel, Ricardo Vidal-Albalate, Lahoucine Idkhajine, Eric Monmasson, and Ramon Blasco-Gimenez. "Embedded Real-Time Simulator for Sensorless Control of Modular Multi-Level Converters." Electronics 11, no. 5 (February 25, 2022): 719. http://dx.doi.org/10.3390/electronics11050719.
Full textAbstract:
This paper suggests the application of an embedded real-time simulator (eRTS) in the context of voltage–sensorless control of a modular multilevel power converter (MMC). This eRTS acts as an observer and ensures digital redundancy in the case of any fault occurring among the capacitor voltage sensors of the MMC submodules. Hence, in such a faulty situation, the MMC controller switches from the measured voltages to their estimated counterparts. As for the digital implementation, to ensure a high level of integration of the overall control system, the Xilinx Zynq-7020 system-on-chip field programmable gate array (SoC-FPGA) device was used. The controller was implemented in the hardwired ARM Cortex-A9 processor, with a 100 µs time step. Regarding the time-sensitive blocks (PWM, eRTS and measurements filtering), a full hardware implementation was privileged, using the FPGA fabric. The execution time of these blocks was 710 ns with a 100 MHz system clock, and the synchronization with the analog to digital acquisition chain was made with a 5 µs time resolution. The whole proof-of-concept system was experimentally tested, including the time/area evaluation of the implemented designs and the experimental validation of the eRTS estimations in both healthy and faulty scenarios.
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Kosanović, Maja, and Miroslava Janković. "Evaluation of the Pattern of Human Serum Glycoproteins in Prostate Cancer." Journal of Medical Biochemistry 28, no. 3 (July 1, 2009): 184–90. http://dx.doi.org/10.2478/v10011-009-0017-8.
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Evaluation of the Pattern of Human Serum Glycoproteins in Prostate CancerGlycoprotein profiling at the level of cells, tissues and biological fluids is aimed at discovering new cancer biomarkers and also at finding specific cancer-related structural alterations of known tumor markers. In this study we comparatively evaluated the glycoprotein patterns of human prostate cancer (PCa)- and normal human sera regarding sialylation and fucosylation as structural characteristics relevant for cancer progression. Glycoproteins were isolated using affinity chromatography on Sambucus nigra agglutinin- and Lens culinaris agglutinin-columns and subsequently characterized by SDS-PAGE and on-chip normal phase-surface capture combined with surface-enhanced laser/desorption ionization time of flight mass spectrometry. Comparative analysis of the glycoproteins purified from healthy and PCa sera indicated differences and redundancy of the isolated molecules in terms of the microheterogeneity of counterpart glycans, the relative abundance and the presence/absence of particular molecular species. In PCa there was a general increase in sialylation and decrease in fucosylation of human serum glycans compared to normal sera. Taken together, the results obtained indicated that an affinity-approach based on the use of lectins of narrow specificity reduced the complexity of the examined samples and at this discovery-phase of our study pointed to specific glyco-changes that may be relevant for improving the monitoring of PCa progression.
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Gereige, Laurraine-Marcelle, Roberto Ferrari, Amelie Montel-Hagen, Matteo Pellegrini, Xinmin Li, Siavash Kurdistani, and Hanna Mikkola. "Specification and Maintenance of the Scl Induced Hematopoietic Stem Cell Fate." Blood 114, no. 22 (November 20, 2009): 1504. http://dx.doi.org/10.1182/blood.v114.22.1504.1504.
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Abstract Abstract 1504 Poster Board I-527 The hematopoietic program is initiated in the embryo by the basic helix-loop-helix (bHLH) transcription factor Scl/Tal1 (stem cell leukemia gene). In the absence of Scl, mesodermal precursors are unable to commit to the hematopoietic fate and the embryo dies due to lack of blood formation. However, Scl becomes dispensable for hematopoietic stem cell(HSC) function shortly after hematopoietic specification, suggesting that once specified by Scl, the hematopoietic fate is maintained by alternative regulatory mechanisms. Scl is required again later for the proper maturation of erythrocytes and megakaryocytes. Despite Scl's pivotal role in initiating hematopoiesis, how Scl dictates HSC development at a molecular level remains unknown. To define how the hematopoietic fate is established by Scl, we performed genome-wide gene expression and ChIP-chip Scl binding analysis on in vitro differentiated hemangioblasts isolated from Scl−/− and control ES cells. Analysis of the 655 Scl-dependent genes and Scl binding revealed that Scl acts both as an activator and a repressor. The group of genes activated by Scl included major hematopoietic transcription factors such as Tel/Etv6, Gfi1, Fli1, cMyb, Gata2, Hhex, Sox17, Lyl1, and JunB, as well as regulators of embryonic vasculogenesis/angiogenesis and/or arterio-venous specification such as Ets1, Ets2, Elk3, Foxo1, Hoxb5, Smarca2, and Sox18. The group of genes repressed by Scl included regulators of alternative mesodermal fates such as Gata4, Tbx20 and Isl1, Foxf1a, and Snail1. These data show that Scl induces the hematopoietic program both by directly activating the major transcriptional networks required for the formation of the hemogenic endothelium and the emergence, self-renewal and survival of HSCs, as well as repressing alternative mesodermal fates. Considering the large number of transcription factors that Scl regulates during specification, we sought to determine at the molecular level how the hematopoietic fate is maintained independently of Scl. Gene expression analysis on Lin−cKit+ HSCs/progenitors isolated from Sclfl/flVavCre+ mice revealed that only 41 genes were Scl dependent, none of which were major hematopoietic factors. Notably, the key hematopoietic transcription factors remained expressed in both control and Scl deficient HSCs/progenitors indicating that the Scl induced program is maintained. Regulators of alternative mesodermal fates remained silenced during adult hematopoiesis. These molecular data were in agreement with the functional data showing that the bone marrow HSC/progenitor pool is maintained stably in the absence of Scl. To test whether Lyl1, a bHLH family member and Scl target gene, has an active role in maintaining the Scl induced hematopoietic fate, we generated HSCs/progenitors that do not express either Scl, or Lyl1, or both, by knocking down Lyl1 in Scl-deficient and control HSCs/progenitors via lentiviral shRNA. Analysis of colony forming capacity of transduced Lin−cKit+ HSCs/progenitors revealed that removing either Lyl1 or Scl alone did not have major impact on the clonogenic progenitor pool, whereas loss of both Lyl1 and Scl abrogated colony formation completely. Furthermore, ChIP-chip data revealed that Lyl1 is recruited to the promoters of the majority of Scl's target genes, and can maintain the hematopoietic program in the absence of Scl. In summary, these data show that Scl is critical in inducing the major transcriptional network of HSC genes while repressing alternative mesodermal fates during hematopoietic specification, after which the program is stabilized by Scl's target gene Lyl1. During adult hematopoiesis, relative redundancy between Scl and Lyl1 ensures stability of the HSC fate, while both factors retain unique functions in lineage differentiation. Disclosures: No relevant conflicts of interest to declare.
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Aranda, Luis Alberto, Antonio Sánchez, Francisco Garcia-Herrero, Yubal Barrios, Roberto Sarmiento, and Juan Antonio Maestro. "Reliability Analysis of the SHyLoC CCSDS123 IP Core for Lossless Hyperspectral Image Compression Using COTS FPGAs." Electronics 9, no. 10 (October 14, 2020): 1681. http://dx.doi.org/10.3390/electronics9101681.
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Hyperspectral images can comprise hundreds of spectral bands, which means that they can represent a large volume of data difficult to manage with the available on-board resources. Lossless compression solutions are interesting for reducing the amount of information stored or transmitted while preserving it at the same time. The Hyperspectral Lossless Compressor for space applications (SHyLoC), which is part of the European Space Agency (ESA) IP core’s library, has been demonstrated to meet the requirements of space missions in terms of compression efficiency, low complexity and high throughput. Currently, there is a trend to use Commercial Off-The-Shelf (COTS) on-board electronic devices on small satellites. Moreover, commercial Field-Programmable Gate Arrays (FPGAs) have been used in a number of them. Hence, a reliability analysis is required to ensure the robustness of the applications to Single Event Upsets (SEUs) in the configuration memory. In this work, we present a reliability analysis of this hyperspectral image compression module as a first step towards the development of ad-hoc fault-tolerant protection techniques for the SHyLoC IP core. The reliability analysis is performed using a fault-injection-based experimental set-up in which a hardware implementation of the Consultative Committee for Space Data Systems (CCSDS) 123.0-B-1 lossless compression standard is tested against configuration memory errors in a Xilinx Zynq XC7Z020 System-on-Chip. The results obtained for unhardened and redundancy-based protected versions of the module are put into perspective in terms of area/power consumption and availability/protection coverage gained to provide insight into the development of more efficient knowledge-based protection schemes.
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Morita, Ken, Kensho Suzuki, Shintaro Maeda, Yoshihide Mitsuda, Ayaka Yano, Yoshimi Yamada, Hiroki Kiyose, et al. "Cluster Regulation of RUNX Family By "Gene Switch" Triggers a Profound Tumor Regression of Diverse Origins." Blood 128, no. 22 (December 2, 2016): 443. http://dx.doi.org/10.1182/blood.v128.22.443.443.
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Abstract Although Runt-related transcription factor 1 (RUNX1), a member of RUNX family and a distant relative of p53, has been generally considered to be a tumor suppressor, a growing body of evidence strongly suggests its pro-oncogenic property in acute myeloid leukemia (AML). Here we demonstrate that switching off RUNX cluster utilizing the newly synthesized compound, which specifically bound to a particular base sequence of DNA, was highly effective against leukemia as well as dismal-prognostic solid tumors arising from diverse origins in vivo. Firstly, to assess the RUNX1 loss in AML cells, we performed shRNA-mediated RUNX1 knockdown experiments. Silencing of RUNX1 stimulated cell cycle arrest at G0/G1 phase and simultaneously induced apoptosis in AML cells bearing wild-type p53. RUNX1 depletion induced remarkable induction of p53 as well as its target gene products and additive knockdown of p53 in these cell lines reverted the phenotype of RUNX1-depletion, indicating that RUNX1 is functionally dependent on proficient p53 pathway. In addition, cycloheximide chase assay revealed that RUNX1 negatively regulates p53 protein in AML cells. In silico data analysis of clinical gene expression array data sets and ChIP-seq experiments using anti-RUNX1 antibody identified 32 candidate genes potentially required for RUNX1-dependent degradation of p53. Among them, we focused on BCL11A and TRIM24, both of which are established mediators of p53 degradation. In accordance with these observations, knockdown of RUNX1 resulted in a significant down-regulation of BCL11A and TRIM24 both at mRNA and protein levels. ChIP-qPCR assay further validated the actual binding of RUNX1 at the promoter regions of these genes, and reintroduction of BCL11A or TRIM24 into RUNX1-silenced AML cells restored their proliferation speed to the control levels. These data suggests that RUNX1 depletion-mediated growth inhibitory effect on leukemia cells depends on p53 activation via transcriptional regulation of BCL11A and TRIM24. Though RUNX1 depletion was highly effective on proliferation of AML cells, a small sub-population of leukemia cells retained the proliferation potential even after the silencing of RUNX1. Since it has been shown that RUNX family member has a redundant function, we next examined the other RUNX family members such as RUNX2 and RUNX3 in RUNX1-knocked down AML cells. Under our tetracycline-inducible shRNA expression system, the expression levels of RUNX1-target genes were decreased at 24 h after RUNX1 knockdown, however, their expression levels were reciprocally increased at 48 h accompanied by increment of RUNX2 and RUNX3 expressions, suggesting that RUNX2 and RUNX3 might compensate for the loss of RUNX1 functions. ChIP-qPCR assay and luciferase reporter experiments confirmed that individual RUNX family member consistently suppressed the promoter activity of the other RUNX members. In accordance with these findings, additional knockdown of RUNX2, RUNX3 or both of them in RUNX1-depleted AML cells effectively repressed RUNX1-target gene expressions and completely suppressed their proliferation. Thus the simultaneous targeting of all RUNX family members as a cluster achieves more stringent control of leukemia cells. Since sequencing analysis of the functional gene alterations of RUNX family members revealed the existence of mutations in a mutual-exclusive manner not only in AML cells but also in various cancers, their functional redundancy in the maintenance of AML cells might be generally accepted. To achieve cluster regulations of RUNX, we conducted a synthesized molecule library screening and succeeded in extracting agents that could irreversibly block the RUNX cluster genes expression profiling through dismantling protein-DNA interactions sequence-specifically. These reagents were highly effective against leukemia as well as dismal-prognostic solid tumors arising from diverse origins in vitro. Furthermore, these reagents were exceptionally well-tolerated in mice and exerted excellent efficacy against xenograft mice models of AML, acute lymphoblastc leukemia, lung and gastric cancers, extending their overall survival periods in vivo. Together, this work identifies the crucial role of RUNX cluster in the maintenance and the progression of cancer cells, and the indicated gene switch technology-dependent its modulation would be a novel strategy to control malignancies. Disclosures No relevant conflicts of interest to declare.
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Hausner, M., C. Hillebrecht, H. Karagözoglu, J. Zacheja, and J. Binder. "On-chip redundant measurement principles realized by a silicon sensor substrate." Journal of Micromechanics and Microengineering 7, no. 3 (September 1, 1997): 259–62. http://dx.doi.org/10.1088/0960-1317/7/3/049.
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