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1
Khani, Elham. "Efficient Montgomery Modular Multiplication by using Residue Number System." INTERNATIONAL JOURNAL OF MANAGEMENT & INFORMATION TECHNOLOGY 2, no. 1 (November 27, 2012): 56–62. http://dx.doi.org/10.24297/ijmit.v2i1.1410.
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Residue number system is a carry free system that performs arithmetic operation on residues instead of the weighted binary number. By applying Residue Number System (RNS) to Montgomery modular multiplication the delay of modular multiplication will be decreased. Modular multiplication over large number is frequently used in some application such as Elliptic Curve Cryptography, digital signal processing, and etc.By choosing appropriate RNS moduli sets the time consuming operation of multiplication can be replaced by smaller operations. In addition because of the property of RNS, arithmetic operations are done over smaller numbers called residues. In this paper by choosing appropriate moduli sets the efficiency of conversion from RNS to RNS that is the most time consuming part of the Montgomery modular multiplication will be increased.
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Guzhov, Vladimir I., Ilya O. Marchenko, Ekaterina E. Trubilina, and Dmitry S. Khaidukov. "Comparison of numbers and analysis of overflow in modular arithmetic." Analysis and data processing systems, no. 3 (September 30, 2021): 75–86. http://dx.doi.org/10.17212/2782-2001-2021-3-75-86.
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The method of modular arithmetic consists in operating not with a number, but with its remainders after division by some integers. In the modular number system or the number system in the residual classes, a multi-bit integer in the positional number system is represented as a sequence of several positional numbers. These numbers are the remainders (residues) of dividing the original number into some modules that are mutually prime integers. The advantage of the modular representation is that it is very simple to perform addition, subtraction and multiplication operations. In parallel execution of operations, the use of modular arithmetic can significantly reduce the computation time. However, there are drawbacks to modular representation that limit its use. These include a slow conversion of numbers from modular to positional representation; the complexity of comparing numbers in modular representation; the difficulty in performing the division operation; and the difficulty of determining the presence of an overflow. The use of modular arithmetic is justified if there are fast algorithms for calculating a number from a set of remainders. This article describes a fast algorithm for converting numbers from modular representation to positional representation based on a geometric approach. The review is carried out for the case of a comparison system with two modules. It is also shown that as a result of increasing numbers in positional calculus, they successively change in a spiral on the surface of a two-dimensional torus. Based on this approach, a fast algorithm for comparing numbers and an algorithm for detecting an overflow during addition and multiplication of numbers in modular representation were developed. Consideration for the multidimensional case is possible when analyzing a multidimensional torus and studying the behavior of the turns on its surface.
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Krasnobayev, V. A., A. S. Yanko, and D. M. Kovalchuk. "METHODS FOR TABULAR IMPLEMENTATION OF ARITHMETIC OPERATIONS OF THE RESIDUES OF TWO NUMBERS REPRESENTED IN THE SYSTEM OF RESIDUAL CLASSES." Radio Electronics, Computer Science, Control, no. 4 (December 3, 2022): 18. http://dx.doi.org/10.15588/1607-3274-2022-4-2.
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Context. Implementation of modular arithmetic operations of addition, subtraction and multiplication by a tabular method based on the use of the tabular multiplication code. The object of the study is the process of tabular implementation of basic arithmetic operations on the residues of numbers represented in the system of residual classes.
Objective. The goal of the work is to develop methods for the tabular implementation of the arithmetic operations of multiplication, addition and subtraction of the residues of two numbers based on the use of the tabular multiplication code.
Method. Tabular methods for implementing integer arithmetic modular operations of addition, subtraction and multiplication are proposed for consideration. In order to reduce the amount of equipment for a tabular operating unit of computer systems that implements modular operations of addition, subtraction and multiplication by reducing the coincidence circuits AND in the nodes of the tables for implementing arithmetic operations based on the code of table multiplication, two methods for performing arithmetic modular operations of addition and subtraction have been developed. These methods are based on the code of tabular multiplication, the use of which will reduce the amount of equipment of the tabular operating unit. Thus, despite the difference in the digital structure of the tables of modular operations of addition, subtraction and multiplication based on the use of the tabular multiplication code, two new tabular methods for implementing arithmetic modular operations of addition and subtraction have been created. Based on them, algorithms for tabular execution of modular arithmetic operations of addition and subtraction have been developed. Using these algorithms, it is possible to synthesize a structurally simple, highly reliable and fast table operating unit that operates in a system of residual classes, which is based on three separate permanent storage devices (read-only memory), each of which implements only one fourth of the corresponding complete table of values of the modular operation, what is earlier in the theory tabular arithmetic was supposed to be impossible.
Results. The developed methods are justified theoretically and studied when performing arithmetic modular operations of addition, subtraction and multiplication using tabular procedures.
Conclusions. The conducted examples of the implementation of integer arithmetic modular operations of addition and subtraction can be considered as presented experiments. The results obtained make it possible to recommend them for use in practice in the design of computer systems operating in a non-positional number system in residual classes. Prospects for further research may be to create a tabular method for implementing integer arithmetic modular division operations based on the use of the tabular multiplication code.
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Shevelev, S. S. "RECONFIGURABLE COMPUTING MODULAR SYSTEM." Radio Electronics, Computer Science, Control 1, no. 1 (March 31, 2021): 194–207. http://dx.doi.org/10.15588/1607-3274-2021-1-19.
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Context. Modern general purpose computers are capable of implementing any algorithm, but when solving certain problems in terms of processing speed they cannot compete with specialized computing modules. Specialized devices have high performance, effectively solve the problems of processing arrays, artificial intelligence tasks, and are used as control devices. The use of specialized microprocessor modules that implement the processing of character strings, logical and numerical values, represented as integers and real numbers, makes it possible to increase the speed of performing arithmetic operations by using parallelism in data processing.
Objective. To develop principles for constructing microprocessor modules for a modular computing system with a reconfigurable structure, an arithmetic-symbolic processor, specialized computing devices, switching systems capable of configuring microprocessors and specialized computing modules into a multi-pipeline structure to increase the speed of performing arithmetic and logical operations, high-speed design algorithms specialized processors-accelerators of symbol processing. To develop algorithms, structural and functional diagrams of specialized mathematical modules that perform arithmetic operations in direct codes on neural-like elements and systems for decentralized control of the operation of blocks.
Method. An information graph of the computational process of a modular system with a reconstructed structure has been built. Structural and functional diagrams, algorithms that implement the construction of specialized modules for performing arithmetic and logical operations, search operations and functions for replacing occurrences in processed words have been developed. Software has been developed for simulating the operation of an arithmetic-symbolic processor, specialized computing modules, and switching systems.
Results. A block diagram of a reconfigurable computing modular system has been developed, which consists of compatible functional modules, it is capable of static and dynamic reconfiguration, has a parallel structure for connecting the processor and computing modules through the use of interface channels. The system consists of an arithmetic-symbolic processor, specialized computing modules and switching systems, performs specific tasks of symbolic information processing, arithmetic and logical operations.
Conclusions. The architecture of reconfigurable computing systems can change dynamically during their operation. It becomes possible to adapt the architecture of a computing system to the structure of the problem being solved, to create problem-oriented computers, the structure of which corresponds to the structure of the problem being solved. As the main computing element in reconfigurable computing systems, not universal microprocessors are used, but programmable logic integrated circuits, which are combined using high-speed interfaces into a single computing field. Reconfigurable multipipeline computing systems based on fields are an effective tool for solving streaming information processing and control problems.
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Schevelev, S. S. "Reconfigurable Modular Computing System." Proceedings of the Southwest State University 23, no. 2 (July 9, 2019): 137–52. http://dx.doi.org/10.21869/2223-1560-2019-23-2-137-152.
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Purpose of research. A reconfigurable computer system consists of a computing system and special-purpose computers that are used to solve the tasks of vector and matrix algebra, pattern recognition. There are distinctions between matrix and associative systems, neural networks. Matrix computing systems comprise a set of processor units connected through a switching device with multi-module memory. They are designed to solve vector, matrix and data array problems. Associative systems contain a large number of operating devices that can simultaneously process multiple data streams. Neural networks and neurocomputers have high performance when solving problems of expert systems, pattern recognition due to parallel processing of a neural network.Methods. An information graph of the computational process of a reconfigurable modular system was plotted. Structural and functional schemes, algorithms that implement the construction of specialized modules for performing arithmetic and logical operations, search operations and functions for replacing occurrences in processed words were developed. Software for modelling the operation of the arithmetic-symbol processor, specialized computing modules, and switching systems was developed.Results. A block diagram of a reconfigurable computing modular system was developed. The system consists of compatible functional modules and is capable of static and dynamic reconfiguration, has a parallel connection structure of the processor and computing modules through the use of interface channels. It consists of an arithmeticsymbol processor, specialized computing modules and switching systems; it performs specific tasks of symbolic information processing, arithmetic and logical operations.Conclusion. Systems with a reconfigurable structure are high-performance and highly reliable computing systems that consist of integrated processors in multi-machine and multiprocessor systems. Reconfigurability of the structure provides high system performance due to its adaptation to computational processes and the composition of the processed tasks.
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Selianinau, Mikhail, and Yuriy Povstenko. "An Efficient CRT-Base Power-of-Two Scaling in Minimally Redundant Residue Number System." Entropy 24, no. 12 (December 14, 2022): 1824. http://dx.doi.org/10.3390/e24121824.
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In this paper, we consider one of the key problems in modular arithmetic. It is known that scaling in the residue number system (RNS) is a rather complicated non-modular procedure, which requires expensive and complex operations at each iteration. Hence, it is time consuming and needs too much hardware for implementation. We propose a novel approach to power-of-two scaling based on the Chinese Remainder Theorem (CRT) and rank form of the number representation in RNS. By using minimal redundancy of residue code, we optimize and speed up the rank calculation and parity determination of divisible integers in each iteration. The proposed enhancements make the power-of-two scaling simpler and faster than the currently known methods. After calculating the rank of the initial number, each iteration of modular scaling by two is performed in one modular clock cycle. The computational complexity of the proposed method of scaling by a constant Sl=2l associated with both required modular addition operations and lookup tables is estimeted as k and 2k+1, respectively, where k equals the number of primary non-redundant RNS moduli. The time complexity is log2k+l modular clock cycles.
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Chernov, V. M. "Number systems in modular rings and their applications to "error-free" computations." Computer Optics 43, no. 5 (October 2019): 901–11. http://dx.doi.org/10.18287/2412-6179-2019-43-5-901-911.
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The article introduces and explores new systems of parallel machine arithmetic associated with the representation of data in the redundant number system with the basis, the formative sequences of degrees of roots of the characteristic polynomial of the second order recurrence. Such number systems are modular reductions of generalizations of Bergman's number system with the base equal to the "Golden ratio". The associated Residue Number Systems is described. In particular, a new "error-free" algorithm for calculating discrete cyclic convolution is proposed as an application to the problems of digital signal processing. The algorithm is based on the application of a new class of discrete orthogonal transformations, for which there are effective “multipication-free” implementations.
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Kalmykov, Igor Anatolyevich, Vladimir Petrovich Pashintsev, Kamil Talyatovich Tyncherov, Aleksandr Anatolyevich Olenev, and Nikita Konstantinovich Chistousov. "Error-Correction Coding Using Polynomial Residue Number System." Applied Sciences 12, no. 7 (March 25, 2022): 3365. http://dx.doi.org/10.3390/app12073365.
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There has been a tendency to use the theory of finite Galois fields, or GF(2n), in cryptographic ciphers (AES, Kuznyechik) and digital signal processing (DSP) systems. It is advisable to use modular codes of the polynomial residue number system (PRNS). Modular codes of PRNS are arithmetic codes in which addition, subtraction and multiplication operations are performed in parallel on the bases of the code, which are irreducible polynomials. In this case, the operands are small-bit residues. However, the independence of calculations on the bases of the code and the lack of data exchange between the residues can serve as the basis for constructing codes of PRNS capable of detecting and correcting errors that occur during calculations. The article will consider the principles of constructing redundant codes of the polynomial residue number system. The results of the study of codes of PRNS with minimal redundancy are presented. It is shown that these codes are only able to detect an error in the code combination of PRNS. It is proposed to use two control bases, the use of which allows us to correct an error in any residue of the code combination, in order to increase the error-correction abilities of the code of the polynomial residue number system. Therefore, the development of an algorithm for detecting and correcting errors in the code of the polynomial residue number system, which allows for performing this procedure based on modular operations that are effectively implemented in codes of PRNS, is an urgent task.
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Rahn, Alexander, Eldar Sultanow, Max Henkel, Sourangshu Ghosh, and Idriss J. Aberkane. "An Algorithm for Linearizing the Collatz Convergence." Mathematics 9, no. 16 (August 9, 2021): 1898. http://dx.doi.org/10.3390/math9161898.
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The Collatz dynamic is known to generate a complex quiver of sequences over natural numbers for which the inflation propensity remains so unpredictable it could be used to generate reliable proof-of-work algorithms for the cryptocurrency industry; it has so far resisted every attempt at linearizing its behavior. Here, we establish an ad hoc equivalent of modular arithmetics for Collatz sequences based on five arithmetic rules that we prove apply to the entire Collatz dynamical system and for which the iterations exactly define the full basin of attractions leading to any odd number. We further simulate these rules to gain insight into their quiver geometry and computational properties and observe that they linearize the proof of convergence of the full rows of the binary tree over odd numbers in their natural order, a result which, along with the full description of the basin of any odd number, has never been achieved before. We then provide two theoretical programs to explain why the five rules linearize Collatz convergence, one specifically dependent upon the Axiom of Choice and one on Peano arithmetic.
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Chervyakov, Nikolay, Pavel Lyakhov, Mikhail Babenko, Irina Lavrinenko, Maxim Deryabin, Anton Lavrinenko, Anton Nazarov, Maria Valueva, Alexander Voznesensky, and Dmitry Kaplun. "A Division Algorithm in a Redundant Residue Number System Using Fractions." Applied Sciences 10, no. 2 (January 19, 2020): 695. http://dx.doi.org/10.3390/app10020695.
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The residue number system (RNS) is widely used for data processing. However, division in the RNS is a rather complicated arithmetic operation, since it requires expensive and complex operators at each iteration, which requires a lot of hardware and time. In this paper, we propose a new modular division algorithm based on the Chinese remainder theorem (CRT) with fractional numbers, which allows using only one shift operation by one digit and subtraction in each iteration of the RNS division. The proposed approach makes it possible to replace such expensive operations as reverse conversion based on CRT, mixed radix conversion, and base extension by subtraction. Besides, we optimized the operation of determining the most significant bit of divider with a single shift operation of the modular divider. The proposed enhancements make the algorithm simpler and faster in comparison with currently known algorithms. The experimental simulation using Kintex-7 showed that the proposed method is up to 7.6 times faster than the CRT-based approach and is up to 10.1 times faster than the mixed radix conversion approach.
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Selianinau, Mikhail, and Yuriy Povstenko. "An Efficient Parallel Reverse Conversion of Residue Code to Mixed-Radix Representation Based on the Chinese Remainder Theorem." Entropy 24, no. 2 (February 5, 2022): 242. http://dx.doi.org/10.3390/e24020242.
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In this paper, we deal with the critical problems in residue arithmetic. The reverse conversion from a Residue Number System (RNS) to positional notation is a main non-modular operation, and it constitutes a basis of other non-modular procedures used to implement various computational algorithms. We present a novel approach to the parallel reverse conversion from the residue code into a weighted number representation in the Mixed-Radix System (MRS). In our proposed method, the calculation of mixed-radix digits reduces to a parallel summation of the small word-length residues in the independent modular channels corresponding to the primary RNS moduli. The computational complexity of the developed method concerning both required modular addition operations and one-input lookup tables is estimated as Ok2/2, where k equals the number of used moduli. The time complexity is Olog2k modular clock cycles. In pipeline mode, the throughput rate of the proposed algorithm is one reverse conversion in one modular clock cycle.
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Yanko, A. S., V. A. Krasnobayev, S. B. Nikolsky, and O. O. Kruk. "METHOD FOR DETERMINING THE BIT GRID OVERFLOW OF A COMPUTER SYSTEM OPERATING IN THE SYSTEM OF RESIDUAL CLASSES." Radio Electronics, Computer Science, Control, no. 1 (April 2, 2024): 228. http://dx.doi.org/10.15588/1607-3274-2024-1-21.
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Context. Consideration of a set of examples of practical application of the procedure for identifying overflow of the bit grid of a computer system operating in a non-positional number system in residual classes. The object of the study is the process of processing data represented in the residual class system.
Objective. The goal of the work is to consider and analyze examples of the bit grid overflow definition of a computer system when implementing the operation of adding two numbers in a system of residual classes based on the application of a method for determining the bit grid overflow, based on the use of the concept of number rank.
Method. The specificity of the functioning of a computer system in a system of residual classes requires the implementation of not only modular operations, but also requires the implementation of additional, so-called non-modular operations. Non-modular operations include the operation of determining the overflow of the bit grid of a computer system in the system of residual classes. In a non-positional number system in residual classes, implementing the process of detecting overflow of the bit grid of a computer system is a difficult task to implement. The method considered in the work for determining the overflow of the bit grid is based on the use of positional features of a non-positional code of numbers in the system of residual classes, namely the true and calculated ranks of a number. The process of determining the overflow of the result of the operation of adding two numbers in the system of residual classes has been studied, since this arithmetic operation is the main, basic operation performed by a computer system.
Results. The developed methods are justified theoretically and studied when performing arithmetic modular operations of addition, subtraction and multiplication using tabular procedures.
Conclusions. The main advantage of the presented method is that the process of determining the overflow of the bit grid can be carried out in the dynamics of the computing process of the computer system, i.e. without stopping the solution of the problem. This circumstance makes it possible to reduce the unproductive expenditure of the computer system in the system of residual classes. In addition, this method can be used to control the operation of adding two numbers in the residual class system. This increases the reliability of obtaining the true result of the operation of adding two numbers in the system of residual classes.
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Chernov, V. M. "Parallel machine arithmetic for recurrent number systems in non-quadratic fields." Computer Optics 44, no. 2 (April 2020): 274–81. http://dx.doi.org/10.18287/2412-6179-co-666.
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The paper proposes a new method of synthesis of computer arithmetic systems for "error-free" parallel calculations. The difference between the proposed approach and calculations in traditional systems of Residue Number Systems for the direct sum of modular rings is the parallelization of calculations in non-quadratic extensions of simple finite fields whose elements are represented in number systems generated by sequences of powers of roots of the characteristic polynomial of the recurrent sequence.
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Babenko, Mikhail, Anton Nazarov, Maxim Deryabin, Nikolay Kucherov, Andrei Tchernykh, Nguyen Viet Hung, Arutyun Avetisyan, and Victor Toporkov. "Multiple Error Correction in Redundant Residue Number Systems: A Modified Modular Projection Method with Maximum Likelihood Decoding." Applied Sciences 12, no. 1 (January 4, 2022): 463. http://dx.doi.org/10.3390/app12010463.
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Error detection and correction codes based on redundant residue number systems are powerful tools to control and correct arithmetic processing and data transmission errors. Decoding the magnitude and location of a multiple error is a complex computational problem: it requires verifying a huge number of different possible combinations of erroneous residual digit positions in the error localization stage. This paper proposes a modified correcting method based on calculating the approximate weighted characteristics of modular projections. The new procedure for correcting errors and restoring numbers in a weighted number system involves the Chinese Remainder Theorem with fractions. This approach calculates the rank of each modular projection efficiently. The ranks are used to calculate the Hamming distances. The new method speeds up the procedure for correcting multiple errors and restoring numbers in weighted form by an average of 18% compared to state-of-the-art analogs.
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Chaves, R., and L. Sousa. "Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures." IET Computers & Digital Techniques 1, no. 5 (2007): 472. http://dx.doi.org/10.1049/iet-cdt:20060059.
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Золотарева, Н. С. "NUMERAL SCALING METHODS IN MODULAR ARITHMETIC: REVIEW, DEVELOPMENT AND ESTIMATION OF THE ALGORITHMS COMPLEXITY." Proceedings in Cybernetics 22, no. 1 (2023): 59–72. http://dx.doi.org/10.35266/1999-7604-2023-1-59-72.
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The study describes two methods of numeral scaling in a modular number system: one which is based on the interval estimation and the other one which uses iterative algorithm of scaling number X by the coefficient K and includes both the stage of base system expansion and the scaling stage itself. The authors demonstrate the examples and results of algorithms operation provided by the programs developed via Python that simulate algorithms execution on a computer. Estimates of the algorithms complexity were defined in order to compare them and to detect the most appropriate ones.
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Lauber, Murray. "Casting Out Nines: An Explanation and Extensions." Mathematics Teacher 83, no. 8 (November 1990): 661–65. http://dx.doi.org/10.5951/mt.83.8.0661.
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The method of casting out 9s has been used for centuries, perhaps even as long as a millenium, for checking computations with integers involving the four mathematical operations. According to Eves (1980, 160–68) it was used by Hindu-Arabic scholars in the Middle Ages. It appears to have been imbibed by Western culture as a part of the decimal system of representation of numbers. With the invention of the electronic calculator its practical value has diminished. However, it is still an intriguing application of modular arithmetic that can be generalized to arithmetic in other bases. This article explains how casting out 9s is done, examines some reasons for including it as a topic for exploration in the mathematics curriculum, and uses modular arithmetic to explore its mathematical basis and its generalizability to computations in bases other than ten. A method of detecting errors in the transmission of computer code with some affinities to its analogues is also explored.
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Inyutin, S. A. "A Method for Reducing the Register Effect for Modular Data Formats." Informacionnye Tehnologii 28, no. 8 (August 15, 2022): 405–10. http://dx.doi.org/10.17587/it.28.405-410.
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The substantiation of the author's method of reducing redundancy from the register effect when placing the components of a tuple representing a numerical value in a modular format designed for storage, transmission and processing in modular arithmetic in a specialized SIMD processor of parallel structure is given. Modular coding allows to obtain parallel execution of ring operations in independent computing paths. This, according to Amdahl's law, accelerates the execution of the computational process on multiprocessor computing systems or on multiple cores. Modular data formats are not consistent with the binary bit grid of a multiprocessor computer. In homogeneous binary registers designed to display modulo deductions, redundancy occurs because not all possible binary combinations in a digital register are used to display data. The method is based on the redistribution of the redundancy of digital registers used to display the components of the modular tuple, which allows to reduce to zero the register effect and redundancy of the representation of the components of the tuple. This makes it possible to obtain a dense packing of components of vector modular formats in homogeneous digital registers, which makes the development of SIMD architecture computers processing data in computer modular formats promising. The simulation results allow us to obtain mutually simple bases of the modular number system that meet the conditions of a new patented method for the complete elimination of redundancy.
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Temple, Christine M., and Susan Sherwood. "Representation and retrieval of arithmetical facts: Developmental difficulties." Quarterly Journal of Experimental Psychology Section A 55, no. 3 (August 2002): 733–52. http://dx.doi.org/10.1080/02724980143000550.
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One form of developmental difficulty with arithmetic affects the storage or retrieval of arithmetical facts, such as tables, which are required to implement arithmetical computations (Temple, 1991, 1994). Such difficulties may arise because of impairment in a specialized system for the storage of arithmetical facts or as a result of causally linked impairment in another cognitive domain. This study explored issues concerning the representation and retrieval of arithmetical facts in children with number fact disorders (NF) and in normal children, in particular the status of hypothesized linked impairments: short-term memory (STM) spans, counting skills, speed of speech, and speed of number fact and lexical retrieval. There was no evidence that NF children had weak STM spans on any span measure or that STM spans related to arithmetical fact skills. There was also no evidence that NF children had weak counting abilities or free counting speeds. The NF children were slower in speeded counting, which also correlated with number fact skill. The significance or not of this is discussed. The NF children were also slower than controls in speed of speech and on some measures of speed of access. However, the absence of correlation with number fact skill, the absence of generality across tasks, and the possibility that delayed speeds in fact retrieval reflect the use of alternative strategies, together suggest that the increased speeds are not causally linked to number fact skill. The results are consistent with modular accounts, in which there is a specialized system for the storage and retrieval of arithmetical facts.
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Krasnobayev, Victor, Alexandr Kuznetsov, and Kateryna Kuznetsova. "Synthesis of the Structure of a Computer System Functioning in Residual Classes." International Journal of Computer Network and Information Security 15, no. 1 (February 8, 2023): 1–13. http://dx.doi.org/10.5815/ijcnis.2023.01.01.
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An important task of designing complex computer systems is to ensure high reliability. Many authors investigate this problem and solve it in various ways. Most known methods are based on the use of natural or artificially introduced redundancy. This redundancy can be used passively and/or actively with (or without) restructuring of the computer system. This article explores new technologies for improving fault tolerance through the use of natural and artificially introduced redundancy of the applied number system. We consider a non-positional number system in residual classes and use the following properties: independence, equality, and small capacity of residues that define a non-positional code structure. This allows you to: parallelize arithmetic calculations at the level of decomposition of the remainders of numbers; implement spatial spacing of data elements with the possibility of their subsequent asynchronous independent processing; perform tabular execution of arithmetic operations of the base set and polynomial functions with single-cycle sampling of the result of a modular operation. Using specific examples, we present the calculation and comparative analysis of the reliability of computer systems. The conducted studies have shown that the use of non-positional code structures in the system of residual classes provides high reliability. In addition, with an increase in the bit grid of computing devices, the efficiency of using the system of residual classes increases. Our studies show that in order to increase reliability, it is advisable to reserve small nodes and blocks of a complex system, since the failure rate of individual elements is always less than the failure rate of the entire computer system.
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Mehrabi, Mohamad Ali. "Improved Sum of Residues Modular Multiplication Algorithm." Cryptography 3, no. 2 (May 29, 2019): 14. http://dx.doi.org/10.3390/cryptography3020014.
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Modular reduction of large values is a core operation in most common public-key cryptosystems that involves intensive computations in finite fields. Within such schemes, efficiency is a critical issue for the effectiveness of practical implementation of modular reduction. Recently, Residue Number Systems have drawn attention in cryptography application as they provide a good means for extreme long integer arithmetic and their carry-free operations make parallel implementation feasible. In this paper, we present an algorithm to calculate the precise value of “ X mod p ” directly in the RNS representation of an integer. The pipe-lined, non-pipe-lined, and parallel hardware architectures are proposed and implemented on XILINX FPGAs.
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Jha, Somnath, and Aprameyo Pal. "Algebraic functional equation for Hida family." International Journal of Number Theory 10, no. 07 (September 9, 2014): 1649–74. http://dx.doi.org/10.1142/s1793042114500493.
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We prove a functional equation for the characteristic ideal of the "big" Selmer group 𝒳(𝒯ℱ/F cyc ) associated to an ordinary Hida family of elliptic modular forms over the cyclotomic ℤp extension of a general number field F, under the assumption that there is at least one arithmetic specialization whose Selmer group is torsion over its Iwasawa algebra. For a general number field, the two-variable cyclotomic Iwasawa main conjecture for ordinary Hida family is not proved and this can be thought of as an evidence to the validity of the Iwasawa main conjecture. The central idea of the proof is to prove a variant of the result of Perrin-Riou [Groupes de Selmer et accouplements; cas particulier des courbes elliptiques, Doc. Math.2003 (2003) 725–760, Extra Volume: Kazuya Kato's fiftieth birthday] by constructing a generalized pairing on the individual Selmer groups corresponding to the arithmetic points and make use of the appropriate specialization techniques of Ochiai [Euler system for Galois deformations, Ann. Inst. Fourier (Grenoble)55(1) (2005) 113–146].
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Aini, Saripah. "Implementasi Algoritma TEA dan Pontifex Dalam Keamanan Data File Dokumen." JURIKOM (Jurnal Riset Komputer) 7, no. 3 (June 14, 2020): 409. http://dx.doi.org/10.30865/jurikom.v7i3.2180.
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Data security is one of the most important aspects in information technology. With a high level of security, hopefully the information presented can be maintained its authenticity. In this final project a system that secures data and information stored on the computer from cryptanalysts is formed. The steps that the author did to make the process of forming the system include the stages of problem analysis, algorithm and flowchart along with modeling the structure of the program and design of the application interface, so that the application formed becomes easy to use and has optimal functions. By using TEA and pontifex algorithms which are secret key cryptographic algorithms, these problems can be overcome. The strength of this algorithm lies in the feistel network (including substitution operations, permutations and modular arithmetic) and delta numbers derived from the golden number.
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Krasnobayev, V. A., A. S. Yanko, V. N. Kurchanov, and S. A. Koshman. "АНАЛІЗ ЗАДАЧ І АЛГОРИТМІВ ЦІЛОЧИСЛОВОЇ ОБРОБКИ ДАНИХ У СИСТЕМІ ЗАЛИШКОВИХ КЛАСІВ." Radioelectronic and Computer Systems, no. 1 (September 2, 2016): 19–28. http://dx.doi.org/10.32620/reks.2016.1.03.
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The coding of remainders number witch submitted the appropriate modules of residual classes system (RCS), made with data from complete system of the smallest non-negative residues (CSSNR) was showed in the article. In this aspect, CSSNR is the basis for the construction of non-positional code structure in RCS. Possible field of science and engineering, where there is an urgent need for fast, reliable and high-precision integer calculations were clarified and systematized in the paper. On the basis of studies of the properties of RCS were examined the advantages and disadvantages of using modular arithmetic (MA). Using the results of the analysis of problems of integer data and a set of positive attributes of MA, the classes of problems and algorithms, which using RCS, much more efficient binary positional numeral systems were defined in the article.
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Souravlas, Stavros, and Sofia Anastasiadou. "Pipelined Dynamic Scheduling of Big Data Streams." Applied Sciences 10, no. 14 (July 13, 2020): 4796. http://dx.doi.org/10.3390/app10144796.
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We are currently living in the big data era, in which it has become more necessary than ever to develop “smart” schedulers. It is common knowledge that the default Storm scheduler, as well as a large number of static schemes, has presented certain deficiencies. One of the most important of these deficiencies is the weakness in handling cases in which system changes occur. In such a scenario, some type of re-scheduling is necessary to keep the system working in the most efficient way. In this paper, we present a pipeline-based dynamic modular arithmetic-based scheduler (PMOD scheduler), which can be used to re-schedule the streams distributed among a set of nodes and their tasks, when the system parameters (number of tasks, executors or nodes) change. The PMOD scheduler organizes all the required operations in a pipeline scheme, thus reducing the overall processing time.
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Mehrabi, Mohamad Ali, and Christophe Doche. "Low-Cost, Low-Power FPGA Implementation of ED25519 and CURVE25519 Point Multiplication." Information 10, no. 9 (September 14, 2019): 285. http://dx.doi.org/10.3390/info10090285.
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Twisted Edwards curves have been at the center of attention since their introduction by Bernstein et al. in 2007. The curve ED25519, used for Edwards-curve Digital Signature Algorithm (EdDSA), provides faster digital signatures than existing schemes without sacrificing security. The CURVE25519 is a Montgomery curve that is closely related to ED25519. It provides a simple, constant time, and fast point multiplication, which is used by the key exchange protocol X25519. Software implementations of EdDSA and X25519 are used in many web-based PC and Mobile applications. In this paper, we introduce a low-power, low-area FPGA implementation of the ED25519 and CURVE25519 scalar multiplication that is particularly relevant for Internet of Things (IoT) applications. The efficiency of the arithmetic modulo the prime number 2 255 - 19 , in particular the modular reduction and modular multiplication, are key to the efficiency of both EdDSA and X25519. To reduce the complexity of the hardware implementation, we propose a high-radix interleaved modular multiplication algorithm. One benefit of this architecture is to avoid the use of large-integer multipliers relying on FPGA DSP modules.
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Inyutin, S. A. "General Approach to the Description of Computer Number Systems." Informacionnye Tehnologii 28, no. 4 (April 14, 2022): 178–84. http://dx.doi.org/10.17587/it.28.178-184.
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General relationships, algorithms, and differences for three numerical systems used in the field of computing technology are analyzed: positional, polyadic and modular. Their power-law modifications are obtained. A single basic algorithm for the formation of components of vectors representing numerical values in these systems, which are residues in relatively simple modules from the set of bases of a numerical system, is analyzed with an estimate of complexity. Vector representation of numerical values is a mathematical and algorithmic basis for generating arithmetic computer formats focused on high-performance parallel processing. Generalization of the representation of numerical values in three computer number systems in the form of vectors with an indication of the limits of change of representation components is intended for the analysis and parallelization of complex computational processes. Analysis from a unified position of computer number systems makes it possible to find computational problems for which the use of individual of them is effective. For tasks in which it is necessary to simultaneously process data in various formats associated with number systems, a correct description from a general point of view of the corresponding data formats is used. The analysis of number systems is intended for the development of mathematical structures as a base of software and algorithmic tools and the generation of machine data formats associated with these systems, designed to increase the efficiency of complex computational processes and assess their convergence for calculations in large computer ranges, focused on serial computers and scalable multiprocessor systems SIMD — architectures.
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KOZHEVNIKOV, ALEKSEY. "SYNTHESIS OF A TABLE-TYPE TONAL ARITHMETIC DEVICE." Computational Nanotechnology 10, no. 1 (March 30, 2023): 95–102. http://dx.doi.org/10.33693/2313-223x-2023-10-1-95-102.
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One of the obstacles to the further development of the capabilities of high-speed measuring technology is the limitations of digital electronics in terms of the ADC control circuit. The paper proposes to use an alternative approach based on arithmetic in the system of residual classes, while discrete phases of harmonic signals are used as the basis for coding modular numbers. Before a high-speed ADC control scheme is implemented, it is necessary to theoretically justify the functioning of basic computing devices. The article discusses algorithms for the operation of a tabular arithmetic device and a phased key with a high rate of state change. A simple model of the computational path is given in order to focus attention on possible problems with the microwave signal. Modern achievements in the field of potential semiconductor and superconducting instrumentation are analyzed.
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Balasubramanian, Padmanabhan, and Douglas L. Maskell. "Gate-Level Hardware Priority Resolvers for Embedded Systems." Journal of Low Power Electronics and Applications 14, no. 2 (April 17, 2024): 25. http://dx.doi.org/10.3390/jlpea14020025.
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An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver.
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Okie, W. R., and E. G. Okie. "Check Digits for Detecting Recording Errors in Horticultural Research: Theory and Examples." HortScience 40, no. 7 (December 2005): 1956–62. http://dx.doi.org/10.21273/hortsci.40.7.1956.
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Check digit technology is frequently used in commercial applications such as shipping labels and credit cards to flag errors in numbers as they are used. Most systems use modular arithmetic to calculate a check digit from the digits in the identification number. Check digits are little used in horticultural research because the guidelines for implementing them are neither well known nor readily accessible. The USDA–ARS stone fruit breeding program at Byron, Ga., plants thousands of trees annually, which are identified using a 2-digit year prefix followed by a sequential number that identifies the tree location in the rows. Various records are taken over the life of the tree including bloom and fruit characteristics. Selected trees are propagated and tested further. To improve the accuracy of our records we have implemented a system which uses a check number which is calculated from the identification number and then converted to a letter that is added onto the end of the identification number. The check letter is calculated by summing the products of each of the digits in the number multiplied by sequential integers, dividing this sum by 23, and converting the remainder into a letter. Adding a single letter suffix is a small change and does not add much complexity to existing data collection. The types of errors caught by this system are discussed, along with those caught by other common check digit systems. Check digit terminology and theory are also covered.
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Babenko, Mikhail, Maxim Deryabin, Stanislaw J. Piestrak, Piotr Patronik, Nikolay Chervyakov, Andrei Tchernykh, and Arutyun Avetisyan. "RNS Number Comparator Based on a Modified Diagonal Function." Electronics 9, no. 11 (October 27, 2020): 1784. http://dx.doi.org/10.3390/electronics9111784.
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Number comparison has long been recognized as one of the most fundamental non-modular arithmetic operations to be executed in a non-positional Residue Number System (RNS). In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set is presented. It is based on a newly introduced modified diagonal function, whose strictly monotonic properties make it possible to replace the cumbersome operations of finding the remainder of the division by a large and awkward number with significantly simpler computations involving only a power of 2 modulus. Comparators of numbers represented in sample RNSs composed of varying numbers of moduli and offering different dynamic ranges, designed using various methods, were synthesized for the 65 nm technology. The experimental results suggest that the new circuits enjoy a delay reduction ranging from over 11% to over 75% compared to the fastest circuits designed using existing methods. Moreover, it is achieved using less hardware, the reduction of which reaches over 41%, and is accompanied by significantly reduced power-consumption, which in several cases exceeds 100%. Therefore, it seems that the presented method leads to the design of the most efficient current hardware comparators of numbers represented using a general RNS moduli set.
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Selvam, Ravikumar, and Akhilesh Tyagi. "An Evaluation of Power Side-Channel Resistance for RNS Secure Logic." Sensors 22, no. 6 (March 14, 2022): 2242. http://dx.doi.org/10.3390/s22062242.
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In this paper, residue number system (RNS) based logic is proposed as a protection against power side-channel attacks. Every input to RNS logic is encrypted as a share of the original input in the residue domain through modulus values. Most existing countermeasures enhance side-channel privacy by making the power trace statistically indistinguishable. The proposed RNS logic provides cryptographic privacy that also offers side-channel resistance. It also offers side-channel privacy by mapping different input bit values into similar bit encodings for the shares. This property is also captured as a symmetry measure in the paper. This side-channel resistance of the RNS secure logic is evaluated analytically and empirically. An analytical metric is developed to capture the conditional probability of the input bit state given the residue state visible to the adversary, but derived from hidden cryptographic secrets. The transition probability, normalized variance, and Kullback–Leibler (KL) divergence serve as side-channel metrics. The results show that our RNS secure logic provides better resistance against high-order side-channel attacks both in terms of power distribution uniformity and success rates of machine learning (ML)-based power side-channel attacks. We performed SPICE simulations on Montgomery modular multiplication and Arithmetic-style modular multiplication using the FreePDK 45 nm Technology library. The simulation results show that the side-channel security metrics using KL divergence are 0.0204 for Montgomery and 0.0020 for the Arithmetic-style implementation. This means that Arithmetic-style implementation has better side-channel resistance than the Montgomery implementation. In addition, we evaluated the security of the AES encryption with RNS secure logic on a Spartan-6 FPGA Board. Experimental results show that the protected AES circuit offers 79% higher resistance compared to the unprotected AES circuit.
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Kolyada, А. А., P. V. Kuchynski, and S. Yu Protasenia. "Method and Algorithm for Implementation of Decoding Operation in the Threshold Cryptomodule of Secret Separation Using a Minimally Redundant Modular Number System." INFORMACIONNYE TEHNOLOGII 27, no. 2 (February 12, 2021): 77–88. http://dx.doi.org/10.17587/it.27.77-88.
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The article presents a new development of method and algorithm for performing secret separation in a threshold cryptomodule with masking transformation of the decoding operation. To solve this problem a recursive binary exponent division scheme and computational technology on the ranges of large numbers of the table-adder type, based on minimally redundant modular arithmetic (MRMA) are applied. A distinctive feature of the developed approach is usage the secret-original domain of finite residue rings for modules that have the form of powers of the number 2. This significantly reduces the complexity of the resulting decoding MRMA-procedure. Decomposition of scalable residues into large modules allows you to efficiently map the computational process being implemented to sets of easily implemented data extraction operations from table memory and their summation, providing a high level of performance, uniformity, and unification of basic structures. In terms of speed, the created MIMA decoding algorithm surpasses non-redundant analogues by at least l(19l-3)/(22l-6) times (l is the number of subscribers restoring the secret original). When l = 7...40 a (6.15...34.65)-fold increase in productivity is achieved.
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Issad, M., B. Boudraa, M. Anane, and A. M. Bellemou. "Efficient PSoC Implementation of Modular Multiplication and Exponentiation Based on Serial-Parallel Combination." Journal of Circuits, Systems and Computers 28, no. 13 (February 18, 2019): 1950229. http://dx.doi.org/10.1142/s0218126619502293.
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This paper presents an FPGA implementation of the most critical operations of Public Key Cryptography (PKC), namely the Modular Exponentiation (ME) and the Modular Multiplication (MM). Both operations are integrated as Programmable System on Chip (PSoC) where the processor Microblaze of Xilinx is used for flexibility. Our objective is to achieve a best trade-off between time execution, occupied area and flexibility. The implementation of these operations on such environment requires taking into account several criteria. Indeed, the Hardware (HW) architectures data bus should be smaller than the input data length. The design must be scalable to support different security levels. The implementation achieves optimums execution time and HW resources number. In order to satisfy these constraints, Montgomery Power Ladder (MPL) and Montgomery Modular Multiplication (MMM) algorithms are utilized for the ME and the MM implementations as HW accelerators, respectively. Our implementation approach is based on the digit-serial method for performing the basic arithmetic operations. Efficient parallel and pipeline strategies are developed at the digit level for the optimization of the execution times. The application for 1024-bits data length shows that the MMM run in 6.24[Formula: see text][Formula: see text]s and requires 647 slices. The ME is executed in 6.75[Formula: see text]ms using 2881 slices.
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Babenko, Mikhail, Stanislaw J. Piestrak, Nikolay Chervyakov, and Maxim Deryabin. "The Study of Monotonic Core Functions and Their Use to Build RNS Number Comparators." Electronics 10, no. 9 (April 28, 2021): 1041. http://dx.doi.org/10.3390/electronics10091041.
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A non-positional residue number system (RNS) enjoys particularly efficient implementation of addition and multiplication, but non-modular arithmetic operations in RNS-like number comparison are known to be difficult. In this paper, a new technique for designing comparators of RNS numbers represented in an arbitrary moduli set is presented. It is based on using the core function for which it was shown that it must be monotonic to allow for RNS number comparison. The conditions of the monotonicity of the core function were formulated, which also ensured the minimal range of the core function (essential to obtain the best characteristics of the comparator). The best choice is a core function in which only one coefficient corresponding to the largest modulus is set to 1 whereas all other coefficients are set to 0. It is also shown that the already known diagonal function is nothing else but the special case of the core function with all coefficients set to 1. Performance evaluation suggests that the new comparator uses less hardware and in some cases also introduces smaller delay than its counterparts based on diagonal function. The potential applications of the new comparator include some recently developed homomorphic encryption algorithms implemented using RNS.
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Liu, Xia, Huan Yang, and Li Yang. "Feasibility Analysis of Cracking RSA with Improved Quantum Circuits of the Shor’s Algorithm." Security and Communication Networks 2023 (November 24, 2023): 1–13. http://dx.doi.org/10.1155/2023/2963110.
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Since the RSA public key cryptosystem was proposed, it has been widely used because of its strong security. Although the proposal of the Shor’s algorithm offers hope for cracking RSA, it is debatable whether the algorithm can actually pose a threat in practice. From the perspective of the quantum circuit of the Shor’s algorithm, we analyse the feasibility of cracking RSA with improved quantum circuits using an ion-trap quantum computer. We present an improved quantum circuit for the modular exponentiation of a constant, which is the most expensive operation in Shor’s algorithm for integer factorization. Whereas previous studies mostly focused on minimizing the number of qubits or the depth of the circuit, we minimize the number of CNOTs, which greatly affects the time to run the algorithm on an ion-trap quantum computer. First, we give the implementation of the basic arithmetic with the lowest known number of CNOTs and the construction of an improved modular exponentiation of a constant by accumulating intermediate data and using a windowing technique. Then, we precisely estimate the number of improved quantum circuits needed to perform the Shor’s algorithm for factoring an n -bit integer, which is 217 n 3 / log 2 n + 4 n 2 + n . We analyse the running time and feasibility of the Shor’s algorithm on an ion-trap quantum computer according to the number of CNOTs. Finally, we discussed the lower bound of the number of CNOTs needed to implement the Shor’s algorithm.
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AITHAL, GANESH, K. N. HARI BHAT, and U. SRIPATI ACHARYA. "HIGH-SPEED AND SECURE ENCRYPTION SCHEMES BASED ON CHINESE REMAINDER THEOREM FOR STORAGE AND TRANSMISSION OF MEDICAL INFORMATION." Journal of Mechanics in Medicine and Biology 10, no. 01 (March 2010): 167–90. http://dx.doi.org/10.1142/s0219519410003307.
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Medical records generated in hospitals often contain private and sensitive information. This privileged information must be prevented from falling into wrong hands. Thus, there is a strong need for developing a secure cryptographic scheme that can be adapted to use in conjunction with transmission and storage of medical information. Previous approaches have proposed the use of the advanced encryption standard (AES) algorithm for this purpose. In this article, we are proposing a new robust, high-speed, and secure cryptographic scheme that has the added advantage of being immune to side-channel attacks. In our article, we have shown that the performance of this scheme is superior in certain aspects to that of the A5/1 system used in global system for mobile (GSM) systems. The parallel architecture employed in this scheme makes it suitable to use in systems where the data-processing operations have to be carried out in real time. Residue number systems (RNS) based on Chinese remainder theorem (CRT) permits the representation of large integers in terms of combinations of smaller ones. The set of all CRT number system representation of an integer from 0 to M-1 with component wise modular addition and multiplication constitutes a direct sum of smaller commutative rings. An encryption and decryption algorithm based on the properties of direct sum of smaller rings offers distinct advantages over decimal or fixed radix arithmetic. We have utilized the representation of integers using CRT to successfully design additive, multiplicative, and affine stream cipher systems. The use of number system based on CRT allows speeding up the encryption/decryption algorithms, reduces the time complexity, and provides immunity to side-channel, algebraic, and known plain text attacks. In this article, the characteristics of additive, multiplicative, and affine stream cipher systems based on CRT number system representation have been studied and analyzed.
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ZHANG, MINGDA, and SHUGANG WEI. "HIGH-SPEED MODULAR MULTIPLIERS BASED ON A NEW BINARY SIGNED-DIGIT ADDER TREE STRUCTURE." Journal of Circuits, Systems and Computers 22, no. 06 (July 2013): 1350043. http://dx.doi.org/10.1142/s0218126613500436.
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Modular multiplication is a very important arithmetic operation in residue-based real-time computing systems. In this paper, we present multipliers using a modified binary tree of the modulo m signed-digit (SD) number adders where m = 2n + μ(μ = ±1, 0). To simplify the residue SD adder, new addition rules are used for generating the intermediate sum and carry with an 1-bit binary encoded number representation. By using the new encoding method, the proposed residue addition requires less hardware and shorter delay time than previous one. A modulo m multiplier can be implemented by a binary modulo m adder tree which has a depth of log 2 n. In order to introduce a binary SD adder tree with the new addition rules, two novel modulo m adders have been proposed in this paper. Finally, the evaluation apparently shows that the proposed two kinds of modulo m adders are performed more efficiency by comparing with the modulo SD adder which is mentioned in our previous work, and a new binary SD adder tree structure has been proposed.
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Vilardy O., Juan M., Leiner Barba J., and Cesar O. Torres M. "Image Encryption and Decryption Systems Using the Jigsaw Transform and the Iterative Finite Field Cosine Transform." Photonics 6, no. 4 (November 26, 2019): 121. http://dx.doi.org/10.3390/photonics6040121.
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We propose the use of the Jigsaw transform (JT) and the iterative cosine transform over a finite field in order to encrypt and decrypt images. The JT is a nonlinear operation that allows one to increase the security over the encrypted images by adding new keys to the encryption and decryption systems. The finite field is a finite set of integer numbers where the basic mathematical operations are performed using modular arithmetic. The finite field used in the encryption and decryption systems has an order given by the Fermat prime number 257. The iterative finite field cosine transform (FFCT) was used in our work with the purpose of obtaining images that had an uniform random distribution. We used a security key given by an image randomly generated and uniformly distributed. The JT and iterative FFCT was utilized twice in the encryption and decryption systems. The encrypted images presented a uniformly distributed histogram and the decrypted images were the same original images used as inputs in the encryption system. The resulting decrypted images had a high level of image quality in comparison to the image quality of the decrypted images obtained by the actual optical decryption systems. The proposed encryption and decryption systems have three security keys represented by two random permutations used in the JTs and one random image. The key space of the proposed encryption and decryption systems is larger. The previous features of the security system allow a better protection of the encrypted image against brute force and statistical analysis attacks.
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Asadpour, Ailin, Amir Sabbagh Molahosseini, and Azadeh Alsadat Emrani Zarandi. "The use of reversible logic gates in the design of residue number systems." International Journal of Electrical and Computer Engineering (IJECE) 13, no. 2 (April 1, 2023): 2009. http://dx.doi.org/10.11591/ijece.v13i2.pp2009-2022.
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Reversible computing is an emerging technique to achieve ultra-low-power circuits. Reversible arithmetic circuits allow for achieving energy-efficient high-performance computational systems. Residue number systems (RNS) provide parallel and fault-tolerant additions and multiplications without carry propagation between residue digits. The parallelism and fault-tolerance features of RNS can be leveraged to achieve high-performance reversible computing. This paper proposed RNS full reversible circuits, including forward converters, modular adders and multipliers, and reverse converters used for a class of RNS moduli sets with the composite form {2<sup>k</sup>, 2<sup>p</sup>-1}. Modulo 2<sup>n</sup>-1, 2<sup>n</sup>, and 2<sup>n</sup>+1 adders and multipliers were designed using reversible gates. Besides, reversible forward and reverse converters for the 3-moduli set {2<sup>n</sup>-1, 2<sup>n+k</sup>, 2<sup>n</sup>+1} have been designed. The proposed RNS-based reversible computing approach has been applied for consecutive multiplications with an improvement of above 15% in quantum cost after the twelfth iteration, and above 27% in quantum depth after the ninth iteration. The findings show that the use of the proposed RNS-based reversible computing in convolution results in a significant improvement in quantum depth in comparison to conventional methods based on weighted binary adders and multipliers.
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CULVER, TIM, JOHN KEYSER, DINESH MANOCHA, and SHANKAR KRISHNAN. "A HYBRID APPROACH FOR DETERMINANT SIGNS OF MODERATE-SIZED MATRICES." International Journal of Computational Geometry & Applications 13, no. 05 (October 2003): 399–417. http://dx.doi.org/10.1142/s0218195903001256.
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Many geometric computations have at their core the evaluation of the sign of the determinant of a matrix. A fast, failsafe determinant sign operation is often a key part of a robust implementation. While linear problems from 3D computational geometry usually require determinants no larger than six, non-linear problems involving algebraic curves and surfaces produce larger matrices. Furthermore, the matrix entries often exceed machine precision, while existing approaches focus on machine-precision matrices. In this paper, we describe a practical hybrid method for computing the sign of the determinant of matrices of order up to 60. The stages include a floating-point filter based on the singular value decomposition of a matrix, an adaptive-precision implementation of Gaussian elimination, and a standard modular arithmetic determinant algorithm. We demonstrate our method on a number of examples encountered while solving polynomial systems.
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Pfänder, O. A., H. J. Pfleiderer, and S. W. Lachowicz. "Configurable multiplier modules for an adaptive computing system." Advances in Radio Science 4 (September 6, 2006): 231–36. http://dx.doi.org/10.5194/ars-4-231-2006.
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Abstract. The importance of reconfigurable hardware is increasing steadily. For example, the primary approach of using adaptive systems based on programmable gate arrays and configurable routing resources has gone mainstream and high-performance programmable logic devices are rivaling traditional application-specific hardwired integrated circuits. Also, the idea of moving from the 2-D domain into a 3-D design which stacks several active layers above each other is gaining momentum in research and industry, to cope with the demand for smaller devices with a higher scale of integration. However, optimized arithmetic blocks in course-grain reconfigurable arrays as well as field-programmable architectures still play an important role. In countless digital systems and signal processing applications, the multiplication is one of the critical challenges, where in many cases a trade-off between area usage and data throughput has to be made. But the a priori choice of word-length and number representation can also be replaced by a dynamic choice at run-time, in order to improve flexibility, area efficiency and the level of parallelism in computation. In this contribution, we look at an adaptive computing system called 3-D-SoftChip to point out what parameters are crucial to implement flexible multiplier blocks into optimized elements for accelerated processing. The 3-D-SoftChip architecture uses a novel approach to 3-dimensional integration based on flip-chip bonding with indium bumps. The modular construction, the introduction of interfaces to realize the exchange of intermediate data, and the reconfigurable sign handling approach will be explained, as well as a beneficial way to handle and distribute the numerous required control signals.
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He, Pengzhou, Samira Carolina Oliva Madrigal, Çetin Kaya Koç, Tianyou Bao, and Jiafeng Xie. "CASA: A Compact and Scalable Accelerator for Approximate Homomorphic Encryption." IACR Transactions on Cryptographic Hardware and Embedded Systems 2024, no. 2 (March 12, 2024): 451–80. http://dx.doi.org/10.46586/tches.v2024.i2.451-480.
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Approximate arithmetic-based homomorphic encryption (HE) scheme CKKS [CKKS17] is arguably the most suitable one for real-world data-privacy applications due to its wider computation range than other HE schemes such as BGV [BGV14], FV and BFV [Bra12, FV12]. However, the most crucial homomorphic operation of CKKS called key-switching induces a great amount of computational burden in actual deployment situations, and creates scalability challenges for hardware acceleration. In this paper, we present a novel Compact And Scalable Accelerator (CASA) for CKKS on the field-programmable gate array (FPGA) platform. The proposed CASA addresses the aforementioned computational and scalability challenges in homomorphic operations, including key-exchange, homomorphic multiplication, homomorphic addition, and rescaling.On the architecture layer, we propose a new design methodology for efficient acceleration of CKKS. We design this novel hardware architecture by carefully studying the homomorphic operation patterns and data dependency amongst the primitive oracles. The homomorphic operations are efficiently mapped into an accelerator with simple control and smooth operation, which brings benefits for scalable implementation and enhanced pipeline and parallel processing (even with the potential for further improvement).On the component layer, we carry out a detailed and extensive study and present novel micro-architectures for primitive function modules, including memory bank, number theoretic transform (NTT) module, modulus switching bank, and dyadic multiplication and accumulation.On the arithmetic layer, we develop a new partially reduction-free modular arithmetic technique to eliminate part of the reduction cost over different prime moduli within the moduli chain of the Residue Number System (RNS). The proposed structure can support arbitrary numbers of security primes of CKKS during key exchange, which offers better security options for adopting the scalable design methodology.As a proof-of-concept, we implement CASA on the FPGA platform and compare it with state-of-the-art designs. The implementation results showcase the superior performance of the proposed CASA in many aspects such as compact area, scalable architecture, and overall better area-time complexities.In particular, we successfully implement CASA on a mainstream resource-constrained Artix-7 FPGA. To the authors’ best knowledge, this is the first compact CKKS accelerator implemented on an Artix-7 device, e.g., CASA achieves a 10.8x speedup compared with the state-of-the-art CPU implementations (with power consumption of only 5.8%). Considering the power-delay product metric, CASA also achieves 138x and 105x improvement compared with the recent GPU implementation.
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Riznyk, V. V. "FORMALIZATION CODING METHODS OF INFORMATION UNDER TOROIDAL COORDINATE SYSTEMS." Radio Electronics, Computer Science, Control, no. 2 (July 7, 2021): 144–53. http://dx.doi.org/10.15588/1607-3274-2021-2-15.
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Contents. Coding and processing large information content actualizes the problem of formalization of interdependence between information parameters of vector data coding systems on a single mathematical platform. Objective. The formalization of relationships between information parameters of vector data coding systems in the optimized basis of toroidal coordinate systems with the achievement of a favorable compromise between contradictory goals. Method. The method involves the establishing harmonious mutual penetration of symmetry and asymmetry as the remarkable property of real space, which allows use decoded information for forming the mathematical principle relating to the optimal placement of structural elements in spatially or temporally distributed systems, using novel designs based on the concept of Ideal Ring Bundles (IRB)s. IRBs are cyclic sequences of positive integers which dividing a symmetric sphere about center of the symmetry. The sums of connected sub-sequences of an IRB enumerate the set of partitions of a sphere exactly R times. Two-and multidimensional IRBs, namely the “Glory to Ukraine Stars”, are sets of t-dimensional vectors, each of them as well as all modular sums of them enumerate the set node points grid of toroid coordinate system with the corresponding sizes and dimensionality exactly R times. Moreover, we require each indexed vector data “category-attribute” mutually uniquely corresponds to the point with the eponymous set of the coordinate system. Besides, a combination of binary code with vector weight discharges of the database is allowed, and the set of all values of indexed vector data sets are the same that a set of numerical values. The underlying mathematical principle relates to the optimal placement of structural elements in spatially and/or temporally distributed systems, using novel designs based on tdimensional “star” combinatorial configurations, including the appropriate algebraic theory of cyclic groups, number theory, modular arithmetic, and IRB geometric transformations. Results. The relationship of vector code information parameters (capacity, code size, dimensionality, number of encodingvectors) with geometric parameters of the coordinate system (dimension, dimensionality, and grid sizes), and vector data characteristic (number of attributes and number of categories, entity-attribute-value size list) have been formalized. The formula system is derived as a functional dependency between the above parameters, which allows achieving a favorable compromise between the contradictory goals (for example, the performance and reliability of the coding method). Theorem with corresponding corollaries about the maximum vector code size of conversion methods for t-dimensional indexed data sets “category-attribute” proved. Theoretically, the existence of an infinitely large number of minimized basis, which give rise to numerous varieties of multidimensional “star” coordinate systems, which can find practical application in modern and future multidimensional information technologies, substantiated. Conclusions. The formalization provides, essentially, a new conceptual model of information systems for optimal coding and processing of big vector data, using novel design based on the remarkable properties and structural perfection of the “Glory to Ukraine Stars” combinatorial configurations. Moreover, the optimization has been embedded in the underlying combinatorial models. The favorable qualities of the combinatorial structures can be applied to vector data coded design of multidimensional signals, signal compression and reconstruction for communications and radar, and other areas to which the GUS-model can be useful. There are many opportunities to apply them to numerous branches of sciences and advanced systems engineering, including information technologies under the toroidal coordinate systems. A perfection, harmony and beauty exists not only in the abstract models but in the real world also.
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Jayakrishna, P., P. Sravani, R. Sakshitha Reddy, and S. Ashritha. "Design of High-Speed Area-Efficient VLSI Architecture of 32-Bit Three-Operand Binary Adder." International Journal for Research in Applied Science and Engineering Technology 11, no. 6 (June 30, 2023): 1353–61. http://dx.doi.org/10.22214/ijraset.2023.53550.
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Abstract: Adders are one of the most widely used digital components in digital integrated circuit design. With the advances in technology, the design that offers either high speed, low power consumption, less area, or a combination of them is designed. There are various processes performed by the digital circuits among which arithmetic operations are prominent. Three-operand binary adder is the basic functional unit to perform the modular arithmetic in various cryptography and pseudorandom bit generator (PRBG) algorithms. Carry save adder (CS3A) is the widely used technique to perform the three-operand addition. However, the ripple carry stage in the CS3A leads to a high propagation delay. Moreover, a parallel prefix two-operand adder such as Han-Carlson (HCA) can also be used for three-operand addition, significantly reducing the critical path delay at the cost of additional hardware. Hence, a new high-speed and area-efficient adder architecture is designed using pre-compute bitwise addition followed by carry prefix computation logic to perform the three-operand binary addition that consumes substantially less area, low power, and drastically reduces the adder delay. To design a faster computing system with less hardware we require some other architecture. The proposed architecture will reduce the area as well as the delay by replacing the Han-Carlson adder with the Ladner fisher adder in a Highspeed area-efficient three-operand binary adder. The proposed architecture is synthesized with the zynq-7000 library. The proposed architecture reduces the LUT count and delay by 20 and 0.4 nanoseconds respectively. By using these synthesis results, we noted the performance parameters like the number of LUTs and delay. We compared the adders in terms of LUTs (represents area) and delay value
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Sayed Ibrahim Ali, Et al. "Abacus Algorithms: A Pure Mathematical Approach to Ancient Calculation Tools." Advances in Nonlinear Variational Inequalities 26, no. 2 (December 1, 2023): 69–75. http://dx.doi.org/10.52783/anvi.v26.i2.270.
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The abacus is one of the oldest calculating tools still in use today. Despite its simplicity, the bead-based interface allows users to conduct complex mathematical operations through a system of sliding beads along wires or rods. While the physical abacus itself provides an intuitive and visual approach to calculation, the underlying operations rely on fundamental mathematical principles. This paper provides a comprehensive mathematical framework that formally describes the algorithms behind abacus calculations. Beginning with basic abacus configuration, we define key components like rods, beads, and bead values required to model abacus states. We then characterize the core abacus algorithms for addition, subtraction, multiplication, and division through set notation, recurrence relations, and state transition diagrams. Our formalized abacus algorithms leverage concepts from number theory, modular arithmetic, combinatorics, and algebra. In addition to offering new mathematical insights into ancient technologies, our work helps bridge connections between the tangible abacus interface and the abstract algorithms powering it. Through examples and proofs, we show how bead manipulations precisely correspond to mathematical transformations. This level of formalization not only helps explain the effectiveness of the abacus, but also illustrates how even rudimentary calculation tools utilize profound mathematical ideas. Our mathematical abacus framework lays the foundation for further analysis as well as modifications and extensions of the classic abacus approach.
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Roy, Indranil, Swathi Kaluvakuri, Koushik Maddali, Ziping Liu, and Bidyut Gupta. "Efficient Communication Protocols for Non DHT-based Pyramid Tree P2P Architecture." WSEAS TRANSACTIONS ON COMPUTERS 20 (July 23, 2021): 108–25. http://dx.doi.org/10.37394/23205.2021.20.13.
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In this paper, we have considered a recently reported 2-layer non-DHT-based structured P2P network. Residue Class based on modular arithmetic has been used to realize the overlay topology. At the heart of the architecture (layer-1), there exists a tree like structure, known as pyramid tree. It is not a conventional tree. A node i in this tree represents the cluster-head of a cluster of peers which are interested in a particular resource of type Ri (i.e. peers with a common interest). The cluster-head is the first among these peers to join the system. Root of the tree is assumed to be at level 1. Such a tree is a complete one if at each level j, there are j number of nodes. It is an incomplete one if only at its leaf level, say k, there are less than k number of nodes. Layer 2 consists of the different clusters. The network has some unique structural properties, e.g. each cluster has a diameter of only 1 overlay hop and the diameter of the network is just (2+2d); d being the number of levels of the layer-1 pyramid tree and d depends only on the number of distinct resources. Therefore, the diameter of the network is independent of the number of peers in the whole network. In the present work, we have used some such properties to design low latency intra and inter cluster data lookup protocols. Our choice of considering non-DHT and interest-based overlay networks is justified by the following facts: 1) intra-cluster data lookup protocol has constant complexity and complexity of inter-cluster data lookup is O(d) if tree traversal is used and 2) search latency is independent of the total number of peers present in the overlay network unlike any structured DHT-based network (as a matter fact unlike any existing P2P network, structured or unstructured). Experimental results as well show superiority of the proposed protocols to some noted structured networks from the viewpoints of search latency and complexity involved in it. In addition, we have presented in detail the process of handling churns and proposed a simple yet very effective technique related to cluster partitioning, which, in turn, helps in reducing the number of messages required to be exchanged to handle churns.
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Fox, Jacob, Max Wenqiang Xu, and Yunkun Zhou. "Discrepancy in modular arithmetic progressions." Compositio Mathematica 158, no. 11 (November 2022): 2082–108. http://dx.doi.org/10.1112/s0010437x22007758.
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Celebrated theorems of Roth and of Matoušek and Spencer together show that the discrepancy of arithmetic progressions in the first $n$ positive integers is $\Theta (n^{1/4})$ . We study the analogous problem in the $\mathbb {Z}_n$ setting. We asymptotically determine the logarithm of the discrepancy of arithmetic progressions in $\mathbb {Z}_n$ for all positive integer $n$ . We further determine up to a constant factor the discrepancy of arithmetic progressions in $\mathbb {Z}_n$ for many $n$ . For example, if $n=p^k$ is a prime power, then the discrepancy of arithmetic progressions in $\mathbb {Z}_n$ is $\Theta (n^{1/3+r_k/(6k)})$ , where $r_k \in \{0,1,2\}$ is the remainder when $k$ is divided by $3$ . This solves a problem of Hebbinghaus and Srivastav.
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Mahlburg, Karl, and Ken Ono. "Arithmetic of certain hypergeometric modular forms." Acta Arithmetica 113, no. 1 (2004): 39–55. http://dx.doi.org/10.4064/aa113-1-4.
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Safieh, Malek, Johann-Philipp Thiers, and Jürgen Freudenberger. "A Compact Coprocessor for the Elliptic Curve Point Multiplication over Gaussian Integers." Electronics 9, no. 12 (December 2, 2020): 2050. http://dx.doi.org/10.3390/electronics9122050.
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This work presents a new concept to implement the elliptic curve point multiplication (PM). This computation is based on a new modular arithmetic over Gaussian integer fields. Gaussian integers are a subset of the complex numbers such that the real and imaginary parts are integers. Since Gaussian integer fields are isomorphic to prime fields, this arithmetic is suitable for many elliptic curves. Representing the key by a Gaussian integer expansion is beneficial to reduce the computational complexity and the memory requirements of secure hardware implementations, which are robust against attacks. Furthermore, an area-efficient coprocessor design is proposed with an arithmetic unit that enables Montgomery modular arithmetic over Gaussian integers. The proposed architecture and the new arithmetic provide high flexibility, i.e., binary and non-binary key expansions as well as protected and unprotected PM calculations are supported. The proposed coprocessor is a competitive solution for a compact ECC processor suitable for applications in small embedded systems.