Dissertations / Theses on the topic 'Number system for modular arithmetic'
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Néto, João Carlos. "Método de multiplicação de baixa potência para criptosistema de chave-pública." Universidade de São Paulo, 2013. http://www.teses.usp.br/teses/disponiveis/3/3141/tde-23052014-010449/.
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Esta tese estuda a utilização da aritmética computacional para criptografia de chave pública (PKC Public-Key Cryptography) e investiga alternativas ao nível da arquitetura de sistema criptográfico em hardware que podem conduzir a uma redução no consumo de energia, considerando o baixo consumo de potência e o alto desempenho em dispositivos portáteis com energia limitada. A maioria desses dispositivos é alimentada por bateria. Embora o desempenho e a área de circuitos consistem desafios para o projetista de hardware, baixo consumo de energia se tornou uma preocupação em projetos de sistema críticos. A criptografia de chave pública é baseada em funções aritméticas como a exponenciação e multiplicação módulo. PKC prove um esquema de troca de chaves autenticada por meio de uma rede insegura entre duas entidades e fornece uma solução de grande segurança para a maioria das aplicações que devem trocar informações sensíveis. Multiplicação em módulo é largamente utilizada e essa operação aritmética é mais complexa porque os operandos são números extremamente grandes. Assim, métodos computacionais para acelerar as operações, reduzir o consumo de energia e simplificar o uso de tais operações, especialmente em hardware, são sempre de grande valor para os sistemas que requerem segurança de dados. Hoje em dia, um dos mais bem sucedidos métodos de multiplicação em módulo é a multiplicação de Montgomery. Os esforços para melhorar este método são sempre de grande importância para os projetistas de hardware criptográfico e de segurança em sistemas embarcados. Esta pesquisa trata de algoritmos para criptografia de baixo consumo de energia. Abrange as operações necessárias para implementações em hardware da exponenciação e da multiplicação em módulo. Em particular, esta tese propõe uma nova arquitetura para a multiplicação em módulo chamado \"Parallel k-Partition Montgomery Multiplication\" e um projeto inovador em hardware para calcular a exponenciação em módulo usando o sistema numérico por resíduos (RNS).This thesis studies the use of computer arithmetic for Public-Key Cryptography (PKC) and investigates alternatives on the level of the hardware cryptosystem architecture that can lead to a reduction in the energy consumption by considering low power and high performance in energy-limited portable devices. Most of these devices are battery powered. Although performance and area are the two main hardware design goals, low power consumption has become a concern in critical system designs. PKC is based on arithmetic functions such as modular exponentiation and modular multiplication. It produces an authenticated key-exchange scheme over an insecure network between two entities and provides the highest security solution for most applications that must exchange sensitive information. Modular multiplication is widely used, and this arithmetic operation is more complex because the operands are extremely large numbers. Hence, computational methods to accelerate the operations, reduce the energy consumption, and simplify the use of such operations, especially in hardware, are always of great value for systems that require data security. Currently, one of the most successful modular multiplication methods is Montgomery Multiplication. Efforts to improve this method are always important to designers of dedicated cryptographic hardware and security in embedded systems. This research deals with algorithms for low-power cryptography. It covers operations required for hardware implementations of modular exponentiation and modular multiplication. In particular, this thesis proposes a new architecture for modular multiplication called Parallel k-Partition Montgomery Multiplication and an innovative hardware design to perform modular exponentiation using Residue Number System (RNS).
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Dosso, Fangan Yssouf. "Contribution de l'arithmétique des ordinateurs aux implémentations résistantes aux attaques par canaux auxiliaires." Electronic Thesis or Diss., Toulon, 2020. http://www.theses.fr/2020TOUL0007.
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Cette thèse porte sur deux éléments actuellement incontournables de la cryptographie à clé publique, qui sont l’arithmétique modulaire avec de grands entiers et la multiplication scalaire sur les courbes elliptiques (ECSM). Pour le premier, nous nous intéressons au système de représentation modulaire adapté (AMNS), qui fut introduit par Bajard et al. en 2004. C’est un système de représentation de restes modulaires dans lequel les éléments sont des polynômes. Nous montrons d’une part que ce système permet d’effectuer l’arithmétique modulaire de façon efficace et d’autre part comment l’utiliser pour la randomisation de cette arithmétique afin de protéger l’implémentation des protocoles cryptographiques contre certaines attaques par canaux auxiliaires. Pour l’ECSM, nous abordons l’utilisation des chaînes d’additions euclidiennes (EAC) pour tirer parti de la formule d’addition de points efficace proposée par Méloni en 2007. L’objectif est d’une part de généraliser au cas d’un point de base quelconque l’utilisation des EAC pour effectuer la multiplication scalaire ; cela, grâce aux courbes munies d’un endomorphisme efficace. D’autre part, nous proposons un algorithme pour effectuer la multiplication scalaire avec les EAC, qui permet la détection de fautes qui seraient commises par un attaquant que nous détaillonsThis thesis focuses on two currently unavoidable elements of public key cryptography, namely modular arithmetic over large integers and elliptic curve scalar multiplication (ECSM). For the first one, we are interested in the Adapted Modular Number System (AMNS), which was introduced by Bajard et al. in 2004. In this system of representation, the elements are polynomials. We show that this system allows to perform modular arithmetic efficiently. We also explain how AMNS can be used to randomize modular arithmetic, in order to protect cryptographic protocols implementations against some side channel attacks. For the ECSM, we discuss the use of Euclidean Addition Chains (EAC) in order to take advantage of the efficient point addition formula proposed by Meloni in 2007. The goal is to first generalize to any base point the use of EAC for ECSM; this is achieved through curves with one efficient endomorphism. Secondly, we propose an algorithm for scalar multiplication using EAC, which allows error detection that would be done by an attacker we detail
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Marrez, Jérémy. "Représentations adaptées à l'arithmétique modulaire et à la résolution de systèmes flous." Electronic Thesis or Diss., Sorbonne université, 2019. https://accesdistant.sorbonne-universite.fr/login?url=https://theses-intra.sorbonne-universite.fr/2019SORUS635.pdf.
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Les calculs modulaires entrant en jeu dans les applications en cryptographie asymétrique utilisent le plus souvent un modulo premier standardisé, dont le choix n’est pas toujours libre en pratique. L’amélioration des opérations modulaires est centrale pour l’efficacité et la sécurité de ces primitives. Cette thèse propose de fournir une arithmétique modulaire efficace pour le plus grand nombre de premiers possible, tout en la prémunissant contre certains types d’attaques. Pour ce faire, nous nous intéressons au système PMNS utilisé pour l’arithmétique modulaire, et proposons des méthodes afin d’obtenir de nombreux PMNS pour un premier donné, avec une arithmétique efficace sur les représentations. Nous considérons également la randomisation des calculs modulaires via des algorithmes de type Montgomery et Babaï en exploitant la redondance intrinsèque aux PMNS. Les changements induits de représentation des données au cours du calcul empêchent un attaquant d’effectuer des hypothèses utiles sur ces représentations. Nous présentons ensuite un système hybride, HyPoRes, avec un algorithme améliorant les réductions modulaires pour tout modulo premier. Les nombres sont représentés dans un PMNS avec des coefficients en RNS. La réduction modulaire est plus rapide qu’en RNS classique pour les premiers standardisés pour ECC. En parallèle, nous étudions un type de représentation utilisé pour la résolution réelle de systèmes flous. Nous revisitons l’approche globale de résolution faisant appel à des techniques algébriques classiques et la renforçons. Ces résultats incluent un système réel appelé la transformation réelle qui simplifie les calculs, et la gestion des signes des solutionsModular computations involved in public key cryptography applications most often use a standardized prime modulo, the choice of which is not always free in practice. The improvement of modular operations is fundamental for the efficiency and safety of these primitives. This thesis proposes to provide an efficient modular arithmetic for the largest possible number of primes, while protecting it against certain types of attacks. For this purpose, we are interested in the PMNS system used for modular arithmetic, and propose methods to obtain many PMNS for a given prime, with an efficient arithmetic on the representations. We also consider the randomization of modular computations via algorithms of type Montgomery and Babaï by exploiting the intrinsic redundancy of PMNS. Induced changes of data representation during the calculation prevent an attacker from making useful assumptions about these representations. We then present a hybrid system, HyPoRes , with an algorithm that improves modular reductions for any prime modulo. The numbers are represented in a PMNS with coefficients in RNS. The modular reduction is faster than in conventional RNS for the primes standardized for ECC. In parallel, we are interested in a type of representation used to compute real solutions of fuzzy systems. We revisit the global approach of resolution using classical algebraic techniques and strengthen it. These results include a real system called the real transform that simplifies computations, and the management of the signs of the solutions
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Vonk, Jan Bert. "The Atkin operator on spaces of overconvergent modular forms and arithmetic applications." Thesis, University of Oxford, 2015. http://ora.ox.ac.uk/objects/uuid:081e4e46-80c1-41e7-9154-3181ccb36313.
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We investigate the action of the Atkin operator on spaces of overconvergent p-adic modular forms. Our contributions are both computational and geometric. We present several algorithms to compute the spectrum of the Atkin operator, as well as its p-adic variation as a function of the weight. As an application, we explicitly construct Heegner-type points on elliptic curves. We then make a geometric study of the Atkin operator, and prove a potential semi-stability theorem for correspondences. We explicitly determine the stable models of various Hecke operators on quaternionic Shimura curves, and make a purely geometric study of canonical subgroups.
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Schill, Collberg Adam. "The last two digits of mk." Thesis, Linköpings universitet, Matematiska institutionen, 2012. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-78532.
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In this thesis the last two digits of m^k, for different cases of the positive integers m and k, in the base of 10 has been determined. Moreover, using fundamental theory from elementary number theory and abstract algebra, results most helpful in finding the last two digits in any base b has been regarded and developed, such as how to reduce large m and k to more manageable numbers.
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Zhu, Dalin. "Residue number system arithmetic inspired applications in cellular downlink OFDMA." Thesis, Manhattan, Kan. : Kansas State University, 2009. http://hdl.handle.net/2097/2070.
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Arnold-Roksandich, Allison F. "There and Back Again: Elliptic Curves, Modular Forms, and L-Functions." Scholarship @ Claremont, 2014. http://scholarship.claremont.edu/hmc_theses/61.
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Younes, Dina. "Využití systému zbytkových tříd pro zpracování digitálních signálů." Doctoral thesis, Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií, 2013. http://www.nusl.cz/ntk/nusl-233606.
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Předkládaná disertační práce se zabývá návrhem základních bloků v systému zbytkových tříd pro zvýšení výkonu aplikací určených pro digitální zpracování signálů (DSP). Systém zbytkových tříd (RNS) je neváhová číselná soustava, jež umožňuje provádět paralelizovatelné, vysokorychlostní, bezpečné a proti chybám odolné aritmetické operace, které jsou zpracovávány bez přenosu mezi řády. Tyto vlastnosti jej činí značně perspektivním pro použití v DSP aplikacích náročných na výpočetní výkon a odolných proti chybám. Typický RNS systém se skládá ze tří hlavních částí: převodníku z binárního kódu do RNS, který počítá ekvivalent vstupních binárních hodnot v systému zbytkových tříd, dále jsou to paralelně řazené RNS aritmetické jednotky, které provádějí aritmetické operace s operandy již převedenými do RNS. Poslední část pak tvoří převodník z RNS do binárního kódu, který převádí výsledek zpět do výchozího binárního kódu. Hlavním cílem této disertační práce bylo navrhnout nové struktury základních bloků výše zmiňovaného systému zbytkových tříd, které mohou být využity v aplikacích DSP. Tato disertační práce předkládá zlepšení a návrhy nových struktur komponent RNS, simulaci a také ověření jejich funkčnosti prostřednictvím implementace v obvodech FPGA. Kromě návrhů nové struktury základních komponentů RNS je prezentován také podrobný výzkum různých sad modulů, který je srovnává a determinuje nejefektivnější sadu pro různé dynamické rozsahy. Dalším z klíčových přínosů disertační práce je objevení a ověření podmínky určující výběr optimální sady modulů, která umožňuje zvýšit výkonnost aplikací DSP. Dále byla navržena aplikace pro zpracování obrazu využívající RNS, která má vůči klasické binární implementanci nižší spotřebu a vyšší maximální pracovní frekvenci. V závěru práce byla vyhodnocena hlavní kritéria při rozhodování, zda je vhodnější pro danou aplikaci využít binární číselnou soustavu nebo RNS.
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Patel, Riyaz Aziz. "A study and implementation of parallel-prefix modular adder architectures for the residue number system." Thesis, University of Sheffield, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.434492.
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Händel, Milene. "Circuitos aritméticos e representação numérica por resíduos." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/12670.
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Este trabalho mostra os diversos sistemas de representação numérica, incluindo o sistema numérico normalmente utilizado em circuitos e alguns sistemas alternativos. Uma maior ênfase é dada ao sistema numérico por resíduos. Este último apresenta características muito interessantes para o desenvolvimento de circuitos aritméticos nos dias atuais, como por exemplo, a alta paralelização. São estudadas também as principais arquiteturas de somadores e multiplicadores. Várias descrições de circuitos aritméticos são feitas e sintetizadas. A arquitetura de circuitos aritméticos utilizando o sistema numérico por resíduos também é estudada e implementada. Os dados da síntese destes circuitos são comparados com os dados dos circuitos aritméticos tradicionais. Com isto, é possível avaliar as potenciais vantagens de se utilizar o sistema numérico por resíduos no desenvolvimento de circuitos aritméticos.This work shows various numerical representation systems, including the system normally used in current circuits and some alternative systems. A great emphasis is given to the residue number system. This last one presents very interesting characteristics for the development of arithmetic circuits nowadays, as for example, the high parallelization. The main architectures of adders and multipliers are also studied. Some descriptions of arithmetic circuits are made and synthesized. The architecture of arithmetic circuits using the residue number system is also studied and implemented. The synthesis data of these circuits are compared with the traditional arithmetic circuits results. Then it is possible to evaluate the potential advantages of using the residue number system in arithmetic circuits development.
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Bowlyn, Kevin Nathaniel. "IMPLEMENTATION OF A NOVEL INTEGRATED DISTRIBUTED ARITHMETIC AND COMPLEX BINARY NUMBER SYSTEM IN FAST FOURIER TRANSFORM ALGORITHM." OpenSIUC, 2017. https://opensiuc.lib.siu.edu/dissertations/1470.
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This research focuses on a novel integrated approach for computing and representing complex numbers as a single entity without the use of any dedicated multiplier for calculating the fast Fourier transform algorithm (FFT), using the Distributed Arithmetic (DA) technique and Complex Binary Number Systems (CBNS). The FFT algorithm is one of the most used and implemented technique employed in many Digital Signal Processing (DSP) applications in the field of science, engineering, and mathematics. The DA approach is a technique that is used to compute the inner dot product between two vectors without the use of any dedicated multipliers. These dedicated multipliers are fast but they consume a large amount of hardware and are quite costly. The DA multiplier process is accomplished by shifting and adding only without the need of any dedicated multiplier. In today's technology, complex numbers are computed using the divide and conquer approach in which complex numbers are divided into two parts: the real and imaginary. The CBNS technique however, allows for each complex addition and multiplication to be computed in one single step instead of two. With the combined DA-CBNS approach for computing the FFT algorithm, those dedicated multipliers are being replaced with a DA system that utilize a Rom-based memory for storing the twiddle factor 'wn' value and the complex arithmetic operations being represented as a single entity, not two, with the CBNS approach. This architectural design was implemented by coding in a very high speed integrated circuit (VHSIC) hardware description language (VHDL) using Xilinx ISE design suite software program version 14.2. This computer aided tool allows for the design to be synthesized to a logic gate level in order to be further implemented onto a Field Programmable Gate Array (FPGA) device. The VHDL code used to build this architecture was downloaded on a Nexys 4 DDR Artix-7 FPGA board for further testing and analysis. This novel technique resulted in the use of no dedicated multipliers and required half the amount of complex arithmetic computations needed for calculating an FFT structure compared with its current traditional approach. Finally, the results showed that for the proposed architecture design, for a 32 bit, 8-point DA-CBNS FFT structure, the results showed a 32% area reduction, 41% power reduction, 59% reduction in run-time, 42% reduction in logic gate cost, and 66% increase in speed. For a 28 bit, 16-point DA-CBNS FFT structure, its area size, power consumption, run-time, and logic gate, were also found to be reduced at approximately 30%, 37%, 60%, and 39%, respectively, with an increase of speed of approximately 67% when compared to the traditional approach that employs dedicated multipliers and computes its complex arithmetic as two separate entities: the real and imaginary.
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Priebe, Débora Danielle Alves Moraes. "Tópicos de aritmética para as séries finais do ensino fundamental: uma proposta focada na resolução de problemas." Universidade Federal de Goiás, 2016. http://repositorio.bc.ufg.br/tede/handle/tede/6585.
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This paper aims to present an educational proposal of some topics of arithmetic, also called Number Theory, for the final grades of elementary school, focusing on solving problems to challenge and entertain students with the range of possibilities arising from properties of Number Theory and develop their thinking skills through interesting problems that will give a new life to the subject . The reader will find in this work topics of divisibility, primes, Greatest Common Divisor, Least Common Multiple, Euclidean Algorithm, congruences, decimal representation, divisibility tests, as well as several examples, challenging problems and also curiosities about the congruence module 9.
Este trabalho tem como objetivo apresentar uma proposta de ensino de alguns tópicos de Aritmética, também denominada de Teoria dos Números, às séries finais do Ensino Fundamental, com foco na resolução de problemas, visando desafiar e fascinar os alunos com a gama de possibilidades oriunda das propriedades da Teoria dos Números e desenvolver sua capacidade de raciocínio através de problemas interessantes que darão uma nova vida ao assunto. O leitor encontrará neste trabalho tópicos de divisibilidade, primos, Máximo Divisor Comum, Mínimo Múltiplo Comum, Algoritmo de Euclides, congruências, representação decimal, testes de divisibilidade, além de diversos exemplos, problemas desafiadores e também curiosidades acerca da congruência módulo 9.
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Uguen, Yohann. "High-level synthesis and arithmetic optimizations." Thesis, Lyon, 2019. http://www.theses.fr/2019LYSEI099.
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À cause de la nature relativement jeune des outils de synthèse de haut-niveau (HLS), de nombreuses optimisations arithmétiques n'y sont pas encore implémentées. Cette thèse propose des optimisations arithmétiques se servant du contexte spécifique dans lequel les opérateurs sont instanciés. Certaines optimisations sont de simples spécialisations d'opérateurs, respectant la sémantique du C. D'autres nécessitent de s'éloigner de cette sémantique pour améliorer le compromis précision/coût/performance. Cette proposition est démontrée sur des sommes de produits de nombres flottants. La somme est réalisée dans un format en virgule-fixe défini par son contexte. Quand trop peu d’informations sont disponibles pour définir ce format en virgule-fixe, une stratégie est de générer un accumulateur couvrant l'intégralité du format flottant. Cette thèse explore plusieurs implémentations d'un tel accumulateur. L'utilisation d'une représentation en complément à deux permet de réduire le chemin critique de la boucle d'accumulation, ainsi que la quantité de ressources utilisées. Un format alternatif aux nombres flottants, appelé posit, propose d'utiliser un encodage à précision variable. De plus, ce format est augmenté par un accumulateur exact. Pour évaluer précisément le coût matériel de ce format, cette thèse présente des architectures d'opérateurs posits, implémentés avec le même degré d'optimisation que celui de l'état de l'art des opérateurs flottants. Une analyse détaillée montre que le coût des opérateurs posits est malgré tout bien plus élevé que celui de leurs équivalents flottants. Enfin, cette thèse présente une couche de compatibilité entre outils de HLS, permettant de viser plusieurs outils avec un seul code. Cette bibliothèque implémente un type d'entiers de taille variable, avec de plus une sémantique strictement typée, ainsi qu'un ensemble d'opérateurs ad-hoc optimisésHigh-level synthesis (HLS) tools offer increased productivity regarding FPGA programming. However, due to their relatively young nature, they still lack many arithmetic optimizations. This thesis proposes safe arithmetic optimizations that should always be applied. These optimizations are simple operator specializations, following the C semantic. Other require to a lift the semantic embedded in high-level input program languages, which are inherited from software programming, for an improved accuracy/cost/performance ratio. To demonstrate this claim, the sum-of-product of floating-point numbers is used as a case study. The sum is performed on a fixed-point format, which is tailored to the application, according to the context in which the operator is instantiated. In some cases, there is not enough information about the input data to tailor the fixed-point accumulator. The fall-back strategy used in this thesis is to generate an accumulator covering the entire floating-point range. This thesis explores different strategies for implementing such a large accumulator, including new ones. The use of a 2's complement representation instead of a sign+magnitude is demonstrated to save resources and to reduce the accumulation loop delay. Based on a tapered precision scheme and an exact accumulator, the posit number systems claims to be a candidate to replace the IEEE floating-point format. A throughout analysis of posit operators is performed, using the same level of hardware optimization as state-of-the-art floating-point operators. Their cost remains much higher that their floating-point counterparts in terms of resource usage and performance. Finally, this thesis presents a compatibility layer for HLS tools that allows one code to be deployed on multiple tools. This library implements a strongly typed custom size integer type along side a set of optimized custom operators
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Shivashankar, Nithin. "Design and Analysis of Modular Architectures for an RNS to Mixed Radix Conversion Multi-processor." University of Cincinnati / OhioLINK, 2014. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1396531505.
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Möller, Kristian. "Visuellt typinstrument : en metrologisk studie." Thesis, Konstfack, Grafisk Design & Illustration, 2014. http://urn.kb.se/resolve?urn=urn:nbn:se:konstfack:diva-5162.
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Visual Type Instrument - VTI, is a tool containing a typeface and a set of geometric calculations that generates numerical data in spreadsheets. The data is determined from the typefaces visual dimensions and is used to calculate leading, type size, margins and format. The aim is to offer, for all of those working with typography and design, a practical way to manage text, image and format in relationship to visual size. Instead of using point measurements, VTI uses a new device called Edo. An Edo is the same as one twelfth of a millimetre. This makes VTI compatible with the metric system and helps us to set text in relation to our own formats which applies namely in millimetres. VTI uses logical arithmetic and geometry that is set in an automated process, and many choices that normally postpone the working process can be excluded. Simultaneously VTI is meant to discreetly make the user aware that more settings can be activated in line with the users own development, which makes the creative flow unaffected. Using a metrics based on simple fractions, a mnemonic awareness is developed with the user and an understanding of how every detail fits together becomes more obvious. The typography becomes the key to any design choices that follows. The user becomes aware of the visual size, and in a cognitive way stimulated to recreate a font size regardless of the fonts limitations.
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Wu, Henry M. "A Multiprocessor Architecture Using Modular Arithmetic for Very High Precision Computation." 1989. http://hdl.handle.net/1721.1/6021.
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We outline a multiprocessor architecture that uses modular arithmetic to implement numerical computation with 900 bits of intermediate precision. A proposed prototype, to be implemented with off-the-shelf parts, will perform high-precision arithmetic as fast as some workstations and mini- computers can perform IEEE double-precision arithmetic. We discuss how the structure of modular arithmetic conveniently maps into a simple, pipelined multiprocessor architecture. We present techniques we developed to overcome a few classical drawbacks of modular arithmetic. Our architecture is suitable to and essential for the study of chaotic dynamical systems.
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Kong, Yinan. "Modular multiplication in the residue number system." Thesis, 2009. http://hdl.handle.net/2440/101502.
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Public-key cryptography is a mechanism for secret communication between parties who have never before exchanged a secret message. This thesis contributes arithmetic algorithms and hardware architectures for the modular multiplication Z = A × B mod M. This operation is the basis of many public-key cryptosystems including RSA and Elliptic Curve Cryptography. The Residue Number System (RNS) is used to speed up long word length modular multiplication because this number system performs certain long word length operations, such as multiplication and addition, much more efficiently than positional systems. A survey of current modular multiplication algorithms shows that most work in a positional number system, e.g. binary. A new classification is developed which classes these algorithms as Classical, Sum of Residues, Montgomery or Barrett. Each class of algorithm is analyzed in detail, new developments are described, and the improved algorithms are implemented and compared using FPGA hardware. Few modular multiplication algorithms for use in the RNS have been published. Most are concerned with short word lengths and are not applicable to public-key cryptosystems that require long word length operations. This thesis sets out the hypothesis that each of the four classes of modular multiplication algorithms possible in positional number systems can also be used for long word length modular multiplication in the RNS; moreover using the RNS in this way will lead to faster implementations than those which restrict themselves to positional number systems. This hypothesis is addressed by developing new Classical, Sum of Residues and Barrett algorithms for modular multiplication in the RNS. Existing Montgomery RNS algorithms are also discussed. The new Sum of Residues RNS algorithm results in a hardware implementation that is novel in many aspects: a highly parallel structure using short arithmetic operations within the RNS; fully scalable hardware; and the fastest ever FPGA implementation of the 1024-bit RSA cryptosystem at 0.4 ms per decryption.Thesis (Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2009.
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Alhazmi, Bader Hammad. "Fast prime field arithmetic using novel large integer representation." Thesis, 2019. http://hdl.handle.net/1828/10955.
Full textAbstract:
Large integers are used in several key areas such as RSA (Rivest-Shamir-Adleman) public-key cryptographic system and elliptic curve public-key cryptographic system. To achieve higher levels of security requires larger key size and this becomes a limiting factor in prime finite field GF(p) arithmetic using large integers because operations on large integers suffer from the long carry propagation problem. Large integer representation has direct impact on the efficiency of the calculations and the hardware and software implementations. Attempts to use different representations such as residue number systems suffer from their own problems. In this dissertation, we propose a novel and efficient attribute-based large integer representation scheme capable of efficiently representing the large integers that are commonly used in cryptography such as the five NIST primes and the Pierpont primes used in supersingular isogeny Diffie-Hellman (SIDH) used in post-quantum cryptography. Moreover, we propose algorithms for this new representation to perform arithmetic operations such as conversions from and to binary representation, two’s complement, left-shift, numbers comparison, addition/subtraction, modular addition/subtraction, modular reduction, multiplication, and modular multiplication. Extensive numerical simulations and software implementations are done to verify the performance of the new number representation. Results show that the attribute-based large integer arithmetic operations are done faster in our proposed representation when compared with binary and residue number representations. This makes the proposed representation suitable for cryptographic applications on embedded systems and IoT devices with limited resources for better security level.Graduate
2020-07-04
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Βασσάλος, Ευάγγελος. "Σχεδίαση κυκλωμάτων με πλεονάζουσες και μη αναπαραστάσεις για το αριθμητικό σύστημα υπολοίπων." Thesis, 2013. http://hdl.handle.net/10889/6353.
Full textAbstract:
Η υλοποίηση αποδοτικών αριθμητικών κυκλωμάτων αποτελεί ένα ανοικτό πεδίο έρευνας καθώς η συνεχής εξέλιξη της τεχνολογίας απαιτεί την επανεκτίμηση των μεθόδων σχεδίασής τους, ενώ παράλληλα δημιουργεί νέους τομείς εφαρμογής τους. Ο τεράστιος όγκος πληροφορίας και η ανάγκη γρήγορης επεξεργασίας της έχει οδηγήσει στην ανάγκη αύξησης της συχνότητας λειτουργίας των αντίστοιχων κυκλωμάτων. Μεγάλης σημασίας παραμένει επίσης η ανάγκη για τη μείωση της κατανάλωσης ισχύος των συστημάτων αυτών, αλλά και του κόστους τους, που συνδέονται άμεσα με την επιφάνεια ολοκλήρωσής τους. Η ικανοποίηση των παραμέτρων αυτών επιτάσσει σε διάφορες περιπτώσεις την υιοθέτηση αριθμητικών συστημάτων, πέραν του συμβατικού δυαδικού συστήματος. Χαρακτηριστικά παραδείγματα αποτελούν το Αριθμητικό Σύστημα Υπολοίπων (Residue Number System – RNS) όπως επίσης και τα αριθμητικά συστήματα πλεοναζουσών αναπαραστάσεων (redundant number systems).
Η διδακτορική αυτή διατριβή ασχολείται με την υλοποίηση αποδοτικών κυκλωμάτων για το Αριθμητικό Σύστημα Υπολοίπων, με την έρευνα να επικεντρώνεται στην υιοθέτηση τόσο πλεοναζουσών όσο και μη-πλεοναζουσών αναπαραστάσεων στα διάφορα κανάλια επεξεργασίας του.
Το πρώτο μέρος της διατριβής έχει ως στόχο τη σχεδίαση αποδοτικών κυκλωμάτων υπολοίπων με χρήση μη-πλεοναζουσών αναπαραστάσεων τόσο για τις κύριες-βασικές αριθμητικές πράξεις (πρόσθεση, πολλαπλασιασμός) όσο και για τις δευτερεύουσες-βοηθητικές (αφαίρεση, ύψωση σε δύναμη) πράξεις. Συγκεκριμένα, παρουσιάζονται κυκλώματα αφαίρεσης και πρόσθεσης/αφαίρεσης για κανάλια υπολοίπου της μορφής 2^n+-1, κυκλώματα πολλαπλασιασμού με σταθερά για το σύνολο διαιρετών {2^n-1, 2^n, 2^n+1} καθώς και κυκλώματα Booth πολλαπλασιασμού προγραμματιζόμενης λογικής για τα κανάλια υπολοίπου 2^n+-1. Επιπλέον, παρουσιάζονται κυκλώματα ύψωσης στον κύβο για το κανάλι υπολοίπου 2^n-1. Προτείνεται επίσης μια οικογένεια αριθμητικών κυκλωμάτων (αθροιστές, αφαιρέτες, πολλαπλασιαστές, κυκλώματα ύψωσης στο τετράγωνο) υπολοίπου 2^n+1 για την αναπαράσταση ελάττωσης κατά 1, που ενσωματώνουν τη μετατροπή του αποτελέσματος στην κανονική αναπαράσταση μέσα στην αρχιτεκτονική τους, ενώ παρουσιάζεται και μία ενιαία μεθοδολογία σχεδίασης κυκλωμάτων ανάστροφης μετατροπής για σύνολα διαιρετών με κανάλια της μορφής 2^n+1 που υιοθετούν την αναπαράσταση ελάττωσης κατά 1. Τέλος, διερευνούνται και οι διαιρέτες της μορφής 2^n-2 και προτείνονται για αυτούς αποδοτικές αρχιτεκτονικές κυκλωμάτων πρόσθεσης, πολλαπλασιασμού, ύψωσης στο τετράγωνο και ευθείας μετατροπής.
Στο δεύτερο μέρος της διατριβής το ενδιαφέρον εστιάζεται σε μία διαφορετική κατηγορία αναπαραστάσεων, οι οποίες παρέχουν περισσότερους από ένα δυνατούς τρόπους κωδικοποίησης των εντέλων τους. Οι πλεονάζουσες αυτές αναπαραστάσεις παρουσιάζουν συγκεκριμένα χαρακτηριστικά, όπως η δυνατότητα εξισορρόπησης ταχύτητας και επιφάνειας υλοποίησης. Στη διατριβή εξετάζονται τρεις πλεονάζουσες αναπαραστάσεις για το Αριθμητικό Σύστημα Υπολοίπων με κανάλια διαιρετών της μορφής 2^n+-1 και παρουσιάζεται μία γενικευμένη μεθοδολογία διαχείρισης των ψηφίων τους, η οποία εφαρμόζεται στη σχεδίαση κυκλωμάτων μετατροπής.
Στο τελευταίο μέρος περιγράφονται δύο εφαρμογές συστημάτων που βασίζονται στο Αριθμητικό Σύστημα Υπολοίπων. Αναλυτικότερα, σχεδιάζεται και υλοποιείται ένα σύστημα ανίχνευσης ακμών σε εικόνα με ένα στάδιο προ-επεξεργασίας για μείωση του θορύβου καθώς και τρία φίλτρα πεπερασμένης κρουστικής απόκρισης.The implementation of efficient arithmetic circuits has always been an open field for research, since the technology evolves rapidly, demanding the reevaluation of their design methods. At the same time this continuous evolution opens new research areas for these circuits. The need for fast processing of a vast amount of information demands an increase of the operational frequency of the corresponding circuits, while at the same time low power consumption, low cost and therefore low area remain of crucial importance. Meeting these needs in arithmetic circuits usually implies the employment of alternative, non-binary number systems. Such examples are the Residue Number System (RNS) and number systems with redundant representations. The subject of this PhD dissertation is the implementation of efficient arithmetic circuits for the RNS emphasizing both in redundant and not redundant representations. The first part of the dissertation deals with the design of efficient non-redundant arithmetic circuits for main arithmetic operations such as addition and multiplication that are met in every processing system, as well as for auxiliary operations like subtraction, squaring and cubing. Specifically, the circuits presented include subtractors and adders/subtractors for the moduli channels of the 2^n+-1 form, single-constant multipliers for the {2^n-1, 2^n, 2^n+1} moduli set, configurable modulo 2^n +-1 Booth-encoded multipliers as well as modulo 2^n-1 cubing units. Furthermore, a family of diminished-1 modulo 2^n+1 arithmetic circuits (adders, subtractors, multipliers and squarers) is also presented, that produces the respective result directly to weighted (normal) representation, embedding that way the conversion process between these two representations. The design of efficient Residue-to-Binary converters is also considered and a novel generic methodology is proposed for the systematic design of those circuits. The modulo 2^n-2 channel is also investigated and an arithmetic processing framework is proposed including adders, multipliers, squarers and Binary-to-Residue converters. In the second part, we focus on a different category of representations, where operands can be encoded in more than one ways. Such representations offer certain characteristics such as a tradeoff between area and speed. In particular, we consider three redundant representations for the RNS processing channels of the 2^n+-1 form, which are the most common choice. A generic methodology is presented for treating their digits in order to design efficient converters for them. The last part of the dissertation presents two applications that are implemented entirely in the RNS domain. Their architectures rely on the proposed arithmetic circuits. The first application is an image edge detector with a pre-processing noise filtering stage. The second application involves the design of three Finite Impulse Response (FIR) filters.
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Garcia, Jesus. "Applying the logarithmic number system to application-specific designs /." Diss., 2004. http://gateway.proquest.com/openurl?url_ver=Z39.88-2004&rft_val_fmt=info:ofi/fmt:kev:mtx:dissertation&res_dat=xri:pqdiss&rft_dat=xri:pqdiss:3147317.
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Liu, Li-wei, and 劉力維. "Implementation of Logarithm Number System Arithmetic on ARM embedded system and its application." Thesis, 2009. http://ndltd.ncl.edu.tw/handle/41577198868032772922.
Full textAbstract:
碩士逢甲大學
資訊工程所
97
Arithmetic units are the main components for microprocessors and digital signal processors. With a suitable arithmetic number system, the performance of the processors can be enhanced. In this thesis, our research objective is to compare the performance of the floating-point (FLP) number system arithmetic and logarithmic number system (LNS) arithmetic that are implemented in software on a Socle ARM926EJ-S embedded platform. This research is based on the observation that low-end ARM processors usually don’t support the hardware for FLP arithmetic instructions. The software implementation of LNS arithmetic can be considered as a good alternative for FLP arithmetic. The computation of the LNS addition and subtraction needs to compute the computation of the function which involves the computation of the exponential and logarithmic functions. The computation of these two functions is performed by using Taylor series expansion and table lookup methods. The operations of LNS arithmetic include addition, subtraction, multiplication, division, and powering (A^B, with A and B being in LNS format).The speedup factors of these operations in LNS arithmetic are 0.403, 0.314, 10.84, 12.07 and 15.91, respectively, in the ADS1.2 platform without operation system. On the other hand, if these operations are performed under operating system in the cross compiler platform, the speedup factors are 0.482, 0.292, 7.81, 9.9, and 17.194, respectively. We also used our designed LNS arithmetic on the Socle CDK board to implement the image tracking system whose tracking algorithm is based on the Kullback-Leibler (KL) divergence method. Because the KL divergence method needs to perform a great deal of series multiplication and powering operations, the LNS arithmetic implementation will gain a large speedup over the FLP arithmetic implementation. Our experimental results show that an average speedup factor equal to 21.45 can be obtained.
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Huang, Kai-Hung, and 黃凱弘. "Efficiency of Arithmetic Representations Using Hybrid Number System to Implement on FPGA." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/45168035139764393362.
Full textAbstract:
碩士淡江大學
電機工程學系碩士班
102
In this paper, we developed a hardware intelligent controller, such as TS-CMAC, implemented on a field programmable gate array (FPGA) platform. We also discuss the impact of arithmetic representation on computing performance of controller. In addition, we implemented a 32-bit hybrid number system processor for TS-CMAC arithmetic operations. However, arithmetic representations for intelligent controller is dependent on computing performance. The tradeoff between precision and representation along with FPGA logic element costs requirements are considered. Therefore, our hardware system architecture seek to fill the gap between why. We proposed hybrid number system for our controller arithmetic representation. The hardware system architecture has advantages: i) low costs of hardware logic element; ii) high computing performance; iii) high accuracy of arithmetic operation. According to experimental results, TS-CMAC arithmetic operation speed can be increased effectively by hybrid number system which can not only reduce area occupied of hardware but also maintain high precision in arithmetic hardware design, and thus enhance TS-CMAC accuracy in intelligent control .
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Sankaran, Siddarth. "Special Cycles on Shimura Curves and the Shimura Lift." Thesis, 2012. http://hdl.handle.net/1807/34874.
Full textAbstract:
The main results of this thesis describe a relationship between two families of arithmetic divisors on an integral model of a
Shimura curve. The first family, studied by Kudla, Rapoport and Yang, parametrizes abelian surfaces with specified endomorphism structure. The second family is comprised of pullbacks of arithmetic cycles on integral models of Shimura varieties associated to unitary groups of signature (1,1). In
the thesis, we construct these families of cycles, and describe their relationship, which is expressed in terms of the ``Shimura lift", a classical tool in the theory of modular forms of half-integral weight. This relations can be viewed as further evidence for the modularity of generating series of arithmetic "special cycles" for
U(1,1), and fits broadly into Kudla's programme for unitary groups.
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Fan, Chih-yen, and 范植硯. "A Comparative Study of Short Word-Length LNS and Floating-Point Number System Arithmetic." Thesis, 2007. http://ndltd.ncl.edu.tw/handle/51697844028230269228.
Full textAbstract:
碩士逢甲大學
資訊工程所
95
Arithmetic units are the main components of digital systems for performing the fundamental operations of arithmetic, especially for microprocessors and digital signal processors. When designing arithmetic units, different number systems will result in different architecture, precision, circuit area and delay of the circuits. In this thesis, we compare and analyze these two arithmetic systems, including Floating-Point (FLP), and Logarithmic Number Systems (LNS). We discuss the design methodology of short word length units, including 16-bits, 20-bits, 24-bits, 28-bits and 32-bits adder, subtraction, multiplier, and divider. Among of LNS’s adder and subtraction, at different word-length we will use different architecture. And according to our estimate it narrowly, we will use three architectures to implement the circuits. At short word length units, the addition and subtraction in LNS arithmetic require the computation of the functions and , which is usually performed by table-lookup operation. But as the word length of the LNS number increases, LNS arithmetic is the exponential increase of this table size. In order to reduce the hardware cost for computing these two functions, at 32-bits, we use a computational approach to approximate the value of Look-Up Table, and solving the large lookup table problem in large word-length LNS addition/subtraction. Using hardware description language, we implement these arithmetic units of the two different number systems in different word lengths, and we synthesis the arithmetic units using Synopsys Design Analyzer with 0.18μ CMOS process technology offered by UMC. These circuits are implemented on the Xilinx Virtex II multimedia FF896 development board, as a co-processor to the Microblaze processor, through the FSL communication link. Final, from the synthesis and simulation results, we can compare and analyzed the advantages and disadvantages of these two number systems, which can be used as a guideline for design engineers in deciding when LNS arithmetic can be adopted for efficient digital system design.
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"Decimal Floating-point Fused Multiply Add with Redundant Number Systems." Thesis, 2013. http://hdl.handle.net/10388/ETD-2013-05-1044.
Full textAbstract:
The IEEE standard of decimal floating-point arithmetic was officially released in 2008. The new decimal floating-point (DFP) format and arithmetic can be applied to remedy the conversion error caused by representing decimal floating-point numbers in binary floating-point format and to improve the computing performance of the decimal processing in commercial and financial applications. Nowadays, many architectures and algorithms of individual arithmetic functions for decimal floating-point numbers are proposed and investigated (e.g., addition, multiplication, division, and square root). However, because of the less efficiency of representing decimal number in binary devices, the area consumption and performance of the DFP arithmetic units are not comparable with the binary counterparts.
IBM proposed a binary fused multiply-add (FMA) function in the POWER series of processors in order to improve the performance of floating-point computations and to reduce the complexity of hardware design in reduced instruction set computing (RISC) systems. Such an instruction also has been approved to be suitable for efficiently implementing not only stand-alone addition and multiplication, but also division, square root, and other transcendental functions. Additionally, unconventional number systems including digit sets and encodings have displayed advantages on performance and area efficiency in many applications of computer arithmetic.
In this research, by analyzing the typical binary floating-point FMA designs and the design strategy of unconventional number systems, ``a high performance decimal floating-point fused multiply-add (DFMA) with redundant internal encodings" was proposed. First, the fixed-point components inside the DFMA (i.e., addition and multiplication) were studied and investigated as the basis of the FMA architecture. The specific number systems were also applied to improve the basic decimal fixed-point arithmetic. The superiority of redundant number systems in stand-alone decimal fixed-point addition and multiplication has been proved by the synthesis results. Afterwards, a new DFMA architecture which exploits the specific redundant internal operands was proposed. Overall, the specific number system improved, not only the efficiency of the fixed-point addition and multiplication inside the FMA, but also the architecture and algorithms to build up the FMA itself.
The functional division, square root, reciprocal, reciprocal square root, and many other functions, which exploit the Newton's or other similar methods, can benefit from the proposed DFMA architecture. With few necessary on-chip memory devices (e.g., Look-up tables) or even only software routines, these functions can be implemented on the basis of the hardwired FMA function. Therefore, the proposed DFMA can be implemented on chip solely as a key component to reduce the hardware cost. Additionally, our research on the decimal arithmetic with unconventional number systems expands the way of performing other high-performance decimal arithmetic (e.g., stand-alone division and square root) upon the basic binary devices (i.e., AND gate, OR gate, and binary full adder). The proposed techniques are also expected to be helpful to other non-binary based applications.
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Santos, Cláudia Fernanda Ribeiro Seabra. "Aritmética modular e suas aplicações: dos sistemas de identificação às mensagens secretas." Master's thesis, 2013. http://hdl.handle.net/10316/33700.
Full textAbstract:
Relatório de estágio do Mestrado em Ensino de Matemática no 3.º ciclo do Ensino Básico e no Secundário apresentado à Faculdade de Ciências e Tecnologia da Universidade de CoimbraA aritmética modular é uma ferramenta importante na teoria dos números. Consiste em trabalhar com o resto da divisão inteira por um determinado número. Esta aritmética está na base da conceção de vários sistemas de identificação, presentes na nossa vida quotidiana, por exemplo em livros, cartões e artigos. É também utilizada na codificação e descodificação de mensagens secretas. Neste relatório pretendemos fazer, numa primeira parte, uma análise de alguns sistemas de identificação modulares maios utilizados, reconhecendo as suas limitações relativamente à det3eção de erros ocorridos na transmissão de números de identificação. Numa segunda parte, pretendemos apresentar, em contexto escolar, aplicações da aritmética modular no dia-a-dia, recorrendo a exemplos animados, práticos e palpáveis, bem como a programas informáticos apropriados.
The modular arithmetic is an important tool of number theory. It consists in working with the remainder of the integer division. This arithmetic is in the basics of the conception of several identification systems, and it appears, for example in books, cards and articles. It is also used in the encryption and decryption of secret messages. In the first part of this report we intend to do an analysis of some widely used modular identification systems, recognizing their limitations regarding the detection of errors in the transmission of identification numbers. In the second part, we explain how we showed, in a school context, daily applications of modular arithmetic, using animated, practical and tangible examples, as well as the appropriate software programs.
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Σχοινιανάκης, Δημήτριος. "Versatile architectures for cryptographic systems." Thesis, 2013. http://hdl.handle.net/10889/7623.
Full textAbstract:
This doctoral thesis approaches the problem of designing versatile architectures for cryptographic hardware. By the term versatile we define hardware architectures capable of supporting a variety of arithmetic operations and algorithms useful in cryptography, with no need to reconfigure the internal interconnections of the integrated circuit.
A versatile architecture could offer considerable benefits to the end-user. By embedding a variety of crucial operations in a common architecture, the user is able to switch seamlessly the underlying cryptographic protocols, which not only gives an added value in the design from flexibility but also from practicality point of view. The total cost of a cryptographic application can be also benefited; assuming a versatile integrated circuit which requires no additional circuitry for other vital operations (for example input–output converters) it is easy to deduce that the total cost of development and fabrication of these extra components is eliminated, thus reducing the total production cost.
We follow a systematic approach for developing and presenting the proposed versatile architectures. First, an in-depth analysis of the algorithms of interest is carried out, in order to identify new research areas and weaknesses of existing solutions. The proposed algorithms and architectures operate on Galois Fields GF of the form GF(p) for integers and GF(2^n) for polynomials. Alternative number representation systems such as Residue Number System (RNS) for integers and Polynomial Residue Number System (PRNS) for polynomials are employed. The mathematical validity of the proposed algorithms and the applicability of RNS and PRNS in the context of cryptographic algorithms is also presented. The derived algorithms are decomposed in a way that versatile structures can be formulated and the corresponding hardware is developed and evaluated. New cryptanalytic properties of the proposed algorithms against certain types of attacks are also highlighted.
Furthermore, we try to approach a fundamental problem in Very Large Scale Integration (VLSI) design, that is the problem of evaluating and comparing architectures using models independent from the underlying fabrication technology. We also provide generic methods to evaluate the optimal operation parameters of the proposed architectures and methods to optimize the proposed architectures in terms of speed, area, and area x speed product, based on the needs of the underlying application. The proposed methodologies can be expanded to include applications other than cryptography.
Finally, novel algorithms based on new mathematical and design problems for the crucial operation of modular multiplication are presented. The new algorithms preserve the versatile characteristics discussed previously and it is proved that, along with existing algorithms in the literature, they may forma large family of algorithms applicable in cryptography, unified under the common frame of the proposed versatile architectures.Η παρούσα διατριβή άπτεται του θέματος της ανάπτυξης ευέλικτων αρχιτεκτονικών κρυπτογραφίας σε ολοκληρωμένα κυκλώματα υψηλής ολοκλήρωσης (VLSI). Με τον όρο ευέλικτες ορίζονται οι αρχιτεκτονικές που δύνανται να υλοποιούν πλήθος βασικών αριθμητικών πράξεων για την εκτέλεση κρυπτογραφικών αλγορίθμων, χωρίς την ανάγκη επαναπροσδιορισμού των εσωτερικών διατάξεων στο ολοκληρωμένο κύκλωμα. Η χρήση ευέλικτων αρχιτεκτονικών παρέχει πολλαπλά οφέλη στο χρήστη. Η ενσωμάτωση κρίσιμων πράξεων απαραίτητων στη κρυπτογραφία σε μια κοινή αρχιτεκτονική δίνει τη δυνατότητα στο χρήστη να εναλλάσσει το υποστηριζόμενο κρυπτογραφικό πρωτόκολλο, εισάγοντας έτσι χαρακτηριστικά ευελιξίας και πρακτικότητας, χωρίς επιπρόσθετη επιβάρυνση του συστήματος σε υλικό. Αξίζει να σημειωθεί πως οι εναλλαγές αυτές δεν απαιτούν τη παρέμβαση του χρήστη. Σημαντική είναι η συνεισφορά μιας ευέλικτης αρχιτεκτονικής και στο κόστος μιας εφαρμογής. Αναλογιζόμενοι ένα ολοκληρωμένο κύκλωμα που μπορεί να υλοποιεί αυτόνομα όλες τις απαραίτητες πράξεις ενός αλγόριθμου χωρίς την εξάρτηση από εξωτερικά υποσυστήματα (π.χ. μετατροπείς εισόδου–εξόδου), είναι εύκολο να αντιληφθούμε πως το τελικό κόστος της εκάστοτε εφαρμογής μειώνεται σημαντικά καθώς μειώνονται οι ανάγκες υλοποίησης και διασύνδεσης επιπρόσθετων υποσυστημάτων στο ολοκληρωμένο κύκλωμα. Η ανάπτυξη των προτεινόμενων αρχιτεκτονικών ακολουθεί μια δομημένη προσέγγιση. Διενεργείται εκτενής μελέτη για τον προσδιορισμό γόνιμων ερευνητικών περιοχών και εντοπίζονται προβλήματα και δυνατότητες βελτιστοποίησης υπαρχουσών κρυπτογραφικών λύσεων. Οι νέοι αλγόριθμοι που αναπτύσσονται αφορούν τα Galois πεδία GF(p) και GF(2^n) και χρησιμοποιούν εναλλακτικές αριθμητικές αναπαράστασης δεδομένων όπως το αριθμητικό σύστημα υπολοίπων (Residue Number System (RNS)) για ακέραιους αριθμούς και το πολυωνυμικό αριθμητικό σύστημα υπολοίπων (Polynomial Residue Number System (PRNS)) για πολυώνυμα. Αποδεικνύεται η μαθηματική τους ορθότητα και βελτιστοποιούνται κατά τέτοιο τρόπο ώστε να σχηματίζουν ευέλικτες δομές. Αναπτύσσεται το κατάλληλο υλικό (hardware) και διενεργείται μελέτη χρήσιμων ιδιοτήτων των νέων αλγορίθμων, όπως για παράδειγμα νέες κρυπταναλυτικές ιδιότητες. Επιπρόσθετα, προσεγγίζουμε στα πλαίσια της διατριβής ένα βασικό πρόβλημα της επιστήμης σχεδιασμού ολοκληρωμένων συστημάτων μεγάλης κλίμακας (Very Large Scale Integration (VLSI)). Συγκεκριμένα, προτείνονται μέθοδοι σύγκρισης αρχιτεκτονικών ανεξαρτήτως τεχνολογίας καθώς και τρόποι εύρεσης των βέλτιστων συνθηκών λειτουργίας των προτεινόμενων αρχιτεκτονικών. Οι μέθοδοι αυτές επιτρέπουν στον σχεδιαστή να παραμετροποιήσει τις προτεινόμενες αρχιτεκτονικές με βάση τη ταχύτητα, επιφάνεια, ή το γινόμενο ταχύτητα x επιφάνεια. Οι προτεινόμενες μεθοδολογίες μπορούν εύκολα να επεκταθούν και σε άλλες εφαρμογές πέραν της κρυπτογραφίας. Τέλος, προτείνονται νέοι αλγόριθμοι για τη σημαντικότατη για την κρυπτογραφία πράξη του πολλαπλασιασμού με υπόλοιπα. Οι νέοι αλγόριθμοι ενσωματώνουν από τη μία τις ιδέες των ευέλικτων δομών, από την άλλη όμως βασίζονται σε νέες ιδέες και μαθηματικά προβλήματα τα οποία προσπαθούμε να προσεγγίσουμε και να επιλύσουμε. Αποδεικνύεται πως είναι δυνατή η ενοποίηση μιας μεγάλης οικογένειας αλγορίθμων για χρήση στην κρυπτογραφία, υπό τη στέγη των προτεινόμενων μεθοδολογιών για ευέλικτο σχεδιασμό.
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Σπύρου, Αναστασία. "Κυκλώματα ύψωσης στο τετράγωνο για το σύστημα αριθμητικής υπολοίπων." Thesis, 2009. http://nemertes.lis.upatras.gr/jspui/handle/10889/1900.
Full textAbstract:
Στα σύγχρονα ψηφιακά συστήματα η ανάγκη για γρήγορους υπολογισμούς είναι πλέον από τους πιο καθοριστικούς παράγοντες. Άλλοι ιδιαίτερα κρίσιμοι παράγοντες είναι η απαιτούμενη επιφάνεια του κυκλώματος και η κατανάλωση ενέργειας. Ωστόσο, ο χρόνος παραμένει ένας από τους πιο σημαντικούς για πλήθος εφαρμογές. Τα αριθμητικά κυκλώματα, όπως αθροιστές, πολλαπλασιαστές και κυκλώματα ύψωσης στο τετράγωνο, είναι πλέον αναπόσπαστο κομμάτι των ψηφιακών κυκλωμάτων, γι’ αυτό η επιτάχυνση των λειτουργιών αυτών είναι ένας στόχος στην κατεύθυνση του οποίου πολλές διαφορετικές αρχιτεκτονικές έχουν προταθεί. Η μείωση της καθυστέρησης στις αριθμητικές μονάδες θα δώσει μεγάλη βελτίωση στη συνολική απόδοση των συστημάτων, μιας και οι περισσότερες εφαρμογές εμπεριέχουν πλήθος αριθμητικών πράξεων.
Η πράξη της ύψωσης στο τετράγωνο αποτελεί ειδική περίπτωση της πράξης του πολλαπλασιασμού, στην οποία ο πολλαπλασιαστέος ισούται με τον πολλαπλασιαστή. Ο λόγος για τον οποίο χρησιμοποιούμε εξειδικευμένα κυκλώματα για την πράξη αυτή είναι η εκμετάλλευση του γεγονότος ότι τα δύο έντελα είναι ίσα, κάτι που οδηγεί σε ελαχιστοποίηση του χρόνου που απαιτείται για την ολοκλήρωση της πράξης, αλλά και μείωση της απαιτούμενης επιφάνειας. Η πράξη της ύψωσης στο τετράγωνο χρησιμοποιείται σε πολλές εφαρμογές των υψηλής απόδοσης επεξεργαστών ψηφιακού σήματος (digital signal processors – DSP). Τέτοιες εφαρμογές συμπεριλαμβάνουν φιλτράρισμα σήματος (signal filtering), επεξεργασία εικόνας (image processing), και διαμόρφωση για τηλεπικοινωνιακά συστήματα. Η πράξη της ύψωσης στο τετράγωνο μπορεί, επίσης, να χρησιμοποιηθεί αποδοτικά στην υλοποίηση κρυπτογραφικών αλγορίθμων για την αποφυγή της χρονοβόρας διαδικασίας της ύψωσης σε δύναμη.
Το Σύστημα Αριθμητικής Υπολοίπων (RNS), είναι ένα αριθμητικό σύστημα το οποίο παρουσιάζει σημαντικά πλεονεκτήματα στην ταχύτητα με την οποία μπορούν να γίνουν οι αριθμητικές πράξεις. Στο RNS οι αριθμοί αναπαρίστανται σαν ένα σύνολο από υπόλοιπα. Για να αναπαραστήσουμε έναν αριθμό ορίζουμε ένα σύνολο από πρώτους μεταξύ τους ακεραίους που ονομάζεται βάση του συστήματος P={p1,p2,…pk}. Η αναπαράσταση ενός αριθμού X στο RNS ορίζεται ως το σύνολο των υπολοίπων του Χ ως προς τα στοιχεία της βάσης Ρ. Προκύπτει, έτσι, ότι X={x1,x2,…,xk} όπου το xi είναι το υπόλοιπο της διαίρεσης του X με το στοιχείο της βάσης pi και συμβολίζεται με Xi=|X|pi. Κάθε ακέραιος Χ που ανήκει στο εύρος τιμών 0<=X
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Poirier, Julie. "Le développement d’une séquence d’enseignement/apprentissage basée sur l’histoire de la numération pour des élèves du troisième cycle du primaire." Thèse, 2011. http://hdl.handle.net/1866/5429.
Full textAbstract:
Notre contexte pratique — nous enseignons à des élèves doués de cinquième année suivant le programme international — a grandement influencé la présente recherche. En effet, le Programme primaire international (Organisation du Baccalauréat International, 2007) propose un enseignement par thèmes transdisciplinaires, dont un s’intitulant Où nous nous situons dans l’espace et le temps. Aussi, nos élèves sont tenus de suivre le Programme de formation de l’école québécoise (MÉLS Ministère de l'Éducation du Loisir et du Sport, 2001) avec le développement, notamment, de la compétence Résoudre une situation-problème et l’introduction d’une nouveauté : les repères culturels. Après une revue de la littérature, l’histoire des mathématiques nous semble tout indiquée. Toutefois, il existe peu de ressources pédagogiques pour les enseignants du primaire. Nous proposons donc d’en créer, nous appuyant sur l’approche constructiviste, approche prônée par nos deux programmes d’études (OBI et MÉLS).
Nous relevons donc les avantages à intégrer l’histoire des mathématiques pour les élèves (intérêt et motivation accrus, changement dans leur façon de percevoir les mathématiques et amélioration de leurs apprentissages et de leur compréhension des mathématiques). Nous soulignons également les difficultés à introduire une approche historique à l’enseignement des mathématiques et proposons diverses façons de le faire. Puis, les concepts mathématiques à l’étude, à savoir l’arithmétique, et la numération, sont définis et nous voyons leur importance dans le programme de mathématiques du primaire. Nous décrivons ensuite les six systèmes de numération retenus (sumérien, égyptien, babylonien, chinois, romain et maya) ainsi que notre système actuel : le système indo-arabe. Enfin, nous abordons les difficultés que certaines pratiques des enseignants ou des manuels scolaires posent aux élèves en numération.
Nous situons ensuite notre étude au sein de la recherche en sciences de l’éducation en nous attardant à la recherche appliquée ou dite pédagogique et plus particulièrement aux apports des recherches menées par des praticiens (un rapprochement entre la recherche et la pratique, une amélioration de l’enseignement et/ou de l’apprentissage, une réflexion de l’intérieur sur la pratique enseignante et une meilleure connaissance du milieu). Aussi, nous exposons les risques de biais qu’il est possible de rencontrer dans une recherche pédagogique, et ce, pour mieux les éviter. Nous enchaînons avec une description de nos outils de collecte de données et rappelons les exigences de la rigueur scientifique.
Ce n’est qu’ensuite que nous décrivons notre séquence d’enseignement/apprentissage en détaillant chacune des activités. Ces activités consistent notamment à découvrir comment différents systèmes de numération fonctionnent (à l’aide de feuilles de travail et de notations anciennes), puis comment ces mêmes peuples effectuaient leurs additions et leurs soustractions et finalement, comment ils effectuaient les multiplications et les divisions.
Enfin, nous analysons nos données à partir de notre journal de bord quotidien bonifié par les enregistrements vidéo, les affiches des élèves, les réponses aux tests de compréhension et au questionnaire d’appréciation. Notre étude nous amène à conclure à la pertinence de cette séquence pour notre milieu : l’intérêt et la motivation suscités, la perception des mathématiques et les apprentissages réalisés. Nous revenons également sur le constructivisme et une dimension non prévue : le développement de la communication mathématique.Our practical context -we teach gifted fifth grade students in an International School- has greatly influenced this research. Indeed, the International Primary Years Programme (International Baccalaureate Organization, 2007) fosters transdisciplinary themes, including one intitled Where we are in place and time. Our students are also expected to follow the Quebec education program schools (Ministry of Education, Recreation and Sport, 2001) with the development of competencies such as: To solve situational problem and the introduction of a novelty: the Cultural References. After the literature review, the history of mathematics seems very appropriate. However, there are few educational resources for primary teachers. This is the reason why we propose creating the resources by drawing upon the constructivist approach, an approach recommended by our two curricula (OBI and MELS). We bring to light the advantages of integrating the history of mathematics for students (increased interest and motivation, change in their perception of mathematics and improvement in learning and understanding mathematics). We also highlight the difficulties in introducing a historical approach to teaching mathematics and suggest various ways to explore it. Then we define the mathematical concepts of the study: arithmetic and counting and we remark their importance in the Primary Mathematics Curriculum. We then describe the six selected number systems (Sumerian, Egyptian, Babylonian, Chinese, Roman and Mayan) as well as our current system: the Indo-Arabic system. Finally, we discuss the difficulties students may encounter due to some teaching practices or textbooks on counting. We situate our study in the research of science of education especially on applied research and the contributions of the teacher research reconciliation between research and practice, the improvement of teaching and / or learning and a reflection within the teaching practice). Also, we reveal the possible biases that can be encountered in a pedagogical research and thus, to better avoid them. Finally, we describe the tools used to collect our data and look at the requirements for scientific rigor. Next, we describe our teaching sequence activities in details. These activities include the discovery of how the different number systems work (using worksheets and old notations) and how the people using the same systems do their additions and subtractions and how they do their multiplications and divisions. Finally, we analyze our data from a daily diary supported by video recordings, students’ posters, the comprehension tests and the evaluation questionnaire. Our study leads us to conclude the relevance of this sequence in our context: interest and motivation, perception of mathematics and learning achieved. We also discuss constructivism and a dimension not provided: the development of mathematical communication.