Journal articles: 'Nonbinary low-density parity check (LDPC) decoder'

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Ramachandran, Varatharajan. "An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 1 (March 1, 2015): 6. http://dx.doi.org/10.11591/ijres.v4.i1.pp6-12.

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<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity, that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

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Dinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (May 31, 2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.

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Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error-correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, an One-Minimum-Only basic-set trellis min-max (OMO-BS-TMM) algorithm and the corresponding decoder architecture are proposed for NBLDPC codes to greatly reduce the complexity of the check node unit (CNU) as well as the whole decoder. In the proposed OMO-BS-TMM algorithm, only the first minimum values are used for generating the check node messages instead of using both the first and second minimum values, and the number of messages exchanged between the check node and the variable node is reduced in comparison with the previous works. Layered decoder architectures based on the proposed algorithm were implemented for the (837, 726) NB-LDPC code over GF(32) using 90-nm CMOS technology. The implementation results showed that the OMO-BS-TMM algorithm achieves the almost similar error-correcting performance, and a reduction of the complexity by 31.8% and 20.5% for the whole decoder, compared to previous works. Moreover, the proposed decoder achieves a higher throughput at 1.4 Gbps, compared with the other state-of-the-art NBLDPC decoders.

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Pham, Huyen Thi, Hung Tuan Dao, and Nghia Xuan Pham. "Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder." Journal of Science and Technology on Information security 9, no. 01 (April 9, 2020): 12–19. http://dx.doi.org/10.54654/isj.v9i01.36.

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Abstract— Nonbinary low-density-parity-check (NB-LDPC) code outperforms their binary counterpart in terms of error correcting performance and error-floor property when the code length is moderate. However, the drawback of NB-LDPC decoders is high complexity and the complexity increases considerably when increasing the Galois-field order. In this paper, a simplified basic-set trellis min-max (sBS-TMM) algorithm that is especially efficient for high-order Galois Fields, is proposed for the variable node processing to reduce the complexity of the variable node unit (VNU) as well as the whole decoder. The decoder architecture corresponding to the proposed algorithm is designed for the (837, 726) NB-LDPC code over GF(32). The implementation results using 90-nm CMOS technology show that the proposed decoder architecture reduces the gate count by 21.35% and 9.4% with almost similar error-correcting performance, compared to the up-to-date works.Tóm tắt— Các mã LDPC phi nhị phân (NB-LDPC) vượt trội so với các mã LDPC nhị phân về chất lượng sửa lỗi và thuộc tính lỗi san bằng khi chiều dài là trung bình. Tuy nhiên, nhược điểm của các bộ giải mã NB-LDPC là tính phức tạp cao và độ phức tạp tăng đáng kể khi bậc của trường Galois cao. Trong bài báo này, thuật toán Trellis Min-Max dựa trên tập cơ sở được đơn giản hóa được đề xuất cho xử lý nốt biến mà hiệu quả cho các trường Galois bậc cao để giảm độ phức tạp của khối nốt biến (VNU) cũng như cả bộ giải mã. Kiến trúc bộ giải mã tương ứng với thuật toán đề xuất được thiết kế cho mã NB-LDPC (837, 726) thông qua trường GF(32). Các kết quả thực hiện sử dụng công nghệ CMOS 90-nm chỉ ra rằng kiến trúc bộ giải mã được đề xuất giảm số lượng cổng logic 21,35% và 9,4% với chất lượng sửa lỗi gần như không thay đổi so với các nghiên cứu gần đây.

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Revathy, M., and R. Saravanan. "A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/327357.

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Low-density parity-check (LDPC) codes have been implemented in latest digital video broadcasting, broadband wireless access (WiMax), and fourth generation of wireless standards. In this paper, we have proposed a high efficient low-density parity-check code (LDPC) decoder architecture for low power applications. This study also considers the design and analysis of check node and variable node units and Euclidean orthogonal generator in LDPC decoder architecture. The Euclidean orthogonal generator is used to reduce the error rate of the proposed LDPC architecture, which can be incorporated between check and variable node architecture. This proposed decoder design is synthesized on Xilinx 9.2i platform and simulated using Modelsim, which is targeted to 45 nm devices. Synthesis report proves that the proposed architecture greatly reduces the power consumption and hardware utilizations on comparing with different conventional architectures.

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Sułek, W. "Pipeline processing in low-density parity-check codes hardware decoder." Bulletin of the Polish Academy of Sciences: Technical Sciences 59, no. 2 (June 1, 2011): 149–55. http://dx.doi.org/10.2478/v10175-011-0019-9.

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Pipeline processing in low-density parity-check codes hardware decoderLow-Density Parity-Check (LDPC) codes are one of the best known error correcting coding methods. This article concerns the hardware iterative decoder for a subclass of LDPC codes that are implementation oriented, known also as Architecture Aware LDPC. The decoder has been implemented in a form of synthesizable VHDL description. To achieve high clock frequency of the decoder hardware implementation - and in consequence high data-throughput, a large number of pipeline registers has been used in the processing chain. However, the registers increase the processing path delay, since the number of clock cycles required for data propagating is increased. Thus in general the idle cycles must be introduced between decoding subiterations. In this paper we study the conditions for necessity of idle cycles and provide a method for calculation the exact number of required idle cycles on the basis of parity check matrix of the code. Then we propose a parity check matrix optimization method to minimize the total number of required idle cycles and hence, maximize the decoder throughput. The proposed matrix optimization by sorting rows and columns does not change the code properties. Results, presented in the paper, show that the decoder throughput can be significantly increased with the proposed optimization method.

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Ali Jassim, Amjad, Wael A. Hadi., and Muhanned Ismael Ibrahim Al-Firas. "Serially Concatenated Low-density Parity Check Codes as Compatible Pairs." International Journal of Engineering & Technology 7, no. 4.15 (October 7, 2018): 301. http://dx.doi.org/10.14419/ijet.v7i4.15.23013.

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Low-density parity checks (LDPC) codes are considered good performance error correction codes. However, decoder complexity increases with increasing code length. In this study, we introduce short-length serially concatenated LDPC codes. The proposed technique uses pairs of compatible LDPC codes that act as outer and inner serially concatenated codes. In this code pair, the inner code takes input that is the same length as the outer LDPC encoder output. This study examined two cases of LDPC codes as compatible pairs with low numbers of iterations and compared bit error rate (BER) performance to a standalone LDPC code with an additive white Gaussian noise channel. We also considered the quadrature phase shift keying QPSK, 16-quadrature amplitude modulation (QAM), and 64-QAM system modulation schemes. Simulation results demonstrate that the proposed system has good BER performance compared to a standalone LDPC code, the results summarized in table and performance curves.

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Kuc, Mateusz, Wojciech Sułek, and Dariusz Kania. "Low Power QC-LDPC Decoder Based on Token Ring Architecture." Energies 13, no. 23 (November 30, 2020): 6310. http://dx.doi.org/10.3390/en13236310.

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The article presents an implementation of a low power Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) decoder in a Field Programmable Gate Array (FPGA) device. The proposed solution is oriented to a reduction in dynamic energy consumption. The key research concepts present an effective technology mapping of a QC-LDPC decoder to an LUT-based FPGA with many limitations. The proposed decoder architecture uses a distributed control system and a Token Ring processing scheme. This idea helps limit the clock skew problem and is oriented to clock gating, a well-established concept for power optimization. Then the clock gating of the decoder building blocks allows for a significant reduction in energy consumption without deterioration in other parameters of the decoder, particularly its error correction performance. We also provide experimental results for decoder implementations with different QC-LDPC codes, indicating important characteristics of the code parity check matrix, for which an energy-saving QC-LDPC decoder with the proposed architecture can be designed. The experiments are based on implementations in the Intel Cyclone V FPGA device. Finally, the presented architecture is compared with the other solutions from the literature.

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Hao, Ning, Yang An Zhang, Jin Nan Zhang, Ming Lun Zhang, and Xue Guang Yuan. "An Application of LDPC Code for Wireless Coherent-Light Commutation in Atmospheric Channel." Applied Mechanics and Materials 347-350 (August 2013): 1864–67. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1864.

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Low Density Parity Check code is more and more taken seriously in high-speed transmission. In this article we represent a LDPC coder and decoder which based on IEEE802.16e and realize the coder and decoder with Virtex-5 FPGA. By using Matlab to make an off-line system simulation, we analyzed and compared the LDPC performance under the different length of code for LDPC coder then analyzed the influence of different iteration to the LDPC BER performance of decoder.

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Lin, Cheng-Hung, Tzu-Hsuan Huang, Shu-Yen Lin, and Yu-Hsuan Lee. "Design and Implementation of Operation-Reduced LDPC Decoder Based on a Check Node Stopping Scheme." Journal of Circuits, Systems and Computers 26, no. 02 (November 3, 2016): 1750028. http://dx.doi.org/10.1142/s0218126617500281.

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In this paper, we propose an operation-reduced low-density parity check (LDPC) decoder design and implementation by stopping reliable operation of check nodes of the iterative two-phase message passing (TPMP) min-sum algorithm (MSA). A check node stopping (CNS) scheme is used to tag reliability of check nodes by detecting the magnitudes of the check node belief messages with a threshold. The operation of reliable check nodes tagged by the CNS scheme can be stopped in the later iterations. The proposed LDPC decoder that employs the CNS scheme can significantly terminate the redundant operations of check nodes and efficiently reduce the power consumption of decoder. From the simulations under WiMAX QC LDPC decoding with high channel quality, the CNS scheme achieves up to 12% stopping rate of check nodes with a loss of coding gain less than 0.1 dB. The WiMAX QC LDPC decoder chip that employs the CNS scheme is implemented by a 90-nm CMOS process. Compared with the LDPC decoder that employs no CNS scheme, the overall power dissipation of the proposed LDPC decoder is decreased by 4.1% with 0.5% area overhead.

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Mishra, Rajarshini. "Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm." International Journal Of Engineering And Computer Science 7, no. 03 (March 26, 2018): 23781–84. http://dx.doi.org/10.18535//ijecs/v7i3.21.

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Low-density parity-check (LDPC) have been shown to have good error correcting performance approaching Shannon’s limit. Good error correcting performance enables efficient and reliable communication. However, a LDPC code decoding algorithm needs to be executed efficiently to meet cost , time, power and bandwidth requirements of target applications. Quasi-cyclic low-density parity-check (QC-LDPC) codes are an important subclass of LDPC codes that are known as one of the most effective error controlling methods. Quasi cyclic codes are known to possess some degree of regularity. Many important communication standards such as DVB-S2 and 802.16e use these codes. The proposed Optimized Min-Sum decoding algorithm performs very close to the Sum-Product decoding while preserving the main features of the Min-Sum decoding, that is low complexity and independence with respect to noise variance estimation errors.Proposed decoder is well matched for VLSI implementation and will be implemented on Xilinx FPGA family

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El habti El idrissi, Anas, Rachid El Gouri, and Hlou Laamari. "Conception of a new LDPC decoder with hardware implementation on FPGA card." International Journal of Engineering & Technology 3, no. 4 (September 18, 2014): 451. http://dx.doi.org/10.14419/ijet.v3i4.3185.

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Low Density Parity-Check codes are one of the hottest topics in coding theory nowadays. Equipped with very fast encoding and decoding algorithms, LDPC codes are very attractive both theoretically and practically. In this paper, A simplified algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity, this algorithm is based on a simple matrix equation which must be resolved in order to calculate all possible solutions of this equation, and then a simple circuit will be used to determine the errors produced during the transmission channel. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of LDPC codes on FPGA card. Keywords: Bit-Flipping Algorithm, Error Detection, FPGA Card, LDPC Decoder, Matrix Equation.

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Khittiwitchayakul, Sirawit, Watid Phakphisut, and Pornchai Supnithi. "Associated Sectors of Magnetic Recording Systems Using Spatially Coupled LDPC Codes." ECTI Transactions on Electrical Engineering, Electronics, and Communications 20, no. 1 (February 18, 2022): 10–21. http://dx.doi.org/10.37936/ecti-eec.2022201.246094.

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In traditional magnetic recording systems, non-associated sectors are mainly adopted, whereby two consecutive sectors are decoded independently by the low-density parity-check (LDPC) codes. In this paper, we propose a magnetic recording system with associated sectors, constructed using spatially coupled low-density parity-check (SC-LDPC) codes. If the SC-LDPC decoder cannot correct the erroneous bits in the current sector, it can request information stored in previous sectors to improve decoding performance. Moreover, we modify protograph-based extrinsic information transfer (P-EXIT) charts to examine the theoretical performance of SC-LDPC codes applied to both non-associated and associated sectors. Our theoretical results show that the associated sectors achieve significant performance gains compared to the traditional non-associated sectors.

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Cai, Fang, and Xinmiao Zhang. "Relaxed Min-Max Decoder Architectures for Nonbinary Low-Density Parity-Check Codes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 11 (November 2013): 2010–23. http://dx.doi.org/10.1109/tvlsi.2012.2226920.

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Mao, Yun, Ying Guo, Jun Peng, Xueqin Jiang, and Moon Ho Lee. "Double-Layer Low-Density Parity-Check Codes over Multiple-Input Multiple-Output Channels." International Journal of Antennas and Propagation 2012 (2012): 1–6. http://dx.doi.org/10.1155/2012/716313.

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We introduce a double-layer code based on the combination of a low-density parity-check (LDPC) code with the multiple-input multiple-output (MIMO) system, where the decoding can be done in both inner-iteration and outer-iteration manners. The present code, called low-density MIMO code (LDMC), has a double-layer structure, that is, one layer defines subcodes that are embedded in each transmission vector and another glues these subcodes together. It supports inner iterations inside the LDPC decoder and outeriterations between detectors and decoders, simultaneously. It can also achieve the desired design rates due to the full rank of the deployed parity-check matrix. Simulations show that the LDMC performs favorably over the MIMO systems.

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Awais, Muhammad, and Carlo Condo. "Flexible LDPC Decoder Architectures." VLSI Design 2012 (June 26, 2012): 1–16. http://dx.doi.org/10.1155/2012/730835.

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Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.

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Thuan. "IMPLEMENTATION OF SOME DECODING ALGORITHMS FOR NB-LDPC CODES ON FPGA." Journal of Military Science and Technology, no. 69A (November 16, 2020): 1–10. http://dx.doi.org/10.54939/1859-1043.j.mst.69a.2020.1-10.

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Non-binary low-density parity-check codes (NB-LDPC) provide better error correction performance in comparison with their counterparts. However, the NB-LDPC decoder has a very high complexity, especially the processing of the check node unit. This paper evaluates the error correction performance of some decoding algorithms for NB-LDPC codes in different fields with different codeword lengths. The paper also presents the results of the implementation a decoder structure for the NB-LDPC (35,23) over GF(8) on the Spartan 6 board. Analysis and evaluation results show that decoding quality on hardware is equivalent to simulation results on software, demonstrating high feasibility in implementing decoder on a hardware platform, capable of application in devices of the advanced communication systems or high-speed read-and-write data storages.

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Anbuselvi, M., P. Saravanan, and S. Joseph Gladwin. "Analysis of a Code Construction Method for Non-Binary Quasi-Cyclic Irregular Low Density Parity Check Decoder." Journal of Computational and Theoretical Nanoscience 15, no. 2 (February 1, 2018): 719–24. http://dx.doi.org/10.1166/jctn.2018.7151.

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Non-binary LDPC codes is a class of linear block code outperform in the short and moderate block length, closer to Shannon's limit. The numerical strength of the decoder is proportional to the sparsity of the parity check matrix. A Hierarchically Diagonal Parity Check Matrix (HDPCM) with better sparseness is constructed to optimize the computation complexity and decoding performance. The decoder based on the proposed matrix using FFT-SP decoding algorithm is analyzed, with different modulation schemes and channel environment. The positive impact of the constructed matrix is elaborated, concludes with the suitability of the HDPCM structure in AWGN channel and BPSK modulation environment.

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Yao, Chang-Kun, Yun-Ching Tang, and Hongchin Lin. "Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA." Journal of Circuits, Systems and Computers 24, no. 02 (November 27, 2014): 1550026. http://dx.doi.org/10.1142/s0218126615500267.

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This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

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Lacruz, Jesus O., Francisco Garcia-Herrero, David Declercq, and Javier Valls. "Simplified Trellis Min–Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 23, no. 9 (September 2015): 1783–92. http://dx.doi.org/10.1109/tvlsi.2014.2344113.

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Thi Bao Nguyen, Tram, Tuy Nguyen Tan, and Hanho Lee. "Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication." Electronics 10, no. 4 (February 22, 2021): 516. http://dx.doi.org/10.3390/electronics10040516.

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This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

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Wang, Zhong-xun, Yang Xi, and Zhan-kai Bao. "Nonbinary Low-Density Parity Check Decoding Algorithm Research-Based Majority Logic Decoding." International Journal of Pattern Recognition and Artificial Intelligence 34, no. 12 (March 20, 2020): 2058016. http://dx.doi.org/10.1142/s0218001420580161.

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In the nonbinary low-density parity check (NB-LDPC) codes decoding algorithms, the iterative hard reliability based on majority logic decoding (IHRB-MLGD) algorithm has poor error correction performance. The essential reason is that the hard information is used in the initialization and iterative processes. For the problem of partial loss of information, when the reliability is assigned during initialization, the error correction performance is improved by modifying the assignment of reliability at initialization. The initialization process is determined by the probability of occurrence of the number of erroneous bits in the symbol and the Hamming distance. In addition, the IHRB-MLGD decoding algorithm uses the hard decision in the iterative decoding process. The improved algorithm adds soft decision information in the iterative process, which improves the error correction performance while only slightly increasing the decoding complexity, and improves the reliability accumulation process which makes the algorithm more stable. The simulation results indicate that the proposed algorithm has a better decoding performance than IHRB algorithm.

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Beuschel, C., and H. J. Pfleiderer. "Hardwarearchitektur für einen universellen LDPC Decoder." Advances in Radio Science 7 (May 19, 2009): 213–18. http://dx.doi.org/10.5194/ars-7-213-2009.

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Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.

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Wang, Zhi Jie, Yan Yan Hao, and Hui Lian. "Effect of Random Jitter on Performance of LDPC." Applied Mechanics and Materials 380-384 (August 2013): 3513–16. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3513.

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Low density parity check codes (LDPC) by now is an excellent channel code that approaches Shannons limit. In order to get the effect of random jitter on performance of LDPC, a simulation model is constructed in this paper. Interpolation, filter delay and decimation methods are used to simulate random jitter induced by circuits of the receiver, changing filter delay to control the jitter step length. Thus the bit error rate of LDPC decoder is gotten that shows the sensitivity of LDPC to synchronization jitter. This paper concludes that, complying with channel coding block in DVB-S2, the bit error rate of LDPC decoder goes up on an exponential trend with the effect of random jitter simulation.

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Ismail, Mohamed, Imran Ahmed, and Justin Coon. "Low Power Decoding of LDPC Codes." ISRN Sensor Networks 2013 (January 17, 2013): 1–12. http://dx.doi.org/10.1155/2013/650740.

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Wireless sensor networks are used in many diverse application scenarios that require the network designer to trade off different factors. Two such factors of importance in many wireless sensor networks are communication reliability and battery life. This paper describes an efficient, low complexity, high throughput channel decoder suited to decoding low-density parity-check (LDPC) codes. LDPC codes have demonstrated excellent error-correcting ability such that a number of recent wireless standards have opted for their inclusion. Hardware realisation of practical LDPC decoders is a challenging area especially when power efficient solutions are needed. Implementation details are given for an LDPC decoding algorithm, termed adaptive threshold bit flipping (ATBF), designed for low complexity and low power operation. The ATBF decoder was implemented in 90 nm CMOS at 0.9 V using a standard cell design flow and was shown to operate at 250 MHz achieving a throughput of 252 Gb/s/iteration. The decoder area was 0.72 mm2 with a power consumption of 33.14 mW and a very small energy/decoded bit figure of 1.3 pJ.

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Zhong, Fei, and Shu Xu Guo. "Study on a New Joint Source-Channel Decoder Design." Applied Mechanics and Materials 340 (July 2013): 471–75. http://dx.doi.org/10.4028/www.scientific.net/amm.340.471.

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To improve upon the Low-Density Parity-Check (LDPC) codes , incorporating compressed sensing (CS) and information redundancy, a new joint decoding algorithm frame is presented. The proposed system exploits the information redundancy by CS reconstruction during the iterative decoding process to correct decoding of LDPC codes. The simulation results show that the algorithm presented can improve system decoding performance and obviously make bit error ratio (BER) lower then traditional LDPC codes. In addition, a relatively short argument is given on different CS reconstructed algorithms in proposed system, the new design is shown to benefit from different CS reconstructed algorithms.

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Lin, Cheng-Hung, Hsin-Hao Su, Tang-Syun Chen, and Cheng-Kai Lu. "Reconfigurable Low-Density Parity-Check (LDPC) Decoder for Multi-Standard 60 GHz Wireless Local Area Networks." Electronics 11, no. 5 (February 26, 2022): 733. http://dx.doi.org/10.3390/electronics11050733.

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In this study, a reconfigurable low-density parity-check (LDPC) decoder is designed with good hardware sharing for IEEE 802.15.3c, 802.11ad, and 802.11ay standards. This architecture flexibly supports 12 types of parity-check matrix. The switching network adopts an architecture that can flexibly switch between different inputs and achieves a low hardware complexity. The check node unit adopts a switchable 8/16/32 reconfigurable structure to match different row weights at different code rates and uses the normalised probability min-sum algorithm to simplify the structure of searching for the minimum value. Finally, the chip is implemented using the TSMC 40 nm CMOS process, based on the IEEE 802.11ad standard decoder, extended to support the IEEE 802.15.3c standard, and upwardly compatible with the next-generation advanced standard IEEE 802.11ay. The chip core size was 1.312 mm × 1.312 mm, the operating frequency was 117 MHz when the maximum number of iterations was five with the power consumption of 57.1 mW, and the throughput of 5.24 Gbps and 3.90 Gbsp was in the IEEE 802.11ad and 802.5.3c standards, respectively.

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Zhao, Ling, Yi Hou, and Rong Ke Liu. "Layered TPMP Decoding for QC-LDPC Codes." Applied Mechanics and Materials 197 (September 2012): 596–603. http://dx.doi.org/10.4028/www.scientific.net/amm.197.596.

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This paper presents a layered two-phase message passing (L-TPMP) decoding algorithm for general quasi-cyclic low-density parity-check (QC-LDPC) codes, which not only achieves high hardware utilization efficiency (HUE), but also brings in great memory block reduction. The main idea is to split the check matrix into several layers row-wise, then to perform the message passing computations sequentially layer by layer and the two-phase computations of different layers can be overlapped performed. There is no constraint to layer the check matrix hence L-TPMP decoding can be used in both high and low throughput applications for any QC-LDPC codes. The overall architecture of L-TPMP decoder is also discussed and an efficient memory arrangement scheme is proposed to reduce the memory blocks. For the (3048, 7493) LDPC code selected form Chinese DTTB, L-TPMP decoding saves over 85% memory blocks comparing with the conventional TPMP decoding, and the HUE of the L-TPMP decoder is 0.97.

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Tuntoolavest, Usana, and Visuttha Manthamkarn. "A Practical Nonbinary Decoder for Low-Density Parity-Check Codes with Packet-Sized Symbols." Engineering Journal 26, no. 9 (September 30, 2022): 35–46. http://dx.doi.org/10.4186/ej.2022.26.9.35.

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Mitra, Ved, Mahesh C. Govil, Girdhari Singh, and Sanjeev Agrawal. "High Throughput and Resource Efficient Pipelined Decoder Designs for Projective Geometry LDPC Codes." Periodica Polytechnica Electrical Engineering and Computer Science 64, no. 2 (December 7, 2019): 179–91. http://dx.doi.org/10.3311/ppee.14807.

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Projective geometry (PG) based low-density parity-check (LDPC) decoder design using iterative sum-product decoding algorithm (SPA) is a big challenge due to higher interconnection and computational complexity, and larger memory requirement caused by relatively higher node degrees. PG-LDPC codes using SPA exhibits the best error performance and faster convergence. This paper presents an efficient novel decoding method, modified SPA (MSPA) that not only shortens the critical-path delay but also improves the hardware utilization and throughput of the decoder while maintaining the error performance of SPA. Three fully-parallel LDPC decoder designs based on PG structure, PG(2,GF( 2s )) of LDPC codes are introduced. These designs differ in their bit-node (BN) and check-node (CN) architectures. Fixed-point, 9-bit quantization scheme is used to achieve better error performance. Another significant contribution of this work is the pipelining of the proposed decoder architectures to further enhance the overall throughput. These parallel and pipelined designs are implemented for 73-bit (rate 0.616) and 1057-bit (rate 0.769) regular-structured PG-LDPC codes, on Xilinx Virtex-6 LX760 FPGA and on 0.18 μm CMOS technology for ASIC. Synthesis and simulation results have shown the better performance, throughput and effectiveness of the proposed designs.

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Kakde, Sandeep, Atish Khobragade, Shrikant Ambatkar, and Pranay Nandanwar. "Implementation of Layered Decoding Architecture for LDPC Code using Layered Min-Sum Algorithm." IIUM Engineering Journal 18, no. 2 (December 1, 2017): 128–36. http://dx.doi.org/10.31436/iiumej.v18i2.677.

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For binary field and long code lengths, Low Density Parity Check (LDPC) code approaches Shannon limit performance. LDPC codes provide remarkable error correction performance and therefore enlarge the design space for communication systems.In this paper, we have compare different digital modulation techniques and found that BPSK modulation technique is better than other modulation techniques in terms of BER. It also gives error performance of LDPC decoder over AWGN channel using Min-Sum algorithm. VLSI Architecture is proposed which uses the value re-use property of min-sum algorithm and gives high throughput. The proposed work has been implemented and tested on Xilinx Virtex 5 FPGA. The MATLAB result of LDPC decoder for low bit error rate (BER) gives bit error rate in the range of 10-1 to 10-3.5 at SNR=1 to 2 for 20 no of iterations. So it gives good bit error rate performance. The latency of the parallel design of LDPC decoder has also reduced. It has accomplished 141.22 MHz maximum frequency and throughput of 2.02 Gbps while consuming less area of the design.

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Kuc, Mateusz, Wojciech Sułek, and Dariusz Kania. "FPGA-Oriented LDPC Decoder for Cyber-Physical Systems." Mathematics 8, no. 5 (May 4, 2020): 723. http://dx.doi.org/10.3390/math8050723.

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A potentially useful Cyber-Physical Systems element is a modern forward error correction (FEC) coding system, utilizing a code selected from the broad class of Low-Density Parity-Check (LDPC) codes. In this paper, development of a hardware implementation in an FPGAs of the decoder for Quasi-Cyclic (QC-LDPC) subclass of codes is presented. The decoder can be configured to support the typical decoding algorithms: Min-Sum or Normalized Min-Sum (NMS). A novel method of normalization in the NMS algorithm is proposed, one that utilizes combinational logic instead of arithmetic units. A comparison of decoders with different bit-lengths of data (beliefs that are messages propagated between computing units) is also provided. The presented decoder has been implemented with a distributed control system. Experimental studies were conducted using the Intel Cyclone V FPGA module, which is a part of the developed testing environment for LDPC coding systems.

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32

Wang, Biao. "Novel Early Termination Method of an ADMM-Penalized Decoder for LDPC Codes in the IoT." Security and Communication Networks 2022 (October 14, 2022): 1–13. http://dx.doi.org/10.1155/2022/4599105.

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As a critical communication technology, low-density parity-check (LDPC) codes are widely concerned with the Internet of things (IoT). To increase the convergence rate of the alternating direction method of multiplier (ADMM)-penalized decoder for LDPC codes, a novel early termination (ET) method is presented by computing the average sum of the hard decision (ASHD) during each ADMM iteration. In terms of the flooding scheduling and layered scheduling ADMM-penalized decoders, the simulation results show that the proposed ET method can significantly reduce the average number of iterations at low signal-to-noise ratios (SNRs) with negligible decoding performance loss.

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33

TSANG, TONY. "A METHOD FOR PERFORMANCE MODELING AND EVALUATION OF LDPC DECODER ARCHITECTURE." International Journal of Modeling, Simulation, and Scientific Computing 04, no. 02 (June 2013): 1350003. http://dx.doi.org/10.1142/s1793962313500037.

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This paper presents a high-throughput memory efficient decoder for low density parity check (LDPC) codes in the high-rate wireless personal area network application. The novel techniques which can apply to our selected LDPC code is proposed, including parallel blocked layered decoding architecture and simplification of the WiGig networks. State-of-the-art flexible LDPC decoders cannot simultaneously achieve the high throughput mandated by these standards and the low power needed for mobile applications. This work develops a flexible, fully pipelined architecture for the IEEE 802.11ad standard capable of achieving both goals. We use Real Time–Performance Evaluation Process Algebra (RT-PEPA) to evaluate a typical LDPC Decoder system's performance. The approach is more convenient, flexible, and lower cost than the former simulation method which needs to develop special hardware and software tools. Moreover, we can easily analyze how changes in performance depend on changes in a particular mode by supplying ranges for parameter values.

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34

Wang, Zhong Xun, and Xing Long Gao. "Design of Modified Minsum Decoder of LDPC Code in the Simplified Difference-Domain." Applied Mechanics and Materials 385-386 (August 2013): 1576–81. http://dx.doi.org/10.4028/www.scientific.net/amm.385-386.1576.

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In this paper, we propose the modified minsum decoding algorithm of LDPC(Low-Density Parity-Check) code in the simplified difference-domain on the basis of detailed analysis of LDPC decoding algorithm in difference-domain. The simulation indicates that the proposed decoding algorithm offers almost no performance degradation compared with the BP(Belief Propagation) decoding algorithm in log-domain and the decoding algorithm in difference-domain and offers better performance than minsum decoding algorithm in log-domain and greatly reduces the computation complexity in AWGN(Additive White Gaussian Noise) channel and under BPSK(Binary Phase Shift Keying) modulation.

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Dai, Jingxin, Hang Yin, Yansong Lv, Weizhang Xu, and Zhanxin Yang. "Multi-Gbps LDPC Decoder on GPU Devices." Electronics 11, no. 21 (October 25, 2022): 3447. http://dx.doi.org/10.3390/electronics11213447.

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To meet the high throughput requirement of communication systems, the design of high-throughput low-density parity-check (LDPC) decoders has attracted significant attention. This paper proposes a high-throughput GPU-based LDPC decoder, aiming at the large-scale data process scenario, which optimizes the decoder from the perspectives of the decoding parallelism and data scheduling strategy, respectively. For decoding parallelism, the intra-codeword parallelism is fully exploited by combining the characteristics of the flooding-based decoding algorithm and GPU programming model, and the inter-codeword parallelism is improved using the single-instruction multiple-data (SIMD) instructions. For the data scheduling strategy, the utilization of off-chip memory is optimized to satisfy the demands of large-scale data processing. The experimental results demonstrate that the decoder achieves 10 Gbps throughput by incorporating the early termination mechanism on general-purpose GPU (GPGPU) devices and can also achieve a high-throughput and high-power-efficiency performance on low-power embedded GPU (EGPU) devices. Compared with the state-of-the-art work, the proposed decoder had a × 1.787 normalized throughput speedup at the same error correcting performance.

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Mosleh, Mahmood Farhan, Fadhil Sahib Hasan, and Ruaa Majeed Azeez. "Design and implementation of log domain decoder." International Journal of Electrical and Computer Engineering (IJECE) 10, no. 2 (April 1, 2020): 1454. http://dx.doi.org/10.11591/ijece.v10i2.pp1454-1468.

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Low-Density-Parity-Check (LDPC) code has become famous in communications systems for error correction, as an advantage of the robust performance in correcting errors and the ability to meet all the requirements of the 5G system. However, the mot challenge faced researchers is the hardware implementation, because of higher complexity and long run-time. In this paper, an efficient and optimum design for log domain decoder has been implemented using Xilinx system generator with FPGA device Kintex 7 (XC7K325T-2FFG900C). Results confirm that the proposed decoder gives a Bit Error Rate (BER) very closed to theory calculations which illustrate that this decoder is suitable for next generation demand which needs high data rate with very low BER.

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37

Mohsenin, Tinoosh, Houshmand Shirani-mehr, and Bevan M. Baas. "LDPC Decoder with an Adaptive Wordwidth Datapath for Energy and BER Co-Optimization." VLSI Design 2013 (May 9, 2013): 1–14. http://dx.doi.org/10.1155/2013/913018.

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An energy efficient low-density parity-check (LDPC) decoder using an adaptive wordwidth datapath is presented. The decoder switches between a Normal Mode and a reduced wordwidth Low Power Mode. Signal toggling is reduced as variable node processing inputs change in fewer bits. The duration of time that the decoder stays in a given mode is optimized for power and BER requirements and the received SNR. The paper explores different Low Power Mode algorithms to reduce the wordwidth and their implementations. Analysis of the BER performance and power consumption from fixed-point numerical and post-layout power simulations, respectively, is presented for a full parallel 10GBASE-T LDPC decoder in 65 nm CMOS. A 5.10 mm2 low power decoder implementation achieves 85.7 Gbps while operating at 185 MHz and dissipates 16.4 pJ/bit at 1.3 V with early termination. At 0.6 V the decoder throughput is 9.3 Gbps (greater than 6.4 Gbps required for 10GBASE-T) while dissipating an average power of 31 mW. This is 4.6 lower than the state of the art reported power with an SNR loss of 0.35 dB at .

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38

Zenkouar, Fatima Zahrae, Mustapha El Alaoui, and Said Najah. "GF(q) LDPC encoder and decoder FPGA implementation using group shuffled belief propagation algorithm." International Journal of Electrical and Computer Engineering (IJECE) 12, no. 3 (June 1, 2022): 2184. http://dx.doi.org/10.11591/ijece.v12i3.pp2184-2193.

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This paper presents field programmable gate array (FPGA) exercises of the GF(q) low-density parity-check (LDPC) encoder and interpreter utilizing the group shuffled belief propagation (GSBP) algorithm are presented in this study. For small blocks, non-dual LDPC codes have been shown to have a greater error correction rate than dual codes. The reduction behavior of non-binary LDPC codes over GF (16) (also known as GF(q)-LDPC codes) over the additive white Gaussian noise (AWGN) channel has been demonstrated to be close to the Shannon limit and employs a short block length (N=600 bits). At the same time, it also provides a non-binary LDPC (NB-LDPC) code set program. Furthermore, the simplified bubble check treasure event count is implemented through the use of first in first out (FIFO), which is based on an elegant design. The structure of the interpreter and the creation of the residential area he built were planned in very high speed integrated circuit (VHSIC) hardware description language (VHDL) and simulated in MODELSIM 6.5. The combined output of the Cyclone II FPGA is combined with the simulation output.

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Anbalgan, Anand, and Senthil Kumar.P. "Progressive edge growth LDPC Encoder with spiral search algorithm." International Journal of Engineering & Technology 7, no. 1.3 (December 31, 2017): 198. http://dx.doi.org/10.14419/ijet.v7i1.3.10673.

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Trapping set causes the drop of performance in error floor region. Identification of TS is done by graphical method and enumerators. The lowest odd degree (minimal) TS is increasing the formation of more unsaturated nodes in iterative decoding. Progressive edge growth (PEG) Low-density parity check code (LDPC) [2] avoidance of trapping sets are mainly based on the distance and degree calculation of successive CN. This simple tool is used to eliminate TS when the encoder ensemble designs itself. Non-zero neighborhood search also made an influence on error floor. The spiral search method is used for Non-zero codeword search (NZCW) search for the first time in this research, at the decoder part. So, Non-zero codeword spiral search (NZCSS) converge fast with less number iteration, and this reduces the iteration of the decoder.

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40

Raveendran, Nithin, and Bane Vasić. "Trapping Sets of Quantum LDPC Codes." Quantum 5 (October 14, 2021): 562. http://dx.doi.org/10.22331/q-2021-10-14-562.

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Iterative decoders for finite length quantum low-density parity-check (QLDPC) codes are attractive because their hardware complexity scales only linearly with the number of physical qubits. However, they are impacted by short cycles, detrimental graphical configurations known as trapping sets (TSs) present in a code graph as well as symmetric degeneracy of errors. These factors significantly degrade the decoder decoding probability performance and cause so-called error floor. In this paper, we establish a systematic methodology by which one can identify and classify quantum trapping sets (QTSs) according to their topological structure and decoder used. The conventional definition of a TS from classical error correction is generalized to address the syndrome decoding scenario for QLDPC codes. We show that the knowledge of QTSs can be used to design better QLDPC codes and decoders. Frame error rate improvements of two orders of magnitude in the error floor regime are demonstrated for some practical finite-length QLDPC codes without requiring any post-processing.

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41

Raveendran, Nithin, and Bane Vasić. "Trapping Sets of Quantum LDPC Codes." Quantum 5 (October 14, 2021): 562. http://dx.doi.org/10.22331/q-2021-10-14-562.

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Iterative decoders for finite length quantum low-density parity-check (QLDPC) codes are attractive because their hardware complexity scales only linearly with the number of physical qubits. However, they are impacted by short cycles, detrimental graphical configurations known as trapping sets (TSs) present in a code graph as well as symmetric degeneracy of errors. These factors significantly degrade the decoder decoding probability performance and cause so-called error floor. In this paper, we establish a systematic methodology by which one can identify and classify quantum trapping sets (QTSs) according to their topological structure and decoder used. The conventional definition of a TS from classical error correction is generalized to address the syndrome decoding scenario for QLDPC codes. We show that the knowledge of QTSs can be used to design better QLDPC codes and decoders. Frame error rate improvements of two orders of magnitude in the error floor regime are demonstrated for some practical finite-length QLDPC codes without requiring any post-processing.

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42

Kang, Peng, Kui Cai, and Xuan He. "Design of Mutual-Information-Maximizing Quantized Shuffled Min-Sum Decoder for Rate-Compatible Quasi-Cyclic LDPC Codes." Electronics 11, no. 19 (October 6, 2022): 3206. http://dx.doi.org/10.3390/electronics11193206.

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In this paper, we propose a finite alphabet iterative decoder (FAID) named rate-compatible mutual-information-maximizing quantized shuffled min-sum (RC-MIM-QSMS) decoder, for decoding quasi-cyclic low-density parity-check (QC-LDPC) codes with various code rates. Our proposed decoder exchanges the coarsely quantized messages represented by symbols from finite alphabets and adopts single-input lookup tables (LUTs) to implement the node updates. To construct the LUTs used for decoding, we first propose a modified density evolution by considering the shuffled schedule to generate the LUTs which vary with different layers and iterations. Furthermore, to reduce the memory requirement for storing the LUTs, we optimize the constructed LUTs into a unique set of LUTs that only change with different decoding iterations. To the best of our knowledge, the RC-MIM-QSMS decoder is the first one to integrate the rate compatibility of LDPC codes with the shuffled decoding schedule. Simulation results show that the proposed RC-MIM-QSMS decoder outperforms the floating-point shuffled belief propagation decoder in the high signal-to-noise region and achieves comparable convergence speed to other state-of-the-art FAIDs. Moreover, the RC-MIM-QSMS decoder is able to save up to 93.22% memory requirement compared to the benchmark MIM-FAIDs.

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43

Chehade, Tarek, Ludovic Collin, Philippe Rostaing, Emanuel Radoi, and Oussama Bazzi. "Power Allocation Optimization: Linear Precoding Adapted to NB-LDPC Coded MIMO Transmission." International Journal of Antennas and Propagation 2015 (2015): 1–11. http://dx.doi.org/10.1155/2015/975139.

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In multiple-input multiple-output (MIMO) transmission systems, the channel state information (CSI) at the transmitter can be used to add linear precoding to the transmitted signals in order to improve the performance and the reliability of the transmission system. This paper investigates how to properly join precoded closed-loop MIMO systems and nonbinary low density parity check (NB-LDPC). Theqelements in the Galois field, GF(q), are directly mapped toqtransmit symbol vectors. This allows NB-LDPC codes to perfectly fit with a MIMO precoding scheme, unlike binary LDPC codes. The new transmission model is detailed and studied for several linear precoders and various designed LDPC codes. We show that NB-LDPC codes are particularly well suited to be jointly used with precoding schemes based on the maximization of the minimum Euclidean distance (max-dmin) criterion. These results are theoretically supported by extrinsic information transfer (EXIT) analysis and are confirmed by numerical simulations.

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44

Petrović, Vladimir, and Mezeni El. "Reduced-complexity offset min-sum check node unit for layered 5G LDPC decoder." Telfor Journal 13, no. 1 (2021): 7–12. http://dx.doi.org/10.5937/telfor2101007p.

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This paper presents a novel approach for the reduced-complexity Min-Sum (MS) decoding of low density parity check (LDPC) codes in the partially parallel layered decoder architecture, which contains a large number of serial check node processors. Reduced complexity is obtained by using the variant of the single-minimum Offset Min-Sum (smOMS) algorithm that approximates a second minimum with the addition of the variable weight parameter to the minimum value. Although the reduced-complexity MS algorithms primarily reduce hardware resources in fully parallel implementations, the results showed that a considerable reduction can be obtained if serial check node processors are used. The paper also proposes a better subminimum estimation for irregular codes from 5G new radio (5G NR). The method uses smaller subminimum estimation weights in check nodes with a higher degree and higher weights in check nodes with a smaller degree, which leads to the significant improvement in the SNR performance. Additionally, it is shown that SNR performance can be further improved by applying offset before minimum calculation, which differs from conventional Min-Sum approaches.

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45

Zhang, Ji, Baoming Bai, Xijin Mu, Hengzhou Xu, Zhen Liu, and Huaan Li. "Construction and Decoding of Rate-Compatible Globally Coupled LDPC Codes." Wireless Communications and Mobile Computing 2018 (2018): 1–14. http://dx.doi.org/10.1155/2018/4397671.

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This paper presents a family of rate-compatible (RC) globally coupled low-density parity-check (GC-LDPC) codes, which is constructed by combining algebraic construction method and graph extension. Specifically, the highest rate code is constructed using the algebraic method and the codes of lower rates are formed by successively extending the graph of the higher rate codes. The proposed rate-compatible codes provide more flexibility in code rate and guarantee the structural property of algebraic construction. It is confirmed, by numerical simulations over the AWGN channel, that the proposed codes have better performances than their counterpart GC-LDPC codes formed by the classical method and exhibit an approximately uniform gap to the capacity over a wide range of rates. Furthermore, a modified two-phase local/global iterative decoding scheme for GC-LDPC codes is proposed. Numerical results show that the proposed decoding scheme can reduce the unnecessary cost of local decoder at low and moderate SNRs, without any increase in the number of decoding iterations in the global decoder at high SNRs.

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Grospellier, Antoine, Lucien Grouès, Anirudh Krishna, and Anthony Leverrier. "Combining hard and soft decoders for hypergraph product codes." Quantum 5 (April 15, 2021): 432. http://dx.doi.org/10.22331/q-2021-04-15-432.

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Hypergraph product codes are a class of constant-rate quantum low-density parity-check (LDPC) codes equipped with a linear-time decoder called small-set-flip (SSF). This decoder displays sub-optimal performance in practice and requires very large error correcting codes to be effective. In this work, we present new hybrid decoders that combine the belief propagation (BP) algorithm with the SSF decoder. We present the results of numerical simulations when codes are subject to independent bit-flip and phase-flip errors. We provide evidence that the threshold of these codes is roughly 7.5% assuming an ideal syndrome extraction, and remains close to 3% in the presence of syndrome noise. This result subsumes and significantly improves upon an earlier work by Grospellier and Krishna (arXiv:1810.03681). The low-complexity high-performance of these heuristic decoders suggests that decoding should not be a substantial difficulty when moving from zero-rate surface codes to constant-rate LDPC codes and gives a further hint that such codes are well-worth investigating in the context of building large universal quantum computers.

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Liu, Xiao Jian, Wei Xu, and Jue Wang. "LDPC Coded PPM and Iterative Detection for Free-Space Optical Links." Applied Mechanics and Materials 651-653 (September 2014): 444–50. http://dx.doi.org/10.4028/www.scientific.net/amm.651-653.444.

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The pulse position modulation, which has the advantage of average energy efficiency and bandwidth efficiency, is an attractive modulation scheme for free-space optical communication. An important practical issue is to employ an efficient channel coding to this modulation. In this view, we consider the use of low density parity-check code together with iterative soft demodulation and channel decoding at the receiver. In particular, we discuss the calculation of the soft information at the demodulator to accommodate the LDPC decoder. We show that the proposed scheme is quite efficient against demodulation errors due to the receiver noise.

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48

Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (January 5, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.1.

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Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

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Senthilpari, Chinnaiyan, Rosalind Deena, and Lee Lini. "Low power, less occupying area, and improved speed of a 4-bit router/rerouter circuit for low-density parity-check (LDPC) decoders." F1000Research 11 (November 14, 2022): 7. http://dx.doi.org/10.12688/f1000research.73404.2.

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Background: Low-density parity-check (LDPC) codes are more error-resistant than other forward error-correcting codes. Existing circuits give high power dissipation, less speed, and more occupying area. This work aimed to propose a better design and performance circuit, even in the presence of noise in the channel. Methods: In this research, the design of the multiplexer and demultiplexer were achieved using pass transistor logic. The target parameters were low power dissipation, improved throughput, and more negligible delay with a minimum area. One of the essential connecting circuits in a decoShder architecture is a multiplexer (MUX) and a demultiplexer (DEMUX) circuit. The design of the MUX and DEMUX contributes significantly to the performance of the decoder. The aim of this paper was the design of a 4 × 1 MUX to route the data bits received from the bit update blocks to the parallel adder circuits and a 1 × 4 DEMUX to receive the input bits from the parallel adder and distribute the output to the bit update blocks in a layered architecture LDPC decoder. The design uses pass transistor logic and achieves the reduction of the number of transistors used. The proposed circuit was designed using the Mentor Graphics CAD tool for 180 nm technology. Results: The parameters of power dissipation, area, and delay were considered crucial parameters for a low power decoder. The circuits were simulated using computer-aided design (CAD) tools, and the results depicted a significantly low power dissipation of 7.06 nW and 5.16 nW for the multiplexer and demultiplexer, respectively. The delay was found to be 100.5 ns (MUX) and 80 ns (DEMUX). Conclusion: This decoder’s potential use may be in low-power communication circuits such as handheld devices and Internet of Things (IoT) circuits.

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ZHENG, XIA, FRANCIS C. M. LAU, CHI K. TSE, and S. C. WONG. "STUDY OF BIFURCATION BEHAVIOR OF LDPC DECODERS." International Journal of Bifurcation and Chaos 16, no. 11 (November 2006): 3435–49. http://dx.doi.org/10.1142/s0218127406016926.

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The use of low-density-parity-check (LDPC) codes in coding digital messages has aroused much research interest because of their excellent bit-error performance. The behavior of the iterative LDPC decoders of finite length, however, has not been fully evaluated under different signal-to-noise conditions. By considering the finite-length LDPC decoders as high-dimensional nonlinear dynamical systems, we attempt to investigate their dynamical behavior and bifurcation phenomena for a range of signal-to-noise ratios (SNRs). Extensive simulations have been performed on both regular and irregular LDPC codes. Moreover, we derive the Jacobian of the system and calculate the corresponding eigenvalues. Results show that bifurcations, including fold, flip and Neimark–Sacker bifurcations, are exhibited by the LDPC decoder. Results are useful for optimizing the choice of parameters that may enhance the effectiveness of the decoding algorithm and improve the convergence rates.

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Journal articles on the topic 'Nonbinary low-density parity check (LDPC) decoder'

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