Academic literature on the topic 'Nonbinary low-density parity check (LDPC) decoder'
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Journal articles on the topic "Nonbinary low-density parity check (LDPC) decoder"
Ramachandran, Varatharajan. "An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control." International Journal of Reconfigurable and Embedded Systems (IJRES) 4, no. 1 (March 1, 2015): 6. http://dx.doi.org/10.11591/ijres.v4.i1.pp6-12.
Full textDinh, The Cuong, Huyen Pham Thi, Hung Dao Tuan, and Nghia Pham Xuan. "ONE-MINIUM-ONLY BASIC-SET TRELLIS MIN-MAX DECODER ARCHITECTURE FOR NONBINARY LDPC CODE." Journal of Computer Science and Cybernetics 37, no. 2 (May 31, 2021): 91–106. http://dx.doi.org/10.15625/1813-9663/37/2/15917.
Full textPham, Huyen Thi, Hung Tuan Dao, and Nghia Xuan Pham. "Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder." Journal of Science and Technology on Information security 9, no. 01 (April 9, 2020): 12–19. http://dx.doi.org/10.54654/isj.v9i01.36.
Full textRevathy, M., and R. Saravanan. "A Low-Complexity Euclidean Orthogonal LDPC Architecture for Low Power Applications." Scientific World Journal 2015 (2015): 1–8. http://dx.doi.org/10.1155/2015/327357.
Full textSułek, W. "Pipeline processing in low-density parity-check codes hardware decoder." Bulletin of the Polish Academy of Sciences: Technical Sciences 59, no. 2 (June 1, 2011): 149–55. http://dx.doi.org/10.2478/v10175-011-0019-9.
Full textAli Jassim, Amjad, Wael A. Hadi., and Muhanned Ismael Ibrahim Al-Firas. "Serially Concatenated Low-density Parity Check Codes as Compatible Pairs." International Journal of Engineering & Technology 7, no. 4.15 (October 7, 2018): 301. http://dx.doi.org/10.14419/ijet.v7i4.15.23013.
Full textKuc, Mateusz, Wojciech Sułek, and Dariusz Kania. "Low Power QC-LDPC Decoder Based on Token Ring Architecture." Energies 13, no. 23 (November 30, 2020): 6310. http://dx.doi.org/10.3390/en13236310.
Full textHao, Ning, Yang An Zhang, Jin Nan Zhang, Ming Lun Zhang, and Xue Guang Yuan. "An Application of LDPC Code for Wireless Coherent-Light Commutation in Atmospheric Channel." Applied Mechanics and Materials 347-350 (August 2013): 1864–67. http://dx.doi.org/10.4028/www.scientific.net/amm.347-350.1864.
Full textLin, Cheng-Hung, Tzu-Hsuan Huang, Shu-Yen Lin, and Yu-Hsuan Lee. "Design and Implementation of Operation-Reduced LDPC Decoder Based on a Check Node Stopping Scheme." Journal of Circuits, Systems and Computers 26, no. 02 (November 3, 2016): 1750028. http://dx.doi.org/10.1142/s0218126617500281.
Full textMishra, Rajarshini. "Design of Quasi-Cyclic Low Density Parity Check Decoder Using Optimized Min-Sum Algorithm." International Journal Of Engineering And Computer Science 7, no. 03 (March 26, 2018): 23781–84. http://dx.doi.org/10.18535//ijecs/v7i3.21.
Full textDissertations / Theses on the topic "Nonbinary low-density parity check (LDPC) decoder"
Liu, Yue Electrical Engineering & Telecommunications Faculty of Engineering UNSW. "Design of structured nonbinary quasi-cyclic low-density parity-check codes." Publisher:University of New South Wales. Electrical Engineering & Telecommunications, 2009. http://handle.unsw.edu.au/1959.4/43616.
Full textKopparthi, Sunitha. "Flexible encoder and decoder designs for low-density parity-check codes." Diss., Manhattan, Kan. : Kansas State University, 2010. http://hdl.handle.net/2097/4190.
Full textZhang, Kai. "High-Performance Decoder Architectures For Low-Density Parity-Check Codes." Digital WPI, 2012. https://digitalcommons.wpi.edu/etd-dissertations/17.
Full textSelvarathinam, Anand Manivannan. "High throughput low power decoder architectures for low density parity check codes." Texas A&M University, 2005. http://hdl.handle.net/1969.1/2529.
Full textShadab, Rakin Muhammad. "Statistical Analysis of a Channel Emulator for Noisy Gradient Descent Low Density Parity Check Decoder." DigitalCommons@USU, 2019. https://digitalcommons.usu.edu/etd/7582.
Full textYang, Lan. "An Area-Efficient Architecture for the Implementation of LDPC Decoder." Case Western Reserve University School of Graduate Studies / OhioLINK, 2011. http://rave.ohiolink.edu/etdc/view?acc_num=case1300337576.
Full textVon, Leipzig Mirko. "Code generation and simulation of an automatic, flexible QC-LDPC hardware decoder." Thesis, Stellenbosch : Stellenbosch University, 2015. http://hdl.handle.net/10019.1/96835.
Full textENGLISH ABSTRACT: Iterative error correcting codes such as LDPC codes have become prominent in modern forward error correction systems. A particular subclass of LDPC codes known as quasicyclic LDPC codes has been incorporated in numerous high speed wireless communication and video broadcasting standards. These standards feature multiple codes with varying codeword lengths and code rates and require a high throughput. Flexible hardware that is capable of decoding multiple quasi-cyclic LDPC codes is therefore desirable. This thesis investigates binary quasi-cyclic LDPC codes and designs a generic, flexible VHDL decoder. The decoder is further enhanced to automatically select the most likely decoder based on the initial a posterior probability of the parity-check equation syndromes. A software system is developed that generates hardware code for such a decoder based on a small user specification. The system is extended to provide performance simulations for this generated decoder.
AFRIKAANSE OPSOMMING: Iteratiewe foutkorreksiekodes soos LDPC-kodes word wyd gebruik in moderne voorwaartse foutkorreksiestelsels. ’n Subklas van LDPC-kodes, bekend as kwasisikliese LDPC-kodes, word in verskeie hoëspoed-kommunikasie- en video-uitsaaistelselstandaarde gebruik. Hierdie standaarde inkorporeer verskeie kodes van wisselende lengtes en kodetempos, en vereis hoë deurset. Buigsame apparatuur, wat die vermoë het om ’n verskeidenheid kwasisikliese LDPC-kodes te dekodeer, is gevolglik van belang. Hierdie tesis ondersoek binêre kwasisikliese LDPC-kodes, en ontwerp ’n generiese, buigsame VHDL-dekodeerder. Die dekodeerder word verder verbeter om outomaties die mees waarskynlike dekodeerder te selekteer, gebaseer op die aanvanklike a posteriori-waarskynlikheid van die pariteitstoetsvergelykings se sindrome. ’n Programmatuurstelsel word ontwikkel wat die fermware-kode vir so ’n dekodeerder genereer, gebaseer op ’n beknopte gebruikerspesifikasie. Die stelsel word uitgebrei om werksverrigting te simuleer vir die gegenereerde dekodeerder.
Gunnam, Kiran Kumar. "Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation." [College Station, Tex. : Texas A&M University, 2006. http://hdl.handle.net/1969.1/ETD-TAMU-1049.
Full textMatcha, Chaitanya Kumar, Mohsen Bahrami, Shounak Roy, Shayan Garani Srinivasa, and Bane Vasic. "Generalized belief propagation based TDMR detector and decoder." IEEE, 2016. http://hdl.handle.net/10150/622831.
Full textMalema, Gabofetswe Alafang. "Low-density parity-check codes : construction and implementation." 2007. http://hdl.handle.net/2440/45525.
Full textThesis(Ph.D.) -- University of Adelaide, School of Electrical and Electronic Engineering, 2007
Book chapters on the topic "Nonbinary low-density parity check (LDPC) decoder"
Shankar Prasad, Mani, and Shivani Verma. "Irreducible Polynomials: Non-Binary Fields." In Recent Advances in Polynomials [Working Title]. IntechOpen, 2022. http://dx.doi.org/10.5772/intechopen.101897.
Full textConference papers on the topic "Nonbinary low-density parity check (LDPC) decoder"
Zarubica, Radivoje, Stephen G. Wilson, and Eric Hall. "Multi-Gbps FPGA-Based Low Density Parity Check (LDPC) Decoder Design." In IEEE GLOBECOM 2007-2007 IEEE Global Telecommunications Conference. IEEE, 2007. http://dx.doi.org/10.1109/glocom.2007.108.
Full textZhu, Yuming, Yanni Chen, Dale Hocevar, and Manish Goel. "A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder." In 2006 IEEE Workshop on Signal Processing Systems Design and Implementation. IEEE, 2006. http://dx.doi.org/10.1109/sips.2006.352560.
Full textShoup, Ryan. "Hardware implementation and characterization of a low density parity check (LDPC) decoder." In SPIE Optics + Photonics, edited by Roger W. Heymann, Charles C. Wang, and Timothy J. Schmit. SPIE, 2006. http://dx.doi.org/10.1117/12.682607.
Full textDuangthong, Chatuporn, and Watid Phakphisut. "Design of Lookup-Table (LUT) Decoder for Protograph-Based Low-Density Parity-Check (LDPC) codes." In 2022 37th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC). IEEE, 2022. http://dx.doi.org/10.1109/itc-cscc55581.2022.9895041.
Full textMaheshwari, Abhishek, Usana Tuntoolavest, and Kazuhiko Fukawa. "Implementation of the Nonbinary Encoder and Decoder for Systematic Low Density Parity Check Codes on Raspberry-pi boards." In 2020 11th IEEE Annual Information Technology, Electronics and Mobile Communication Conference (IEMCON). IEEE, 2020. http://dx.doi.org/10.1109/iemcon51383.2020.9284943.
Full textJemima, A., and G. Manoj. "Post and pre-layout analysis of Low Density Parity Check (LDPC) decoder using 120nm technology Cadence Encounter Tool." In 2015 2nd International Conference on Electronics and Communication Systems (ICECS). IEEE, 2015. http://dx.doi.org/10.1109/ecs.2015.7124921.
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