Journal articles: 'Non-Volatile SRAM'

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Wang, Ming Qian, Jie Tao Diao, Nan Li, Xi Wang, and Kai Bu. "A Study on Reconfiguring On-Chip Cache with Non-Volatile Memory." Applied Mechanics and Materials 644-650 (September 2014): 3421–25. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3421.

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NVM has become a promising technology to partly replace SRAM as on-chip cache and reduce the gap between the core and cache. To take all advantages of NVM and SRAM, we propose a Hybrid Cache, constructing on-chip cache hierarchies with different technologies. As shown in article, hybrid cache performance and power consumption of Hybrid Cache have a large advantage over caches base on single technologies. In addition, we have shown some other methods that can optimize the performance of hybrid cache.

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Mispan, Mohd Syafiq, Aiman Zakwan Jidin, Muhammad Raihaan Kamarudin, and Haslinah Mohd Nasir. "Lightweight hardware fingerprinting solution using inherent memory in off-the-shelf commodity devices." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (January 1, 2022): 105. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp105-112.

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An emerging technology known as Physical unclonable function (PUF) can provide a hardware root-of-trust in building the trusted computing system. PUF exploits the intrinsic process variations during the integrated circuit (IC) fabrication to generate a unique response. This unique response differs from one PUF to the other similar type of PUFs. Static random-access memory PUF (SRAM-PUF) is one of the memory-based PUFs in which the response is generated during the memory power-up process. Non-volatile memory (NVM) architecture like SRAM is available in off-the-shelf microcontroller devices. Exploiting the inherent SRAM as PUF could wide-spread the adoption of PUF. Therefore, in this study, we evaluate the suitability of inherent SRAM available in ATMega2560 microcontroller on Arduino platform as PUF that can provide a unique fingerprint. First, we analyze the start-up values (SUVs) of memory cells and select only the cells that show random values after the power-up process. Subsequently, we statistically analyze the characteristic of fifteen SRAM-PUFs which include uniqueness, reliability, and uniformity. Based on our findings, the SUVs of fifteen on-chip SRAMs achieve 42.64% uniqueness, 97.28% reliability, and 69.16% uniformity. Therefore, we concluded that the available SRAM in off-the-shelf commodity hardware has good quality to be used as PUF.

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Angizi, Shaahin, Navid Khoshavi, Andrew Marshall, Peter Dowben, and Deliang Fan. "MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET." ACM Transactions on Design Automation of Electronic Systems 27, no. 2 (March 31, 2022): 1–18. http://dx.doi.org/10.1145/3484222.

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Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time, build a device-to-architecture cross-layer evaluation framework to quantitatively analyze and benchmark the MeF-RAM design with other memory technologies, including both volatile memory (i.e., SRAM, eDRAM) and other popular non-volatile emerging memory (i.e., ReRAM, STT-MRAM, and SOT-MRAM). The experiment results for the PARSEC benchmark suite indicate that, as an L2 cache memory, MeF-RAM reduces Energy Area Latency ( EAT ) product on average by ~98% and ~70% compared with typical 6T-SRAM and 2T1R SOT-MRAM counterparts, respectively.

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Vijay, H. M., and V. N. Ramakrishnan. "Radiation effects on memristor-based non-volatile SRAM cells." Journal of Computational Electronics 17, no. 1 (November 8, 2017): 279–87. http://dx.doi.org/10.1007/s10825-017-1080-x.

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Singh, Damyanti, Neeta Pandey, and Kirti Gupta. "Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell." Microelectronics Journal 135 (May 2023): 105773. http://dx.doi.org/10.1016/j.mejo.2023.105773.

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Janniekode, Uma Maheshwar, Rajendra Prasad Somineni, Osamah Ibrahim Khalaf, Malakeh Muhyiddeen Itani, J. Chinna Babu, and Ghaida Muttashar Abdulsahib. "A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications." Symmetry 14, no. 4 (April 7, 2022): 768. http://dx.doi.org/10.3390/sym14040768.

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This paper proposes a symmetric eight transistor-three-memristor (8T3R) non-volatile static random-access memory (NVSRAM) cell. Non-volatile operation is achieved through the use of a memristor element, which stores data in the form of its resistive state and is referred to as RRAM. This cell is able to store the information after power-off mode and provides fast power-on/power-off speeds. The proposed symmetric 8T3R NVSRAM cell performs better instant-on operation compared to existing NVSRAMs at different technology nodes. The simulation results show that resistance of RAM-based 8T3R SRAM cell consumes less power in standby mode and has excellent switching performance during power on/off speed. It also has better read and write stability and significantly improves noise tolerance than the conventional asymmetrical 6T SRAM and other NVSRAM cells. The power dissipation is evaluated at different technology nodes. Hence, our proposed symmetric 8T3R NVSRAM cell is suitable to use at low power and embedded applications.

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Priya, G. Lakshmi, Namita Rawat, Abhishek Sanagavarapu, M. Venkatesh, and A. Andrew Roobert. "Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell." Micromachines 14, no. 2 (January 17, 2023): 232. http://dx.doi.org/10.3390/mi14020232.

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Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatile, memristive devices are also characterized by the high switching frequency, low wattage requirement, and compact size. Traditional transistors can be replaced by silicon substrate-based FinFETs, which are substantially more efficient in terms of area and power, to improve the design. As a result, the design of non-volatile SRAM cell in conjunction with silicon substrate-based FinFET and Metal Insulator Metal (MIM) based Memristor is proposed and compared to traditional SRAMs. The power consumption of the proposed hybrid design has outperformed the standard Silicon substrate FinFET design by 91.8% better. It has also been reported that the delay for the suggested design is actually quite a bit shorter, coming in at approximately 1.989 ps. The proposed architecture has been made significantly more practical for use as a low-power and high-speed memory system because of the incorporation of high-K insulation at the interface of metal regions. In addition, Monte Carlo (MC) simulations have been run for the reported 6T-SRAM designs in order to have a better understanding of the device stability.

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Khan, Asif. "(Invited) Ferroelectric Field-Effect Transistors as High-Density, Ultra-fast, Embedded Non-Volatile Memories." ECS Meeting Abstracts MA2022-02, no. 15 (October 9, 2022): 805. http://dx.doi.org/10.1149/ma2022-0215805mtgabs.

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Ferroelectric field-effect transistors (FEFETs) are receiving significant attention from the microelectronics community for next-generation memory technologies, especially as embedded non-volatile elements for data-centric applications. The main attractive features of FEFETs are that write energy and speed of FEFETs are within an order of magnitude of respective metrics for SRAMs (FEFET ~1 fJ and 1-10 ns vs. SRAM: <1 fJ and <1 ns), all the while requiring a significantly smaller cell size (FEFET 50-60F2 vs. SRAM 120-150F2) and close-to-zero standby leakage power – provided that FEFETs are integrated at the same advanced technology nodes as SRAMs [1]. In this talk, we will discuss the potential path for FEFET toward fulfilling this vision, by addressing the outstanding technological challenges: ultra-fast read-after write, reliability, voltage scaling and variation. To that end, our recent exposition on the trap and reliability physics of FEFETs will highlighted. We will highlight, based on newly developed experimental schemes, how the simultaneous capture and emission of electrons and holes in write cycles occur at the interface and the grain boundaries in the time domain, where in the band-diagram, these traps (acceptors and donors) are located and how exactly they result in the degradation of the read speed and reliability with continued write cycling. Based on these insights, we move on show how engineering the interfacial layer and the ferroelectric grain structure can enable ultra-fast read-after write and write voltage and dramatic improvements in reliability and variation, towards achieving a high-density, ultra-high speed memory technology. This research is supported by the National Science Foundation, the Defense Advanced Research Program Agency (DARPA), the Semiconductor Research Corporation (SRC) - Global Research Collaboration (GRC) program, the Applications and Systems-Driven Center for Energy-Efficient Integrated Nano Technologies (ASCENT), one of six centers in the Joint University Microelectronics Program (JUMP), a SRC program sponsored by the DARPA, and an Intel Rising Star award. [1] Mikolajick, T., Schroeder, U. & Slesazeck, S. The past, the present, and the future of ferroelectric memories. IEEE Trans. Electron Devices 67, 1434–1443 (2020). [2] Asif Islam Khan, Ali Keshavarzi, and Suman Datta. “The future of ferroelectric field-effect transistor technology." Nature Electronics 3.10 (2020): 588-597.

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Pan, James N. "Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology." MRS Advances 4, no. 48 (2019): 2577–84. http://dx.doi.org/10.1557/adv.2019.212.

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ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of only one transistor (MOSFET) – small size, and more cost effective, compared with a 6-Transistor SRAM. There is no need to refresh, as required by DRAM. The access time can be less than 1ns – close to the speed level of relaxation time - much faster than traditional FLASH memories and comparable to volatile DRAM. The operating voltages for all memory functions can be as low as high speed CMOS.

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P, Saleem Akram. "Non-Volatile 7T1R SRAM cell design for low voltage applications." International Journal of Emerging Trends in Engineering Research 7, no. 11 (November 15, 2019): 704–7. http://dx.doi.org/10.30534/ijeter/2019/487112019.

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Wang, Jinhui, Lina Wang, Haibin Yin, Zikui Wei, Zezhong Yang, and Na Gong. "cNV SRAM: CMOS Technology Compatible Non-Volatile SRAM Based Ultra-Low Leakage Energy Hybrid Memory System." IEEE Transactions on Computers 65, no. 4 (April 1, 2016): 1055–67. http://dx.doi.org/10.1109/tc.2014.2375187.

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Jafari, Atousa, Christopher Münch, and Mehdi Tahoori. "A Spintronic 2M/7T Computation-in-Memory Cell." Journal of Low Power Electronics and Applications 12, no. 4 (December 6, 2022): 63. http://dx.doi.org/10.3390/jlpea12040063.

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Computing data-intensive applications on the von Neumann architecture lead to significant performance and energy overheads. The concept of computation in memory (CiM) addresses the bottleneck of von Neumann machines by reducing the data movement in the computing system. Emerging resistive non-volatile memory technologies, as well as volatile memories (SRAM and DRAM), can be used to realize architectures based on the CiM paradigm. In this paper, we propose a hybrid cell design to provide the opportunity for CiM by combining the magnetic tunnel junction (MTJ) and the conventional 6T-SRAM cell. The cell performs CiM operations based on stateful in-array computation, which has better scalability for multiple operands compared with stateless computation in the periphery. Various logic operations such as XOR, OR, and IMP can be performed with the proposed design. In addition, the proposed cell can also operate as a conventional memory cell to read and write volatile as well as non-volatile data. The obtained simulation results show that the proposed CiM-A design can increase the performance of regular memory architectures by reducing the delay by 8 times and the energy by 13 times for database query applications consisting of consecutive bitwise operations with minimum overhead.

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Jovanovic, Bojan, Raphael Brum, and Lionel Torres. "MTJ-based hybrid storage cells for “normally-off and instant-on” computing." Facta universitatis - series: Electronics and Energetics 28, no. 3 (2015): 465–76. http://dx.doi.org/10.2298/fuee1503465j.

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Besides increasing a computing throughput, multi-core processor architectures bring increased capacity of SRAM-based cache memory. As a result, cache memory now occupies large proportion of recent processor chips, becoming a major source of the leakage power consumption. The power gating technique applied on a SRAM cache is not efficient since it is paid by data loss. In this paper, we present two hybrid memory cells that combine a conventional volatile CMOS part with Magnetic Tunnel Junctions (MTJs) able to store a data bit in a non-volatile way. Being inherently non-volatile, these hybrid cells enable instantaneous power off and thus complete reduction of the leakage power. Moreover, given that the data bit can be stored in local MTJs and not in distant storage memories, these cells also offer instantaneous and efficient data retrieval. To demonstrate their functionality, the cells are designed using 28 nm FD-SOI technology for the CMOS part and 45 nm round spin transfer torque MTJs (STT-MTJs) with perpendicular magnetization anisotropy. We report the measured performances of the cells in terms of required silicon area, robustness, read/write speed and energy consumption.

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Sharma, Parul, Balwinder Raj, and Sandeep Singh Gill. "Spintronics Based Non-Volatile MRAM for Intelligent Systems." International Journal on Semantic Web and Information Systems 18, no. 1 (January 1, 2022): 1–16. http://dx.doi.org/10.4018/ijswis.310056.

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In this paper the spintronic-based memory MRAM is presented that showed how it can replace both SRAM and DRAM and provide the high speed with great chip size. Moreover, MRAM is the nonvolatile memory that provides great advancement in the storage process. The different types of MRAM are mentioned with the techniques used for writing purpose and also mention which one is more used and why. The basic working principle and the function performed by the MRAM are discussed. Artificial intelligence (AI) is mentioned with its pros and cons for intelligent systems. Neuromorphic computing is also explained along with its important role in intelligent systems. Some reasons are also discussed as to why neuromorphic computing is so important. This paper also presents how spintronic-based devices especially memory can be used in intelligent systems and neuromorphic computing. Nanoscale spintronic-based MRAM plays a key role in intelligent systems and neuromorphic computing applications.

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Mounica, J., and G. V. Ganesh. "Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1183. http://dx.doi.org/10.11591/ijece.v6i3.9448.

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Now-a-days, Energy consumption is the major key factor in Memories. By switching the circuit in off mode and with an lower voltages, leads to decrease in an power dissipation of the circuit. Compared to DRAM SRAM’S are mostly used because of their data retaining capability. The major advantage of using SRAM’s rather than DRAM’S is that, they are providing fast power-on/off speeds. Hence SRAM’s are more preferred over DRAM’s for better instant-on operation. Generally SRAM’s are classified in to two types namely volatile and non-volatile SRAM’s. A non-volatile SRAM enables chip to achieve performance factors and also provides an restore operation which will be enabled by an restore signal to restore the data and also power-up operation is performed. This paper describes about novel NVSRAM circuit which produces better “instant-on operation” compared to previous techniques used in SRAM’s. In addition to normal 6T SRAM core, we are using RRAM circuitry (Resistive RAM) to provide better instant-on operation. By comparing the performance factors with 8T2R and 9T2R, 8T1R design performs the best in the Nano meter scale. Thus this paper provides better performances in power, energy, propagation delay and area factors as compared with other designs.

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Mounica, J., and G. V. Ganesh. "Design Of A Nonvolatile 8T1R SRAM Cell For Instant-On Operation." International Journal of Electrical and Computer Engineering (IJECE) 6, no. 3 (June 1, 2016): 1183. http://dx.doi.org/10.11591/ijece.v6i3.pp1183-1189.

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Now-a-days, Energy consumption is the major key factor in Memories. By switching the circuit in off mode and with an lower voltages, leads to decrease in an power dissipation of the circuit. Compared to DRAM SRAM’S are mostly used because of their data retaining capability. The major advantage of using SRAM’s rather than DRAM’S is that, they are providing fast power-on/off speeds. Hence SRAM’s are more preferred over DRAM’s for better instant-on operation. Generally SRAM’s are classified in to two types namely volatile and non-volatile SRAM’s. A non-volatile SRAM enables chip to achieve performance factors and also provides an restore operation which will be enabled by an restore signal to restore the data and also power-up operation is performed. This paper describes about novel NVSRAM circuit which produces better “instant-on operation” compared to previous techniques used in SRAM’s. In addition to normal 6T SRAM core, we are using RRAM circuitry (Resistive RAM) to provide better instant-on operation. By comparing the performance factors with 8T2R and 9T2R, 8T1R design performs the best in the Nano meter scale. Thus this paper provides better performances in power, energy, propagation delay and area factors as compared with other designs.

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Ge, Fen, Lei Wang, Ning Wu, and Fang Zhou. "A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs." Electronics 8, no. 6 (June 6, 2019): 639. http://dx.doi.org/10.3390/electronics8060639.

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Recently, in 3D Chip-Multiprocessors (CMPs), a hybrid cache architecture of SRAM and Non-Volatile Memory (NVM) is generally used to exploit high density and low leakage power of NVM and a low write overhead of SRAM. The conventional access policy does not consider the hybrid cache and cannot make good use of the characteristics of both NVM and SRAM technology. This paper proposes a Cache Fill and Migration policy (CFM) for multi-level hybrid cache. In CFM, data access was optimized in three aspects: Cache fill, cache eviction, and dirty data migration. The CFM reduces unnecessary cache fill, write operations to NVM, and optimizes the victim cache line selection in cache eviction. The results of experiments show that the CFM can improve performance by 24.1% and reduce power consumption by 18% when compared to conventional writeback access policy.

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., D. Ane Delphin. "DESIGN OF A 4-BIT NON-VOLATILE SRAM USING MAGNETIC TUNNEL JUNCTION." International Journal of Research in Engineering and Technology 05, no. 16 (May 25, 2016): 186–91. http://dx.doi.org/10.15623/ijret.2016.0516039.

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Lemanov, V. V., Yu V. Frolov, A. A. Iofan, and V. K. Yarmarkin. "Some physical and technological aspects of designing of ferroelectric non-volatile SRAM." Microelectronic Engineering 29, no. 1-4 (December 1995): 37–40. http://dx.doi.org/10.1016/0167-9317(95)00111-5.

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Itoh, Kiyoo. "Trends in low-voltage embedded-RAM technology." Facta universitatis - series: Electronics and Energetics 15, no. 1 (2002): 1–12. http://dx.doi.org/10.2298/fuee0201001i.

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First, trends in the gate-oxide thickness of MOSFET for DRAM and MPU are discussed to clarify the strong need for low-voltage operation of embedded RAMs. Then, modern peripheral logic circuits for reducing leakage currents and DRAM/SRAM cells to cope with the ever-decreasing signal charges are described. Finally, needs for developments of subthreshold-current reduction circuits for use in active mode, memory-rich SoC architectures, and gain cells and non-volatile cells are emphasized.

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Shin, Donghwa. "Design Space Exploration of EEPROM-SRAM Hybrid Non-volatile Counter Considering Energy Consumption and Memory Endurance." IEMEK Journal of Embedded Systems and Applications 11, no. 4 (August 31, 2016): 201–8. http://dx.doi.org/10.14372/iemek.2016.11.4.201.

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Bazzi, Hussein, Hassen Aziza, Mathieu Moreau, and Adnan Harb. "Performances and Stability Analysis of a Novel 8T1R Non-Volatile SRAM (NVSRAM) versus Variability." Journal of Electronic Testing 37, no. 4 (August 2021): 515–32. http://dx.doi.org/10.1007/s10836-021-05965-x.

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Lin, Zhiting, Yong Wang, Chunyu Peng, Wenjuan Lu, Xuan Li, Xiulong Wu, and Junning Chen. "Read‐decoupled 8T1R non‐volatile SRAM with dual‐mode option and high restore yield." Electronics Letters 55, no. 9 (May 2019): 519–21. http://dx.doi.org/10.1049/el.2019.0295.

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Junsangsri, Pilin, Jie Han, and Fabrizio Lombardi. "Design of a hybrid non-volatile SRAM cell for concurrent SEU detection and correction." Integration 52 (January 2016): 156–67. http://dx.doi.org/10.1016/j.vlsi.2015.09.005.

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Abbasi, Alireza, Farbod Setoudeh, Mohammad Bagher Tavakoli, and Ashkan Horri. "A novel design of high performance and robust ultra-low power SRAM cell based on memcapacitor." Nanotechnology 33, no. 16 (January 24, 2022): 165202. http://dx.doi.org/10.1088/1361-6528/ac46d6.

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Abstract The present paper proposes a six-FinFET two-memcapacitor (6T2MC) non-volatile static random-access memory (NVSRAM). In this design, the two memcapacitors are used as non-volatile memory elements. The proposed cell is flexible against data loss when turned off and offers significant improvement in read and write operations compared to previous NVSRAMs. The performance of the new NVSRAM design is evaluated in terms of read and write operation at particular nanometric feature sizes. Moreover, the proposed 6T2MC cell is compared with 8T2R, 8T1R, 7T1R, and 7T2R cells. The results show that 6T2MC has a 5.50% lower write delay and 98.35% lower read delay compared to 7T2R and 7T1R cells, respectively. The 6T2MC cell exhibits 38.86% lower power consumption and 23.80% lower leakage power than 7T2R and 7T1R cells. The proposed cell is significantly improved in terms of HSNM, RSNM, and WSNM compared to 8T2R, 8T1R, 7T2R, and 7T1R cells, respectively. Important cell parameters, such as power consumption, data read/write delay, and SNM, are significantly improved. The superior characteristics of FinFET over MOSFET and the combination of this technology with memcapacitors lead to significant improvement in the proposed design.

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Bagheriye, Leila, Siroos Toofan, Roghayeh Saeidi, Behzad Zeinali, and Farshad Moradi. "A Reduced Store/Restore Energy MRAM-Based SRAM Cell for a Non-Volatile Dynamically Reconfigurable FPGA." IEEE Transactions on Circuits and Systems II: Express Briefs 65, no. 11 (November 2018): 1708–12. http://dx.doi.org/10.1109/tcsii.2017.2768409.

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Rani, Khushboo, and Hemangee K. Kapoor. "Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects." IET Computers & Digital Techniques 13, no. 6 (November 1, 2019): 481–92. http://dx.doi.org/10.1049/iet-cdt.2019.0039.

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Asad, Arghavan, Mahdi Fazeli, Mohammad Reza Jahed-Motlagh, Mahmood Fathy, and Farah Mohammadi. "An Energy-Efficient Reliable Heterogeneous Uncore Architecture for Future 3D Chip-Multiprocessors." Journal of Circuits, Systems and Computers 28, no. 13 (March 12, 2019): 1950224. http://dx.doi.org/10.1142/s0218126619502244.

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Uncore components such as cache hierarchy and on-chip interconnects consume a significant portion of overall energy consumption in emerging embedded processors. In Nanoscale technologies, static power consumption due to leakage current has become a serious issue in the design of SRAM-based on-chip cache memories and interconnections. To address this issue, non-volatile memory technologies such as STT-RAMs have been proposed as a replacement for SRAM cells due to their near-zero static power and high memory density. Nonetheless, STT-RAMs suffer from some failures such as read-disturb and limited endurance as well as high switching energy. One effective way to decrease the STTRAMs’ switching energy is to reduce their retention time; however, reducing the retention time has a negative impact on the reliability of STT-RAM cells. In this paper, we propose a heterogeneous last level cache (LLC) architecture for 3D embedded chip-multiprocessors (3D eCMPs) which employs two types of STT-RAM memory banks with retention time of 1s and 10ms to provide a beneficial trade-off between reliability, energy consumption, and performance. To this end, we also propose a convex optimization model to find the optimal configurations for these two kinds of memory banks. In parallel with hybrid memory architecting, optimizing the number and placement of through silicon vias (TSVs) as a main component of on-chip interconnection for building 3D CMPs is another important target of the proposed optimization approach. Experimental results show that the proposed method improves the energy-delay products and throughput by about 69% and 34.5% on average compared with SRAM configurations.

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Kanika, R. Sankara Prasad, Nitin Chaturvedi, and S. Gurunarayanan. "A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications." Integration 65 (March 2019): 43–50. http://dx.doi.org/10.1016/j.vlsi.2018.11.002.

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Hraziia, Adam Makosiej, Giorgio Palma, Jean-Michel Portal, Marc Bocquet, Olivier Thomas, Fabien Clermidy, et al. "Operation and stability analysis of bipolar OxRRAM-based Non-Volatile 8T2R SRAM as solution for information back-up." Solid-State Electronics 90 (December 2013): 99–106. http://dx.doi.org/10.1016/j.sse.2013.02.045.

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Zhang, Honghong, and Guoguo Zhang. "Review of Research on Storage Development." Scalable Computing: Practice and Experience 22, no. 3 (November 21, 2021): 365–85. http://dx.doi.org/10.12694/scpe.v22i3.1904.

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The development of computer external storage has undergone the continuous change of perforated cassettes, tapes, floppy disks, hard disks, optical disks and flash disks. Internal memory has gone through the development of drum storage, Williams tube, mercury delay line, and magnetic core storage, until the emergence of semiconductor memory. Later RAM and ROM were born. RAM was divided into DRAM and SRAM. Due to its structure and cost advantages, DRAM has gradually developed into the widely used DDR series. At the same time, the low-power LPDDR series has also been advancing. At present, with the development of NVRAM technology, non-volatile random access memory with both internal and external storage functions is born. Dual-space storage based on NVRAM combines internal and external storage into one, and large capacity dual-space storage has become the development trend of storage.

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Luo, Yandong, Panni Wang, and Shimeng Yu. "Accelerating On-Chip Training with Ferroelectric-Based Hybrid Precision Synapse." ACM Journal on Emerging Technologies in Computing Systems 18, no. 2 (April 30, 2022): 1–20. http://dx.doi.org/10.1145/3473461.

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In this article, we propose a hardware accelerator design using ferroelectric transistor (FeFET)-based hybrid precision synapse (HPS) for deep neural network (DNN) on-chip training. The drain erase scheme for FeFET programming is incorporated for both FeFET HPS design and FeFET buffer design. By using drain erase, high-density FeFET buffers can be integrated onchip to store the intermediate input-output activations and gradients, which reduces the energy consuming off-chip DRAM access. Architectural evaluation results show that the energy efficiency could be improved by 1.2× ∼ 2.1×, 3.9× ∼ 6.0× compared to the other HPS-based designs and emerging non-volatile memory baselines, respectively. The chip area is reduced by 19% ∼ 36% compared with designs using SRAM on-chip buffer even though the capacity of FeFET buffer is increased. Besides, by utilizing drain erase scheme for FeFET programming, the chip area is reduced by 11% ∼ 28.5% compared with the designs using body erase scheme.

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Escuin, Carlos, Pablo Ibáñez, Denis Navarro, Teresa Monreal, José M. Llabería, and Víctor Viñals. "L2C2: Last-level compressed-contents non-volatile cache and a procedure to forecast performance and lifetime." PLOS ONE 18, no. 2 (February 7, 2023): e0278346. http://dx.doi.org/10.1371/journal.pone.0278346.

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Several emerging non-volatile (NV) memory technologies are rising as interesting alternatives to build the Last-Level Cache (LLC). Their advantages, compared to SRAM memory, are higher density and lower static power, but write operations wear out the bitcells to the point of eventually losing their storage capacity. In this context, this paper presents a novel LLC organization designed to extend the lifetime of the NV data array and a procedure to forecast in detail the capacity and performance of such an NV-LLC over its lifetime. From a methodological point of view, although different approaches are used in the literature to analyze the degradation of an NV-LLC, none of them allows to study in detail its temporal evolution. In this sense, this work proposes a forecasting procedure that combines detailed simulation and prediction, allowing an accurate analysis of the impact of different cache control policies and mechanisms (replacement, wear-leveling, compression, etc.) on the temporal evolution of the indices of interest, such as the effective capacity of the NV-LLC or the system IPC. We also introduce L2C2, a LLC design intended for implementation in NV memory technology that combines fault tolerance, compression, and internal write wear leveling for the first time. Compression is not used to store more blocks and increase the hit rate, but to reduce the write rate and increase the lifetime during which the cache supports near-peak performance. In addition, to support byte loss without performance drop, L2C2 inherently allows N redundant bytes to be added to each cache entry. Thus, L2C2+N, the endurance-scaled version of L2C2, allows balancing the cost of redundant capacity with the benefit of longer lifetime. For instance, as a use case, we have implemented the L2C2 cache with STT-RAM technology. It has affordable hardware overheads compared to that of a baseline NV-LLC without compression in terms of area, latency and energy consumption, and increases up to 6-37 times the time in which 50% of the effective capacity is degraded, depending on the variability in the manufacturing process. Compared to L2C2, L2C2+6 which adds 6 bytes of redundant capacity per entry, that means 9.1% of storage overhead, can increase up to 1.4-4.3 times the time in which the system gets its initial peak performance degraded.

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Garzón, Esteban, Adam Teman, and Marco Lanuzza. "Embedded Memories for Cryogenic Applications." Electronics 11, no. 1 (December 25, 2021): 61. http://dx.doi.org/10.3390/electronics11010061.

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The ever-growing interest in cryogenic applications has prompted the investigation for energy-efficient and high-density memory technologies that are able to operate efficiently at extremely low temperatures. This work analyzes three appealing embedded memory technologies under cooling—from room temperature (300 K) down to cryogenic levels (77 K). As the temperature goes down to 77 K, six-transistor static random-access memory (6T-SRAM) presents slight improvements for static noise margin (SNM) during hold and read operations, while suffering from lower (−16%) write SNM. Gain-cell embedded DRAM (GC-eDRAM) shows significant benefits under these conditions, with read voltage margins and data retention time improved by about 2× and 900×, respectively. Non-volatile spin-transfer torque magnetic random access memory (STT-MRAM) based on single- or double-barrier magnetic tunnel junctions (MTJs) exhibit higher read voltage sensing margins (36% and 48%, respectively), at the cost of longer write access time (1.45× and 2.1×, respectively). The above characteristics make the considered memory technologies to be attractive candidates not only for high-performance computing, but also enable the possibility to bridge the gap from room-temperature to the realm of cryogenic applications that operate down to liquid helium temperatures and below.

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Zhang, Tiefei, Jixiang Zhu, Jun Fu, and Tianzhou Chen. "CWC: A Companion Write Cache for Energy-Aware Multi-Level Spin-Transfer Torque RAM Cache Design." Journal of Circuits, Systems and Computers 24, no. 06 (May 26, 2015): 1550079. http://dx.doi.org/10.1142/s0218126615500796.

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Due to its large leakage power and low density, the conventional SARM becomes less appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile memory technologies, such as phase change memory (PCM) and spin-transfer torque RAM (STT-RAM), have advantages of low leakage power and high density, which makes them good candidates for on-chip cache. In particular, STT-RAM has longer endurance and shorter access latency over PCM. There are two kinds of STT-RAM so far: single-level cell (SLC) STT-RAM and multi-level cell (MLC) STT-RAM. Compared to the SLC STT-RAM, the MLC STT-RAM has higher density and lower leakage power, which makes it a even more promising candidate for future on-chip cache. However, MLC STT-RAM improves density at the cost of almost doubled write latency and energy compared to the SLC STT-RAM. These drawbacks degrade the system performance and diminish the energy benefits. To alleviate these problems, we propose a novel cache organization, companion write cache (CWC), which is a small fully associative SRAM cache, working with the main MLC STT-RAM cache in a master-and-servant way. The key function of CWC is to absorb the energy-consuming write updates from the MLC STT-RAM cache. The experimental results are promising that CWC can greatly reduce the write energy and dynamic energy, improve the performance and endurance of MLC STT-RAM cache compared to a baseline.

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Pandu, Ratnakar. "CrFe 2O4 - BiFeO3 Perovskite Multiferroic Nanocomposites – A Review." Material Science Research India 11, no. 2 (December 24, 2014): 128–45. http://dx.doi.org/10.13005/msri/110206.

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Though semiconductor technology has advanced significantly in miniaturization and processor speed the “ideal” nonvolatile memory - memory that retains information even when the power goes is still elusive. There is a large demand for non-volatile memories with the popularity of portable electronic devices like cell phones and note books. Semiconductor memories like SRAMs and DRAMs are available but, such memories are volatile. After the advent of ferroelectricity many materials with crystal structures of Perovskite, pyrochlore and tungsten bronze have been derived and studied for the applications in memory devices. Ferroelectric Random Access Memories (FeRAM) are most promising. They are nonvolatile and have the greater radiation hardness and higher speed. These devices use the switchable spontaneous polarization arising suitable positional bi-stability of constituent ions and store the information in the form of charge. This paper is focused on the synthesis and characterizations of BiFeO3 and xCrFe2O4-(1-x) BiFeO3 nanoceramics which are most promising FeRAM materials. The effect of various-dopant-induced changes in structural, dielectric, ac impedance, ferroelectric hysteresis, mechanism of the dielectric peak broadening and frequency dispersion have been addressed. It also deals with low temperature processing technique of those nanoceramics which has high dielectric and ferroelectric properties. These studies can be further extended to reinforce BiFeO3 and CrFeO4 materials with carbon nanotubes to obtain conductive composites using appropriate techniques.

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"Low Power Non-Volatile 7T1M Subthreshold SRAM Cell." Indian Journal of Pure & Applied Physics, 2022. http://dx.doi.org/10.56042/ijpap.v60i12.67455.

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"Memristor based Non-Volatile Random Access Memory Cell by 45nm CMOS Techology." International Journal of Recent Technology and Engineering 9, no. 1 (May 30, 2020): 1432–35. http://dx.doi.org/10.35940/ijrte.f8714.059120.

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Rapid memories receives time to live attentive of substantial concluding mission available overstretched. Objectives of principle memory innovation is to create a excessive piece thickness part. Presents new problems in extremely large scale integrated (VLSI) circuit plan. Worldwide inconstancy to accomplish excessive return SRAM objects. Semiconductor reminiscence gadgets are commonly classified as risky or non-unpredictable arbitrary get right of entry to reminiscences. SRAM is delegated an unpredictable reminiscence because it is predicated on the usage of steady capability to hold up the placed away information. In the event that the pressure is interfered with, the reminiscence substance are decimated besides if a again-up battery stockpiling framework is saved up. In this mission a non-unpredictable SRAM cellular is planned utilising a blend of memristor and metal-oxide semiconductor devices. The records is placed away inside the reminiscence in any occasion, while the pressure is killed for an inconclusive time. The precept highlight of the proposed circuit element is its non-instability

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Raman, Siddhartha Raman Sundara, S. S. Nibhanupudi, and Jaydeep P. Kulkarni. "Enabling In-Memory Computations in Non-Volatile SRAM Designs." IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 2022, 1. http://dx.doi.org/10.1109/jetcas.2022.3174148.

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Bazzi, Hussein, Adnan Harb, Hassen Aziza, and Mathieu Moreau. "Non-volatile SRAM memory cells based on ReRAM technology." SN Applied Sciences 2, no. 9 (August 8, 2020). http://dx.doi.org/10.1007/s42452-020-03267-z.

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Badri, Satya Jaswanth, Mukesh Saini, and Neeraj Goel. "Mapi-Pro: An Energy Efficient Memory Mapping Technique for Intermittent Computing." ACM Transactions on Architecture and Code Optimization, October 20, 2023. http://dx.doi.org/10.1145/3629524.

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Battery-less technology evolved to replace battery usage in space, deep mines, and other environments to reduce cost and pollution. Non-volatile memory (NVM) based processors were explored for saving the system state during a power failure. Such devices have a small SRAM and large non-volatile memory. To make the system energy efficient, we need to use SRAM efficiently. So we must select some portions of the application and map them to either SRAM or FRAM. This paper proposes an ILP-based memory mapping technique for intermittently powered IoT devices. Our proposed technique gives an optimal mapping choice that reduces the system’s Energy-Delay Product (EDP). We validated our system using TI-based MSP430FR6989 and MSP430F5529 development boards. Our proposed memory configuration consumes 38.10% less EDP than the baseline configuration and 9.30% less EDP than the existing work under stable power. Our proposed configuration achieves 20.15% less EDP than the baseline configuration and 26.87% less EDP than the existing work under unstable power. This work supports intermittent computing and works efficiently during frequent power failures.

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Gupta, Pankaj, Kanchan Sharma, and Sneha Barnawal. "LOW POWER NON-VOLATILE 11T2R and 13T2R SRAM CELL USING MEMRISTOR." Telecommunications and Radio Engineering, 2021. http://dx.doi.org/10.1615/telecomradeng.2021038115.

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Kumar, C. S. Hemanth, and B. S. Kariyappa. "Node Voltage and KCL Model-Based Low Leakage Volatile and Non-Volatile 7T SRAM Cells." IETE Journal of Research, February 8, 2022, 1–17. http://dx.doi.org/10.1080/03772063.2022.2027279.

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Prinz, Erwin Josef. "Materials Challenges in Automotive Embedded Non-Volatile Memories." MRS Proceedings 997 (2007). http://dx.doi.org/10.1557/proc-0997-i02-01.

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AbstractSilicon-based nonvolatile memory modules are widely used in microcontrollers, where they are embedded into a monolithic system on a chip (SoC) which also includes high speed logic transistors, cache SRAM, and peripheral circuits for communicating with the external world. The physical principle most widely exploited for nonvolatile code and data storage is charge storage in floating gates. Recently, charge storage in nitride traps and nanocrystals also has been explored.The most demanding use profiles with respect to temperatures, data retention times, and low failure rates are encountered in automotive engine control applications, where junction temperatures up to 150°C are common, for 1000's of hours. Starting with the 130nm technology node, embedded Flash technology has been integrated with copper interconnects, and at the 90nm node, low dielectric constant interlevel dielectrics are also employed to increase circuit performance. To achieve automotive reliability, the materials surrounding the silicon floating gate, nanocrystal, or nitride charge storage area must be evaluated for parasitic charge storage, write/erase stress-induced leakage current, and other parameters important for reliability. Any movement of parasitic charge, potentially over a long period of time, can reduce the sensing window of the Flash EEPROM bitcell.

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Singh, Damyanti, Neeta Pandey, and Kirti Gupta. "Schmitt Trigger 12T1M Non-volatile SRAM Cell with Improved Process Variation Tolerance." AEU - International Journal of Electronics and Communications, February 2023, 154573. http://dx.doi.org/10.1016/j.aeue.2023.154573.

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Bazzi, Hussein, Adnan Harb, Hassen Aziza, Mathieu Moreau, and Abdallah Kassem. "RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications." Analog Integrated Circuits and Signal Processing, January 24, 2020. http://dx.doi.org/10.1007/s10470-020-01587-z.

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Sivakumar, S., John Jose, and Vijaykrishnan Narayanan. "Enhancing Lifetime and Performance of MLC NVM Caches using Embedded Trace buffers." ACM Transactions on Design Automation of Electronic Systems, April 16, 2024. http://dx.doi.org/10.1145/3659102.

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Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable properties. Compared to traditional memory technologies like SRAM and DRAM, they have minimal leakage current and high packing density. Non Volatile Memories (NVM), however, have a low write endurance, a high write latency, and high write energy. Non-volatile Single Level Cell (SLC) memories can store a single bit of data in each memory cell, whereas Multi Level Cells (MLC) can store two or more bits in each memory cell. Although MLC NVMs have substantially higher packing density than SLCs, their lifetime and access speed are key concerns. For a given cache size, MLC caches consume 1.84x less space and 2.62x less leakage power than SLC caches. We propose Trace buffer Assisted Non-volatile Memory Cache (TANC), an approach that increases the lifespan and performance of MLC-based last-level caches using the underutilised Embedded Trace Buffers (ETB). TANC improves the lifetime of MLC LLCs up to 4.36x, and decreases average memory access time by 4% compared to SLC NVM LLCs and by 6.41x and 11%, respectively, compared to baseline MLC LLCs.

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Wang, Jianjian, Jinshun Bi, Gang Liu, Hua Bai, Kai Xi, Bo Li, Sandip Majumdar, Lanlong Ji, Ming Liu, and Zhangang Zhang. "Simulations of single event effects on the ferroelectric capacitor-based non-volatile SRAM design." Science China Information Sciences 64, no. 4 (November 19, 2020). http://dx.doi.org/10.1007/s11432-019-2854-9.

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Zhao, Dongyan, Yubo Wang, Yanning Chen, Jin Shao, Zhen Fu, Guangyao Wang, Peng Zhang, Cheng Pan, and Biao Pan. "Radiation Hardening Design of Non-Volatile Hybrid Flip-Flop Based on Spin Orbit Torque MTJ and SRAM." SPIN, June 17, 2022. http://dx.doi.org/10.1142/s2010324722500163.

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Hyun, Gihwan, Batyrbek Alimkhanuly, Donguk Seo, Minwoo Lee, Junseong Bae, Seunghyun Lee, Shubham Patil, et al. "CMOS‐Integrated Ternary Content Addressable Memory using Nanocavity CBRAMs for High Sensing Margin." Small, April 12, 2024. http://dx.doi.org/10.1002/smll.202310943.

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AbstractThe development of data‐intensive computing methods imposes a significant load on the hardware, requiring progress toward a memory‐centric paradigm. Within this context, ternary content‐addressable memory (TCAM) can become an essential platform for high‐speed in‐memory matching applications of large data vectors. Compared to traditional static random‐access memory (SRAM) designs, TCAM technology using non‐volatile resistive memories (RRAMs) in two‐transistor‐two‐resistor (2T2R) configurations presents a cost‐efficient alternative. However, the limited sensing margin between the match and mismatch states in RRAM structures hinders the potential of using memory‐based TCAMs for large‐scale architectures. Therefore, this study proposes a practical device engineering method to improve the switching response of conductive‐bridge memories (CBRAMs) integrated with existing complementary metal‐oxide‐semiconductor (CMOS) transistor technology. Importantly, this work demonstrates a significant improvement in memory window reaching 1.87 × 107 by incorporating nanocavity arrays and modifying electrode geometry. Consequently, TCAM cells using nanocavity‐enhanced CBRAM devices can exhibit a considerable increase in resistance ratio up to 6.17 × 105, thereby closely approximating the sensing metrics observed in SRAM‐based TCAMs. The improved sensing capability facilitates the parallel querying of extensive data sets. TCAM array simulations using experimentally verified device models indicate a substantial sensing margin of 65× enabling a parallel search of 2048 bits.

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Journal articles on the topic 'Non-Volatile SRAM'

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