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Relevant bibliographies by topics / Non-Volatile SRAM

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Journal articles

Academic literature on the topic 'Non-Volatile SRAM'

Author: Grafiati

Published: 25 May 2024

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Journal articles on the topic "Non-Volatile SRAM"

1

Wang, Ming Qian, Jie Tao Diao, Nan Li, Xi Wang, and Kai Bu. "A Study on Reconfiguring On-Chip Cache with Non-Volatile Memory." Applied Mechanics and Materials 644-650 (September 2014): 3421–25. http://dx.doi.org/10.4028/www.scientific.net/amm.644-650.3421.

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NVM has become a promising technology to partly replace SRAM as on-chip cache and reduce the gap between the core and cache. To take all advantages of NVM and SRAM, we propose a Hybrid Cache, constructing on-chip cache hierarchies with different technologies. As shown in article, hybrid cache performance and power consumption of Hybrid Cache have a large advantage over caches base on single technologies. In addition, we have shown some other methods that can optimize the performance of hybrid cache.

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2

Mispan, Mohd Syafiq, Aiman Zakwan Jidin, Muhammad Raihaan Kamarudin, and Haslinah Mohd Nasir. "Lightweight hardware fingerprinting solution using inherent memory in off-the-shelf commodity devices." Indonesian Journal of Electrical Engineering and Computer Science 25, no. 1 (2022): 105. http://dx.doi.org/10.11591/ijeecs.v25.i1.pp105-112.

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An emerging technology known as Physical unclonable function (PUF) can provide a hardware root-of-trust in building the trusted computing system. PUF exploits the intrinsic process variations during the integrated circuit (IC) fabrication to generate a unique response. This unique response differs from one PUF to the other similar type of PUFs. Static random-access memory PUF (SRAM-PUF) is one of the memory-based PUFs in which the response is generated during the memory power-up process. Non-volatile memory (NVM) architecture like SRAM is available in off-the-shelf microcontroller devices. Exp

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3

Angizi, Shaahin, Navid Khoshavi, Andrew Marshall, Peter Dowben, and Deliang Fan. "MeF-RAM: A New Non-Volatile Cache Memory Based on Magneto-Electric FET." ACM Transactions on Design Automation of Electronic Systems 27, no. 2 (2022): 1–18. http://dx.doi.org/10.1145/3484222.

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Magneto-Electric FET ( MEFET ) is a recently developed post-CMOS FET, which offers intriguing characteristics for high-speed and low-power design in both logic and memory applications. In this article, we present MeF-RAM , a non-volatile cache memory design based on 2-Transistor-1-MEFET ( 2T1M ) memory bit-cell with separate read and write paths. We show that with proper co-design across MEFET device, memory cell circuit, and array architecture, MeF-RAM is a promising candidate for fast non-volatile memory ( NVM ). To evaluate its cache performance in the memory system, we, for the first time,

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4

Vijay, H. M., and V. N. Ramakrishnan. "Radiation effects on memristor-based non-volatile SRAM cells." Journal of Computational Electronics 17, no. 1 (2017): 279–87. http://dx.doi.org/10.1007/s10825-017-1080-x.

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5

Singh, Damyanti, Neeta Pandey, and Kirti Gupta. "Process invariant Schmitt Trigger non-volatile 13T1M SRAM cell." Microelectronics Journal 135 (May 2023): 105773. http://dx.doi.org/10.1016/j.mejo.2023.105773.

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6

Janniekode, Uma Maheshwar, Rajendra Prasad Somineni, Osamah Ibrahim Khalaf, Malakeh Muhyiddeen Itani, J. Chinna Babu, and Ghaida Muttashar Abdulsahib. "A Symmetric Novel 8T3R Non-Volatile SRAM Cell for Embedded Applications." Symmetry 14, no. 4 (2022): 768. http://dx.doi.org/10.3390/sym14040768.

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This paper proposes a symmetric eight transistor-three-memristor (8T3R) non-volatile static random-access memory (NVSRAM) cell. Non-volatile operation is achieved through the use of a memristor element, which stores data in the form of its resistive state and is referred to as RRAM. This cell is able to store the information after power-off mode and provides fast power-on/power-off speeds. The proposed symmetric 8T3R NVSRAM cell performs better instant-on operation compared to existing NVSRAMs at different technology nodes. The simulation results show that resistance of RAM-based 8T3R SRAM cel

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7

Priya, G. Lakshmi, Namita Rawat, Abhishek Sanagavarapu, M. Venkatesh, and A. Andrew Roobert. "Hybrid Silicon Substrate FinFET-Metal Insulator Metal (MIM) Memristor Based Sense Amplifier Design for the Non-Volatile SRAM Cell." Micromachines 14, no. 2 (2023): 232. http://dx.doi.org/10.3390/mi14020232.

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Maintaining power consumption has become a critical hurdle in the manufacturing process as CMOS technologies continue to be downscaled. The longevity of portable gadgets is reduced as power usage increases. As a result, less-cost, high-density, less-power, and better-performance memory devices are in great demand in the electronics industry for a wide range of applications, including Internet of Things (IoT) and electronic devices like laptops and smartphones. All of the specifications for designing a non-volatile memory will benefit from the use of memristors. In addition to being non-volatil

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8

Khan, Asif. "(Invited) Ferroelectric Field-Effect Transistors as High-Density, Ultra-fast, Embedded Non-Volatile Memories." ECS Meeting Abstracts MA2022-02, no. 15 (2022): 805. http://dx.doi.org/10.1149/ma2022-0215805mtgabs.

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Ferroelectric field-effect transistors (FEFETs) are receiving significant attention from the microelectronics community for next-generation memory technologies, especially as embedded non-volatile elements for data-centric applications. The main attractive features of FEFETs are that write energy and speed of FEFETs are within an order of magnitude of respective metrics for SRAMs (FEFET ~1 fJ and 1-10 ns vs. SRAM: <1 fJ and <1 ns), all the while requiring a significantly smaller cell size (FEFET 50-60F2 vs. SRAM 120-150F2) and close-to-zero standby leakage power – provided that FEFETs ar

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9

Pan, James N. "Atomic Force High Frequency Phonons Non-volatile Dynamic Random-Access Memory Compatible with Sub-7nm ULSI CMOS Technology." MRS Advances 4, no. 48 (2019): 2577–84. http://dx.doi.org/10.1557/adv.2019.212.

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ABSTRACTThis paper reports a novel low power, fast nonvolatile memory utilizing high frequency phonons, atomic force dual quantum wells, ferromagnetism, coupled magnetic dipoles and random accessed magnetic devices. Very high-speed memories, such as SRAM and DRAM, are mostly volatile (data are lost when power is off). Nonvolatile memories, including FLASH and MRAM, are typically not as fast has DRAM or SRAM, and the voltages for WRITE/ERASE operations are relatively high. This paper describes a silicon nonvolatile memory that is compatible with advanced sub-7nm CMOS process. It consists of onl

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10

P, Saleem Akram. "Non-Volatile 7T1R SRAM cell design for low voltage applications." International Journal of Emerging Trends in Engineering Research 7, no. 11 (2019): 704–7. http://dx.doi.org/10.30534/ijeter/2019/487112019.

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