Dissertations / Theses on the topic 'Non-binary codes'
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Gilra, Deepak. "A class of non-binary LDPC codes." Texas A&M University, 2003. http://hdl.handle.net/1969/67.
Full textChilumuru, Suma Namuduri Kameswara. "Distributed video coding using non-binary LDPC codes." Diss., A link to full text of this thesis in SOAR, 2006. http://soar.wichita.edu/dspace/handle/10057/619.
Full text"December 2006." Title from PDF title page (viewed on Oct. 29, 2007). Thesis adviser: Kamesh Namuduri. Includes bibliographic references (leaves 47-50).
Reid, Andrew Carey. "Turbo codes: convergence phenomena & non-binary constructions." Thesis, University of Canterbury. Electrical and Electronic Engineering, 2002. http://hdl.handle.net/10092/5462.
Full textCiobanu, Alexandru. "Adaptive multiset stochastic decoding of non-binary LDPC codes." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106390.
Full textDans cette thèse, nous proposons un nouvel algorithme de décodage stochastique pour des codes LDPC non-binaires avec d_v = 2, qui est basé sur le concept de multiensemble, une généralisation de l'ensemble où un élément peut apparaître plusieurs fois. L'algorithme est appelé Algorithme Stochastique à Multiensembles Adaptifs (ASMA) et représente des fonctions de masse comme multiensembles, ce qui simplifie la structure du nœud de variable. ASMA réduit la complexité d'exécution d'une itération de décodage à O(q) pour les architectures de mémoire ordinaire, et O(1) si une architecture SRAM personnalisée est utilisée. Deux décodeurs ASMA tout-parallèles sont mis en œuvre sur FPGA pour deux versions d'un code (192,96) (2,4)-réguliers, l'un sur GF(64) et le l'autre sur GF(256), et tous les deux atteignent une fréquence d'horloge maximale de 108 MHz et un débit de 65 Mbit/s à E_b/N_0 = 2.4 dB. Nous proposons aussi une architecture SRAM pour les implémentations ASIC qui réduit la complexité d'exécution d'un cycle de décodage à O(1) et atteint 698 Mbit/s au même niveau de bruit. L'algorithme a un taux d'erreur de trame de 3.5 x 10^-7 à E_b/N_0 = 2.4 dB pour la version GF(256) du code. Au meilleur de notre connaissance, les décodeurs présentés ici sont les premiers décodeurs LDPC non-binaires opérant sur GF(64) et GF(256) et tout-parallèles rapportés dans la littérature.
García, Herrero Francisco Miguel. "Architectures for soft-decision decoding of non-binary codes." Doctoral thesis, Universitat Politècnica de València, 2013. http://hdl.handle.net/10251/33753.
Full textGarcía Herrero, FM. (2013). Architectures for soft-decision decoding of non-binary codes [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/33753
TESIS
Premiado
Zhou, Biyun. "Non-binary cyclic codes and its applications in decoding of high dimensional trellis-coded modulation." Ohio : Ohio University, 2000. http://www.ohiolink.edu/etd/view.cgi?ohiou1173380815.
Full textShams, Bilal. "Codes LDPC non-binaire de nouvelle generation." Phd thesis, Université de Cergy Pontoise, 2010. http://tel.archives-ouvertes.fr/tel-00766409.
Full textCai, Fang. "Low-complexity Decoding Algorithms and Architectures for Non-binary LDPC Codes." Case Western Reserve University School of Graduate Studies / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=case1372338108.
Full textGarrammone, Giuliano [Verfasser]. "Non-Binary Codes with Applications to Satellite and Space Communications / Giuliano Garrammone." München : Verlag Dr. Hut, 2015. http://d-nb.info/1074063392/34.
Full textBhutto, Tarique Inayat. "Root LDPC Codes for Non Ergodic Transmission Channels." Thesis, Blekinge Tekniska Högskola, Sektionen för ingenjörsvetenskap, 2011. http://urn.kb.se/resolve?urn=urn:nbn:se:bth-5938.
Full textpostal address: Björnkullaringen 26, LGH 1029 14151 Huddinge Stockholm Sweden. Mobile: +46-720 490 967
Uzunoglu, Cihan. "Performance Comparison Of Message Passing Decoding Algorithms For Binary And Non-binary Low Density Parity Check (ldpc) Codes." Master's thesis, METU, 2007. http://etd.lib.metu.edu.tr/upload/2/12609072/index.pdf.
Full textKlaimi, Rami. "Etude de turbocodes non binaires pour les futurs systèmes de communication et de diffusion." Thesis, Ecole nationale supérieure Mines-Télécom Atlantique Bretagne Pays de la Loire, 2019. http://www.theses.fr/2019IMTA0141.
Full textNowadays communication standards have adopted different binary forward error correction codes. Turbo codes were adopted for the long term evolution standard, while binary LDPC codes were standardized for the fifth generation of mobile communication (5G) along side with the polar codes. Meanwhile, the focus of the communication community is shifted towards the requirement of beyond 5G standards. Networks for the year 2030 and beyond are expected to support novel forward-looking scenarios, such as holographic communications, autonomous vehicles, massive machine-type communications, tactile Internet… To respond to the expected requirements of new communication systems, non-binary LDPC codes were defined, and they are shown to achieve better error correcting performance than the binary LDPC codes. This performance gain was followed by a high decoding complexity, depending on the field order.Similar studies emerged in the context of turbo codes, where the non-binary turbo codes were defined, and have shown promising error correcting performance, while imposing high complexity. The aim of this thesis is to propose a new low-complex structure of non-binary turbocodes. The constituent blocks of this structure were optimized in this work, and a new low complexity decoding algorithm was proposed targeting a future hardware implementation. The obtained results are promising, where the proposed codes are shown to outperform existing binary and non-binary codes from the literature
Gorgolione, Matteo. "Analyse et construction de codes LDPC non-binaires pour des canaux à évanouissement." Phd thesis, Université de Cergy Pontoise, 2012. http://tel.archives-ouvertes.fr/tel-00819415.
Full textShams, Bilal. "Les Codes LDPC non-binaires de nouvelle génération." Thesis, Cergy-Pontoise, 2010. http://www.theses.fr/2010CERG0525/document.
Full textIn this thesis we present our work in the domain of non-binary decoding algorithm for general classes of non-binary LDPC codes. Low-Density Parity-Check (LDPC) codes were originally presented by Gallager in 1963, and after some fundamental theoretical advancements, they were considered in standards like DVB-S2, WI-MAX, DSL, W-LAN etc. Later on, non-binary LDPC (NB-LDPC)codes were proposed in the litterature, and showed better performance for small lengths or when used on non-binary channels. However, the advantages of using NB-LDPC codes comes with the consequence of an heavily increased decoding complexity. For a code defined in GF(q), the complexity is of the order O(q^2). Similarly, the memory required for storing messages is of order O(q). Consequently, the implementation of an LDPC-decoder defined over a field order q > 64 becomes practically impossible.The main objective of the thesis is to develop reduced complexity algorithms for non-binary LDPC codes that exhibit excellent performance and is practically im-plementable. For better decoding performance, not only the decoding algorithm is important, but also the structure of the code plays an important role. With this goal in mind, a new family of codes called cluster-NB-LDPC codes was developped and specific improvements of the NB decoder for cluster-NB-LDPC codes were proposed. Our principal result is that we were able to propose decoders for cluster-NB-LDPC codes with reduced complexity compared to usual decoders for NB-LDPC codes on fields, without any performance loss in error correction capability
Klinc, Demijan. "On applications of puncturing in error-correction coding." Diss., Georgia Institute of Technology, 2011. http://hdl.handle.net/1853/39610.
Full textGriffiths, Wayne Bradley. "On a posteriori probability decoding of linear block codes over discrete channels." University of Western Australia. School of Electrical, Electronic and Computer Engineering, 2008. http://theses.library.uwa.edu.au/adt-WU2008.0156.
Full textDudal, Clément. "Forme d'onde multiporteuse pour de la diffusion par satellite haute capacité." Phd thesis, Toulouse, INPT, 2012. http://oatao.univ-toulouse.fr/8342/1/dudal.pdf.
Full textHarb, Hassan. "Conception du décodeur NB-LDPC à débit ultra-élevé." Thesis, Lorient, 2018. http://www.theses.fr/2018LORIS504/document.
Full textThe Non-Binary Low Density Parity Check (NB-LDPC) codes constitutes an interesting category of error correction codes, and are well known to outperform their binary counterparts. However, their non-binary nature makes their decoding process of higher complexity. This PhD thesis aims at proposing new decoding algorithms for NB-LDPC codes that will be shaping the resultant hardware architectures expected to be of low complexity and high throughput rate. The first contribution of this thesis is to reduce the complexity of the Check Node (CN) by minimizing the number of messages being processed. This is done thanks to a pre-sorting process that sorts the messages intending to enter the CN based on their reliability values, where the less likely messages will be omitted and consequently their dedicated hardware part will be simply removed. This reliability-based sorting enabling the processing of only the highly reliable messages induces a high reduction of the hardware complexity of the NB-LDPC decoder. Clearly, this hardware reduction must come at no significant performance degradation. A new Hybrid architectural CN model (H-CN) combining two state-of-the-art algorithms - Forward-Backward CN (FB-CN) and Syndrome Based CN (SB-CN) - has been proposed. This hybrid model permits to effectively exploit the advantages of pre-sorting. This thesis proposes also new methods to perform the Variable Node (VN) processing in the context of pre-sorting-based architecture. Different examples of implementation of NB-LDPC codes defined over GF(64) and GF(256) are presented. For decoder to run faster, it must become parallel. From this perspective, we have proposed a new efficient parallel decoder architecture for a 5/6 rate NB-LDPC code defined over GF(64). This architecture is characterized by its fully parallel CN architecture receiving all the input messages in only one clock cycle. The proposed new methodology of parallel implementation of NB-LDPC decoders constitutes a new vein in the hardware conception of ultra-high throughput rate decoders. Finally, since the NB-LDPC decoders requires the implementation of a sorting function to extract P minimum values among a list of size Ns, a chapter is dedicated to this problematic where an original architecture called First-Then-Second-Extrema-Selection (FTSES) has been proposed
Lin, Changyu. "Non-Binary Coded Modulation for FMF-Based Coherent Optical Transport Networks." Diss., The University of Arizona, 2016. http://hdl.handle.net/10150/613281.
Full textChang, Yung-Hsiang, and 張詠翔. "Turbo Codes and Trellis Coded Modulation Using Non-Binary Convolutional Codes." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/33271629933732544954.
Full text國立臺灣科技大學
電子工程系
96
Because of the rapid and widespread development of communication techniques, transmission style has developed from wire communication into wireless communication. It is necessary that we apply channel coding techniques in data transmission when we transmit data in wireless enviroment, which typically suffers from serious signal fading and degradation. Turbo codes are very powerful error correcting for added white Gaussian noise (AWGN) channel. In this thesis, we consider a non-binary turbo codes system, including non-binary systematic (NBS) turbo code and non-binary non-systematic (NBNS) turbo code. The performances of those techniques mentioned above are evaluated by computer simulation in added white Gaussian noise (AWGN) channels. Then, we compare those two techniques. Besides, this thesis also combines non-binary systematic convolutional code and turbo trellis-coded modulation. Encoded signals are transmitted in AWGN channel. We employ turbo trellis-coded modulation decoder and non-binary systematic convolutional code decoder in the receiver. Finally, this thesis also uses extrinsic information transfer chart (EXIT chart) to describe the mutual information transfer characteristics of the decoders in the receiver. And then we analyze the convergence behavior of the turbo system. The exchange of extrinsic information is visualized as a decoding trajectory in the extrinsic information transfer chart. This allows the prediction of turbo cliff position and bit error rate after an arbitrary number of iterations.
Ghayoor, Farzad. "Non-binary compound codes based on single parity-check codes." Thesis, 2013. http://hdl.handle.net/10413/10422.
Full textThesis (Ph.D.)-University of KwaZulu-Natal, Durban, 2013.
Ghiya, Ankit. "Nested low-density lattice codes based on non-binary LDPC codes." Thesis, 2010. http://hdl.handle.net/2152/ETD-UT-2010-08-1589.
Full texttext
Chilumuru, Suma. "Distributed video coding using non-binary LDPC codes." Thesis, 2006. http://hdl.handle.net/10057/619.
Full text"December 2006."
Thesis (M.S.)--Wichita State University, College of Engineering, Dept. of Electrical and Computer Engineering.
Gao, Yingzi. "Design and implementation of non-binary convolutional turbo codes." Thesis, 2001. http://spectrum.library.concordia.ca/2435/1/MQ68439.pdf.
Full textLiao, JingMin, and 廖經旻. "Design of Non-Binary LDPC Codes for Gaussian BroadcastChannels." Thesis, 2010. http://ndltd.ncl.edu.tw/handle/02830356402617024418.
Full text國立中正大學
通訊工程學系
98
The achievable rate regions for Gaussian broadcast channels were established by Cover. Since then, how to attain the achievable rate regions becomes an open problem. In this thesis, we attempt to design non-binary low-density parity-check codes (LDPC) to approach the achievable rate regions for Gaussian broadcast channels. In order to analysis the code, we generalize several properties of non-binary LDPC codes. The permutation-invariance and symmetry properties of the proposed codes enable the approximation of the LLR vector as the Gaussian random vector which can be described by a single parameter. By this characteristic, we apply extrinsic information transfer (EXIT) charts to design non-binary LDPC codes for Gaussian broadcast channels. In addition, we adopt non-uniform signal constellations modulation to further obtain shaping gain. Simulation results show that the proposed codes approach achievable rate regions for Gaussian broadcast channels.
Yang, Chih-Wen, and 楊志文. "Area-efficient Stochastic Decoder Architectures for Non-binary LDPC Codes." Thesis, 2014. http://ndltd.ncl.edu.tw/handle/869s25.
Full text國立交通大學
電子工程學系 電子研究所
103
Non-binary LDPC codes extended from binary LDPC codes have outstanding decoding performance and combat burst error. Recently, stochastic computation is a promising decoding method for non-binary LDPC codes. Although the previous stochastic works reduce the complexity by using symbol-serial representation of probability, the stochastic decoder for non-binary LDPC codes still has bottlenecks for VLSI implementation due to high computational complexity and huge storage requirements. In this thesis, three novel stochastic decoders: TFM-based, probability-RHS-based, and log-RHS-based are proposed. All of proposed decoders are synthesized in UMC 90-nm process with high area efficiency due to our improved architectures which have low computational complexity and less storage requirements. Finally, the log-RHS-based stochastic decoder for a (168, 84) regular-(2, 4) code over GF(16) is fabricated in chip with 3.75 mm2 core area including testing consideration and 96.6% chip density. According to the measurement results, this decoder can support a throughput of 1.32 Gb/s under 368 MHz clock frequency with 1014 k gate counts and its power consumption is 588 mW. Compared with the related state-of-the-art designs, this work has not only 2 times improvement in hardware efficiency but also 7 times improvement in energy efficiency. Moreover, to the best of our knowledge, this is the first chip of stochastic decoder for non-binary LDPC codes.
陳書偉. "An Error-Floor Lowering technique for Non-binary QC-LDPC Codes." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/21042264194582108114.
Full textLI, WEN-SHI, and 李汶羲. "Investigation and implementation of counting cycle over non-binary LDPC codes." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/ucqb6b.
Full text國立中正大學
通訊工程研究所
106
The low density parity check (LDPC) codes is a kind of error correction codes. The error correction performance of LDPC codes is close to Shannon limit. Thus, LDPC codes are widely applied to various communication systems. In general, these codes can be described by Tanner graph. Finding and removing cycles are essential, because the cycles are generally considered to affect the performance of LDPC codes in Tanner graph. To extend this study with Galois field, non-binary LDPC codes have better capability of error correction to against noise, especially for short code length. However, the computational complexity and memory requirement are relatively high in the decoding process and code construction. In this paper, we propose a cycle counting algorithm based on cycle check table with less complexity. Basically, the cycle check table records the connection of nodes in Tanner Graph. Each layer in the table contains three rows. The first row has the record of target node. The second row denotes the previous node of the node in the first row, and the third row has the indices of the position of the node in previous row. In cycle searching, there are two conditions needed to be satisfied within cycle check table. The fist condition is that there are two same nodes in the first row of Nth layer. The second condition is that the nodes in previous path of two nodes which satisfy the first condition are different. To evaluate the proposed scheme, the computational complexity of proposed algorithm is , and the memory requirement is , where m is the number of parity check equations, n is the code block length, wr and wc are the row weight and column weight, respectively, wmax is the maximum of wr and wc, and N is the half length of cycles. The proposed algorithm can perform 9.44 times faster than the conventional method while considering the LDPC codes with code length 3000 and girth (g) 6. Besides, we can find the length longer than 2g-2 which is the upper bound of some existing methods. Eventually, the proposed algorithm is applied to the construction of parallelized-decoding LDPC codes over Galois field to improve the capability of LDPC codes.
Huang, Chao-Cheng, and 黃朝政. "Parallel Symbol-Flipping Decoding for Non-Binary Low-Density Parity-Check Codes." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/14836540276040036910.
Full text國立清華大學
通訊工程研究所
100
Two versions of a new parallel symbol-flipping decoding algorithm for non-binary low-density parity-check (NB-LDPC) codes are proposed. Simulation results show that the soft-decision parallel symbol-flipping decoding outperforms quite a number of existing reliability-based message-passing algorithms. It provides an effective trade-off between error performance anddecoding complexity compared with the q-ary sum-product algorithm. The algorithm can be simplified to hard-decision parallel symbol-flipping decoding for applications in communication or storage systems where either soft information is not available or a simple decoder is needed. They are particularly effective for decoding NB-LDPC codes whose parity-check matrices have large row/column weights.
Tu, Shu-Wen, and 凃淑文. "Design and Implementation for Non-binary Low-density Parity-check Codes (NB-LDPC) Decoders." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/39120352634119597898.
Full text國立交通大學
電子研究所
101
Non-binary LDPC codes which extended from binary LDPC codes have ex- cellent decoding performance, and it is robust to various channel impairments. With the remarkable decoding ability, the high computational complexity and huge memory usage are the main challenges for non-binary LDPC codes to be imple- mented in practical. This thesis presents a high hardware efficient architecture for implementing non-binary LDPC decoder using improved Extended Min-Sum de- coding algorithm with layered scheduling. Based on the enhancement in the check node processing and efficient memory storing, the proposed decoder can double the throughput and have half reduction in storing the edge messages. Using 90- nm CMOS process technology, a (2,4)-regular non-binary QC-LDPC decoder over GF(26) is implemented. In the post-layout simulation results, the decoder through- put can reach over 100 Mbps at 10 iterations. Compared with state-of-the-art de- signs, this implementation has at least 4.3 times improvement in hardware effi- ciency (throughput-to-gate-count-ratio), and the decoding performance still keep competitive.
Louw, Daniel Johannes. "Non-binary LDPC coded STF-MIMO-OFDM with an iterative joint receiver structure." Diss., 2010. http://hdl.handle.net/2263/28061.
Full textDissertation (MEng)--University of Pretoria, 2010.
Electrical, Electronic and Computer Engineering
unrestricted
Bruwer, Christian S. "Correlation attacks on stream ciphers using convolutional codes." Diss., 2005. http://hdl.handle.net/2263/24740.
Full textDissertation (MEng (Electronic Engineering))--University of Pretoria, 2007.
Electrical, Electronic and Computer Engineering
unrestricted
Sarma, Anurupa. "Quantum codes over Finite Frobenius Rings." Thesis, 2012. http://hdl.handle.net/1969.1/ETD-TAMU-2012-08-11529.
Full textLiao, Kuo-Hsuan, and 廖國軒. "A High-Throughput Trellis-Based Layered Decoding Architecture for Non-binary LDPC Codes Using Max-Log-QSPA." Thesis, 2012. http://ndltd.ncl.edu.tw/handle/34961381892802366278.
Full textLee, Wei-hsin, and 李威信. "Power allocation for non-binary LDPC coded STBC-OFDM systems." Thesis, 2008. http://ndltd.ncl.edu.tw/handle/92228513651509429532.
Full text國立臺灣科技大學
電子工程系
96
Channel coding is one of the most popular topics of today’s wireless communications. It is an essential technique when the channel is noisy and fading. There are many kinds of channel coding, such as turbo code, convolutional code, Hamming code and LDPC code. LDPC (low-density parity-check) code has been shown to have excellent performance. It is the channel coding technique that we adopt in this thesis. In our research, we find that the performance of non-binary LDPC over GF(q) outperforms that of binary LDPC. However, non-binary LDPC has higher computation complexity. To solve this problem, we use FFT transform to reduce the complexity. It is pointed out that use of multiple antenna raises performance and gain for transmitting and receiving in wireless transmission. Therefore, we use space-time block code to provide diversity and capacity in this thesis. We also use OFDM to eliminate ISI. In combining OFDM and LDPC codes, power allocation to make each subcarriers have the same SNR(signal-to-noise ratio) is necessary and is the main topic of this thesis. Sub-carrier selection helps us to strike a balance between data transmission rate and BER(bit error rate) performance. In addition, we derive a scheme to determine the number of subcarriers to be retained when the acceptable BER is specified.
Rogers, D. P. "Non-binary spread-spectrum multiple-access communications / Derek Paul Rogers." 1995. http://hdl.handle.net/2440/18541.
Full textix, 201 leaves : ill. ; 30 cm.
Title page, contents and abstract only. The complete thesis in print form is available from the University Library.
This thesis investigates non-binary spread-spectrum multiple-access communications. The research considers wide generation techniques, system performance, how performance is influenced by the different properties of the codes, and how those properties relate to the code generation technqiue. The research refines the code design philosophy and investigates this by developing a novel code generation technique.
Thesis (Ph.D.)--University of Adelaide, Dept. of Electrical and Electronic Engineering, 1995?
Du, Yimin. "Hardware implementation of non-binary turbo code for DVB/RCS." Thesis, 2003. http://spectrum.library.concordia.ca/1919/1/MQ77967.pdf.
Full textFaraji-Dana, Zahra. "On Non-Binary Constellations for Channel Encoded Physical Layer Network Coding." Thesis, 2012. http://hdl.handle.net/10012/6624.
Full textHsu, Chih-Hung, and 許志弘. "Performance Analysis of A Non-binary LDPC Coded FH System Using Linear Diversity Combining Detection under Multi-tone Follower Jamming." Thesis, 2011. http://ndltd.ncl.edu.tw/handle/04571201987354130860.
Full text元智大學
通訊工程學系
99
This thesis discusses about using non-binary LDPC codes to resist the intentional multi-tone follower jamming for frequency hopping systems. We calculate the capacities for several jamming channels so that we can evaluate the influences to communication quality. When the channels are also Rayleigh faded or with AWGN, soft decoding is applied to the decoder and the probabilities of channel values for decoding are theoretically formulated. We especially focus on resisting two tone follower jamming by using different code rates of non-binary regular LDPC codes. By using the technique of ratio threshold test (RTT), the calculation of the probabilities of channel values can be simplified. Based on RTT, we propose a linear diversity combing detector to combat multi-tone follower jamming. Simulation results show that the code rates of non-binary LDPC codes can be increased when using these techniques and the system can achieve the purpose on resisting the multi-tone follower jamming.