Dissertations / Theses on the topic 'NOCs'
To see the other types of publications on this topic, follow the link: NOCs.
Create a spot-on reference in APA, MLA, Chicago, Harvard, and other styles
Consult the top 50 dissertations / theses for your research on the topic 'NOCs.'
Next to every source in the list of references, there is an 'Add to bibliography' button. Press on it, and we will generate automatically the bibliographic reference to the chosen work in the citation style you need: APA, MLA, Harvard, Chicago, Vancouver, etc.
You can also download the full text of the academic publication as pdf and read online its abstract whenever available in the metadata.
Browse dissertations / theses on a wide variety of disciplines and organise your bibliography correctly.
1
Vivoda, Vlado, and vlado vivoda@flinders edu au. "THE RETURN OF THE OBSOLESCING BARGAIN AND THE DECLINE OF BIG OIL: A STUDY OF BARGAINING IN THE CONTEMPORARY OIL INDUSTRY." Flinders University. School of Politics and International Studies, 2008. http://catalogue.flinders.edu.au./local/adt/public/adt-SFU20080305.150535.
Full textAbstract:
This thesis centres on studying intricate bargaining relationships between the major actors
in the highly politicised oil industry. By covering the period between 1998 and early 2007,
this study focuses exclusively on contemporary bargaining in the oil industry, as it is
unfeasible to cover a longer time-span. In the current decade, which unlike previous two
cooperative decades, can be characterised as conflictual, and thus politicised, the structure
of the oil industry can best be understood by studying bargaining between numerous
actors, the main of which are the international oil companies (IOCs), oil-exporting states,
oil-importing states, and the national oil companies (NOCs). The central argument is that due to their weak relative bargaining power, the IOCs have been on the losing side in their bargaining with oil exporting countries and/or their NOCs in the current decade when compared to the late 1990s, and thus, we are witnessing the
return of the obsolescing bargain.
2
Hervé, Marcos Barcellos. "Métodos de teste de redes-em-chip (NoCs)." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/25498.
Full textAbstract:
Este trabalho tem como objetivo estudar e propor métodos de teste funcional visando a detecção e localização de falhas na infra-estrutura das redes-em-chip. Para isso, o trabalho apresenta, inicialmente, uma descrição das principais características das redes-em-chip, explicando o que elas são e para que elas servem. Em seguida são apresentados conceitos de teste de circuitos integrados, bem como trabalhos relacionados ao teste das redes-em-chip. Um método de teste visando a detecção de falhas nas interconexões de dados de uma NoC é apresentado no trabalho, sendo este método posteriormente estendido para incluir as interconexões de controle. Os circuitos de teste necessários para implementar a estratégia de teste proposta também são descritos. A partir do método de teste apresentado, é feito um estudo sobre sua capacidade de localização de falhas, onde alterações visando o aumento dessa capacidade de localização de falhas são propostas. Por fim o método de teste é estendido para detecção de falhas nos roteadores da rede.The purpose of this work is to study and propose functional test methods that aim the detection and location of faults in the NoC’s infrastructure. In order to do so, this work presents, initially, a description of the main characteristics of networks-on-chip, explaining what are NoCs and what is their purpose. Fallowing this description, some concepts related to the test of integrated circuits are presented as well as related works on NoC testing. A method aiming the detection of data interconnect faults in a NoC is presented in this work. This method is later extended to include faults in the control interconnections as well. The circuits used to implement the proposed strategy are also described here. Based on the proposed test strategy, the method’s capability to locate faults is studied. Changes are proposed to the test method in order to increase this fault location capability. Finally, the test method is extended to include faults inside the router’s logic.
3
Alshraiedeh, Juman. "Wear-out Leveling in Network on Chips (NoCs)." Ohio University / OhioLINK, 2017. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1492677926079357.
Full text
4
Helmy, Amr. "Mise en œuvre de techniques de démonstration automatique pour la vérification formelle des NoCs." Grenoble INPG, 2010. http://www.theses.fr/2010INPG0035.
Full textAbstract:
Les technologies actuelles permettent l'intégration sur une même puce de systèmes complexes (SoCs) qui sont composés de blocs préconçus (IPs) pouvant être interconnectés grâce à un réseau sur la puce (NoCs). De manière générale, les IPs sont validés par diverses techniques (simulation, test, vérification formelle) et le problème majeur reste la validation des infrastructures des communications. Cette thèse se concentre sur la vérification formelle des réseaux sur puce à l'aide d'un outil de preuve automatique, le démonstrateur de théorèmes ACL2. Un méta-modèle pour les réseaux sur puce a été développé et implémenté dans ACL2. Il satisfait des propriétés de correction générique, conséquences logiques d'un ensemble d'obligations de preuve sur les constituants principaux du réseau (topologie, routage, technique de commutation,. . . ). La preuve de correction pour une instance spécifique de réseau sur puce est alors réduite à la vérification de ces obligations de preuve. Cette thèse poursuit les travaux entrepris dans ce domaine en étendant ce méta-modèle dans plusieurs directions : prise en compte plus fine de la modélisation temporelle, du contrôle de flux, des mécanismes de priorités,. . . Les résultats sont démontrés sur plusieurs réseaux actuels : Hermes (Université fédérale du Rio Grande do Sul, Brésil et LIRMM) et Nostrum (Royal Institute Of Technology, Suéde)The current technology allows the integration on a single die of complex systems-on-chip (SoC's) composed of manufactured blocks (IP's) that can be interconnected through specialized networks-on-chip (NoCs). IP's have usually been validated by diverse techniques (simulation, test, formal verification) and the key problem remains the validation of the communication infrastructure. This thesis addresses the formal verification of NoCs by means of a mechanized proof tool, the ACL2 theorem prover. A meta-model for NoCs has been developed and implemented in ACL2. It satisfies generic correctness statements, which are logical consequences of a set of proof obligations for each one of the NoC constituents (topology, routing, switching technique,. . . ). Thus the verification of a particular NoC instance is reduced to discharging this set of proof obligations. The purpose of this thesis is to extend this meta-model in several directions: more accurate timing modeling, flow control, priority mechanisms,. . . The methodology is demonstrated on realistic and state-of-the-art NoC designs: Spidergon (STMicroelectronics), Hermes (The Federal University of Rio Grande do Sul, Brazil, and LIRMM) , and Nostrum (Royal Institute Of Technology, Sweden)
5
Santos, Flávia de Oliveira 1986. "MediaBox : uma plataforma baseada em NoCs para aplicações multimídia." [s.n.], 2013. http://repositorio.unicamp.br/jspui/handle/REPOSIP/275649.
Full textAbstract:
Orientadores: Guido Costa Souza de Araújo, Sandro RigoDissertação (mestrado) - Universidade Estadual de Campinas, Instituto de Computação
Made available in DSpace on 2018-08-22T12:10:10Z (GMT). No. of bitstreams: 1 Santos_FlaviadeOliveira_M.pdf: 1899166 bytes, checksum: 5f1ea70dfec475a34e56a6f493eda1aa (MD5) Previous issue date: 2013
Resumo: Arquiteturas tradicionais para sistemas modernos consistem em SoCs com múltiplos processadores integrados em um único chip conhecidos como MPSoCs. A maioria dos IPs de um MPSoC são altamente configuráveis, cada um com uma complicada relação custo-benefício entre métricas como desempenho, área e consumo de energia, tornando o espaço de projeto de um MPSoC bastante amplo. Aliado a essa complexidade de projeto está o fato de que não é possível realizar a verificação de um MPSoC sem a aplicação em software e muito menos desenvolver o software sem modelos de hardware. Por isso é importante que os projetistas possam começar com modelos do sistema completo nos quais subsistemas possam ser independentemente substituídos por modelos refinados, de forma a haver uma validação contínua do sistema. Neste contexto, o conceito de plataforma virtual tem sido utilizado para desenvolvimento paralelo de hardware e software. Através de plataformas virtuais, projetistas podem analisar antecipadamente muitos problemas de projeto em um MPSoC, obtendo assim estimativas para consumo de energia, tráfego de barramento, uso de memória, eficiência dos periféricos e, principalmente, desempenho do sistema como um todo. Este projeto visa prover uma plataforma virtual em nível ESL chamada MediaBox. A MediaBox tem como mecanismo de interconexão uma NoC (Network-on-Chip) que introduz o conceito de rede na plataforma e possibilita a comunicação simultânea entre seus IPs. A plataforma desenvolvida possibilita a avaliação de desempenho de sistemas multimídia e sua execução facilita a produção de grandes quantidades de informação poupando tempo e esforço ao desenvolvedor. O estudo de caso realizado demonstra que a MediaBox é uma boa solução para simular aplicações multimídia e para análise de desempenho. Devido ao grande tráfego existente entre os IPs, o uso de uma NoC como meio de interconexão mostrou-se eficaz. A MediaBox possibilita o uso de diferentes configurações através de um arquivo de configuração e de um mapa de endereçamento que permitem explorar essas opções. Essa flexibilidade permite aos usuários conceber e testar diferentes arquiteturas através das quais pode ser estudado o comportamento e o desempenho de sistemas multiprocessados em um chip
Abstract: Traditional architectures for modern systems consist on SoCs with multiple processors integrated in a single chip known as MPSoCs. Most of the IPs in a MPSoC are highly configurable, each with a complicated trade-o_ between metrics such as performance, area and energy consumption making the design space of a MPSoC incredibly wide. Allied to this project complexity is the fact that it is not possible to perform verification of a MPSoC without the application in software and much less develop the software without hardware models. For this reason, it is important that designers start with complete system models in which subsystems may be independently replaced by refined models, so that there is a continuous system validation. In this context, the concept of a virtual platform has been used for parallel development of hardware and software. Through virtual platforms, designers are able to analyze in advance many design problems in a MPSoC, thus obtaining estimates for energy consumption, bus trafic, memory usage, peripherals efficiency and mainly performance of the system as a whole. This project aims to provide a virtual platform in ESL called MediaBox. The Media- Box interconnection mechanism is a NoC (Network-on-chip) that introduces the concept of a network inside a platform and enables simultaneous communication between its IPs. The developed platform enables multimedia systems performance evaluation and its execution facilitates the production of a large amount of information saving the developer's time and effort. The case study developed demonstrates that MediaBox is a good solution for simulating multimedia applications and for performance analysis. Due to the amount of traffic between the IPs, the use of a NoC as the interconnection mechanism proved to be effective. MediaBox enables the usage of different configurations through a configuration file and an address map that allows to explore these options. This _exibility allows the users to conceive and test different architectures through which the behavior and the performance of multiprocessor systems in a single chip can be studied
Mestrado
Ciência da Computação
Mestre em Ciência da Computação
6
Tedesco, Leonel Pablo. "Monitoração e roteamento adaptativo para fluxos QoS em NoCs." Pontifícia Universidade Católica do Rio Grande do Sul, 2010. http://hdl.handle.net/10923/1475.
Full textAbstract:
Made available in DSpace on 2013-08-07T18:42:24Z (GMT). No. of bitstreams: 1
000424524-Texto+Completo-0.pdf: 1961872 bytes, checksum: 05389810cf9264c18fc855018d938536 (MD5)
Previous issue date: 2010The growing number of applications running on emerging MPSoCs can be characterized by their high demand of computation and communication in different parts of the chip. The processing elements that execute these applications bring a dynamic and unpredictable nature to the on-chip traffic, due to the variability on data injection rates that they can generate. Networks on chip (NoCs) are the communication infrastructure to be used in such systems, due to their performance, reliability and scalability. To deal with the dynamic behavior of the application traffic, several methods are proposed at the system level (at runtime) and at the architecture level (at design time). The subject of this Thesis is the use of techniques for adaptability in NoCs at both system and architecture levels: buffer sizing and adaptive routing. The first technique introduces a decoupling buffer (D-buffer) on the target IP. This buffer receives data from the NoC with jitter, while the target IP consumes data from this buffer at the application rate, without jitter. Two problems must be solved to implement D-buffers: (i) which size must the buffer have? (ii) how much time should pass before data consumption starts (threshold)? A general method to define D-buffer size and threshold, considering the influence of packaging, arbitration, routing and concurrency between flows is presented. The second technique is an adaptive routing algorithm for NoCs, where the path between source and target IPs may be modified due to congestion events. The major part of the state of art proposals have a limited view of congestion, since each NoC router takes decisions based on the status of a few neighbors. Such local decisions may route packets to other congested regions, making the algorithm inefficient. This work presents a new method where congestion analysis considers information of all routers in the source-to-target path. This method relies on a protocol for QoS session establishment, followed by distributed monitoring and re-route to noncongested regions. Experimental results demonstrate the impact on multimedia flows with fixed and variable packet sizes (from real traffic traces) in the buffer sizing, and the percentage of deadline violations as a function of the D-buffer size. In terms of adaptive routing, the obtained results present the influence of different levels of traffic locality on packets latency, NoC occupation and adaptive routing reactivity to congestion events.
O crescente número de aplicações executando em MPSoCs emergentes pode ser caracterizado pela sua alta demanda de computação e comunicação nas diferentes parte do chip. Os elementos de processamento que executam estas aplicações trazem uma natureza dinâmica e imprevisível para o tráfego em chip, devido à variabilidade nas taxas de injeção de dados que eles podem gerar. As redes em chip (NoC – do inglês Network-on-Chip) são as estruturas de comunicação a serem utilizadas em tais sistemas, devido ao seu desempenho, confiabilidade e escalabilidade. Para lidar com o comportamento dinâmico do tráfego de aplicações, vários métodos de adaptação são propostos em nível de sistema (em tempo de execução) e em nível de arquitetura (em tempo de projeto). Esta Tese aborda o uso de técnicas de adaptação em NoCs em nível de sistema e de arquitetura: dimensionamento de buffer e roteamento adaptativo. A primeira técnica introduz um buffer de desacoplamento (D-buffer) no IP destino. Este buffer recebe dados da NoC com jitter, enquanto que o IP destino consome dados deste buffer na taxa da aplicação, sem jitter. Dois problemas devem ser resolvidos para a implementação de D-buffers: (i) qual tamanho este buffer deve possuir? (ii) quanto tempo deve ser esperado antes do início do consumo de dados (threshold)? Propõe-se aqui um método geral para definir o tamanho e threshold de D-buffers, considerando a influência do empacotamento, arbitragem, roteamento e concorrência entre fluxos. A segunda técnica é um algoritmo de roteamento adaptativo para NoCs, onde o caminho entre o IPs origem e destino pode ser modificado devido a eventos de congestionamento. A maior parte das propostas do estado da arte possui uma visão limitada de congestionamento, considerando que cada roteador da NoC toma decisões baseado no estado de seus vizinhos. Esta decisão local pode rotear pacotes a outras regiões congestionadas, o que pode tornar o algoritmo ineficiente. Este trabalho apresenta um novo método onde a análise de congestionamento considera informações de todos os roteadores no caminho entre a origem e destino. Este método é composto por um protocolo para estabelecimento de sessões QoS, seguido de monitoração distribuída e re-roteamento para regiões não congestionadas. Resultados experimentais demonstram o impacto de fluxos multimídia com tamanhos de pacotes fixo e variável (a partir de traces reais de tráfego) no dimensionamento de buffers, e o percentual de violações de prazos em função do tamanho do D-buffer. Em termos de roteamento adaptativo, os resultados obtidos apresentam a influência de diferentes níveis de localidade de tráfego na latência de pacotes, ocupação da NoC e reatividade do roteamento adaptativo a eventos de congestionamento.
7
Antunes, Eduardo de Brum. "Particionamento e mapeamento de MPSOCS homogêneos baseados em NOCS." Pontifícia Universidade Católica do Rio Grande do Sul, 2012. http://hdl.handle.net/10923/1660.
Full textAbstract:
Made available in DSpace on 2013-08-07T18:43:27Z (GMT). No. of bitstreams: 1
000437796-Texto+Completo-0.pdf: 2125944 bytes, checksum: 5e312ec4db3f55dac8ce8c7388128326 (MD5)
Previous issue date: 2012The increasing complexity of the applications demands more processing capacity, which boosts the development of a computational system composed of modules, such as processors, memories and specific hardware cores, called Multi-Processor System-on- Chip (MPSoC). If the modules of this system are connected through a Network-on-Chip (NoC) communication infrastructure and all processors are of the same type, they are known by homogeneous NoC based MPSoC. One of the main problems relating to MPSoCs design is the definition of which processors of the system will be responsible for each application task execution, objecting to meet the design requirements, such as the energy consumption minimization and the application execution time reduction. This work aims to carry out quickly and efficiently partitioning and mapping activities for the design of homogeneous MPSoCs. More specifically, the partitioning application's task into groups, and mapping of tasks or task groups into a target architecture type homogeneous NoC-based MPSoC. These activities are guided by requirements of energy consumption minimization and load balancing, and delimited by constraints of maximum energy consumption, maximum processing load and maxima areas of data and code of each processor. The work shows the complexity of partitioning and mapping activities separately and jointly. It also shows that the mapping is more efficient on energy consumption minimization, when compared to partitioning, yet the effect of partitioning cannot be neglected. Moreover, the joint effect of both activities saves in average 37% of energy. The mapping when performed at runtime may be inefficient, due to the short time and the large number of solutions to be explored. Having an approach that applies a static partition before the dynamic mapping, it is possible to achieve more efficient mappings. It happens due to the fact that static task partition onto groups minimizes the search space of the mapping. Experiments with several synthetic applications and four embedded applications show that the energy consumption is reduced 23. 5%, in average. This paper presents the PALOMA framework that performs the partitioning of tasks onto groups and the CAFES framework to map these ones into tiles of the target architecture, where each position contains a processor. These activities enable planning systems with less energy consumption, faster and in an acceptable design time.
O aumento da complexidade das aplicações demanda maior capacidade de processamento, impulsionando o desenvolvimento de um sistema computacional compostos por módulos como processadores, memórias e núcleos de hardware específicos, chamado de Multi-Processor System-on-Chip (MPSoC). Se os módulos deste sistema forem conectados por uma infraestrutura de comunicação do tipo Network-on- Chip (NoC) e todos os processadores forem de um único tipo, este é chamado de MPSoC homogêneo baseado em NoC. Um dos principais problemas relativo ao projeto de MPSoCs é a definição de qual dos processadores do sistema será responsável pela execução de cada tarefa de uma aplicação, visando atender os requisitos de projeto, tais como a redução do consumo de energia e a redução do tempo de execução da aplicação. Este trabalho tem como objetivo a realização de forma rápida e eficiente das atividades de particionamento e mapeamento para o projeto de MPSoCs homogêneos. Mais especificamente o particionamento de tarefas de uma aplicação em grupos, e o mapeamento de tarefas ou grupos de tarefas em processadores homogêneos de uma arquitetura alvo do tipo MPSoC baseado em NoC. Sendo estas atividades guiadas por requisitos de redução do consumo de energia e balanceamento de carga, e delimitadas por restrições de máximo consumo de energia, máxima carga de processamento e máximas áreas de dados e código associadas a cada processador. O trabalho mostra a complexidade das atividades de particionamento e mapeamento, separadas e conjuntamente. Mostra também que o mapeamento é mais eficiente na redução de consumo de energia, quando comparado com o particionamento, mas mesmo assim o efeito do particionamento não pode ser negligenciado. Além disto, o efeito conjunto de ambas as atividades reduz em média 37% o consumo de energia.O mapeamento, quando realizado em tempo de execução, pode ser pouco eficiente, devido ao tempo exíguo e ao grande número de soluções a serem exploradas. Utilizando uma abordagem que aplica um particionamento estático anterior ao mapeamento dinâmico, permite obter mapeamentos mais eficientes. Isto porque o particionamento estático de tarefas em grupos reduz o espaço de busca que o mapeamento necessita realizar. Experimentos com várias aplicações sintéticas e quatro aplicações embarcadas mostram que a redução média do consumo de energia é de 23,5%. Este trabalho apresenta o framework PALOMA que realiza o particionamento de tarefas em grupos e o framework CAFES para fazer o mapeamento destes em posições da arquitetura alvo, onde cada posição contém um processador. Estas atividades permitem planejar sistemas com menor consumo de energia, mais velozes e em tempo de projeto aceitável.
8
Silva, Douglas Roberto Guarani da. "Improving QoS by employing multiple physical NoCs on MPSoCs." Pontifícia Universidade Católica do Rio Grande do Sul, 2016. http://hdl.handle.net/10923/8193.
Full textAbstract:
Made available in DSpace on 2016-05-04T12:04:26Z (GMT). No. of bitstreams: 1
000478388-Texto+Completo-0.pdf: 3535458 bytes, checksum: a287a27f46a74cc898a15dccbe61ef44 (MD5)
Previous issue date: 2016Embedded systems adopt NoC-based MPSoCs since a large number of processing elements (PEs) enables the simultaneous execution of several applications, where some of these applications require real-time (RT) constraints. PEs communicate using messages in distributed memory MPSoCs. These messages can be classified as application messages, being the data generated by the applications, and management messages, used to ensure the correct operation of the platform. As the communication has a large impact on the application performance, an important concern in the design of MPSoCs is to improve the performance of the applications’ communication, particularly for RT applications. Two possible methods to optimize the communication performance includes: (i) prioritize the RT application messages over the messages generated by best-effort (BE) applications; (ii) isolate the application messages from the management messages, considering that complex MPSoCs require a large number of management services to meet the performance constraints. The NoC literature contains several works that differentiate traffic classes, proposing the isolation of these traffic classes by the use of multiple physical (MP) NoCs, reducing interferences among the flows belonging to different classes. The main goal of this work is to propose and to evaluate MP NoCs, with one network dedicated to the application messages and a second network for the management messages (MNoC).Based on the evaluation of the impact of the management traffic in the overall NoC communication, two different versions of M-NoCs are implemented and evaluated. Another important consideration for RT applications is to ensure that these applications meet their deadlines. The execution of these applications must have higher priority over the BE applications by dedicating more processing resources using a specialized RT scheduler. This work presents and evaluates an MPSoC platform capable of supporting both communication and computation QoS, being extensible for a large number of management services by to the use of MP NoCs. Results show that M-NoCs may be customized to have a small area overhead. The adoption of M-NoCs improves the communication performance, latency and jitter, even when the network used in the platform has QoS mechanisms (e. g. priority flows and circuit switching), by isolating the management traffic from the application traffic.
Sistemas embarcados adotam MPSoCs baseados em NoCs visto que um número grande de elementos de processamento (PEs) permitem a execução simultânea de várias aplicações, onde algumas dessas aplicações necessitam de restrições de tempo real (RT). PEs comunicam-se utilizando troca de mensagens em MPSoCs com memória distribuída. Essas mensagens podem ser classificadas como mensagens de aplicação, sendo os dados gerados pelas aplicações, e mensagens de gerência, utilizadas para garantir a operação correta da plataforma. Visto que a comunicação possui um forte impacto no desempenho da aplicação, uma preocupação importante no projeto de MPSoCs é de melhorar o desempenho da comunicação das aplicações, especialmente para aplicações RT. Dois métodos possíveis para otimizar o desempenho de comunicação incluem: (i) priorizar as mensagens das aplicações de RT sobre as mensagens geradas por aplicações de melhor esforço (do inglês, best effort, BE); (ii) isolar as mensagens de aplicações das mensagens de gerência, considerando que MPSoCs complexos necessitam de um grande número de serviços de gerência para satisfazer os requisitos de desempenho. Na literatura sobre NoCs há vários trabalhos que diferenciam classes de tráfego, propondo o isolamento dessas classes de tráfego pela utilização de múltiplas NoCs físicas (do inglês, multiple physical NoCs, MP NoCs), reduzindo interferências entre fluxos pertencentes a classes diferentes. O principal objetivo deste trabalho é propor e avaliar MP NoCs, onde uma rede é dedicada para mensagens de aplicação e uma segunda rede é utilizada para mensagens de gerência (M-NoC).Baseado na avaliação do impacto do tráfego de gerência na comunicação da NoC, duas versões da M-NoC são implementadas e avaliadas. Outra consideração importante para aplicações RT é garantir que os deadlines dessas aplicações sejam satisfeitos. A execução dessas aplicações deve ser priorizada sobre as aplicações BE através do fornecimento de mais recursos de processamento utilizando um escalonador RT especializado. Esse trabalho apresenta e avalia uma plataforma MPSoC capaz de suportar QoS de comunicação e de computação, sendo extensível para um número grande de serviços de gerência pelo uso de MP NoCs. Resultados mostram que as M-NoCs podem ser personalizadas para terem um pequeno impacto de área. A utilização de M-NoCs melhora o desempenho de comunicação, latência e jitter, mesmo considerando que a plataforma já possui mecanismos de QoS (como fluxos prioritários e chaveamento de circuitos), pelo isolamento do tráfego de gerência do tráfego de aplicação.
9
Frantz, Arthur Pereira. "Designing fault tolerant NoCs to improve reliability on SoCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/11302.
Full textAbstract:
Com a redução das dimensões dos dispositivos nas tecnologias sub-micrônicas foi possível um grande aumento no número de IP cores integrados em um mesmo chip e consequentemente novas arquiteturas de comunicação são usadas bucando atingir os requisitos de desempenho e potência. As redes intra-chip (Networks-on-Chip) foram propostas como uma plataforma alternativa de comunicação capaz de prover interconexões e comunicação entre os cores de um mesmo chip, tratando questões como desempenho, consumo de energia e reusabilidade para grandes sistemas integrados. Por outro lado, a mesma evolução tecnológica dos processos nanométricos reduziu drasticamente a confiabilidade de circuitos integrados, tornando dispositivos e interconexões mais sensíveis a novos tipos de falhas. Erros podem ser gerados por variações no processo de fabricação ou mesmo pela susceptibilidade do projeto, quando este opera em um ambiente hostil. Na comunicação de NoCs as duas principais fontes de erros são falhas de crosstalk e soft errors. No passado, se assumia que interconexões não poderiam ser afetadas por soft errors, por não possuirem circuitos seqüenciais. Porém, quando NoCs são usadas, buffers e circuitos seqüenciais estão presentes nos roteadores e, consequentemente, podem ocorrer soft errors entre a fonte e o destino da comunicação, provocando erros. Técnicas de tolerância a falhas, que tem sido aplicadas em circuitos em geral, podem ser usadas para proteger roteadores contra bit-flips. Neste cenário, este trabalho inicia com a avaliação dos efeitos de soft errors e falhas de crosstalk em uma arquitetura de NoC, através de simulação de injeção de falhas, analisando detalhadamente o impacto de tais falhas no roteador. Os resultados mostram que os efeitos dessas falhas na comunicação do SoC podem ser desastrosos, levando a perda de pacotes e travamento ou indisponibilidade do sistema. Então é proposta e avaliada a aplicação de um conjunto de técnicas de tolerância a falhas em roteadores, possibilitando diminuir os soft errors e falhas de crosstalk no nível de hardware. Estas técnicas propostas foram baseadas em códigos de correção de erros e redundância de hardware. Resultados experimentais mostram que estas técnicas podem obter zero erros com 50% a menos de overhead de área, quando comparadas com a duplicação simples. Entretanto, algumas dessas técnicas têm um grande consumo de potência, pois toda essas técnicas são baseadas na adição de hardware redundante. Considerando que as técnicas de proteção baseadas em software também impõe um considerável overhead na comunicação devido à retransmissão, é proposto o uso de técnicas mistas de hardware e software, que podem oferecer um nível de proteção satisfatório, baseado na análise do ambiente onde o sistema irá operar (soft error rate), fatores relativos ao projeto e fabricação (variações de atraso em interconexões, pontos susceptíveis a crosstalk), a probabilidade de uma falha gerar um erro em um roteador, a carga de comunicação e os limites de potência e energia suportados.As the technology scales down into deep sub-micron domain, more IP cores are integrated in the same die and new communication architectures are used to meet performance and power constraints. Networks-on-Chip have been proposed as an alternative communication platform capable of providing interconnections and communication among onchip cores, handling performance, energy consumption and reusability issues for large integrated systems. However, the same advances to nanometric technologies have significantly reduced reliability in mass-produced integrated circuits, increasing the sensitivity of devices and interconnects to new types of failures. Variations at the fabrication process or even the susceptibility of a design under a hostile environment might generate errors. In NoC communications the two major sources of errors are crosstalk faults and soft errors. In the past, it was assumed that connections cannot be affected by soft errors because there was no sequential circuit involved. However, when NoCs are used, buffers and sequential circuits are present in the routers, consequently, soft errors can occur between the communication source and destination provoking errors. Fault tolerant techniques that once have been applied in integrated circuits in general can be used to protect routers against bit-flips. In this scenario, this work starts evaluating the effects of soft errors and crosstalk faults in a NoC architecture by performing fault injection simulations, where it has been accurate analyzed the impact of such faults over the switch service. The results show that the effect of those faults in the SoC communication can be disastrous, leading to loss of packets and system crash or unavailability. Then it proposes and evaluates a set of fault tolerant techniques applied at routers able to mitigate soft errors and crosstalk faults at the hardware level. Such proposed techniques were based on error correcting codes and hardware redundancy. Experimental results show that using the proposed techniques one can obtain zero errors with up to 50% of savings in the area overhead when compared to simple duplication. However some of these techniques are very power consuming because all the tolerance is based on adding redundant hardware. Considering that softwarebased mitigation techniques also impose a considerable communication overhead due to retransmission, we then propose the use of mixed hardware-software techniques, that can develop a suitable protection scheme driven by the analysis of the environment that the system will operate in (soft error rate), the design and fabrication factors (delay variations in interconnects, crosstalk enabling points), the probability of a fault generating an error in the router, the communication load and the allowed power or energy budget.
10
Zhang, Yixuan. "High-Performance Crossbar Designs for Network-on-Chips (NoCs)." Ohio University / OhioLINK, 2010. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1282056856.
Full text
11
Tedesco, Leonel Pablo. "Monitora??o e roteamento adaptativo para fluxos QoS em NoCs." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2010. http://tede2.pucrs.br/tede2/handle/tede/5098.
Full textAbstract:
Made available in DSpace on 2015-04-14T14:49:23Z (GMT). No. of bitstreams: 1
424524.pdf: 1961872 bytes, checksum: 05389810cf9264c18fc855018d938536 (MD5)
Previous issue date: 2010-05-12O crescente n?mero de aplica??es executando em MPSoCs emergentes pode ser caracterizado pela sua alta demanda de computa??o e comunica??o nas diferentes parte do chip. Os elementos de processamento que executam estas aplica??es trazem uma natureza din?mica e imprevis?vel para o tr?fego em chip, devido ? variabilidade nas taxas de inje??o de dados que eles podem gerar. As redes em chip (NoC do ingl?s Network-on-Chip) s?o as estruturas de comunica??o a serem utilizadas em tais sistemas, devido ao seu desempenho, confiabilidade e escalabilidade. Para lidar com o comportamento din?mico do tr?fego de aplica??es, v?rios m?todos de adapta??o s?o propostos em n?vel de sistema (em tempo de execu??o) e em n?vel de arquitetura (em tempo de projeto). Esta Tese aborda o uso de t?cnicas de adapta??o em NoCs em n?vel de sistema e de arquitetura: dimensionamento de buffer e roteamento adaptativo. A primeira t?cnica introduz um buffer de desacoplamento (D-buffer) no IP destino. Este buffer recebe dados da NoC com jitter, enquanto que o IP destino consome dados deste buffer na taxa da aplica??o, sem jitter. Dois problemas devem ser resolvidos para a implementa??o de D-buffers: (i) qual tamanho este buffer deve possuir? (ii) quanto tempo deve ser esperado antes do in?cio do consumo de dados (threshold)? Prop?e-se aqui um m?todo geral para definir o tamanho e threshold de D-buffers, considerando a influ?ncia do empacotamento, arbitragem, roteamento e concorr?ncia entre fluxos. A segunda t?cnica ? um algoritmo de roteamento adaptativo para NoCs, onde o caminho entre o IPs origem e destino pode ser modificado devido a eventos de congestionamento. A maior parte das propostas do estado da arte possui uma vis?o limitada de congestionamento, considerando que cada roteador da NoC toma decis?es baseado no estado de seus vizinhos. Esta decis?o local pode rotear pacotes a outras regi?es congestionadas, o que pode tornar o algoritmo ineficiente. Este trabalho apresenta um novo m?todo onde a an?lise de congestionamento considera informa??es de todos os roteadores no caminho entre a origem e destino. Este m?todo ? composto por um protocolo para estabelecimento de sess?es QoS, seguido de monitora??o distribu?da e re-roteamento para regi?es n?o congestionadas. Resultados experimentais demonstram o impacto de fluxos multim?dia com tamanhos de pacotes fixo e vari?vel (a partir de traces reais de tr?fego) no dimensionamento de buffers, e o percentual de viola??es de prazos em fun??o do tamanho do D-buffer. Em termos de roteamento adaptativo, os resultados obtidos apresentam a influ?ncia de diferentes n?veis de localidade de tr?fego na lat?ncia de pacotes, ocupa??o da NoC e reatividade do roteamento adaptativo a eventos de congestionamento.
12
Antunes, Eduardo de Brum. "Particionamento e mapeamento de MPSOCS homog?neos baseados em NOCS." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2012. http://tede2.pucrs.br/tede2/handle/tede/5159.
Full textAbstract:
Made available in DSpace on 2015-04-14T14:49:42Z (GMT). No. of bitstreams: 1
437796.pdf: 2125944 bytes, checksum: 5e312ec4db3f55dac8ce8c7388128326 (MD5)
Previous issue date: 2012-02-29The increasing complexity of the applications demands more processing capacity, which boosts the development of a computational system composed of modules, such as processors, memories and specific hardware cores, called Multi-Processor System-on- Chip (MPSoC). If the modules of this system are connected through a Network-on-Chip (NoC) communication infrastructure and all processors are of the same type, they are known by homogeneous NoC based MPSoC. One of the main problems relating to MPSoCs design is the definition of which processors of the system will be responsible for each application task execution, objecting to meet the design requirements, such as the energy consumption minimization and the application execution time reduction. This work aims to carry out quickly and efficiently partitioning and mapping activities for the design of homogeneous MPSoCs. More specifically, the partitioning application's task into groups, and mapping of tasks or task groups into a target architecture type homogeneous NoC-based MPSoC. These activities are guided by requirements of energy consumption minimization and load balancing, and delimited by constraints of maximum energy consumption, maximum processing load and maxima areas of data and code of each processor. The work shows the complexity of partitioning and mapping activities separately and jointly. It also shows that the mapping is more efficient on energy consumption minimization, when compared to partitioning, yet the effect of partitioning cannot be neglected. Moreover, the joint effect of both activities saves in average 37% of energy. The mapping when performed at runtime may be inefficient, due to the short time and the large number of solutions to be explored. Having an approach that applies a static partition before the dynamic mapping, it is possible to achieve more efficient mappings
O aumento da complexidade das aplica??es demanda maior capacidade de processamento, impulsionando o desenvolvimento de um sistema computacional compostos por m?dulos como processadores, mem?rias e n?cleos de hardware espec?ficos, chamado de Multi-Processor System-on-Chip (MPSoC). Se os m?dulos deste sistema forem conectados por uma infraestrutura de comunica??o do tipo Network-on- Chip (NoC) e todos os processadores forem de um ?nico tipo, este ? chamado de MPSoC homog?neo baseado em NoC. Um dos principais problemas relativo ao projeto de MPSoCs ? a defini??o de qual dos processadores do sistema ser? respons?vel pela execu??o de cada tarefa de uma aplica??o, visando atender os requisitos de projeto, tais como a redu??o do consumo de energia e a redu??o do tempo de execu??o da aplica??o. Este trabalho tem como objetivo a realiza??o de forma r?pida e eficiente das atividades de particionamento e mapeamento para o projeto de MPSoCs homog?neos. Mais especificamente o particionamento de tarefas de uma aplica??o em grupos, e o mapeamento de tarefas ou grupos de tarefas em processadores homog?neos de uma arquitetura alvo do tipo MPSoC baseado em NoC. Sendo estas atividades guiadas por requisitos de redu??o do consumo de energia e balanceamento de carga, e delimitadas por restri??es de m?ximo consumo de energia, m?xima carga de processamento e m?ximas ?reas de dados e c?digo associadas a cada processador. O trabalho mostra a complexidade das atividades de particionamento e mapeamento, separadas e conjuntamente. Mostra tamb?m que o mapeamento ? mais eficiente na redu??o de consumo de energia, quando comparado com o particionamento, mas mesmo assim o efeito do particionamento n?o pode ser negligenciado. Al?m disto, o efeito conjunto de ambas as atividades reduz em m?dia 37% o consumo de energia. O mapeamento, quando realizado em tempo de execu??o, pode ser pouco eficiente, devido ao tempo ex?guo e ao grande n?mero de solu??es a serem exploradas. Utilizando uma abordagem que aplica um particionamento est?tico anterior ao mapeamento din?mico, permite obter mapeamentos mais eficientes. Isto porque o particionamento est?tico de tarefas em grupos reduz o espa?o de busca que o mapeamento necessita realizar. Experimentos com v?rias aplica??es sint?ticas e quatro aplica??es embarcadas mostram que a redu??o m?dia do consumo de energia ? de 23,5%. Este trabalho apresenta o framework PALOMA que realiza o particionamento de tarefas em grupos e o framework CAFES para fazer o mapeamento destes em posi??es da arquitetura alvo, onde cada posi??o cont?m um processador. Estas atividades permitem planejar sistemas com menor consumo de energia, mais velozes e em tempo de projeto aceit?vel
13
Jung, Kyung S. "Corporate governance of NOCs : the case of Korean Olympic Committee." Thesis, Loughborough University, 2013. https://dspace.lboro.ac.uk/2134/13462.
Full textAbstract:
This study identifies the characteristics of seven key principles of good/corporate governance at three levels: as notions that originated in business; in their applications to sport through systematic review; and in relation to the interpretations given to them in the Olympic Movement. The aims of this study are, thus, to establish and utilise the IOC s definitions/interpretations and operationalisations of corporate and/or good governance developed in a western framework and apply to a non-western NOC, the Korean Olympic Committee (KOC). This study adopts critical realist assumptions which give rise to the hypothesis that both the regularities of the Korean society and its unobservable social structures have an impact on the corporate governance of the KOC. It also uses Critical Discourse Analysis (CDA) to examine each interviewee s discourse in order to identify the knowledge embraced by it and to interpret social practice(s) and the exercise of power. CDA is employed in relation to four selected events follows: the KOC/KSC merger, budgetary planning, the recruitment of staff in terms of gender and disability equity and the processes used for selecting the KOC President and the Chef de Mission. The unobservable deep structure is shown to be real domain in Korean society by the social practices exhibited in the four events. The government and, in particular, the State President represent the highest and most influential authority in decision-making on Korean sports policy. That power relationship coupled with the pre-existing structure of the KOC/KSC s financial dependency on the government has resulted in a situation where the government has been able to interfere greatly in the KOC/KSC s overall decision-making on sports policy including the election of the President of the KOC. The KOC/KSC President is the most influential stakeholder in the decision-making within the organisation including the selection of Chef de Mission. As the pre-existing structure of cultural expectations determines that women should usually quit their jobs after marriage and that people with disabilities are incapable of working, the strongly male with abilities-dominated organisational culture has resulted in a social phenomenon whereby few females or people with impairments have succeeded in being promoted to senior positions. From the macro-level perspective, the first KOC/KSC merger accomplished on the orders of the State President shows the dominance of economic power as suggested in Marxist influenced forms of analysis. The incumbent KOC President, who is at the pinnacle of the business elite, contributed to the KOC/KSC merger, which illustrates the aspect of elitism. In connection with the budgetary process, this may be viewed as evidence of the existence of a neo-corporatist structure in which the state plays a central role and acts in a unitary way with the involvement of a limited number of actors. With respect to the meso-level perspective, the aspect of clientelism is exhibited since the government habitually appoints its political aides to be the heads of various sporting organisations. Concerning political governance, it becomes obvious that the government has direct control over KOC/KSC s policy. In terms of systemic governance, the relations among the domestic stakeholders of the KOC are more likely to follow a hierarchical type of governance, as the government has adopted the highest position and the National Federations are under the control of the KOC/KSC. With reference to Lukes (1974) second dimension of power this can be evidenced in the context of the non-decision making roles of women and the disabled. The IOC s interpretations of the key principles of corporate governance in a western framework are applied to the KOC. Accountability, responsibility, transparency and democracy are established but the KOC s governance practices are not equivalent, while effectiveness and efficiency are interpreted as the same ways of the IOC s. In general, power centralisation is apparent throughout the Korean cultural context. The KOC s power structure and organisational culture is likely to be concentrated to the KOC President within the organisation and broadly, the Korean government enjoys its power centralisation decision-making in the Korean context which gives rise to a peculiarly Korean way of interpreting and applying the principles of corporate governance. In such circumstances, nevertheless, where the KOC is making an effort to align its practices with the IOC s recommendations as much as possible, the indication is that the KOC is on course to reflect the IOC s governance practices.
14
Morris, Randy W. Jr. "Energy-Efficient and High-Performance Nanophotonic Interconnects for Shared Memory Multicores." Ohio University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1335980809.
Full text
15
Stefani, Marco Pokorski. "Particionamento e mapeamento de aplicações em MPSoCs baseados em NoCs 3D." Pontifícia Universidade Católica do Rio Grande do Sul, 2015. http://hdl.handle.net/10923/7438.
Full textAbstract:
Made available in DSpace on 2015-06-30T02:06:09Z (GMT). No. of bitstreams: 1
000471296-Texto+Completo-0.pdf: 2108698 bytes, checksum: 3b45f65685531967cfcb1b4458fc269a (MD5)
Previous issue date: 2015Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) incorporates a lot of Processing Elements (PEs) in order to perform applications with high degree of parallelism/concurrence. These applications consist of several communicating tasks that are dynamically mapped into the PEs of the target architecture. When the number of application tasks grows, the complexity of mapping also grows, possibly reducing the effectiveness and/or efficiency of the solution. An approach for the mapping optimization is the introduction of a previous step called partitioning, which allows to organize the tasks interaction through an efficient grouping, reducing the number of mapping alternatives. This paper proposes the Partition Reduce (PR) algorithm, which is a task partitioning approach inspired on MapReduce algorithm, where tasks are partitioned by a deterministic iterative clustering. The PR was analyzed according to its effectiveness and efficiency to minimize the energy consumption caused by the communication in the target architecture and to balance the processing load on the PEs. Experimental results, containing a wide range of complex tasks, show that PR is more effective in generating partitions with low power consumption and efficient load balancing at any level of tasks complexity, when compared with the simulated annealing (SA) algorithm. Moreover, the results show that the algorithm is efficient only for medium or high complexity applications.
Sistema multiprocessado intrachip, em inglês Multiprocessor System-on-Chip (MPSoC), com comunicação baseada em rede intrachip, em inglês Network-on-Chip (NoC), integra grande quantidade de Elementos de Processamento (PEs) com o objetivo de executar aplicações com alto grau de paralelismo/concorrência. Estas aplicações são compostas por diversas tarefas comunicantes, que são mapeadas dinamicamente nos PEs da arquitetura alvo. Quando cresce o número de tarefas da aplicação, a complexidade do mapeamento também cresce, podendo reduzir a eficácia e/ou a eficiência da solução encontrada. Uma abordagem para otimizar o mapeamento é a introdução de uma etapa anterior denominada particionamento, que permite organizar a interação das tarefas através de um agrupamento eficiente, reduzindo o número de alternativas do mapeamento. Esta dissertação propõe o algoritmo Partition Reduce (PR), que é uma abordagem de particionamento de tarefas baseada no algoritmo MapReduce, onde as tarefas são particionadas através de um agrupamento iterativo determinístico. O PR foi analisado quanto a sua eficácia e eficiência para minimizar o consumo de energia causada pela comunicação na arquitetura alvo e para balancear a carga de processamento nos PEs. Resultados experimentais, contendo um conjunto variado de complexidade de tarefas, demonstram que o PR é mais eficiente na geração de partições com baixo consumo de energia e com um balanceamento de carga eficiente para qualquer nível de complexidade de tarefas, quando comparado com o Simulated Annealing (SA). Por outro lado, os resultados mostram que o algoritmo é eficaz apenas para aplicações de média e alta complexidade.
16
Bhattacharya, Prasun. "Comparisonof single-port and multi-port NoCs with contemporary buses on FPGAs." Cincinnati, Ohio : University of Cincinnati, 2006. http://www.ohiolink.edu/etd/view.cgi?acc%5Fnum=ucin1142842819.
Full textAbstract:
Thesis (M.S.)--University of Cincinnati, 2006.Title from electronic thesis title page (viewed Sept. 15, 2006). Includes abstract. Keywords: NoC, Routers, SoC, FPGA. Includes bibliographical references.
17
M'Zah, Abir. "Les méthodologies de conception ASIC des NoCs 3D dédiées aux MPSOCs Hétérogènes." Phd thesis, Ecole Polytechnique X, 2012. http://pastel.archives-ouvertes.fr/pastel-00769455.
Full textAbstract:
La feuille de route d'ITRS prévoit que le nombre de processeurs dans la même puce va augmenter suivant une courbe exponentielle. Assurer la connexion entre les différents processeurs dans la même puce constitue un vrai défi quand le nombre des composants est important. L'utilisation d'un réseau sur puce est une solution efficace qui résout les problèmes des moyens classiques de connexion comme le bus et le point à point. Le réseau sur puce régulier coûte cher en termes de surface et d'énergie, c'est pourquoi la conception d'une architecture optimale représente une motivation majeure. En plus, avec la réduction de la taille des transistors, le temps de propagation dans les liens dépasse celui des portes logiques. En effet, il est indispensable de trouver de nouvelles techniques qui permettent de continuer le développement des circuits du semi conducteur. La conception 3D des circuits intégrés est une solution prometteuse qui peut réduire la longueur des liens, la surface de la puce et qui permet d'utiliser des technologies différentes dans la même architecture. Vu le manque d'implémentations réelles des architectures à base de multiprocesseurs avec la technique 3D, nous proposons dans cette thèse d'étudier les méthodologies de conception ASIC des architectures MPSOC à base du NoC 3D. Bien que les réseaux sur puce soient considérés comme une solution efficace pour le problème de connexions entre les processeurs, rares sont les travaux qui valident le NoC par une vraie implémentation sur FPGA/ASIC. Nous considérons que la validation d'un NoC par émulation nous permet de garantir la bonne fonctionnalité de notre architecture lors de l'implémentation en 3D. La technique de conception en 3D IC est confrontée à plusieurs problèmes comme le placement des connexions verticales, la dissipation de chaleur et le problème de partitionnement. Dans ce cadre, nous proposons dans cette thèse une nouvelle méthodologie de synthèse NoC 3D qui se base sur les algorithmes évolutionnaires. Nous avons implémenté une architecture MPSOC avec la technologie 3D de Tezzaron. Notre cas d'étude représente une architecture significative qui tient en considération les contraintes de la technologie 3D de Tezzaron.
18
Stefani, Marco Pokorski. "Particionamento e mapeamento de aplica??es em MPSoCs baseados em NoCs 3D." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2015. http://tede2.pucrs.br/tede2/handle/tede/6188.
Full textAbstract:
Submitted by Setor de Tratamento da Informa??o - BC/PUCRS (tede2@pucrs.br) on 2015-06-29T12:40:33Z
No. of bitstreams: 1
471296 - Texto Completo.pdf: 2108698 bytes, checksum: 3b45f65685531967cfcb1b4458fc269a (MD5)Made available in DSpace on 2015-06-29T12:40:33Z (GMT). No. of bitstreams: 1 471296 - Texto Completo.pdf: 2108698 bytes, checksum: 3b45f65685531967cfcb1b4458fc269a (MD5) Previous issue date: 2015-03-30
Multiprocessor System-on-Chip (MPSoC) based on Network-on-Chip (NoC) incorporates a lot of Processing Elements (PEs) in order to perform applications with high degree of parallelism/concurrence. These applications consist of several communicating tasks that are dynamically mapped into the PEs of the target architecture. When the number of application tasks grows, the complexity of mapping also grows, possibly reducing the effectiveness and/or efficiency of the solution. An approach for the mapping optimization is the introduction of a previous step called partitioning, which allows to organize the tasks interaction through an efficient grouping, reducing the number of mapping alternatives. This paper proposes the Partition Reduce (PR) algorithm, which is a task partitioning approach inspired on MapReduce algorithm, where tasks are partitioned by a deterministic iterative clustering. The PR was analyzed according to its effectiveness and efficiency to minimize the energy consumption caused by the communication in the target architecture and to balance the processing load on the PEs. Experimental results, containing a wide range of complex tasks, show that PR is more effective in generating partitions with low power consumption and efficient load balancing at any level of tasks complexity, when compared with the simulated annealing (SA) algorithm. Moreover, the results show that the algorithm is efficient only for medium or high complexity applications.
Sistema multiprocessado intrachip, em ingl?s Multiprocessor System-on-Chip (MPSoC), com comunica??o baseada em rede intrachip, em ingl?s Network-on-Chip (NoC), integra grande quantidade de Elementos de Processamento (PEs) com o objetivo de executar aplica??es com alto grau de paralelismo/concorr?ncia. Estas aplica??es s?o compostas por diversas tarefas comunicantes, que s?o mapeadas dinamicamente nos PEs da arquitetura alvo. Quando cresce o n?mero de tarefas da aplica??o, a complexidade do mapeamento tamb?m cresce, podendo reduzir a efic?cia e/ou a efici?ncia da solu??o encontrada. Uma abordagem para otimizar o mapeamento ? a introdu??o de uma etapa anterior denominada particionamento, que permite organizar a intera??o das tarefas atrav?s de um agrupamento eficiente, reduzindo o n?mero de alternativas do mapeamento. Esta disserta??o prop?e o algoritmo Partition Reduce (PR), que ? uma abordagem de particionamento de tarefas baseada no algoritmo MapReduce, onde as tarefas s?o particionadas atrav?s de um agrupamento iterativo determin?stico. O PR foi analisado quanto a sua efic?cia e efici?ncia para minimizar o consumo de energia causada pela comunica??o na arquitetura alvo e para balancear a carga de processamento nos PEs. Resultados experimentais, contendo um conjunto variado de complexidade de tarefas, demonstram que o PR ? mais eficiente na gera??o de parti??es com baixo consumo de energia e com um balanceamento de carga eficiente para qualquer n?vel de complexidade de tarefas, quando comparado com o Simulated Annealing (SA). Por outro lado, os resultados mostram que o algoritmo ? eficaz apenas para aplica??es de m?dia e alta complexidade.
19
BHATTACHARYA, PRASUN. "COMPARISON OF SINGLE-PORT AND MULTI-PORT NoCs WITH CONTEMPORARY BUSES ON FPGAs." University of Cincinnati / OhioLINK, 2006. http://rave.ohiolink.edu/etdc/view?acc_num=ucin1142842819.
Full text
20
Matos, Débora da Silva Motta. "Exploring hierarchy, adaptability and 3D in NoCs for the next generation of MPSoCs." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2014. http://hdl.handle.net/10183/94764.
Full textAbstract:
A demanda por sistemas com elevado desempenho tem trazido a necessidade de aumentar o número de elementos de processamento, surgindo os chamados Sistemas em Chip Multiprocessados (MPSoCs). Além disso, com a possibilidade de redução da escala tecnológica na era submicrônica, permitindo a integração de vários dispositivos, os chips têm se tornado ainda mais complexos. No entanto, com o aumento no número de elementos de processamento, as interconexões são vistas com o principal gargalo dos sistemas-em-chip. Com isso, uma preocupação na forma como tais elementos se comunicam e estão interconectados tem sido levantada, uma vez que tais características são cruciais nos aspectos de desempenho, energia e potência, principalmente em sistemas embarcados. Essa necessidade permitiu o advento das redes-em-chip (Networks-on-Chip – NoCs) e inúmeros estudos já foram realizados para tais dispositivos. No entanto, devido ao aceleramento tecnológico atual, que traz a necessidade por sistemas ainda mais complexos, que consumam baixa energia e que permitam que as aplicações sejam constantemente atualizadas sem perder as características de desempenho, as arquiteturas de interconexão tradicionais não serão suficientes para satisfazer tais desafios. Outras alternativas de interconexão para MPSoCs precisam ser investigadas e nesse trabalho novas arquiteturas para NoCs com tais requisitos são apresentadas. As soluções propostas exploram hierarquia, adaptabilidade e interconexões em três dimensões. Esse trabalho aborda a necessidade do uso de diferentes estratégias em NoCs a fim de atingir os requisitos de desempenho e baixo consumo de potência dos atuais e futuros MPSoCs. Dessa forma, serão verificadas as diversas arquiteturas de interconexões para sistemas heterogêneos, sua escalabilidade, suas principais características e as vantagens das propostas apresentadas sobre as demais soluções.The demand for systems with high performance has brought the need to increase the number of cores, emerging the called Multi-Processors System-on-Chip (MPSoCs). Also, with the shrinking feature size in deep-submicron era, allowing the integration of several devices, chips have become even more complex. However, with the increase in these elements, interconnections are seen as the main bottleneck in many core systemson- chip. With this, a concern about how these devices communicate and are interconnected has been raised, since these features are crucial for the performance, energy and power consumption aspects, mainly in embedded systems. This need allows the advent of the Networks-on-Chip (NoCs) and countless studies had already been done to analyze such interconnection devices. However, due to the current technological accelerating that brings the need for even more complex systems, consuming lower energy and providing constant application updates without losing performance features, traditional interconnect architectures will not be sufficient to satisfy such challenges. Other interconnecting alternatives for MPSoCs need to be investigated and in this work, novel architectures for NoCs meeting such requirements are presented. The proposed solutions explore hierarchy, adaptability and three dimensional interconnections. This work approaches the requirements in the use of different strategies for NoCs in order to reach the performance requisites and low power consumption of the current and future MPSoCs. Hence, in this approach, several interconnection architectures for heterogeneous systems, their scalability and the main features and advantages of the proposed strategies in comparison with others will be verified.
21
Wronski, Fabio. "Alocação dinâmica de tarefas periódicas em NoCs malha com redução do consumo de energia." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2007. http://hdl.handle.net/10183/11177.
Full textAbstract:
O objetivo deste trabalho é propor técnicas de alocação dinâmica de tarefas periódicas em MPSoCs homogêneos, com processadores interligados por uma rede emchip do tipo malha, visando redução do consumo de energia do sistema. O foco principal é a definição de uma heurística de alocação, não se considerando protocolos de escalonamento distribuído, uma vez que este ainda é um primeiro estudo para o desenvolvimento de um alocador dinâmico. Na arquitetura alvo utilizada, cada nodo do sistema é dado como autônomo, possuindo seu próprio escalonador EDF. Além disso, são aplicadas técnicas de voltage scaling e power managmenent para redução do consumo de energia durante o escalonamento. Durante a pesquisa do estado da arte, não foram encontradas técnicas de alocação dinâmica em NoCs com restrições temporais e minimização do consumo de energia. Por isso, esse trabalho se concentra em avaliar técnicas de alocação convencionais, como bin-packing e técnicas baseadas em teoria de grafos, no contexto de sistemas embarcados. Dessa forma, o modelo de estimativas do consumo de energia de alocações é baseado no escalonamento de grafos de tarefas, e foi utilizado para implementar a ferramenta Serpens com este propósito. Os grafos de tarefas utilizados nos experimentos são tirados do benchmark E3S – Embedded System Synthesis Benchmark Suite, composto por um conjunto de grafos de tarefas gerados aleatoriamente com a ferramenta TGFF – Task Graph for Free, a partir de dados de aplicações comuns em sistemas embarcados obtidos no EEMBC – Embedded Microprocessor Benchmark Consortium. Entre as heurísticas de bin-packing, Best-Fit, First-Fit e Next-Fit geram alocações com concentração de carga, enquanto a heurística Worst-Fit faz balanceamento de carga. O balanceamento de carga favorece a aplicação de voltage scaling enquanto a concentração favorece o power management. Como o bin-packing não contempla comunicação e dependência entre tarefas em seu modelo, o mesmo foi reformulado para atender esta necessidade. Nos experimentos, a alocação inicial com bin-packing original apresentou perdas de deadlines de até 84 % para a heurística Worst-Fit, passando para perdas em torno de 16% na alocação final, praticamente com o mesmo consumo de energia, após a reformulação do modelo.The goal of this work is to offer dynamic allocation techniques of periodic tasks in mesh networks-on-chip, aiming to reduce the system power consumption. The main focus is the definition of an allocation heuristic, which does not consider distributed scheduling protocols, since this is the beginning of a study for the development of a dynamic partitioning tool. In the target architecture, each system node is self-contained, that is, the nodes contain their own EDF scheduler. Besides, voltage-scaling and power management techniques are applied for reducing power consumption during the scheduling. To the best of our knowledge, this is the first research effort considering both temporal constraints and power consumption minimization on the dynamic allocation of tasks in a mesh NoC. This way, our concentrates in the evaluation of dynamic allocation techniques, which are generally used in distributed systems, in the embedded systems context, as bin-packing and graph theory based techniques. Therefore, the estimation model for power consumption is based on task graph scheduling, and it was used for implementing the Serpens tool with this purpose. The task graphs used in the experiments were obtained from the E3S benchmark (Embedded System Synthesis Benchmark Suite), which is composed by a set of task graphs randomly generated with the TGFF tool (Task Graph for Free), from common application data obtained from the EEMBC (Embedded Microprocessor Benchmark Consortium). Among the bin-packing heuristics, Best-Fit, First-Fit, and Next-Fit generate allocations with load concentration, while the Worst-Fit heuristics works with load balancing. Load balancing favors the application of voltage scaling, while load concentration favors the utilization of power management. Since the bin-packing model does not consider inter-task communication and dependency, it has been modified to fulfill this need. In the experiments, the initial allocation using the original bin-packing model presented deadline losses of up to 84% for the Worst-Fit heuristic, changing for losses around 16% in the final allocation, after modification of the model, maintaining almost the same power consumption.
22
Dun, Yarui. "State capitalism: a comparative study of National Oil Companies (NOCs) between Brazil and China." reponame:Repositório Institucional do FGV, 2017. http://hdl.handle.net/10438/18290.
Full textAbstract:
Submitted by Yarui Dun (yarui0422@gmail.com) on 2017-05-17T19:30:55Z
No. of bitstreams: 1
Dissertation Yarui Dun.pdf: 3370034 bytes, checksum: 0971a3c099bb023b78027e1514037a71 (MD5)Approved for entry into archive by ÁUREA CORRÊA DA FONSECA CORRÊA DA FONSECA (aurea.fonseca@fgv.br) on 2017-05-18T14:29:11Z (GMT) No. of bitstreams: 1 Dissertation Yarui Dun.pdf: 3370034 bytes, checksum: 0971a3c099bb023b78027e1514037a71 (MD5)
Made available in DSpace on 2017-05-30T17:36:05Z (GMT). No. of bitstreams: 1 Dissertation Yarui Dun.pdf: 3370034 bytes, checksum: 0971a3c099bb023b78027e1514037a71 (MD5) Previous issue date: 2017-05-02
State capitalism, the statist planning in certain economic sectors, has generated several state-owned enterprises (SOEs) that represent a significant share of activity in the global market. Despite decades of liberalization and privatization in many countries, state ownership and state-led business activity remain widespread; yet new varieties of state capitalism have also emerged. Among these new varieties, state-controlled oil and natural gas entities, also known as nation oil companies (NOCs), represent a type of hybrid organization that specifically deserves scholars’ attention as they dominate the world’s oil & gas industry; yet many of the cases prove to be problematic. The emerging markets possess some of the most important NOC players, yet scant examination has been made to question their appropriateness. This paper presents a contextualized comparison between two NOCs that root in Brazil and China to illustrate how similar and different they are in terms of their ownership style, corporate governance characteristics, and the interactions they have with the host government. We analyzed the findings by matching them with the past theories that offer explanations on NOC performance variation. We concluded that first, regime type is not a dependable factor to indicate the actual state incentives to maintain NOCs, and the goals of state serve only as an equivocate factor in explaining the variation in NOC performances. Secondly, we speculated that due to the absence of a cohesive institutional logic and consistency, Brazil has a fragmented governance system that implies in inappropriateness of state capitalism. Thirdly, we discovered that the unique dynamics between informal and formal institutions in China may justify the better fitness of state capitalism when compared with Brazil. Certain limits to the research method and expectations on further inquiries are also developed.
23
Bhattacharya, Prasun. "Comparison of single-port and multi-port NoCs with contemporary buses WITH on ON FPGAs." Cincinnati, Ohio : University of Cincinnati, 2006. http://www.ohiolink.edu/etd/view.cgi?acc%5Fnum=ucin1142842819.
Full textAbstract:
Thesis (M.S.)--University of Cincinnati, 2006.Title from electronic thesis title page (viewed Sept. 15, 2006). Includes abstract. Keywords: NoC, Routers, SoC, FPGA Includes bibliographical references.
24
Morris, Randy W. Jr. "PROPEL: Power & Area-Efficient, Scalable Opto-Electronic Network-on-Chip." Ohio University / OhioLINK, 2009. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1244146228.
Full text
25
Fernandes, Ramon Costi. "A security-aware routing approach for networks-on-chip." Pontif?cia Universidade Cat?lica do Rio Grande do Sul, 2017. http://tede2.pucrs.br/tede2/handle/tede/7431.
Full textAbstract:
Submitted by Caroline Xavier (caroline.xavier@pucrs.br) on 2017-06-30T13:50:31Z
No. of bitstreams: 1
DIS_RAMON_COSTI_FERNANDES_COMPLETO.pdf: 4552821 bytes, checksum: 31f78eb686d2c3126cf0abf4584de386 (MD5)Made available in DSpace on 2017-06-30T13:50:31Z (GMT). No. of bitstreams: 1 DIS_RAMON_COSTI_FERNANDES_COMPLETO.pdf: 4552821 bytes, checksum: 31f78eb686d2c3126cf0abf4584de386 (MD5) Previous issue date: 2017-03-13
A pr?xima gera??o de sistemas multiprocessados intra-chip, do ingl?s MultiProcessor Systems-on-Chip (MPSoC), comportar? centenas de elementos de processamento num ?nico chip, com a promessa de alta vaz?o de comunica??o, baixa lat?ncia e, preferencialmente, baixo consumo de energia. Devido ? elevada demanda de comunica??o paralela de aplica??es para MPSoCs, a rede intra-chip, do ingl?s Network-on-Chip (NoC), tem sido amplamente adotada como um meio de comunica??o confi?vel e escal?vel para MPSoCs. O espa?o de projeto para NoCs deve ser explorado para atender ? demanda das aplica??es atuais. Dentre os par?metros que definem uma NoC, o algoritmo de roteamento tem sido utilizado para prover servi?os como toler?ncia ? falhas, liberdade de deadlocks e de livelocks, assim como Quality of Service (QoS). Conforme a ado??o e complexidade de Systems-on-Chip (SoC) aumenta para sistemas embarcados, a preocupa??o com a prote??o de dados tamb?m torna-se um requisito para o projeto de MPSoCs. Atualmente, MPSoCs podem ser atacados explorando vulnerabilidades em hardware ou software, sendo o ?ltimo respons?vel por 80% dos incidentes de seguran?a em sistemas embarcados. A prote??o contra vulnerabilidades de software pode acontecer em: (i) N?vel de Aplica??o, utilizando t?cnicas como a criptografia, para evitar a transmiss?o de dados desprotegidos entre os elementos de um MPSoC, conhecidos como m?dulos de propriedade intelectual, do ingl?s Intellectual Property (IP); ou (ii) N?vel de Comunica??o, inspecionando ou filtrando elementos na arquitetura de interconex?o atrav?s de monitores de comunica??o ou firewalls, respectivamente. Portanto, um algoritmo de roteamento, ciente dos requisitos de seguran?a do sistema, deve oferecer prote??o ao utilizar rotas confi?veis na NoC, evitando elementos potencialmente maliciosos em rotas porventura inseguras. A principal contribui??o deste trabalho ? uma t?cnica de prote??o para NoCs que atua em n?vel de comunica??o, adaptando os algoritmos Segment-based Routing (SBR) e Region-based Routing (RBR) para que estes considerem aspectos de seguran?a do sistema, estes caracterizados por zonas de seguran?a definidas na NoC de acordo com o mapeamento de aplica??es nos IPs. A avalia??o da t?cnica de roteamento considera aspectos como a escalabilidade das tabelas de roteamento, a quantidade de rotas seguras definidas entre os IPs, e o impacto desta t?cnica de roteamento em aplica??es do benchmark NASA Numerical Aerodynamic Simulation (NAS) Parallel Bencharm (NPB).
The next generation of MultiProcessor Systems-on-Chip (MPSoC) will encompass hundreds of integrated processing elements into a single chip, with the promise of highthroughput, low latency and, preferably, low energy utilization. Due to the high communication parallelism required by several applications targeting MPSoC architectures, the Network-on-Chip (NoC) has been widely adopted as a reliable and scalable interconnection mechanism. The NoC design space should be explored to meet the demanding requirements of current applications. Among the parameters that define a NoC configuration, the routing algorithm has been employed to provide services such as fault tolerance, deadlock and livelock freedom, as well as Quality of Service (QoS). As the adoption and complexity of System-on-Chip (SoC) increases for embedded systems, the concern for data protection appears as a new design requirement. Currently, MPSoCs can be attacked by exploiting either hardware or software vulnerabilities, with the later responsible for 80% of the security incidents in embedded systems. Protection against software vulnerabilities can occur at (i) Application Level, by using techniques such as data encryption to avoid plain data transmissions between Intellectual Property (IP) modules; or (ii) Communication Level, inspecting or filtering elements at the interconnect fabric with communication monitors or firewalls, respectively. As such, a routing algorithm aware of security requirements could also offer protection utilizing trusted communication paths in the NoC, avoiding potential malicious elements in otherwise unsafe communication paths. The main contribution of this work is a NoC protection technique at communication level by adapting Segment-based Routing (SBR) and Region-based Routing (RBR) algorithms to consider system security requirements, characterized by security zones which are defined on the NoC according to the mapping of applications on IP modules. Evaluation of the proposed routing technique considers aspects such as the scalability of routing tables, the number of secure communication paths, and the impact of this technique on applications of the NASA Numerical Aerodynamic Simulation (NAS) Parallel Benchmark (NPB).
26
Chen, Yiling. "EXPERIMENTAL AND COMPUTATIONAL EVIDENCE FOR REDUCTION MECHANISMS OF N–O CONTAINING COMPOUNDS(NOCs) BY AQUEOUS FeII–TIRON COMPLEX." Diss., Temple University Libraries, 2016. http://cdm16002.contentdm.oclc.org/cdm/ref/collection/p245801coll10/id/421631.
Full textAbstract:
Environmental EngineeringPh.D.
The nitrogen–oxygen single bond (>N–O–) is commonly found in organic contaminants ranging from aromatic N–oxides (ANOs), oximes, isoxazoles, to hydroxylamines. The introduction of N–O containing contaminants (NOCs) such as pesticides, pharmaceuticals, and reaction intermediates into aquatic environments is arguably an important emerging water issue. Soluble FeII and natural organic ligands, commonly co-existing in reducing environments, have been found to quickly reduce a number of organic contaminants in anoxic aqueous solution due to their low reduction potentials and high redox reactivity. The major objective of this research was to understand the reduction kinetics and mechanisms of various NOCs by FeII–tiron complex, a highly reactive, homogenous model environmental reductant. Experimental results show that various NOCs were reduced by FeII–tiron complex at different rates. The 1:2 FeII–tiron complex, FeL26-, is the dominant reactive species because its concentration highly correlated with the observed NOC reactivity. Depending on the structure, NOCs may undergo different reaction pathways, and the rate-limiting steps can be protonation, complexation, electron transfer or N–O bond cleavage. Specifically, for ANOs, three types of complexes can form between ANOs and FeII–tiron, leading to different reactivity and mechanisms: type I refers to those forming 5-membered ring complexes through the N and O atoms on the side chain; type II refers to those forming 6-membered ring complexes through the N-oxide O atom and the O atom on the side chain; and type III refers to complexation through the N-oxide O atom only. The density functional theory calculations suggested that the elementary reactions, including protonation, N–O bond cleavage, and the 2nd electron transfer processes, are barrierless, indicating that the first electron transfer is rate-limiting. Consistent with the theoretical results, the experimental solvent isotope effect, KIEH, for the reduction of quinoline N-oxide (a type III ANO) was obtained to be 1.072 ± 0.025, suggesting protonation was not involved in the rate-limiting step. The measured nitrogen kinetic isotope effect, KIEN, for the reduction of pyridine N-oxide (a type III ANO) (1.022 ± 0.006) is in good agreement with the calculated KIEN for its first electron transfer (1.011 ~ 1.028), confirming that the first electron transfer is rate-limiting. Electrochemical cell experiments demonstrated that the electron transfer process can be facilitated significantly by type I complexation with FeL26-, to some extent by type II complexation with free FeII, but not by weak type III complexation. Reduction products of several ANOs were identified by HPLC and LC-QToF-MS to be the deoxygenated analogs. Similar to ANOs, reduction products of various substituted isoxazoles (ISXs) were identified by HPLC/QToF-MS to be the ring-cleavage analogs. The density functional theory calculations suggested that the elementary protonation processes are barrierless, while the N–O bond cleavage processes have small energy barriers, suggesting they are not the rate-limiting step. The experimental iron kinetic isotope effects, KIEFe, for the reduction of 3-amino-5-methylisoxazole (AMX) and 3,5-dimethylisoxazole (DMX) were obtained to be 1.0076 ± 0.0049 and 1.0075 ± 0.0018. Both numbers revealed that FeII participated in the rate-limiting step, demonstrating that the electron transfer step is rate-limiting. Meanwhile, KIEH for the reduction of AMX was obtained to be 1.992 ± 0.068, indicating that proton is involved in the rate-limiting step, while that for DMX was 1.209 ± 0.079, suggesting no protonation is involved in the rate-limiting step. Thus, the reduction of AMX and DMX undergoes different pathways. Ring complexes formed between ISXs and FeII–tiron species can be categorized into three types: type I complex forms through 3-N and ring-O; type II complex forms through 5-N/O and ring-N; and type III complex forms through 6-O and ring-N. However, complexation only occured after ring cleavage due to the lower energies calculated for the ring-opened complexes. Electrochemical cell experiments revealed that the electron transfer process can be facilitated by various types of complexation at different levels. The kobs of type I or II ISXs increased a few times as [FeII] increased significantly in the cathodic cell, suggesting that the reduction can be accelerated by either type I or II complexation with free FeII to some extent. Meanwhile, the significantly higher kobs of ISXs in the batch experiments than that in the cell experiments indicated that type I and type II-N complexation with FeL26- can strongly facilitate ISX degradation. Based on these findings, future work will rely on both experimental and computational approaches to examine the reduction kinetics and mechanisms of other categories of NOCs. Upon successfully elucidating the rate-limiting step for each group of NOC, various molecular descriptors will be examined to develop QSARs as predictive tools for reducing activity of other structurally-related NOCs. Overall, this project has provided a wealth of new mechanistic information on the transformation of NOCs in model aquatic environments, which will enable researchers and regulatory agencies to develop environmental fate simulators to accurately assess their fate in and possible risks to water supply and environmental systems.
Temple University--Theses
27
Concatto, Caroline Martins. "Coping with permanent faults in NoCs by using adaptive strategies based on router design-level and routing algorithm-level." reponame:Biblioteca Digital de Teses e Dissertações da UFRGS, 2009. http://hdl.handle.net/10183/76242.
Full textAbstract:
Hoje em dia, as redes intra chip (NoC) são cada vez mais utilizadas como uma arquitetura de comunicação alternativa para sistemas complexos, pois estas permitem flexibilidade e desempenho da comunicação. Porém, o grande número de interconexões da rede, aliado à diminuição das dimensões dos transistores fabricados nas tecnologias nanométricas, fazem com que a NoC possa ter um grande número de falhas durante sua fabricação, ou por desgaste durante sua vida útil. Sabe-se que, em futuras tecnologias os circuitos integrados terão uma taxa de falhas permanentes de 20 a 30%. Entretanto, mesmo na presença de falhas, é desejável que a NoC permaneça funcionando corretamente. A partir do diagnóstico das falhas, a NoC deve ser capaz de buscar alternativas para manter a comunicação entre os núcleos, evitando os canais e os roteadores com falhas. O objetivo deste trabalho é propor mecanismos adaptativos de proteção contra falhas permanentes. Mesmo quando são adicionados componentes extras para a substituição em SoCs, a ocorrência de falhas permanentes na rede intrachip impede a substituição ou reparo de um componente no sistema intrachip. Portanto a tolerância a falhas na NoC será crucial para reduzir custo de manufatura, e aumentar o rendimento e o tempo de vida do circuito integrado. O mecanismo proposto é capaz de evitar falhas sabendo anteriormente, na fase de teste e diagnóstico, a localização especifica da falha. Portanto, as técnicas se adaptam em cada roteador para evitar as falhas permanentes, sempre buscando manter desempenho, aumentar o rendimento e a confiabilidade do sistema.Nowadays, networks-on-chip (NoCs) have been used as an alternative communication architecture inside complex system on-chip. They offer better scalability and performance than the traditional bus. However, the growing number of interconnects that have to be inserted using smaller transistors means that NoCs have a growing number of faults, either from manufacturing or due to aging. In future systems-on-chip (SoCs), the fault rate will be around 20 to 30% of the contact and transistors of integrated circuits. Therefore, even in the presence of a fault, it is still desirable that NoCs properly work. The main idea of this work is to implement adaptive mechanisms to protect NoCs against permanent faults. The main advantage of such mechanism is to manage failures based on data from the testing and diagnosing phase. The mechanisms are adapted in each router in order to sustain performance, increasing the system yield and reliability even in the presence of failures. Even if one adds extra blocks for replacement, the occurrence of permanent faults in a NoC might preclude the replacement or repair of a faulty component within the SoC. In such case, fault-tolerant NoCs are able to reduce manufacturing costs, increase yield and the lifetime of the chip.
28
Semykoz, Mariia M. "The "Neo‐Oligarchical" Ownership Regime in Putin's Russia: Implications for Oil Sector." Miami University / OhioLINK, 2012. http://rave.ohiolink.edu/etdc/view?acc_num=miami1343060056.
Full text
29
Ibrahim, Hatem Musbah. "Performance Modelling and Evaluation of Network On Chip Under Bursty Traffic. Performance evaluation of communication networks using analytical and simulation models in NOCs with Fat tree topology under Bursty Traffic with virtual channels." Thesis, University of Bradford, 2014. http://hdl.handle.net/10454/7826.
Full textAbstract:
Physical constrains of integrated circuits (commonly called chip) in regards to size and finite number of wires, has made the design of System-on-Chip (SoC) more interesting to study in terms of finding better solutions for the complexity of the chip-interconnections. The SoC has hundreds of Processing Elements (PEs), and a single shared bus can no longer be acceptable due to poor scalability with the system size. Networks on Chip (NoC) have been proposed as a solution to mitigate complex on-chip communication problems for complex SoCs. They consists of computational resources in the form of PE cores and switching nodes which allow PEs to communicate with each other. In the design and development of Networks on Chip, performance modelling and analysis has great theoretical and practical importance. This research is devoted to developing efficient and cost-effective analytical tools for the performance analysis and enhancement of NoCs with m-port n-tree topology under bursty traffic. Recent measurement studies have strongly verified that the traffic generated by many real-world applications in communication networks exhibits bursty and self-similar properties in nature and the message destinations are uniformly distributed. NoC's performance is generally affected by different traffic patterns generated by the processing elements. As the first step in the research, a new analytical model is developed to capture the burstiness and self-similarity characteristics of the traffic within NoCs through the use of Markov Modulated Poisson Process. The performance results of the developed model highlight the importance of accurate traffic modelling in the study and performance evaluation of NoCs. Having developed an efficient analytical tool to capture the traffic behaviour with a higher accuracy, in the next step, the research focuses on the effect of topology on the performance of NoCs. Many important challenges still remain as vulnerabilities within the design of NoCs with topology being the most important. Therefore a new analytical model is developed to investigate the performance of NoCs with the m-port n-tree topology under bursty traffic. Even though it is broadly proved in practice that fat-tree topology and its varieties result in lower latency, higher throughput and bandwidth, still most studies on NoCs adopt Mesh, Torus and Spidergon topologies. The results gained from the developed model and advanced simulation experiments significantly show the effect of fat-tree topology in reducing latency and increasing the throughput of NoCs. In order to obtain deeper understanding of NoCs performance attributes and for further improvement, in the final stage of the research, the developed analytical model was extended to consider the use of virtual channels within the architecture of NoCs. Extensive simulation experiments were carried out which show satisfactory improvements in the throughput of NoCs with fat-tree topology and VCs under bursty traffic. The analytical results and those obtained from extensive simulation experiments have shown a good degree of accuracy for predicting the network performance under different design alternatives and various traffic conditions.
30
Lundin, Mattias. "Students’ participation in the realization of school science activities." Doctoral thesis, Linköpings universitet, Institutionen för samhälls- och välfärdsstudier, 2007. http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-8772.
Full textAbstract:
I denna avhandling visar jag hur elever och lärare genomför NO-verksamhet i grundskolan. Avhandlingen illustrerar hur elevers frågor och uttryckta erfarenheter blir en del av ett etablerat ämnesinnehåll. Syftet med studien är att skapa förståelse för hur två agendor – varav den ena baseras på elevers deltagande och den andra baseras på ett etablerat ämnesinnehåll – orkestreras så att båda agendorna tillgodoses vid genomförandet av NO-verksamheten. Studien bygger på videoobservationer under NOlektioner i skolår 5-9. Analysen visar hur olika aktiviteter i genomförandet av ett NOprojekt orkestrerar elevers frågor och uttryckta erfarenheter med ett naturvetenskapligt innehåll. Analysen visar också hur naturvetenskapens karaktär, the Nature of Science (NOS), kommuniceras som följemening till instruktioner. Vidare illustrerar avhandlingen olika sätt att använda frågor för att överbrygga vetenskapliga och vardagliga sätt att kommunicera. Resultaten visar också olika roller som elevers erfarenheter antar i en NOverksamhet. Resultaten utgör en konkretisering av skolans naturvetenskap, the Nature of School Science (NOSS). Skolans naturvetenskapliga aktiviteter begripliggörs lämpligen om de betraktas utifrån sina egna syften och förutsättningar. I avhandlingen utvecklas begreppet NOSS för att lyfta fram sådana syften och förutsättningar såsom dessa framträder i aktiviteten.This thesis investigates and considers how students and teachers realize school science activities. Students’ questions and accounts of their experiences as they become part of an established science content form the focus of this work. Its purpose is to provide an understanding of how two agendas –one, based on students’ participation and the other, based on the already established science content –are orchestrated so that both are accounted for. The empirical work is based on video-recorded observations in science classrooms. The findings show how different activities in the accomplishment of a school science project orchestrate students’ questions and accounts of experiences with the science content. The findings also show how the nature of science (NOS) is communicated as a by-product of instruction. In addition, different uses of questions for bridging science and everyday ways of communicating are shown in the results. The findings also indicate the different roles that students’ experiences acquire in a school science activity. These results should be seen as a step towards a definition of the nature of school science (NOSS). School science activities become intelligible if we consider them from a basis of their own purposes and prerequisites. The concept of NOSS is described to elicit such purposes and prerequisites as they become apparent in the activity.
31
Da, penha coelho Alexandre Augusto. "Tolérance aux fautes et fiabilité pour les réseaux sur puce 3D partiellement connectés." Thesis, Université Grenoble Alpes (ComUE), 2019. http://www.theses.fr/2019GREAT054.
Full textAbstract:
Le paradigme de réseaux sur puce (NoC), basé sur un mécanisme modulaire de commutation par paquets, peut répondre à de nombreux défis de communication sur puce tels que la complexité du câblage, la latence des communications et la bande passante. De plus, les avantages combinés des circuits intégrés 3D et des NoCs offrent la possibilité de concevoir un système haute performance dans une zone limitée de la puce. Les NoCs 3D souffrent de certains problèmes de fiabilité tels que la variabilité des processus de fabrication 3D-IC. En particulier, le faible rendement de la connexion verticale a un impact significatif sur la conception des piles de matrices tridimensionnelles avec un grand nombre de TSV. De même, les progrès des technologies de fabrication de circuits intégrés entraînent une augmentation potentielle de leur sensibilité aux effets des rayonnements présents dans l'environnement dans lequel ils vont fonctionner. En fait, le nombre croissant de défaillances transitoires est devenu, au cours des dernières années, une préoccupation majeure dans la conception des systèmes de contrôle critiques. Par conséquent, l'évaluation de la sensibilité des circuits et des applications aux événements causés par les particules énergétiques présentes dans l'environnement réel est une préoccupation majeure à laquelle il faut répondre. Cette thèse présente donc des contributions dans deux domaines importants de la recherche sur la fiabilité : dans la conception et la mise en œuvre de schémas de routage à tolérance de pannes sans blocage pour les réseaux sur puce tridimensionnels émergents ; et dans la conception de cadres d'injection de défauts capables d'émuler des défauts transitoires simples et multiples dans les circuits basés sur HDL. La première partie de cette thèse aborde les problèmes des défauts transitoires et permanents dans l'architecture des NoCs 3D et présente une nouvelle unité de calcul de routage résiliente ainsi qu'un nouveau schéma de routage tolérant aux défauts d'exécution. Un nouveau mécanisme résilient est introduit afin de tolérer les défauts transitoires se produisant dans l'unité de calcul de route (RCU), qui est l'élément logique le plus important dans les routeurs NoC. En combinant un circuit de détection de défauts fiable à double échantillonnage au niveau du circuit et un mécanisme de réacheminement économique, nous développons une solution complète de tolérance aux fautes qui peut détecter et corriger efficacement ces erreurs fatales avant que les paquets affectés ne quittent le routeur. Pourtant, dans la première partie de cette thèse, un nouveau schéma de routage à tolérance de pannes pour les réseaux 3D sur puce à connexion verticale partielle appelé FL-RuNS est présenté. Grâce à une distribution asymétrique des canaux virtuels, FL-RuNS peut garantir une distribution de paquets à 100% sous un ensemble non contraint de temps d'exécution et de pannes permanentes des liaisons verticales. Dans le but d'émuler les effets du rayonnement sur les nouvelles conceptions de SoCs, la deuxième partie de cette thèse aborde les méthodologies d'injection de fautes en introduisant deux outils appelés NETFI-2 et NoCFI. NETFI-2 est une méthodologie d'injection de fautes capable d'émuler des défauts transitoires tels que SEU et SET dans un circuit HDL. Des expériences approfondies réalisées sur deux études de cas attrayantes sont présentées pour démontrer les caractéristiques et les avantages de NETFI-2. Enfin, dans la dernière partie de ce travail, nous présentons NoCFI comme une nouvelle méthodologie pour injecter des défauts multiples tels que les MBU et SEMT dans une architecture de réseaux sur puce. NoCFI combine ASIC-design-flow, afin d'extraire les informations de layout, et FPGA-design-flow pour émuler plusieurs défauts transitoiresNetworks-on-Chip (NoC) have emerged as a viable solution for the communication challenges in highly complex Systems-on-Chip (SoC). The NoC architecture paradigm, based on a modular packet-switched mechanism, can address many of the on-chip communication challenges such as wiring complexity, communication latency, and bandwidth. Furthermore, the combined benefits of 3D IC and Networks-on-Chip (NoC) schemes provide the possibility of designing a high-performance system in a limited chip area. The major advantages of Three-Dimensional Networks-on-Chip (3D-NoCs) are a considerable reduction in the average wire length and wire delay, resulting in lower power consumption and higher performance. However, 3D-NoCs suffer from some reliability issues such as the process variability of 3D-IC manufacturing. In particular, the low yield of vertical connection significantly impacts the design of three-dimensional die stacks with a large number of Through Silicon Via (TSV). Equally concerning, advances in integrated circuit manufacturing technologies are resulting in a potential increase in their sensitivity to the effects of radiation present in the environment in which they will operate. In fact, the increasing number of transient faults has become, in recent years, a major concern in the design of critical SoC. As a result, the evaluation of the sensitivity of circuits and applications to events caused by energetic particles present in the real environment is a major concern that needs to be addressed. So, this thesis presents contributions in two important areas of reliability research: in the design and implementation of deadlock-free fault-tolerant routing schemes for the emerging three-dimensional Networks-on-Chips; and in the design of fault injection frameworks able to emulate single and multiple transient faults in the HDL-based circuits. The first part of this thesis addresses the issues of transient and permanent faults in the architecture of 3D-NoCs and introduces a new resilient routing computation unit as well as a new runtime fault-tolerant routing scheme. A novel resilient mechanism is introduced in order to tolerate transient faults occurring in the route computation unit (RCU), which is the most important logical element in NoC routers. Failures in the RCU can provoke misrouting, which may lead to severe effects such as deadlocks or packet loss, corrupting the operation of the entire chip. By combining a reliable fault detection circuit leveraging circuit-level double-sampling, with a cost-effective rerouting mechanism, we develop a full fault-tolerance solution that can efficiently detect and correct such fatal errors before the affected packets leave the router. Yet in the first part of this thesis, a novel fault-tolerant routing scheme for vertically-partially-connected 3D Networks-on-Chip called FL-RuNS is presented. Thanks to an asymmetric distribution of virtual channels, FL-RuNS can guarantee 100% packet delivery under an unconstrained set of runtime and permanent vertical link failures. With the aim to emulate the radiation effects on new SoCs designs, the second part of this thesis addresses the fault injection methodologies by introducing two frameworks named NETFI-2 (Netlist Fault Injection) and NoCFI (Networks-on-Chip Fault Injection). NETFI-2 is a fault injection methodology able to emulate transient faults such as Single Event Upsets (SEU) and Single Event Transient (SET) in a HDL-based (Hardware Description Language) design. Extensive experiments performed on two appealing case studies are presented to demonstrate NETFI-2 features and advantage. Finally, in the last part of this work, we present NoCFI as a novel methodology to inject multiple faults such as MBUs and SEMT in a Networks-on-Chip architecture. NoCFI combines ASIC-design-flow, in order to extract layout information, and FPGA-design-flow to emulate multiple transient faults
32
Housted, Friederike W. "Stednavne af slavisk oprindelse på Lolland, Falster og Møn /." Kobenhavn : C. A. Reitzels, 1994. http://catalogue.bnf.fr/ark:/12148/cb357422004.
Full text
33
Bessat, Hubert Germi Claudette. "Les noms du patrimoine alpin /." Grenoble : ELLUG, Université Stendahl, 2004. http://catalogue.bnf.fr/ark:/12148/cb39205825q.
Full text
34
Naud, Elisabeth. "Le fragment comme théâtralité : le fragment, cet arlequin du langage nous séduit, nous étonne et nous charme, mais disparaît à nos yeux quand il enlève son masque." Paris 8, 1999. http://www.theses.fr/1999PA081711.
Full textAbstract:
Le phenomene de fragmentation qui s'est de plus en plus repandu tout au long du 20eme siecle dans le domaine des arts, semble difficilement compatible avec une des fonctions principales du theatre a savoir : celle de la communication sociale pour les sujets de culture et de moeurs. Il s'avere en effet que celle-ci est par ce mode d'expression tres menacee en cette fin de siecle. Aussi apparait-ilnecessaire d'elucider plus en profondeur la nature de l'expression fragmentaire au theatre et ses rapports avec la theatralite, soit "le fragment comme theatralite". Nous avons opte pour une approche phenomenologique de ce qui au depart etait assez flou, a savoir la notion de fragment et celle de theatralite, cela sans nous attacher au domaine exclusif du theatre mais a celui de la vie en generalet des arts en particulier. Notre reflexion se developpe en trois parties : phenomenologie de la fragmentation et de la theatralite, modernite espace de rencontre , vivre la mort de dieu. Dans ces trois parties, en nous appuyant sur l'esthetique englobante de f. Nietzsche, nous avons tente de theoriser l'espace theatral, d'en montrer la genese et le fonctionnement. L'evolution de l'espace tragiquenous a permis de constater que la mimesis est la creation de la conscience imageante et que le fragment n'est pas un phenomene propre et exclusif a/de de la periode contemporaine, mais le signe persistant de notre avancee chancelante au coeur de la mort de dieu.
35
Iglesias, Hector. "Noms de lieux et de personnes à Bayonne, Anglet et Biarritz au XVIIIe siècle : origine, signification, localisation, proportion et fréquence des noms recensés /." Bayonne : Elkarlanean, 2000. http://catalogue.bnf.fr/ark:/12148/cb371937888.
Full textAbstract:
Texte remanié de: Th. doct.--Université Michel de Montaigne--Bordeaux 3, 2000. Titre de soutenance : Onomastique du secteur littoral de Bayonne-Anglet-Biarritz au XVIIIe siècle.Bibliogr. p. 339-365. Notes bibliogr. Glossaire. Index.
36
Maʻani, Sultan al. "Nordjordanische Ortsnamen : Eine etymologische und semantische Untersuchung /." Hildesheim : G. Olms, 1992. http://catalogue.bnf.fr/ark:/12148/cb39277103d.
Full text
37
Gervais, Mathieu. "« Nous on se sauve nous-mêmes… ». Sécularisation et identité paysanne en France de 1940 à nos jours : le cas de l’agriculture paysanne." Thesis, Paris, EPHE, 2015. http://www.theses.fr/2015EPHE5053.
Full textAbstract:
Quelle place occupe la religion dans l'engagement des agriculteurs-paysans français, soucieux de la nature ? Pour répondre à cette question, nous déployons une approche sociologique historicisée de la construction d'une identité paysanne militante depuis la fin des années 1940. À partir de la philosophie de Jacques Maritain, une pensée nouvelle de la modernité infuse le mouvement paysan via l'Action catholique. Contre le traditionalisme s'élabore une personnalisation de l’engagement chrétien et paysan, moteur de la modernisation des campagnes dans une mise à distance d'un ordre naturel, politique et social lié au catholicisme. Plus tard, sous l’influence majeure d’un marxisme diffusé et retravaillé par des traducteurs chrétiens, une partie des agriculteurs progressistes radicalise ses analyses politiques et se rapproche de nouvelles luttes et de nouveaux acteurs sociaux tels que l’écologie. Dans ce rapprochement, les institutions religieuses et le discours qu’elles entretiennent sur la nature se trouvent mis à distance. Toutefois, les conceptions politiques, sociales et économiques embrassées – conceptualisées dans l’agriculture-paysanne – conservent la trace d’un héritage religieux de plus en plus éthicisé. Cette éthique prend comme objet central le respect de la vie, et légitime des pratiques agricoles alternatives selon le primat du spirituel contre l'anomie moderne. Autour de ce thème se fédèrent des profils variés, enfants d'agriculteurs et néoruraux, catholiques, agnostiques et adeptes de spiritualités diversesWhat part does religion play in the practices of farmers concerned about the environment? To answer this question, we shall employ a sociological yet historical approach to the building of an activist peasant identity since the end of the 1940s. At the time, based on the philosophical perspective developed by Jacques Maritain, a new understanding of modernity influenced the peasant movement via the Catholic Action. In reaction to traditionalism, this approach soon gave way to a more personal and individual conception of peasant and Christian activism, providing a new impetus for the modernisation of rural areas while marginalizing the natural, political and social order inherited from Catholicism. Later, under the significant influence of a revised version of Marxism spread by Christian translators, some progressive farmers radicalised their political analyses and showed a growing interest in new battles and new social operators such as ecology. As a consequence, this new interest edged out religious institutions and their positions about nature. Yet, today, the intertwined political, social and economic conceptions–conceptualised all together in peasant-farming–still retain the mark of a religious heritage in an increasingly ethical way. This ethical stance considers the right to life a core value, and finds legitimacy in alternative farming approaches on the basis of the prevalence of spirituality over modern anomie. This topic brings together people from various horizons, such as farmers’ children, neo-rural individuals, Catholics, agnostics and spiritually diverse people
38
Elitzur, Yoel. "Ancient place names in the Holy Land preservation and history /." Jerusalem : Winona Lake, Indiana : the Hebrew University Magnes Press ; Eisenbrauns, 2004. http://catalogue.bnf.fr/ark:/12148/cb39200608c.
Full textAbstract:
Basé sur la thèse (Ph.D.) de l'auteur (Universiṭah ha-ʻIvrit bi-Yerushalayim, 1993), dont le titre est : Shemot meḳomot ʻatiḳim she-nishtamru befi ha-ʻArvim ba-arets.Bibliogr. p. [388]-409. Index.
39
Ansari, Amir. "Analyse contrastive des mots persans et français." Paris 3, 2000. http://www.theses.fr/2000PA030092.
Full textAbstract:
La problematique centrale de ce travail repose sur l'applicabilite du cadre theorique de la grammaire homologique a la langue persane. Cette grammaire propose un modele qui s'applique aussi bien aux unites des strates du plan de l'expression (la phonematique et la graphematique) qu'a celles des strates du plan du contenu (la morphematique et la lexematique). L'opposition x-on/x-eme, fondamentale dans ce modele, se rencontre aussi en persan dans les strates qui traitent du mot ecrit et de ses composants, a savoir graphematique, morphematique et lexematique. La notion de marquage, entendue dans cette grammaire comme tout ecart de l'unite de ces strates par rapport au fonctionnement basique n'est pas etrangere au persan. La demarche adoptee comprend deux analyses : la premiere, distributionnelle, consiste a isoler les unites generiques de chaque strate (les x), la seconde, fonctionnelle, s'interesse a la valeur des unites ainsi isolees. La mise en parallele de la graphemique de nos deux langues montre que le persan est une langue a dominante phonogrammique, alors que le francais demeure phono-morpholexogrammique. L'observation de l'ensemble du corpus montre que ce sont uniquement lesmots-bases verbaux qui sont sujets aux modifications formelles (cf. L'alternance, la suppletion et l'effacement). En revanche, la forme des mots-bases substantivaux et adjectivaux demeure en l'etat dans leurs derives respectifs. Le morphe affixal n'est que rarement affecte dans sa forme. L'economie des mots s'eclaire d'un jour different selon la perspective adoptee. Le persan, tout comme le francais, connait des mots consideres en synchronie comme des mots simples, mais qui sont diachroniquement des mots construits. Le mecanisme qui a assure leur construction n'est plus actuellement percu.
40
Ernst, Peter. "Die althochdeutschen Siedlungsnamentypen in Niederösterreich und Wien /." Wien : VWGÖ, 1989. http://catalogue.bnf.fr/ark:/12148/cb355185938.
Full text
41
Lenschow, Sabine. "Die Funktion und Verwendung der Propria in der mittelhochdeutschen Dietrich-Epik /." Hildesheim ; Zürich ; New York : G. Olms, 1996. http://catalogue.bnf.fr/ark:/12148/cb37321013v.
Full text
42
Chareille, Pascal. "Genèse médiévale de l'anthroponymie moderne. histoire et statistiques : quelles méthodes quantitatives pour une étude de l'anthroponymie médiévale ? /." Tours : Université de Tours, 2008. http://catalogue.bnf.fr/ark:/12148/cb41400299r.
Full textAbstract:
Texte remanié de: Thèse de doctorat--Histoire--Paris 1, 2003. Titre de soutenance : Le nom : histoire et statistiques : quelles méthodes quantitatives pour une étude de l'anthroponymie médiévale ?Avant-titre : "Études d'anthroponymie médiévale" Bibliogr. p. 223-296. Notes bibliogr. Préface en anglais.
43
Nitschke, Claudia. "Die novgoroder Namenlandschaft zu Beginn des 17. Jahrhunderts /." München : O. Sagner, 2006. http://catalogue.bnf.fr/ark:/12148/cb40946692f.
Full text
44
Beauseroy, Delphine. "Syntaxe et sémantique des noms abstraits : des propriétés verbales et adjectivales aux propriétés nominales." Thesis, Nancy 2, 2009. http://www.theses.fr/2009NAN21016/document.
Full textAbstract:
Le but de ce travail est d'examiner les propriétés sémantiques et morphosyntaxiques des noms abstraits apparentés à des prédicats verbaux ou adjectivaux. D’un point de vue sémantique, nous montrons que la notion d’aspect, généralement réservée au domaine verbal, est pertinente dans le domaine nominal et que les 'noms abstraits intensifs' (Van de Velde 1995 et Flaux & Van de Velde 2000) forment une classe aspectuelle homogène puisque tous partagent le trait [-DYNAMIQUE]. En nous fondant sur l'hypothèse que le caractère statif commun à ces noms permet une analyse unifiée, nous proposons une étude de leurs différents emplois et montrons notamment qu’outre une acception stative, ces noms peuvent avoir une seconde lecture et dénotent alors des occurrences. Dans la seconde partie, nous nous intéressons au comportement syntaxique des noms statifs, i.e. le nombre et la détermination, mais aussi la modification adjectivale. Ceci nous permet de dégager deux comportements morphosyntaxiques distincts, corrélés à la distinction entre les deux lectures mise en évidence dans la première partie. Dans leur lecture stative, ces noms ont un comportement proche de celui des noms massifs concrets et fonctionnent comme des noms relationnels : ils nécessitent un argument avec lequel ils entrent dans une relation syntaxique de prédication. Inversement, dans leur lecture d’occurrence, ces noms se comportent comme des noms comptables concrets et ne sont pas intrinsèquement relationnels. L’analyse des noms statifs que nous proposons tend à montrer que ceux-ci partagent leurs propriétés sémantiques avec certains types de prédicats verbaux et adjectivaux, et leurs propriétés syntaxiques avec diverses classes de noms concretsThe aim of this thesis is to examine the morphosyntactic and semantic properties of abstract nouns related to verbal and adjectival predicates. Since the nouns we examine are linked to verbal and adjectival predicates, the first part focuses on the question of aspectual properties in the nominal domain. We show that 'intensive abstract nouns' (Van de Velde 1995 and Flaux & Van de Velde 2000) constitute a unified aspectual class characterized by the feature [-DYNAMIC]. From the assumption that the stative feature common to these nouns allows a unified analysis, we propose a study relying on the idea that stative nouns are distinguished by their uses, and show that, in addition to a purely stative meaning, these nouns can also convey other information, in which they denote occurrences. The second part is dedicated to the syntactic behaviour of stative nouns, i.e. number and determination, but also adjectival modification. This enables us to identify two distinct morphosyntactic behaviours, that parallel the distinction between stative and occurrence understanding highlighted in the first part. On the one hand, in their property sense, these nouns have a behaviour similar to that of massive concrete nouns and qualify as relational nouns, i.e. they require an argument with which they enter into a predication relationship (at the syntactic level). On the other hand, in their occurrence sense, these nouns behave like concrete count nouns and are not inherently relational. To sum up, the analysis of stative nouns shows that they share semantic properties with certain types of verbal and adjectival predicates, as well as syntactic properties with various classes of concrete nouns
45
Du, Bouchet Julien. "Recherches sur les noms de la rue en grec ancien." Paris 10, 2004. https://hal.archives-ouvertes.fr/tel-01327974.
Full text
46
Friburger, Nathalie. "Reconnaissance automatique des noms propres : application à la classification automatique de textes journalistiques." Tours, 2002. http://www.theses.fr/2002TOUR4011.
Full textAbstract:
Dans les textes journalistiques, les noms propres sont très importants pour une compréhension précise du sens des textes, mais ils sont très peu représentés dans les ressources lexicales disponibles. Le travail réalisé ici cherche à automatiser leur extraction et leur catégorisation. Nous avons implanté le système CasSys qui permet l'utilisation de cascade de transducteurs et peut ainsi réaliser de l'analyse syntaxique d'un texte ou de l'extraction d'information. Le système d'extraction de noms propres crée, extracNP, utilise casSys ; les phénomènes d'ambigui͏̈tés, de segmentation et de catégorisation des noms propres sont ainsi gérés par la cascade. Par cette méthode, nous avons obtenu une précision de 94% avec un rappel de plus de 93%. Puis, nous avons montré que les noms propres sont porteurs d'une information qui les rend particulièrement intéressants pour obtenir une classification de qualité.
47
Rohden, Jens-Uwe von. "Die Gewässernamen im Einzugsgebiet der Treene : ein Beitrag zur Ortsnamenforschung in Schleswig-Holstein /." Neumünster : K. Wachholtz, 1989. http://catalogue.bnf.fr/ark:/12148/cb35566869s.
Full text
48
Lochner, von Hüttenbach Fritz. "Die römerzeitlichen Personennamen der Steiermark : Herkunft und Auswertung /." Graz : Leykam, 1989. http://catalogue.bnf.fr/ark:/12148/cb35572640r.
Full textAbstract:
Texte remanié de: Habilitationsschrift--Philosophische Fakultät--Graz--Karl-Franzens-Universität, 1968. Titre de soutenance : Die Personennamen auf den römerzeitlichen Inschriftsteinen der Steiermark : ein Beitrag zur ostalpinen Namenkunde.
49
Di, Vito Roberto A. "Studies in third millennium Sumerian and Akkadian personal names : the designation and conception of the personal god /." Roma : Pontificio istituto biblico, 1993. http://catalogue.bnf.fr/ark:/12148/cb35587004n.
Full text
50
Brumberg-Chaumont, Julie. "Sémantiques anciennes et médiévales du nom propre." Paris, EPHE, 2004. http://www.theses.fr/2004EPHE5018.
Full textAbstract:
Nous avons cherché à éclairer le statut ambigu du nom propre dans la logique ancienne et médiévale. Celui-ci apparaît à la fois comme un modèle d’intelligibilité pour comprendre la capacité référentielle des noms et des propositions dans lesquelles ils entrent et un cas-limite pour une sémantique issue du Peri Hermeneias et de l’interprétation néoplatonicienne des « Catégories » formatée pour les termes prédicables. Notre enquête comprend donc l’analyse des noms d’individus chez Aristote (Catégories, Métaphysique, Réfutations Sophistiques et Peri Hermeneias) et Porphyre (Partie I), sa réception chez Boèce (Partie II), et l’étude de l’émergence de la catégorie nom propre dans la grammaire grecque et latine à partir de son invention stoïcienne (Partie III). Elle s’attache ensuite à suivre la résurgence de cette problématique au moment où s’esquissent les conditions d’émergence d’une philosophie du langage ordinaire, dans la grammaire spéculative et chez Abélard (Partie IV), puis la systématisation des notions alors mises en œuvres dans les sommes de logique du premier terminisme (Partie V). On constate la nécessité d’appliquer aux noms propres la définition grammaticale du propre du nom (signifier la substance et la qualité), et la sémantique triadique issue de Boèce (mot / concept-qualité signifié(e) / chose), qui assure à la fois l’explication de son imposition et sa capacité à entrer dans une proposition à titre de terme, en même temps que l’impossible isomorphisme sémantique entre tous les noms du fait de la valeur d’universalité et de prédication attachée au signifié intermédiaire (concept / qualité) fondée en sous-main sur une métaphysique de la forme communeWe have tried an understanding of the ambiguous status of proper name in ancient and medieval logic. Proper name is both a paradigm for the referential power of words and propositions and a borderline case for a semantics founded in the “Peri Hermeneias” and the neoplatonic interpretation of the “Categories”, and so shaped for predicable terms. Our research included the analysis of individual names in Aristotle (Catégories, Metaphysics, Sophistical Refutations, Peri Hermeneias) and Porphyry (Part I), its reception in Boethius (Part II), and the study of the birth of proper name as part of speech, in Greek and Latin authors, from its invention in Ancient Stoicism (Part III). We then follow the transformation of this problematics when the conditions for the appearance of a philosophy of ordinary language tend to be satisfied, in speculative grammar and Abailard (Part IV), and study the systematic ordering of the notions then created in logic soms of the first terminism (Part V). We observe the necessity for applying to proper name the grammatical definition of the proper of name (signifying the substance and the quality) and the triadic semantics of Boethius (words / concepts-quality signified / things), which garanties both the explanation of its imposition and its ability to enter a proposition as its term, and the impossibility of a semantic isomorphism of names because of the universal and predicative value of the in-between significate founded (though not explicitly) to a metaphysics of common form