Relevant bibliographies by topics / NM TECHNOLOGY NODE

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'NM TECHNOLOGY NODE'

Author: Grafiati
Published: 11 September 2023

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Journal articles on the topic "NM TECHNOLOGY NODE"

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Itani, Toshiro. "157 nm Lithography for 70 nm Technology Node." Japanese Journal of Applied Physics 41, Part 1, No. 6B (June 30, 2002): 4033–36. http://dx.doi.org/10.1143/jjap.41.4033.

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Thompson, K., J. H. Booske, Y. B. Gianchandani, and R. F. Cooper. "Electromagnetic annealing for the 100 nm technology node." IEEE Electron Device Letters 23, no. 3 (March 2002): 127–29. http://dx.doi.org/10.1109/55.988813.

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Ogawa, Yoshihiro. "Cleaning Technology for Advanced Devices beyond 20 nm Node." Solid State Phenomena 195 (December 2012): 7–12. http://dx.doi.org/10.4028/www.scientific.net/ssp.195.7.

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Several attempts have recently been made to use novel high-k dielectric materials, such as AlxOy, HfxAlyOz, HfxSiyOz, and HfxOy, to improve electrical device characteristics of advanced devices. Moreover, it is becoming increasingly important in the ULSI manufacturing process to suppress contamination by metal or particles from the wafer backside or edge. This paper reviews the wafer backside/edge control technology for suppression of metal contamination.
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SHAHIDI, GHAVAM G. "ARE WE AT THE END OF CMOS SCALING?" International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 3–8. http://dx.doi.org/10.1142/s0129156406003503.

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CMOS scaling enabled by advances in lithography has been behind the information revolution. Over the last 15 years, there has been a new CMOS technology node approximately every two years. The key feature of every node has been 2X density shrink and ~35% performance gain per technology node. At 90 nm node a number usual knobs that have enabled the scaling have approached their limits. Furthermore chip power (both active and stand-by) has been increasing rapidly, approaching air cool limit. Chip stand-by power, which was negligible a few years ago, is now about the same order of magnitude as the active power in high end microprocessors. In this talk it will be argued that because of power density limitation of 90 nm, 65 nm, and beyond nodes, performance and ability to shrink are more than ever linked, and in fact if the performance gain would significantly slow down (for the designs that operate at the existing cooling limit). It is more than ever critical to come up with technology features that will enhance the performance, at a given device leakage.
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Feudel, Thomas. "Advanced Annealing Schemes for High-Performance SOI Logic Technologies." Materials Science Forum 573-574 (March 2008): 387–400. http://dx.doi.org/10.4028/www.scientific.net/msf.573-574.387.

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We have extensively studied the impact of advanced annealing schemes for highperformance SOI logic technologies. Starting with the 130 nm technology node, we introduced spike rapid thermal annealing (sRTA). Continuous temperature reduction combined with implant scaling helped to improve transistor performance and short channel behavior. During the development of the 90 nm technology we evaluated flash lamp and laser annealing (FLA). These techniques became an essential part of the 65 nm node. At this node we also faced major challenges in terms of compatibility with new materials like SiGe as well as the need for reduction of process parameter fluctuations. Scaling will be continued with the 45 nm technology node towards a truly diffusionless process.
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Li, Zongru, Christopher Jarrett Elash, Chen Jin, Li Chen, Jiesi Xing, Zhiwu Yang, and Shuting Shi. "Comparison of Total Ionizing Dose Effects in 22-nm and 28-nm FD SOI Technologies." Electronics 11, no. 11 (June 1, 2022): 1757. http://dx.doi.org/10.3390/electronics11111757.

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Total ionizing dose (TID) effects from Co-60 gamma ray and heavy ion irradiation were studied at the 22-nm FD SOI technology node and compared with the testing results from the 28-nm FD SOI technology. Ring oscillators (RO) designed with inverters, NAND2, and NOR2 gates were used to observe the output frequency drift and current draw. Experimental results show a noticeable increased device current draw and decreases in RO frequencies where NOR2 ROs have the most degradation. As well, the functionality of a 256 kb SRAM block and shift-register chains were evaluated during C0-60 irradiation. SRAM functionality deteriorated at 325 krad(Si) of the total dosage, while the FF chains remained functional up to 1 Mrad(Si). Overall, the 22-nm FD SOI results show better resilience to TID effects compared to the 28-nm FD SOI technology node.
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Suganaga, Toshifumi. "157 nm lithography with high numerical aperture lens for the 70 nm technology node." Journal of Micro/Nanolithography, MEMS, and MOEMS 1, no. 3 (October 1, 2002): 206. http://dx.doi.org/10.1117/1.1501565.

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Allgair, John, Benjamin Bunday, Aaron Cordes, Pete Lipscomb, Milt Godwin, Victor Vartanian, Michael Bishop, Doron Arazi, and Kye-Weon Kim. "Metrology Requirements for the 32 nm Technology Node and Beyond." ECS Transactions 18, no. 1 (December 18, 2019): 151–60. http://dx.doi.org/10.1149/1.3096443.

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Wakabayashi, H., G. S. Samudra, I. J. Djomehri, H. Nayfeh, and D. A. Antoniadis. "Supply-voltage optimization for below-70-nm technology-node MOSFETs." IEEE Transactions on Semiconductor Manufacturing 15, no. 2 (May 2002): 151–56. http://dx.doi.org/10.1109/66.999586.

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Takeda, Eiji, Eiichi Murakami, Kazuyoshi Torii, Yutaka Okuyama, Eishi Ebe, Kenji Hinode, and Shin'ichiro Kimura. "Reliability issues of silicon LSIs facing 100-nm technology node." Microelectronics Reliability 42, no. 4-5 (April 2002): 493–506. http://dx.doi.org/10.1016/s0026-2714(02)00029-x.

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Dissertations / Theses on the topic "NM TECHNOLOGY NODE"

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Bansal, Anil Kumar. "CMOS scaling considerations in sub 10-nm node multiple-gate FETS." Thesis, IIT Delhi, 2019. http://eprint.iitd.ac.in:80//handle/2074/8046.

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Deng, Jie. "Device modeling and circuit performance evaluation for nanoscale devices : silicon technology beyond 45 nm node and carbon nanotube field effect transistors /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Szucs, Anna. "Diminution of the lithographic process variability for advanced technology nodes." Thesis, Université Grenoble Alpes (ComUE), 2015. http://www.theses.fr/2015GREAT129/document.

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A l’heure actuelle, la lithographie optique 193 nm arrive à ces limites de capacité en termes de résolution des motifs dans la fenêtre du procédé souhaitée pour les nœuds avancés. Des lithographies de nouvelle génération (NGL) sont à l’étude, comme la lithographie EUV (EUV). La complexité de mise en production de ces nouvelles lithographie entraine que la lithographie 193 nm continue à être exploitée pour les nœuds 28 nm et au-delà. Afin de suivre la miniaturisation le rôle des techniques alternatives comme le RET (en anglais Resolution Enhancement Technique) tels que l’OPC (Optical Proximity Correction) est devenu primordial et essentiel. Néanmoins, la complexité croissante de design et de la variabilité du procédé lithographique font qu’il est nécessaire de faire des compromis. Dans ce contexte de complexité croissante du procédé de fabrication, l’objectif de la thèse est de mettre en place une méthode de boucles de correction des facteurs de variabilité. Cela signifie une diminution de la variabilité des motifs complexes pour assurer une résolution suffisante dans la fenêtre de procédé. Ces motifs complexes sont très importants, car c’est eux qui peuvent diminuer la profondeur du champ commune (uDoF). Afin d'accomplir cette tâche, nous avons proposé et validé un enchainement qui pourra être plus tard implémenté en production. L’enchainement en question consiste en une méthodologie de détection basée sur la simulation des motifs les plus critiques étant impactés par les effets issus de la topographie du masque et du profil de la résine. En outre cette méthodologie consiste en une diminution et la compensation de ces effets, une fois que ces motifs les plus critiques sont détectés. Le résultat de l’enchaînement complété sont encourageants : une méthode qui détecte et diminue les variabilités du processus lithographique pour des nœuds de technologie de 28nm a été validée. En plus elle pourrait être adaptée pour les nœuds au-delà de 28 nm
The currently used 193 nm optical lithography reaches its limits from resolution point of view. Itis despite of the fact that various techniques have been developed to push this limit as much aspossible. Indeed new generation lithography exists such as the EUV, but are not yet reliable to beapplied in mass production. Thus in orders to maintain a robust lithographic process for theseshrunk nodes, 28 nm and beyond, the optical lithography needs to be further explored. It ispossible through alternatives techniques: e.g. the RETs (Resolution Enhancement Techniques),such as OPC (Optical Proximity Correction) and the double patterning. In addition to theresolution limits, advanced technology nodes are dealing with increasing complexity of design andsteadily increasing process variability requiring more and more compromises.In the light of this increasing complexity, this dissertation work is addressed to mitigate thelithographic process variability by the implementation of a correction (mitigation) flow exploredmainly through the capability of computational lithography. Within this frame, our main objectiveis to participate to the challenge of assuring a good imaging quality for the process windowlimiting patterns with an acceptable gain in uDoF (usable Depth of Focus).In order to accomplish this task, we proposed and validated a flow that might be laterimplemented in the production. The proposed flow consists on simulation based detectionmethodology of the most critical patterns that are impacted by effects coming from the masktopography and the resist profile. Furthermore it consists of the mitigation and the compensationof these effects, once the critical patterns are detected. The obtained results on the completedflow are encouraging: a validated method that detects the critical patterns and then mitigates thelithographic process variability been developed successfully
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Chen, Hsiu Pin, and 陳修斌. "Device-level Doping Profile Analysis for Saddle-fin Device in 30 nm DRAM Technology Node." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/u452zb.

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Shi-HaoChen and 陳仕豪. "Performance Optimization of Gate-All-Around MOSFETs by Inner Spacers at 5 nm Technology Node." Thesis, 2018. http://ndltd.ncl.edu.tw/handle/jg54wt.

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碩士
國立成功大學
奈米積體電路工程碩士學位學程
106
The evolution of semiconductor technology has been progressed since Moore’s Law proposed in 1964. Dimension scaling is always the challenge for each technology node to reduce producing cost. With the continuous scaling of devices, short-channel effects are more and more severe in limiting the performance enhancement. Multi-gate struc-tures, which enhance the gate control on short-channel effects and optimize the electri-cal characteristics, can overcome the limitation; FinFET is generally applied for ad-vanced semiconductor fabrications. However, for sub-5 nm technology node, FinFETs can not offer the enough gate control, resulting in worse short-channel effects. On the other hand, GAA MOSFETs with the superior gate control of channel electrostatic are considered as a possible extension for the following technology nodes. Nevertheless, they increase the undesirable parasitic capacitances. In this thesis, an analytical model is used to calculate the parasitic capacitances caused by GAA MOSFETs. Next, the optimization by inner spacer is presented to re-duce the additional parasitic capacitances. Such methodology helps us to ensure that the improvement is effective and feasible. Then we use Synopsys TCAD to do the process simulations. GAA MOSFETs are processed with SiGe epitaxy. Electrical characteristic comparison for the devices with and without inner spacers is discussed. 5nm technology node in ITRS roadmap is the specification we adopt in this thesis. Different spacer lengths are the main topic; the longer spacers extend the effective channel length and improve short-channel effects. Furthermore, the future design, a new integration scheme featuring bulk Si-base and cost-effective fabrication, is proposed. To overcome the drawback of GAA MOSFETs compared to FinFET: the increase of parasitic capacitances, inner spacers are adopted in fabrication. The proposed process is feasible and promising in the future based on our preliminary data.
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YADAV, PUNEET. "DESIGN AND ANALYSIS OF A LOW POWER AND HIGH PERFORMANCE 10T SRAM CELL AT 32 NM TECHNOLOGY NODE." Thesis, 2023. http://dspace.dtu.ac.in:8080/jspui/handle/repository/19835.

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Memory is known to be one of the most crucial parts of any electronic system. However, a class of memory called the cache memory is even more crucial among the type of memories since it is the one working closely in synchronization with the central processing unit. There are millions of SRAM cells inside cache memory. SRAM cells must therefore possess a few essential attributes for cache memory to be reliable, including low dynamic and static power consumption, high data stability, and low read latency. A comprehensive review of the design and analysis of SRAM cells are performed, focusing on the fundamental building block, the SRAM cell, and its critical performance parameters. The aim is to provide a concise overview of the key concepts and challenges involved in SRAM cell design, highlighting recent advancements and future directions. The review begins with an introduction to SRAM and its significance in various applications. It explores the basic structure and operation of an SRAM cell, emphasizing the importance of stability, read and write capabilities, and power consumption. The different SRAM cell topologies are discussed, along with their advantages and trade-offs. The critical design considerations of SRAM cells, including noise immunity, process variations, and leakage current. Various techniques for improving the stability of SRAM cells, such as the use of feedback and assist circuits, are examined. Moreover, the impact of scaling technologies, such as process technology nodes and transistor scaling, on SRAM cell performance is explored. Additionally, the analysis of SRAM cell performance metrics, including read and write access times, write margin, stability, and power dissipation have been studied. The influence of key parameters, such as supply voltage, transistor sizing, and load capacitance, on these metrics is discussed. Furthermore, the impact of process variations on yield and reliability is addressed, along with reliability-enhancement techniques. To successfully incorporate these qualities, a comparative analysis of different 10T and 11T SRAM cells has been performed. The performance of the conventional TG10T and 11T SRAM models are compared to the 10T SRAM to showcase enhancements obtained. TG10T SRAM cell deploys two transmission gates instead of two NMOS access vi transistors to strengthen writing ability. It also employs two additional buffer transistors so that read stability can be enhanced. The TG10T SRAM cell is proven to be more enhanced in almost every aspect but it consumes more power. The read SNM and write SNM are found to be the largest in the TG10T SRAM cell. The power dissipated by the TG10T cell (i.e., 233.69nW) is approximately two times as compared to the 10T SRAM cell (i.e., 108.65nW) and 11T SRAM cell (i.e., 88.491nW). The analysis also shows that both read and write delay is minimal in TG10T SRAM cells. The read delay is 343.3 psec and the write delay is 494 psec respectively. A 10T SRAM cell has been proposed and comparison between of different existing 10T and 11T SRAM cells has been performed. The power consumption and read-write behaviors of all the SRAM cells are studied. The power consumed by the TG10T cell (i.e., 233.69nW) is approximately two times in contrast to the 10T SRAM cell (i.e., 108.65nW) and five times when collated to the proposed 10T SRAM cell (i.e., 44.794nW). The analysis associated depicts that the read and write delay is minimum in the proposed 10T SRAM (i.e., 97.7psec & 154.3psec) respectively. All simulations are carried out using LTSPICE software operating at 0.5 Volt in 32 nm CMOS process technology. The proposed transmission gate based 10T SRAM cell consumes minimum power and has better overall read stability as compared to the other designs. The review concludes by highlighting emerging trends and challenges in SRAM cell design, including the exploration of novel device architectures, non-volatile SRAM, and low power designs for energy-efficient computing systems. It emphasizes the need for continued research and innovation to address the increasing demands for higher density, lower power consumption, and improved reliability in future SRAM cell designs. A comprehensive overview of the design and analysis of SRAM cells serves as a valuable resource for researchers, engineers, and students working in the field of digital integrated circuit design, offering insights into the current state of SRAM cell technology and potential future directions.
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"Predictive Process Design Kits for the 7 nm and 5 nm Technology Nodes." Doctoral diss., 2019. http://hdl.handle.net/2286/R.I.55687.

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abstract: Recent years have seen fin field effect transistors (finFETs) dominate modern complementary metal oxide semiconductor (CMOS) processes, [1][2], e.g., at the sub 20 nm technology nodes, as they alleviate short channel effects, provide lower leakage, and enable some continued VDD scaling. However, a realistic finFET based predictive process design kit (PDK) that supports investigation into both circuit and physical design, encompassing all aspects of digital design, for academic use has been unavailable. While the finFET based FreePDK15 was supplemented with a standard cell library, it lacked full physical verification (LVS) and parasitic extraction at the time [3][4]. Consequently, the only available sub 45 nm educational PDKs are the planar CMOS based Synopsys 32/28 nm and FreePDK45 (45 nm PDK) [5][6]. The cell libraries available for those processes are not realistic since they use large cell heights, in contrast to recent industry trends. Additionally, the SRAM rules and cells provided by these PDKs are not realistic. Because finFETs have a 3D structure, which affects transistor density, using planar libraries scaled to sub 22 nm dimensions for research is likely to give poor accuracy. Commercial libraries and PDKs, especially for advanced nodes, are often difficult to obtain for academic use, and access to the actual physical layouts is even more restricted. Furthermore, the necessary non disclosure agreements (NDAs) are un manageable for large university classes and the plethora of design rules can distract from the key points. NDAs also make it difficult for the publication of physical design as these may disclose proprietary design rules and structures. This work focuses on the development of realistic PDKs for academic use that overcome these limitations. These PDKs, developed for the N7 and N5 nodes, even before 7 nm and 5 nm processes were available in industry, are thus predictive. The predictions have been based on publications of the continually improving lithography, as well as estimates of what would be available at N7 and N5. For the most part, these assumptions have been accurate with regards to N7, except for the expectation that extreme ultraviolet (EUV) lithography would be widely available, which has turned out to be optimistic.
Dissertation/Thesis
Doctoral Dissertation Electrical Engineering 2019
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Meng-YenWu and 吳孟晏. "The Evaluation of 6T-SRAM for GAA MOSFETs and FinFETs at 7 nm and 10 nm Technology Nodes." Thesis, 2016. http://ndltd.ncl.edu.tw/handle/x699be.

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碩士
國立成功大學
微電子工程研究所
104
As the semiconductor industry continues to advance, it has encountered many physical limitations, mostly related to short-channel effects (SCEs). Below node 22, the multi-gate structure has become the solution to improve the gate controllability. In this thesis, we benchmark 6T-SRAM of GAA MOSFETs and FinFETs and present the performance of both devices. We find that GAA MOSFETs with stacking technique provide higher drive current (per pitch) than FinFETs do. However the intrinsic delay (CV/ID) property is contrary. Static random access memory (SRAM) occupies a large portion of die size and consumes most of the standby leakages. 6T-SRAM has been designed as different configurations for high density (HD), low voltage (LV) and high performance (HP). Using a calibrated compact model, we can project the SNM and writeability of the 6T-SRAM for both devices in different configurations. And the characteristics of 6T-SRAM for all combination are demonstrated. The yield estimation is also done by the calibrated macro-model. The yield estimation and the minimum cell operation voltage (Vmin) for all design combinations of SRAM are presented in this work. By adjusting the channel width of the pass-gate devices, we optimize the GAA MOSFET SRAM in LV configuration to improve Vmin. However, this method can not be used for FinFETs. Although it suffers from the area penalty, the GAA MOSFETs show the potential for SRAM design.
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Books on the topic "NM TECHNOLOGY NODE"

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Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6.

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Wang, Guilei. Investigation on Sige Selective Epitaxy for Source and Drain Engineering in 22 Nm CMOS Technology Node and Beyond. Springer Singapore Pte. Limited, 2020.

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Wang, Guilei. Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond. Springer, 2019.

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Balasinski, Artur. Design for Manufacturability: From 1d to 4D for 90 22 NM Technology Nodes. Springer New York, 2016.

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Balasinski, Artur. Design for Manufacturability: From 1D to 4D for 90–22 nm Technology Nodes. Springer, 2013.

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Balasinski, Artur. Design for Manufacturability: From 1D to 4D for 90-22 Nm Technology Nodes. Springer London, Limited, 2013.

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Book chapters on the topic "NM TECHNOLOGY NODE"

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Tomita, Hiroshi, Yuji Yamada, Hidenobu Nagashima, Norio Ishikawa, and Yumiko Taniguchi. "New FEOL Cleaning Technology for Advanced Devices beyond 45 nm Node." In Solid State Phenomena, 185–88. Stafa: Trans Tech Publications Ltd., 2007. http://dx.doi.org/10.4028/3-908451-46-9.185.

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Wang, Guilei. "Strained Silicon Technology." In Investigation on SiGe Selective Epitaxy for Source and Drain Engineering in 22 nm CMOS Technology Node and Beyond, 9–21. Singapore: Springer Singapore, 2019. http://dx.doi.org/10.1007/978-981-15-0046-6_2.

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Saxena, Anmol, Vyom Saraf, and Rutu Parekh. "ASIC Implementation of a 16-Bit Brent–Kung Adder at 45 nm Technology Node." In Sustainable Technology and Advanced Computing in Electrical Engineering, 83–105. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-4364-5_8.

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Ayush, Poornima Mittal, and Rajesh Rohilla. "Comparative Analysis of Current Sense Amplifier Architectures for SRAM at 45 nm Technology Node." In Advances in Data-Driven Computing and Intelligent Systems, 633–40. Singapore: Springer Nature Singapore, 2023. http://dx.doi.org/10.1007/978-981-99-3250-4_48.

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Mal, Agnish, Akshat Chitransh, Harsh Srivastava, Suraj Kumar Saw, and Vijay Nath. "Analysis of a Self-compensating, Low-Noise, Low-Power PLL Circuit @ 45-nm Technology Node." In Lecture Notes in Electrical Engineering, 361–70. Singapore: Springer Singapore, 2017. http://dx.doi.org/10.1007/978-981-10-2999-8_30.

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Ahlawat, Siddhant, Siddharth, Bhawna Rawat, and Poornima Mittal. "A Comparative Performance Analysis of Varied 10T SRAM Cell Topologies at 32 nm Technology Node." In Modeling, Simulation and Optimization, 63–75. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-0836-1_5.

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Tripathi, Suman Lata, Sobhit Saxena, Yogesh Kumar Verma, and Manoj Singh Adhikari. "Low Power Ge-Si0.7Ge0.3 nJLTFET and pJLTFET Design and Characterization in Sub-20 nm Technology Node." In Composite Materials, 199–212. First edition. | Boca Raton, FL : CRC Press, 2021.: CRC Press, 2020. http://dx.doi.org/10.1201/9781003080633-11.

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Singh, Shikha, and Yagnesh B. Shukla. "Design and Analysis of Low Power FinFET-Based Hybrid Full Adders at 16 nm Technology Node." In Intelligent Sustainable Systems, 631–41. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-2894-9_48.

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Kaur, Ravneet, Charu Madhu, and Deepti Singh. "Impact of Buried Oxide Layer Thickness on the Performance Parameters of SOI FinFET at 22 nm Node Technology." In Advances in Intelligent Systems and Computing, 537–44. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-5903-2_54.

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Rawat, Bhawna, and Poornima Mittal. "Investigating the Impact of Schmitt Trigger on SRAM Cells at 32 nm Technology Node for Low Voltage Applications." In Lecture Notes in Electrical Engineering, 53–63. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-19-6780-1_5.

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Conference papers on the topic "NM TECHNOLOGY NODE"

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Tyminski, Jacek K., and Toshiharu Nakashima. "Technology qualification for 65-nm node." In Optical Microlithography XVIII. SPIE, 2005. http://dx.doi.org/10.1117/12.600246.

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Eng, Yi-Chuen, and Jyi-Tsong Lin. "Advanced ¿-FET Technology for 45 nm Technology Node." In 2007 14th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IEEE, 2007. http://dx.doi.org/10.1109/ipfa.2007.4378081.

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Chabala, Jan M., Suzanne Weaver, David W. Alexander, Maiying Lu, Nam-Wook Kim, and Damon M. Cole. "130-nm node mask development." In 17th European Conference on Mask Technology for Integrated Circuits and Microcomponents. SPIE, 2001. http://dx.doi.org/10.1117/12.425102.

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Robinson, Tod, Andrew Dinsdale, Ron Bozak, Roy White, David A. Lee, and Ken Roessler. "Mask repair for the 65-nm technology node." In Photomask Technology 2005, edited by J. Tracy Weed and Patrick M. Martin. SPIE, 2005. http://dx.doi.org/10.1117/12.634758.

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Liebmann, Lars W., Jennifer Lund, Ioana C. Graur, Fook-Luen Heng, Carlos A. Fonseca, James Culp, and Allen H. Gabor. "Enabling the 70-nm technology node with 193-nm altPSM lithography." In Design, Process Integration, and Characterization for Microelectronics, edited by Alexander Starikov and Kenneth W. Tobin, Jr. SPIE, 2002. http://dx.doi.org/10.1117/12.475663.

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Borodovsky, Yan A., Richard E. Schenker, Gary A. Allen, Edita Tejnil, David H. Hwang, Fu-Chang Lo, Vivek K. Singh, Robert E. Gleason, Joseph E. Brandenburg, and Robert M. Bigwood. "Lithography strategy for 65-nm node." In Photomask and Next Generation Lithography Mask Technology IX, edited by Hiroichi Kawahira. SPIE, 2002. http://dx.doi.org/10.1117/12.476916.

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Yoshikawa, Ryoji, Hiroyuki Tanizaki, Tomohide Watanabe, Hiromu Inoue, Riki Ogawa, Satoshi Endo, Masami Ikeda, Yoichiro Takahashi, and Hidehiro Watanabe. "257-nm wavelength mask inspection for 65-nm node reticles." In Photomask and Next Generation Lithography Mask Technology XI, edited by Hiroyoshi Tanabe. SPIE, 2004. http://dx.doi.org/10.1117/12.557725.

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Li, K., P. Liu, Q. Wang, I. Tee, and J. Teong. "Physical characterization challenges in 45 nm technology node." In 2008 15th International Symposium on the Physical and Failure Analysis of Integrated Circuits. IEEE, 2008. http://dx.doi.org/10.1109/ipfa.2008.4588202.

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Kroyan, Armen, and Hua-Yu Liu. "Resolution enhancement technology requirements for 65-nm node." In Advanced Microelectronic Manufacturing, edited by Alexander Starikov. SPIE, 2003. http://dx.doi.org/10.1117/12.485486.

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Deschacht, D. "Interconnect design for a 32 nm node technology." In Technology of Integrated Systems in Nanoscale Era (DTIS). IEEE, 2011. http://dx.doi.org/10.1109/dtis.2011.5941410.

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