Journal articles: 'Network architectures'

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DELGADO-FRIAS, JOSE G., STAMATIS VASSILIADIS, and JAMSHID GOSHTASBI. "SEMANTIC NETWORK ARCHITECTURES: AN EVALUATION." International Journal on Artificial Intelligence Tools 01, no. 01 (March 1992): 57–83. http://dx.doi.org/10.1142/s0218213092000132.

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Semantic networks as a means for knowledge representation and manipulation are used in many artificial intelligence applications. A number of computer architectures, that have been reported for semantic network processing, are presented in this paper. A novel set of evaluation criteria for such semantic network architectures has been developed. Semantic network processing as well as architectural issues are considered in such evaluation criteria. A study of how the reported architectures meet the requirements of each criterion is presented. This set of evaluation criteria is useful for future designs of machines for semantic networks because of its comprehensive range of issues on semantic networks and architectures.

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Zurn, Perry, and Danielle S. Bassett. "Network architectures supporting learnability." Philosophical Transactions of the Royal Society B: Biological Sciences 375, no. 1796 (February 24, 2020): 20190323. http://dx.doi.org/10.1098/rstb.2019.0323.

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Human learners acquire complex interconnected networks of relational knowledge. The capacity for such learning naturally depends on two factors: the architecture (or informational structure) of the knowledge network itself and the architecture of the computational unit—the brain—that encodes and processes the information. That is, learning is reliant on integrated network architectures at two levels: the epistemic and the computational, or the conceptual and the neural. Motivated by a wish to understand conventional human knowledge, here, we discuss emerging work assessing network constraints on the learnability of relational knowledge, and theories from statistical physics that instantiate the principles of thermodynamics and information theory to offer an explanatory model for such constraints. We then highlight similarities between those constraints on the learnability of relational networks, at one level, and the physical constraints on the development of interconnected patterns in neural systems, at another level, both leading to hierarchically modular networks. To support our discussion of these similarities, we employ an operational distinction between the modeller (e.g. the human brain), the model (e.g. a single human’s knowledge) and the modelled (e.g. the information present in our experiences). We then turn to a philosophical discussion of whether and how we can extend our observations to a claim regarding explanation and mechanism for knowledge acquisition. What relation between hierarchical networks, at the conceptual and neural levels, best facilitate learning? Are the architectures of optimally learnable networks a topological reflection of the architectures of comparably developed neural networks? Finally, we contribute to a unified approach to hierarchies and levels in biological networks by proposing several epistemological norms for analysing the computational brain and social epistemes, and for developing pedagogical principles conducive to curious thought. This article is part of the theme issue ‘Unifying the essential concepts of biological networks: biological insights and philosophical foundations’.

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Dinn, Neil F. "Network architectures." Future Generation Computer Systems 7, no. 1 (October 1991): 79–89. http://dx.doi.org/10.1016/0167-739x(91)90018-s.

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Neeb, C., M. J. Thul, and N. Wehn. "Application driven evaluation of network on chip architectures forcation parallel signal processing." Advances in Radio Science 2 (May 27, 2005): 181–86. http://dx.doi.org/10.5194/ars-2-181-2004.

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Abstract. Today’s signal processing applications exhibit steadily increasing throughput requirements which can be achieved by parallel architectures. However, efficient communication is mandatory to fully exploit their parallelism. Turbo-Codes as an instance of highly efficient forward-error correction codes are a very good application to demonstrate the communication complexity in parallel architectures. We present a network-on-chip approach to derive an optimal communication architecture for a parallel Turbo-Decoder system. The performance of such a system significantly depends on the efficiency of the underlying interleaver network to distribute data among the parallel units. We focus on the strictly orthogonal n-dimensional mesh, torus and k-ary-n cube networks comparing deterministic dimension-order and partially adaptive negative- first and planar-adaptive routing algorithms. For each network topology and routing algorithm, input- and output-queued packet switching schemes are compared on the architectural level. The evaluation of candidate network architectures is based on performance measures and implementation cost to allow a fair trade-off.

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Lee, Woosik, Eun Suk Suh, Woo Young Kwak, and Hoon Han. "Comparative Analysis of 5G Mobile Communication Network Architectures." Applied Sciences 10, no. 7 (April 4, 2020): 2478. http://dx.doi.org/10.3390/app10072478.

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Mobile communication technology is evolving from 4G to 5G. Compared to previous generations, 5G has the capability to implement latency-critical services, such as autonomous driving, real-time AI on handheld devices and remote drone control. Multi-access Edge Computing is one of the key technologies of 5G in guaranteeing ultra-low latency aimed to support latency critical services by distributing centralized computing resources to networks edges closer to users. However, due to its high granularity of computing resources, Multi-access Edge Computing has an architectural vulnerability in that it can lead to the overloading of regional computing resources, a phenomenon called regional traffic explosion. This paper proposes an improved communication architecture called Hybrid Cloud Computing, which combines the advantages of both Centralized Cloud Computing and Multi-access Edge Computing. The performance of the proposed network architecture is evaluated by utilizing a discrete-event simulation model. Finally, the results, advantages, and disadvantages of various network architectures are discussed.

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Orhan, Orhan, and Huseyin Goren. "Largely Scalable Wireless Network Formation Architectures for Internet of Things." International Research Journal of Electronics and Computer Engineering 3, no. 4 (December 29, 2017): 17. http://dx.doi.org/10.24178/irjece.2017.3.4.17.

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As number of mobile devices increases with Internet of Things (IoT) capability and power consumption is important in multi hop communication, there is need of considering network formation architectures inIoT networks.In this work power levels of nodes, urgency of messages to be transmitted are not taken into consideration, a general approach considered with all nodes with same power levels and no priority for messages to be sent.Another assumption is all nodes are on the same 2D plane. Multi hop wireless network architectures studied and scalable, best performing architecture which is hypercubic network architecture is highlighted for IoT networks. Especially for large number of nodes needs to be considered hypercubic architecture performs much better than mesh, tree and ring kind of architectures in terms of dilation and number of connections. The simulation results are based on a simulator developed on C++ program. The results are showed that Hypercubic architecture with logarithmic dilation is much better than other network types. Cube Connected Cycles (CCC)based network architecture (which is derivative of Hypercube) can be preferred, especially when a constant degree is needed, in communication technologies such as Bluetooth. As a future work, a network architecture study can be made which takes energy levels and urgency of messages to be sent.

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Fernandes, Silvio R., Ivan S. Silva, and Marcio Kreutz. "Packet-driven General Purpose Instruction Execution on Communication-based Architectures." Journal of Integrated Circuits and Systems 5, no. 1 (November 21, 2010): 53–66. http://dx.doi.org/10.29292/jics.v5i1.310.

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In the last few years, the development of Multi-Core architectures was driven by the crescent advance in integration technology. In this scenario, when the number of cores increases, problems found on shared communication media, such as busses, can be addressed by using a network approach. This paper proposes the usage of communication capabilities of Networks-on-Chip (NoCs) to execute general purpose instructions. The main idea behind this approach is to allow networks-on-chip architectures to execute general purpose instructions inside each router architecture. This paper addresses the main architectural concerns involved on creating datapaths for routers as well as the programming model suggested to pack instructions on messages. Simulation results on two case studies illustrate the benefits of the proposed architecture when compared to an equivalent NoC-based MP-SoC.

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Pelt, Daniël M., and James A. Sethian. "A mixed-scale dense convolutional neural network for image analysis." Proceedings of the National Academy of Sciences 115, no. 2 (December 26, 2017): 254–59. http://dx.doi.org/10.1073/pnas.1715832114.

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Deep convolutional neural networks have been successfully applied to many image-processing problems in recent works. Popular network architectures often add additional operations and connections to the standard architecture to enable training deeper networks. To achieve accurate results in practice, a large number of trainable parameters are often required. Here, we introduce a network architecture based on using dilated convolutions to capture features at different image scales and densely connecting all feature maps with each other. The resulting architecture is able to achieve accurate results with relatively few parameters and consists of a single set of operations, making it easier to implement, train, and apply in practice, and automatically adapts to different problems. We compare results of the proposed network architecture with popular existing architectures for several segmentation problems, showing that the proposed architecture is able to achieve accurate results with fewer parameters, with a reduced risk of overfitting the training data.

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Dovrolis, Constantine, and J. Todd Streelman. "Evolvable network architectures." ACM SIGCOMM Computer Communication Review 40, no. 2 (April 9, 2010): 72–77. http://dx.doi.org/10.1145/1764873.1764886.

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Littmann, Enno, and Helge Ritter. "Learning and Generalization in Cascade Network Architectures." Neural Computation 8, no. 7 (October 1996): 1521–39. http://dx.doi.org/10.1162/neco.1996.8.7.1521.

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Incrementally constructed cascade architectures are a promising alternative to networks of predefined size. This paper compares the direct cascade architecture (DCA) proposed in Littmann and Ritter (1992) to the cascade-correlation approach of Fahlman and Lebiere (1990) and to related approaches and discusses the properties on the basis of various benchmark results. One important virtue of DCA is that it allows the cascading of entire subnetworks, even if these admit no error-backpropagation. Exploiting this flexibility and using LLM networks as cascaded elements, we show that the performance of the resulting network cascades can be greatly enhanced compared to the performance of a single network. Our results for the Mackey-Glass time series prediction task indicate that such deeply cascaded network architectures achieve good generalization even on small data sets, when shallow, broad architectures of comparable size suffer from overfitting. We conclude that the DCA approach offers a powerful and flexible alternative to existing schemes such as, e.g., the mixtures of experts approach, for the construction of modular systems from a wide range of subnetwork types.

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Duan, Qiang. "Intelligent and Autonomous Management in Cloud-Native Future Networks—A Survey on Related Standards from an Architectural Perspective." Future Internet 13, no. 2 (February 5, 2021): 42. http://dx.doi.org/10.3390/fi13020042.

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Cloud-native network design, which leverages network virtualization and softwarization together with the service-oriented architectural principle, is transforming communication networks to a versatile platform for converged network-cloud/edge service provisioning. Intelligent and autonomous management is one of the most challenging issues in cloud-native future networks, and a wide range of machine learning (ML)-based technologies have been proposed for addressing different aspects of the management challenge. It becomes critical that the various management technologies are applied on the foundation of a consistent architectural framework with a holistic vision. This calls for standardization of new management architecture that supports seamless the integration of diverse ML-based technologies in cloud-native future networks. The goal of this paper is to provide a big picture of the recent developments of architectural frameworks for intelligent and autonomous management for future networks. The paper surveys the latest progress in the standardization of network management architectures including works by 3GPP, ETSI, and ITU-Tand analyzes how cloud-native network design may facilitate the architecture development for addressing management challenges. Open issues related to intelligent and autonomous management in cloud-native future networks are also discussed in this paper to identify some possible directions for future research and development.

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Rowshanrad, Shiva, Mohamad Reza Parsaei, and Manijeh Keshtgari. "IMPLEMENTING NDN USING SDN: A REVIEW ON METHODS AND APPLICATIONS." IIUM Engineering Journal 17, no. 2 (November 30, 2016): 11–20. http://dx.doi.org/10.31436/iiumej.v17i2.590.

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In recent years many claims about the limitations of todaysâ€™ network architecture, its lack of flexibility and ability to response to ongoing changes and increasing users demands. In this regard, new network architectures are proposed. Software Defined Networking (SDN) is one of these new architectures which centralizes the control of network by separating control plane from data plane. This separation leads to intelligence, flexibility and easier control in computer networks. One of the advantages of this framework is the ability to implement and test new protocols and architectures in actual networks without any concern of interruption.Named Data Networking (NDN) is another paradigm for future network architecture. With NDN the network becomes aware of the content that is providing, rather than just transferring it among end-points. NDN attracts researchersâ€™ attention and known as the potential future of networking and internet. Providing NDN functionalities over SDN is an important requirement to enable the innovation and optimization of network resources. In this paper first we describe about SDN and NDN, and then we introduce methods for implementing NDN using SDN. We also point out the advantages and applications of implementing NDN over SDN.

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Zkik, Karim, Said EL Hajji, and Ghizlane Orhanou. "A centralized secure plan for detecting and mitigation incidents in hybrid SDN." MATEC Web of Conferences 189 (2018): 10015. http://dx.doi.org/10.1051/matecconf/201818910015.

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The information technology sector has experienced phenomenal growth during recent years. To follow this development many new technologies have emerged to satisfy the expectations of businesses and customers, such as Cloud Computing, mobility, virtualization, Internet of things and big data. Traditional network cannot longer support this growth and suffers more and more in terms of misconfiguration,management and configurations complexity. Software defined network (SDN) architectures can be considered as a big revolution in the field of computer networks, because they offer a centralized control on infrastructure, services and the applications deployed which facilitate configuration and management on the network. The implementation of this type of architecture is not obvious and requires great expertise and good handling and management of network equipment. To remedy this problem the SDN architectures have evolved towards distributed and hybrid architectures. Despites the advantages of using SDN, security issues remain a real obstacle in front of the deployment of this type of architecture. The centralized architecture of this type of networks makes it vulnerable to several types of attacks and intrusions, and the implementation of security equipment generally causes a decrease in performance and increase latency.

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Wang, Yan, and Jun Hui Zheng. "A Well Modularized Computer Network Architecture." Applied Mechanics and Materials 631-632 (September 2014): 902–5. http://dx.doi.org/10.4028/www.scientific.net/amm.631-632.902.

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By analyzing a variety of computer network architectures, we can find that researchers establish different computer network models from their different starting points and get different computer network architectures by different modularization methods. We establish a well modularized non-layered computer network architecture. This paper compares it with the layered architecture and obtains a conclusion that it is superior to the layered architecture. We have developed two framework prototypes of it. In the one of them we develop some application softwares of TCP/IP, including E-mail, FTP, Web and standard IP telephone, which have been tested by the third-party. It could show the accuracy and easily implemented property of this architecture.

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Et al., Sarayut Chaisuriya. "A Ring-Based Cybersecurity Architecture for Critical Infrastructure." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 6 (April 5, 2021): 2826–40. http://dx.doi.org/10.17762/turcomat.v12i6.5790.

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A defense-in-depth (DID) approach for securing critical information infrastructure has been a common method used in cybersecurity. However, holistic design guidelines are lacking which precludes organizations from adopting them. Therefore, this paper sets out to outline and detail a holistic framework using ring-based nested network zone architecture for the design and implementation of highly secured networked environments. The proposed cybersecurity architecture framework offers a structural design for holistically designed N-tier system architectures. Several implementation options, including zoning perimeters, are suggested as being capable of offering different security capability levels by trading off amongst various security aspects. Also, the proposed architecture allows adaptability in implementations for various real-world networks. This paper also proposes an attack-hops verification approach to evaluate the architectural design.

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Konarev, D. I., and A. A. Gulamov. "Synthesis of Neural Network Architecture for Recognition of Sea-Going Ship Images." Proceedings of the Southwest State University 24, no. 1 (June 23, 2020): 130–43. http://dx.doi.org/10.21869/2223-1560-2020-24-1-130-143.

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Purpose of research. The current task is to monitor ships using video surveillance cameras installed along the canal. It is important for information communication support for navigation of the Moscow Canal. The main subtask is direct recognition of ships in an image or video. Implementation of a neural network is perspectively.Methods. Various neural network are described. images of ships are an input data for the network. The learning sample uses CIFAR-10 dataset. The network is built and trained by using Keras and TensorFlow machine learning libraries.Results. Implementation of curving artificial neural networks for problems of image recognition is described. Advantages of such architecture when working with images are also described. The selection of Python language for neural network implementation is justified. The main used libraries of machine learning, such as TensorFlow and Keras are described. An experiment has been conducted to train swirl neural networks with different architectures based on Google collaboratoty service. The effectiveness of different architectures was evaluated as a percentage of correct pattern recognition in the test sample. Conclusions have been drawn about parameters influence of screwing neural network on showing its effectiveness.Conclusion. The network with a single curl layer in each cascade showed insufficient results, so three-stage curls with two and three curl layers in each cascade were used. Feature map extension has the greatest impact on the accuracy of image recognition. The increase in cascades' number has less noticeable effect and the increase in the number of screwdriver layers in each cascade does not always have an increase in the accuracy of the neural network. During the study, a three-frame network with two buckling layers in each cascade and 128 feature maps is defined as an optimal architecture of neural network under described conditions. operability checking of architecture's part under consideration on random images of ships confirmed the correctness of optimal architecture choosing.

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Kim, Myung, and Ram Narasimhan. "Designing Supply Networks in Automobile and Electronics Manufacturing Industries: A Multiplex Analysis." Processes 7, no. 3 (March 26, 2019): 176. http://dx.doi.org/10.3390/pr7030176.

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This study investigates the process of how the original equipment manufacturers (OEMs) in automobile and consumer electronics industries design their supply networks. In contrast to the sociological viewpoint, which regards the emergence of networks as a social and psychological phenomenon occurring among non-predetermined individuals, this paper attempts to provide a strategic supply network perspective that views the supply network as a strategic choice made by an OEM. Anchored in the multiplex investigation of supply network architectures, this study looks into the following specific questions: (1) Are an OEM’s strategic intent choices associated with supply network architecture and (2) If so, what differential effects do those strategic intents have on the architectural properties of the supply network? Further field investigations were conducted to provide deeper insights into the quantitative and qualitative findings from statistical analyses.

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de Paulo, Vitor, and Cristinel Ababei. "3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans." International Journal of Reconfigurable Computing 2010 (2010): 1–12. http://dx.doi.org/10.1155/2010/603059.

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We propose new 3D 2-layer and 3-layer NoC architectures that utilizehomogeneousregular mesh networks on a separate layer and one or twoheterogeneousfloorplanning layers. These architectures combine the benefits of compact heterogeneous floorplans and of regular mesh networks. To demonstrate these benefits, a design methodology that integrates floorplanning, routers assignment, and cycle-accurate NoC simulation is proposed. The implementation of the NoC on a separate layer offers an additional area that may be utilized to improve the network performance by increasing the number of virtual channels, buffers size, or mesh size. Experimental results show that increasing the number of virtual channels rather than the buffers size has a higher impact on network performance. Increasing the mesh size can significantly improve the network performance under the assumption that the clock frequency is given by the length of the physical links. In addition, the 3-layer architecture can offer significantly better network performance compared to the 2-layer architecture.

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Vinayakumar, R., K. P. Soman, and Prabaharan Poornachandran. "Evaluation of Recurrent Neural Network and its Variants for Intrusion Detection System (IDS)." International Journal of Information System Modeling and Design 8, no. 3 (July 2017): 43–63. http://dx.doi.org/10.4018/ijismd.2017070103.

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This article describes how sequential data modeling is a relevant task in Cybersecurity. Sequences are attributed temporal characteristics either explicitly or implicitly. Recurrent neural networks (RNNs) are a subset of artificial neural networks (ANNs) which have appeared as a powerful, principle approach to learn dynamic temporal behaviors in an arbitrary length of large-scale sequence data. Furthermore, stacked recurrent neural networks (S-RNNs) have the potential to learn complex temporal behaviors quickly, including sparse representations. To leverage this, the authors model network traffic as a time series, particularly transmission control protocol / internet protocol (TCP/IP) packets in a predefined time range with a supervised learning method, using millions of known good and bad network connections. To find out the best architecture, the authors complete a comprehensive review of various RNN architectures with its network parameters and network structures. Ideally, as a test bed, they use the existing benchmark Defense Advanced Research Projects Agency / Knowledge Discovery and Data Mining (DARPA) / (KDD) Cup ‘99' intrusion detection (ID) contest data set to show the efficacy of these various RNN architectures. All the experiments of deep learning architectures are run up to 1000 epochs with a learning rate in the range [0.01-0.5] on a GPU-enabled TensorFlow and experiments of traditional machine learning algorithms are done using Scikit-learn. Experiments of families of RNN architecture achieved a low false positive rate in comparison to the traditional machine learning classifiers. The primary reason is that RNN architectures are able to store information for long-term dependencies over time-lags and to adjust with successive connection sequence information. In addition, the effectiveness of RNN architectures are shown for the UNSW-NB15 data set.

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Hsu, Chia-Hsin, Chien-Kuo Chen, and Ming-Jing Hwang. "The architectural design of networks of protein domain architectures." Biology Letters 9, no. 4 (August 23, 2013): 20130268. http://dx.doi.org/10.1098/rsbl.2013.0268.

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Protein domain architectures (PDAs), in which single domains are linked to form multiple-domain proteins, are a major molecular form used by evolution for the diversification of protein functions. However, the design principles of PDAs remain largely uninvestigated. In this study, we constructed networks to connect domain architectures that had grown out from the same single domain for every single domain in the Pfam-A database and found that there are three main distinctive types of these networks, which suggests that evolution can exploit PDAs in three different ways. Further analysis showed that these three different types of PDA networks are each adopted by different types of protein domains, although many networks exhibit the characteristics of more than one of the three types. Our results shed light on nature's blueprint for protein architecture and provide a framework for understanding architectural design from a network perspective.

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Smith, Cameron, Ximo Pechuan, Raymond S. Puzio, Daniel Biro, and Aviv Bergman. "Potential unsatisfiability of cyclic constraints on stochastic biological networks biases selection towards hierarchical architectures." Journal of The Royal Society Interface 12, no. 108 (July 2015): 20150179. http://dx.doi.org/10.1098/rsif.2015.0179.

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Constraints placed upon the phenotypes of organisms result from their interactions with the environment. Over evolutionary time scales, these constraints feed back onto smaller molecular subnetworks comprising the organism. The evolution of biological networks is studied by considering a network of a few nodes embedded in a larger context. Taking into account this fact that any network under study is actually embedded in a larger context, we define network architecture, not on the basis of physical interactions alone, but rather as a specification of the manner in which constraints are placed upon the states of its nodes. We show that such network architectures possessing cycles in their topology, in contrast to those that do not, may be subjected to unsatisfiable constraints. This may be a significant factor leading to selection biased against those network architectures where such inconsistent constraints are more likely to arise. We proceed to quantify the likelihood of inconsistency arising as a function of network architecture finding that, in the absence of sampling bias over the space of possible constraints and for a given network size, networks with a larger number of cycles are more likely to have unsatisfiable constraints placed upon them. Our results identify a constraint that, at least in isolation, would contribute to a bias in the evolutionary process towards more hierarchical -modular versus completely connected network architectures. Together, these results highlight the context dependence of the functionality of biological networks.

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Anusree S, Anusree S. "Architectures of Fault-Tolerant Network Interfaces and Router For Network-On-Chip." International Journal of Scientific Research 3, no. 5 (June 1, 2012): 190–94. http://dx.doi.org/10.15373/22778179/may2014/58.

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Bezzubtsev, Stanislav O., Vyacheslav V. Vasin, Dmitry Yu Volkanov, Shynar R. Zhailauova, Vladislav A. Miroshnik, Yuliya A. Skobtsova, and Ruslan L. Smeliansky. "An Approach to the Construction of a Network Processing Unit." Modeling and Analysis of Information Systems 26, no. 1 (March 15, 2019): 39–62. http://dx.doi.org/10.18255/1818-1015-2019-1-39-62.

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The paper proposes the architecture and basic requirements for a network processor for OpenFlow switches of software-defined networks. An analysis of the architectures of well-known network processors is presented − NP-5 from EZchip (now Mellanox) and Tofino from Barefoot Networks. The advantages and disadvantages of two different versions of network processor architectures are considered: pipeline-based architecture, the stages of which are represented by a set of general-purpose processor cores, and pipeline-based architecture whose stages correspond to cores specialized for specific packet processing operations. Based on a dedicated set of the most common use case scenarios, a new architecture of the network processor unit (NPU) with functionally specialized pipeline stages was proposed. The article presents a description of the simulation model of the NPU of the proposed architecture. The simulation model of the network processor is implemented in C ++ languages using SystemC, the open-source C++ library. For the functional testing of the obtained NPU model, the described use case scenarios were implemented in C. In order to evaluate the performance of the proposed NPU architecture a set of software products developed by KM211 company and the KMX32 family of microcontrollers were used. Evaluation of NPU performance was made on the basis of a simulation model. Estimates of the processing time of one packet and the average throughput of the NPU model for each scenario are obtained.

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Shapovalova, Svitlana, and Yurii Moskalenko. "METHODS FOR INCREASING THE CLASSIFICATION ACCURACY BASED ON MODIFICATIONS OF THE BASIC ARCHITECTURE OF CONVOLUTIONAL NEURAL NETWORKS." ScienceRise, no. 6 (December 30, 2020): 10–16. http://dx.doi.org/10.21303/2313-8416.2020.001550.

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Object of research: basic architectures of deep learning neural networks. Investigated problem: insufficient accuracy of solving the classification problem based on the basic architectures of deep learning neural networks. An increase in accuracy requires a significant complication of the architecture, which, in turn, leads to an increase in the required computing resources, as well as the consumption of video memory and the cost of learning/output time. Therefore, the problem arises of determining such methods for modifying basic architectures that improve the classification accuracy and require insignificant additional computing resources. Main scientific results: based on the analysis of existing methods for improving the classification accuracy on the convolutional networks of basic architectures, it is determined what is most effective: scaling the ScanNet architecture, learning the ensemble of TreeNet models, integrating several CBNet backbone networks. For computational experiments, these modifications of the basic architectures are implemented, as well as their combinations: ScanNet + TreeNet, ScanNet + CBNet. The effectiveness of these methods in comparison with basic architectures has been proven when solving the problem of recognizing malignant tumors with diagnostic images – SIIM-ISIC Melanoma Classification, the train/test set of which is presented on the Kaggle platform. The accuracy value for the area under the ROC curve metric has increased from 0.94489 (basic architecture network) to 0.96317 (network with ScanNet + CBNet modifications). At the same time, the output compared to the basic architecture (EfficientNet-b5) increased from 440 to 490 seconds, and the consumption of video memory increased from 8 to 9.2 gigabytes, which is acceptable. Innovative technological product: methods for achieving high recognition accuracy from a diagnostic signal based on deep learning neural networks of basic architectures. Scope of application of the innovative technological product: automatic diagnostics systems in the following areas: medicine, seismology, astronomy (classification by images) onboard control systems and systems for monitoring transport and vehicle flows or visitors (recognition of scenes with camera frames).

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Sharp, Duane E. "Network Architectures and Performance." Information Systems Management 15, no. 2 (March 1998): 7–12. http://dx.doi.org/10.1201/1078/43184.15.2.19980301/31113.2.

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Stewart, H. "Future access network architectures." Computer Communications 22, no. 18 (December 1999): 1638–40. http://dx.doi.org/10.1016/s0140-3664(99)00144-9.

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Hác, Anna. "Wireless ATM network architectures." International Journal of Network Management 11, no. 3 (May 2001): 161–67. http://dx.doi.org/10.1002/nem.399.

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Doverspike, R. D., S. Phillips, and A. R. Westbrook. "Future transport network architectures." IEEE Communications Magazine 37, no. 8 (1999): 96–101. http://dx.doi.org/10.1109/35.783131.

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Katifori, Eleni, and Marcelo O. Magnasco. "Quantifying Loopy Network Architectures." PLoS ONE 7, no. 6 (June 6, 2012): e37994. http://dx.doi.org/10.1371/journal.pone.0037994.

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Thompson, Lionel R. "Local area network architectures." Microprocessors and Microsystems 13, no. 1 (January 1989): 64. http://dx.doi.org/10.1016/0141-9331(89)90040-9.

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Marsden, Brian W. "Local Area Network Architectures." Computer Communications 12, no. 2 (April 1989): 107. http://dx.doi.org/10.1016/0140-3664(89)90066-2.

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State, Radu. "Review: Network Security Architectures." Queue 3, no. 1 (February 2005): 61. http://dx.doi.org/10.1145/1046931.1046951.

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Raza Naqvi, Muhammad. "Low power network on chip architectures: A survey." Computer Science and Information Technologies 2, no. 3 (November 1, 2020): 158–68. http://dx.doi.org/10.11591/csit.v2i3.p158-168.

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Mostly communication now days is done through SoC (system on chip) models so, NoC (network on chip) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.

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Broustis, Ioannis, and Michalis Faloutsos. "Routing in Vehicular Networks: Feasibility, Modeling, and Security." International Journal of Vehicular Technology 2008 (April 21, 2008): 1–8. http://dx.doi.org/10.1155/2008/267513.

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Vehicular networks are sets of surface transportation systems that have the ability to communicate with each other. There are several possible network architectures to organize their in-vehicle computing systems. Potential schemes may include vehicle-to-vehicle ad hoc networks, wired backbone with wireless last hops, or hybrid architectures using vehicle-to-vehicle communications to augment roadside communication infrastructures. Some special properties of these networks, such as high mobility, network partitioning, and constrained topology, differentiate them from other types of wireless networks. We provide an in-depth discussion on the important studies related to architectural design and routing for such networks. Moreover, we discuss the major security concerns appearing in vehicular networks.

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Muir, Dylan R. "Feedforward Approximations to Dynamic Recurrent Network Architectures." Neural Computation 30, no. 2 (February 2018): 546–67. http://dx.doi.org/10.1162/neco_a_01042.

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Recurrent neural network architectures can have useful computational properties, with complex temporal dynamics and input-sensitive attractor states. However, evaluation of recurrent dynamic architectures requires solving systems of differential equations, and the number of evaluations required to determine their response to a given input can vary with the input or can be indeterminate altogether in the case of oscillations or instability. In feedforward networks, by contrast, only a single pass through the network is needed to determine the response to a given input. Modern machine learning systems are designed to operate efficiently on feedforward architectures. We hypothesized that two-layer feedforward architectures with simple, deterministic dynamics could approximate the responses of single-layer recurrent network architectures. By identifying the fixed-point responses of a given recurrent network, we trained two-layer networks to directly approximate the fixed-point response to a given input. These feedforward networks then embodied useful computations, including competitive interactions, information transformations, and noise rejection. Our approach was able to find useful approximations to recurrent networks, which can then be evaluated in linear and deterministic time complexity.

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Balandin, Sergey, and Michel Gillet. "Embedded Networks in Mobile Devices." International Journal of Embedded and Real-Time Communication Systems 1, no. 1 (January 2010): 22–36. http://dx.doi.org/10.4018/jertcs.2010103002.

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The concept of a mobile phone has recently transformed into a new concept of mobile multimedia devices capable of performing multiple complex tasks and integrating multiple functionalities. It has resulted in a significant increase of device integration costs and complicated deployment of new technologies. Device integrator companies favor modularity everywhere possible, which results in a new trend toward networked architectures for the mobile devices. However, comparing to the best-known embedded network solutions, e.g., SoC and NoC, these architectures have unique constraints and requirements, which also are significantly different from the wide area networks. The main constraints are power consumption and having a modular architecture to allow reuse of the components. Transition to the new architectures for mobile devices is a time consuming task that requires the analysis of many solutions applied in other contexts, especially for embedded protocols, QoS and resource management. This article reviews the state of the art in embedded networks research and the key assumptions, restrictions and limitations faced by designers of embedded networks architectures for mobile devices.

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Colonnese, Stefania, Mauro Biagi, Tiziana Cattai, Roberto Cusani, Fabrizio De Vico Fallani, and Gaetano Scarano. "Green Compressive Sampling Reconstruction in IoT Networks." Sensors 18, no. 8 (August 20, 2018): 2735. http://dx.doi.org/10.3390/s18082735.

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In this paper, we address the problem of green Compressed Sensing (CS) reconstruction within Internet of Things (IoT) networks, both in terms of computing architecture and reconstruction algorithms. The approach is novel since, unlike most of the literature dealing with energy efficient gathering of the CS measurements, we focus on the energy efficiency of the signal reconstruction stage given the CS measurements. As a first novel contribution, we present an analysis of the energy consumption within the IoT network under two computing architectures. In the first one, reconstruction takes place within the IoT network and the reconstructed data are encoded and transmitted out of the IoT network; in the second one, all the CS measurements are forwarded to off-network devices for reconstruction and storage, i.e., reconstruction is off-loaded. Our analysis shows that the two architectures significantly differ in terms of consumed energy, and it outlines a theoretically motivated criterion to select a green CS reconstruction computing architecture. Specifically, we present a suitable decision function to determine which architecture outperforms the other in terms of energy efficiency. The presented decision function depends on a few IoT network features, such as the network size, the sink connectivity, and other systems’ parameters. As a second novel contribution, we show how to overcome classical performance comparison of different CS reconstruction algorithms usually carried out w.r.t. the achieved accuracy. Specifically, we consider the consumed energy and analyze the energy vs. accuracy trade-off. The herein presented approach, jointly considering signal processing and IoT network issues, is a relevant contribution for designing green compressive sampling architectures in IoT networks.

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Shu, Hantao, Jingtian Zhou, Qiuyu Lian, Han Li, Dan Zhao, Jianyang Zeng, and Jianzhu Ma. "Modeling gene regulatory networks using neural network architectures." Nature Computational Science 1, no. 7 (July 2021): 491–501. http://dx.doi.org/10.1038/s43588-021-00099-8.

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Guesmi, Tawfik, Anwar Kalghoum, Badr M. Alshammari, Haitham Alsaif, and Ahmed Alzamil. "Leveraging Software-Defined Networking Approach for Future Information-Centric Networking Enhancement." Symmetry 13, no. 3 (March 9, 2021): 441. http://dx.doi.org/10.3390/sym13030441.

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Information-centric networking (ICN) has been developed as a potential candidate for future networks. In this model, users are provided with content rather than communication channels between the different hosts. The ICN network has several problems such as scalability issues and bandwidth consumption. However, software-defined networking (SDN) has been proposed to improve the networking architectures. The goal of our paper is to propose a new approach to named-data networking (NDN) based on the paradigm of SDN. Our work introduces various research studies carried out in the SDN and ICN contexts. We first present the SDN architecture. Then, we focus on work that combines ICN and SDN architectures. Finally, we show the effects of using the SDN architecture on the named-data network (NDN). Our experimental results show that the use of the SDN architecture has a positive effect on NDN network performance.

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Müller, Peter, and David Rios Insua. "Issues in Bayesian Analysis of Neural Network Models." Neural Computation 10, no. 3 (April 1, 1998): 749–70. http://dx.doi.org/10.1162/089976698300017737.

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Stemming from work by Buntine and Weigend (1991) and MacKay (1992), there is a growing interest in Bayesian analysis of neural network models. Although conceptually simple, this problem is computationally involved. We suggest a very efficient Markov chain Monte Carlo scheme for inference and prediction with fixed-architecture feedforward neural networks. The scheme is then extended to the variable architecture case, providing a data-driven procedure to identify sensible architectures.

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Mohamed, Soha Abd El-Moamen, Marghany Hassan Mohamed, and Mohammed F. Farghally. "A New Cascade-Correlation Growing Deep Learning Neural Network Algorithm." Algorithms 14, no. 5 (May 19, 2021): 158. http://dx.doi.org/10.3390/a14050158.

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In this paper, a proposed algorithm that dynamically changes the neural network structure is presented. The structure is changed based on some features in the cascade correlation algorithm. Cascade correlation is an important algorithm that is used to solve the actual problem by artificial neural networks as a new architecture and supervised learning algorithm. This process optimizes the architectures of the network which intends to accelerate the learning process and produce better performance in generalization. Many researchers have to date proposed several growing algorithms to optimize the feedforward neural network architectures. The proposed algorithm has been tested on various medical data sets. The results prove that the proposed algorithm is a better method to evaluate the accuracy and flexibility resulting from it.

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Uzdiaev, M. Yu, R. N. Iakovlev, D. M. Dudarenko, and A. D. Zhebrun. "Identification of a Person by Gait in a Video Stream." Proceedings of the Southwest State University 24, no. 4 (February 4, 2021): 57–75. http://dx.doi.org/10.21869/2223-1560-2020-24-4-57-75.

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Purpose of research. The given paper considers the problem of identifying a person by gait through the use of neural network recognition models focused on working with RGB images. The main advantage of using neural network models over existing methods of motor activity analysis is obtaining images from the video stream without frames preprocessing, which increases the analysis time. Methods. The present paper presents an approach to identifying a person by gait. The approach is based upon the idea of multi-class classification on video sequences. The quality of the developed approach operation was evaluated on the basis of CASIA Gait Database data set, which includes more than 15,000 video sequences. As classifiers, 5 neural network architectures have been tested: the three-dimensional convolutional neural network I3D, as well as 4 architectures representing convolutional-recurrent networks, such as unidirectional and bidirectional LTSM, unidirectional and bidirectional GRU, combined with the convolutional neural network of ResNet architecture being used in these architectures as a visual feature extractor. Results. According to the results of the conducted testing, the developed approach makes it possible to identify a person in a video stream in real-time mode without the use of specialized equipment. According to the results of its testing and through the use of the neural network models under consideration, the accuracy of human identification was more than 80% for convolutional-recurrent models and 79% for the I3D model. Conclusion. The suggested models based on I3D architecture and convolutional-recurrent architectures have shown higher accuracy for solving the problem of identifying a person by gait than existing methods. Due to the possibility of frame-by-frame video processing, the most preferred classifier for the developed approach is the use of convolutional-recurrent architectures based on unidirectional LSTM or GRU models, respectively.

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Back, Andrew D., and Ah Chung Tsoi. "A Low-Sensitivity Recurrent Neural Network." Neural Computation 10, no. 1 (January 1, 1998): 165–88. http://dx.doi.org/10.1162/089976698300017935.

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The problem of high sensitivity in modeling is well known. Small perturbations in the model parameters may result in large, undesired changes in the model behavior. A number of authors have considered the issue of sensitivity in feedforward neural networks from a probabilistic perspective. Less attention has been given to such issues in recurrent neural networks. In this article, we present a new recurrent neural network architecture, that is capable of significantly improved parameter sensitivity properties compared to existing recurrent neural networks. The new recurrent neural network generalizes previous architectures by employing alternative discrete-time operators in place of the shift operator normally used. An analysis of the model demonstrates the existence of parameter sensitivity in recurrent neural networks and supports the proposed architecture. The new architecture performs significantly better than previous recurrent neural networks, as shown by a series of simple numerical experiments.

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Zheng, Olivier Z., Maaruf Ali, and Kashinath Basu. "Comparing the Complexity of Two Network Architectures." Annals of Emerging Technologies in Computing 1, no. 1 (October 1, 2017): 7–18. http://dx.doi.org/10.33166/aetic.2017.01.002.

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A Service Provider has different methods to provide a VPN service to its customers. But which method is the least complex to implement? In this paper, two architectures are described and analysed. Based on the analyses, two methods of complexity calculation are designed to evaluate the complexity of the architecture: the first method evaluates the resources consumed, the second evaluates the number of cases possible.

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Daltro Duarte, Gabriel, Claudio Pereira Mego Quinteros, and Lincoln Machado Araújo. "Cinemática Inversa com Redes Neurais Aplicadas em Robôs Manipuladores." Revista Principia - Divulgação Científica e Tecnológica do IFPB 1, no. 43 (November 20, 2018): 49. http://dx.doi.org/10.18265/1517-03062015v1n43p49-63.

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Today’s world is going through what is known as the Fourth Industrial Revolution. Robots have been gaining more and more space in the industry and going beyond expectations. The use of robots in industry is related to the increasing production and the quality of the electronic products. For an accurate movement of a robot manipulator it is necessary to obtain its inverse kinematic model, however, obtaining this model requires the challenging solution of a set of nonlinear equations. For this system of nonlinear equations there is no generic solution method. In view of this matter, this research aims to solve the problem of the inverse kinematics of a robot manipulator using artificial neural networks without the need to model the robot’s direct kinematics. Two neural network training methodologies, called offline training and online training were used. The basic difference between these two is that in the offline methodology all training points are obtained before any training of the neural network occurs, whereas in online training the use of a training method is recurrent. As the robot moves, new training points are obtained and training processes with the new acquired points are executed, allowing a learning process of continuous inverse kinematics. To validate the proposed methodology a prototype of a manipulated planar robot with one degree of freedom was developed and several architectures of neural networks were tested to find the optimal architecture. The offline training methodology obtained very satisfactory results for most of the neural network architectures tested. The online training only achieved satisfactory results in neural network architectures with quantities of neurons much larger than the quantities used in the architectures used in offline training and still obtained inferior results. The neural networks trained in offline mode, when compared to the training networks in the online mode, presented a greater capacity of generalization and a smaller value of output error. The online training has only achieved satisfactory results in neural network architectures with quantities of neurons much larger than the quantities used in the trained architectures in offline mode.

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Iyoda, Eduardo Masato, Kaoru Hirota, and Fernando J. Von Zuben. "Sigma-Pi Cascade Extended Hybrid Neural Network." Journal of Advanced Computational Intelligence and Intelligent Informatics 6, no. 3 (October 20, 2002): 126–34. http://dx.doi.org/10.20965/jaciii.2002.p0126.

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A nonparametric neural architecture called the Sigma-Pi Cascade extended Hybrid Neural Network σπ-(CHNN) is proposed to extend approximation capabilities in neural architectures such as Projection Pursuit Learning (PPL) and Hybrid Neural Networks (HNN). Like PPL and HNN, σπ-CHNN also uses distinct activation functions in its neurons but, unlike these previous neural architectures, it may consider multiplicative operators in its hidden neurons, enabling it to extract higher-order information from given data. σπ-CHNN uses arbitrary connectivity patterns among neurons. An evolutionary learning algorithm combined with a conjugate gradient algorithm is proposed to automatically design the topology and weights of σπ-CHNN. σπ-CHNN performance is evaluated in five benchmark regression problems. Results show that σπ-CHNN provides competitive performance compared to PPL and HNN in most problems, either in computational requirements to implement the proposed neural architecture or in approximation accuracy. In some problems, σπ-CHNN reduces the approximation error on the order of 10-1 compared to PPL and HNN, whereas in other cases it achieves the same approximation error as these neural architectures but uses a smaller number of hidden neurons (usually 1 hidden neuron less than PPL and HNN).

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Nugroho, Herry Prasetyo, Muhammad Irfan, and Amrul Faruq. "Software Defined Networks: a Comparative Study and Quality of Services Evaluation." Scientific Journal of Informatics 6, no. 2 (December 1, 2019): 181–92. http://dx.doi.org/10.15294/sji.v6i2.20585.

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Software-Defined Network (SDN) as architecture network that separates the control and forwarding functions, so that network operators and administrators can configure the networks in a simple and centrally between thousands of devices. This study is designed and evaluate the Quality of Services (QoS) performances between the two networks employed SDN-based architecture and without SDN-based. MinNet as a software emulator used as a data plane in the network Software Define Network. In this study, comparison of the value of the QoS on the network based on Software Defined Network and traditional network during the test run from the source node is investigated. Network testing by using traffic loads. Traffic loads are used starting from 20Mbps-100Mbps. The result is verified that the QoS analysis of the Software-Defined Network architecture performed better than conventional network architectures. The value of the latency delay on the Software Define Network range between 0,019-0,084ms, and with 0% packet loss when addressed the network traffics of 10-100Mbps.

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AGYEMAN, MICHAEL O., ALI AHMADINIA, and ALIREZA SHAHRABI. "HETEROGENEOUS 3D NETWORK-ON-CHIP ARCHITECTURES: AREA AND POWER AWARE DESIGN TECHNIQUES." Journal of Circuits, Systems and Computers 22, no. 04 (April 2013): 1350016. http://dx.doi.org/10.1142/s0218126613500163.

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Three-dimensional Network-on-Chip (3D NoC) architectures have gained a lot of popularity to solve the on-chip communication delays of next generation System-on-Chip (SoC) systems. However, the vertical interconnects of 3D NoC are expensive and complex to manufacture. Also, 3D router architecture consumes more power and occupies more area per chip floorplan compared to a 2D router. Hence, more efficient architectures should be designed. In this paper, we propose area efficient and low power 3D heterogeneous NoC architectures, which combines both the power and performance benefits of 2D routers and 3D NoC-bus hybrid router architectures in 3D NoC architectures. Experimental results show a negligible penalty (less than 5%) in average packet latency of the proposed heterogeneous 3D NoC architectures compared to typical homogeneous 3D NoCs, while the heterogeneity provides power and area efficiency of up to 61% and 19.7%, respectively.

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Strzęciwilk, Dariusz. "Examination of Transmission Quality in the IP Multi-Protocol Label Switching Corporate Networks." International Journal of Electronics and Telecommunications 58, no. 3 (September 2012): 267–72. http://dx.doi.org/10.2478/v10177-012-0037-z.

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Abstract The paper presents the examination of quality of transmission designed and built based on IP/MPLS technology as well as BGP and OSPF routing protocols of corporate network. It indicates the factors forming and affecting the service quality in IP network, including QoS support network architecture, particularly the architecture of DiffServ differentiated services. Main problems occurring in these architectures have been discussed. The analysis of data and voice transmission via IP network of Best Effort architecture and in Differentiated Service architecture of differentiated transmission quality have been conducted. It has been presented that the MPLS technology may be effectively applied in building corporate networks requiring network services of highest quality parameters with lossless packet transmission and maximum delay guarantee.

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VASSILIADIS, STAMATIS, GERALD G. PECHANEK, and JOSÉ G. DELGADO-FRIAS. "SPIN: THE SEQUENTIAL PIPELINED NEUROEMULATOR." International Journal on Artificial Intelligence Tools 02, no. 01 (March 1993): 117–32. http://dx.doi.org/10.1142/s0218213093000084.

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This paper proposes a novel digital neural network architecture referred to as the Sequential PIpelined Neuroemulator or Neurocomputer (SPIN). The SPIN processor emulates neural networks producing high performance with minimum hardware by sequentially processing each neuron in the modeled completely connected network with a pipelined physical neuron structure. In addition to describing SPIN, performance equations are estimated for the ring systolic, the recurrent systolic array, and the neuromimetic neurocomputer architectures, three previously reported schemes for the emulation of neural networks, and a comparison with the SPIN architecture is reported.

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Journal articles on the topic 'Network architectures'

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