Dissertations / Theses on the topic 'NanoMagnets Logic'

In the last decades CMOS technology has ruled the electronic scenario thanks to the constant scaling of transistor sizes. With the reduction of transistor sizes circuit area decreases, clock frequency increases and power consumption decreases accordingly. However CMOS scaling is now approaching its physical limits and many believe that CMOS technology will not be able to reach the end of the Roadmap. This is mainly due to increasing difficulties in the fabrication process, that is becoming very expensive, and to the unavoidable impact of leakage losses, particularly thanks to gate tunnel current. In this scenario many alternative technologies are studied to overcome the limitations of CMOS transistors. Among these possibilities, magnetic based technologies, like NanoMagnet Logic (NML) are among the most interesting. The reason of this interest lies in their magnetic nature, that opens up entire new possibilities in the design of logic circuits, like the possibility to mix logic and memory in the same device. Moreover they have no standby power consumption and potentially a much lower power consumption of CMOS transistors. In literature NML logic is well studied and theoretical and experimental proofs of concept were already found. However two important points are not enough considered in the analysis approach followed by most of the work in literature. First of all, no complex circuits are analyzed. NML logic is very different from CMOS technologies, so to completely understand the potential of this technology it is mandatory to investigate complex architectures. Secondly, most of the solutions proposed do not take into account the constraints derived from fabrication process, making them unrealistic and difficult to be fabricated experimentally. This thesis focuses therefore on NML logic keeping into account these two important limitations in the research approach followed in literature. The aim is to obtain a complete and accurate overview of NML logic, finding realistic circuital solutions and trying to improve at the same time their performance. After a brief and complete introduction (Chapter 1), the thesis is divided in two parts, which cover the two fundamental points followed in this three years of research: A circuits architecture analysis and a technological analysis. In the architecture analysis first an innovative VHDL model is described in Chapter 2. This model is extensively used in the analysis because it allows fast simulation of complex circuits, with, at the same time, the possibility to estimate circuit per- formance, like area and power consumption. In Chapter 3 the problem of signals synchronization in complex NML circuits is analyzed and solved, using as benchmark a simple but complete NML microprocessor. Different solutions based on asynchronous logic are studied and a new asynchronous solution, specifically designed to exploit the potential of NML logic, is developed. In Chapter 4 the layout of NML circuits is studied on a more physical level, considering the limitations of fabrication processes. The layout of NML circuits is therefore changed accordingly to these constraints. Secondly CMOS circuits architectures are compared to more simple architectures, evaluating therefore which one is more suited for NML logic. Finally the problem of interconnections in NML technology is analyzed and solutions to improve it are found. In Chapter 5 the problem of feedback signals in heavy pipelined technologies, like NML, is studied. Solutions to improve performances and synchronize signals are developed. Systolic arrays are then analyzed as possible candidate to exploit NML potential. Finally in Chapter 6 ToPoliNano, a simulator dedicated to NML and other emerging technologies, that we are developing, is described. This simulator allows to follow the same top-down approach followed for CMOS technology. The layout generator and the simulation engine are detailed described. In the first chapter of the technological analysis (Chapter 7), the performance of NML logic is explored throughout low level simulations. The aim is to understand if these circuits can be fabricated with optical lithography, allowing therefore the commercial development of NML logic. Basic logic gates and the clock system are there analyzed from a low level perspective. In Chapter 8 an innovative electric clock system for NML technology is shown and the first experimental results are reported. This clock system allows to achieve true low power for NML technology, obtaining a reduction of power consumption of 20 times considering the best CMOS transistors available. This power consumption takes into account all the losses, also the clock system losses. Moreover the solution presented can be fabricated with current technological processes. The research work behind this thesis represents an important breakthrough in NML logic. The solutions here presented allow the design and fabrication of complex NML circuits, considering the particular characteristics of this technology and considerably improving the performance. Moreover the technological solutions here presented allow the design and fabrication of circuits with available fabrication process with a considerable advantage over CMOS in terms of power consumption. This thesis represents therefore a considerable step froward in the study and development of NML technology.

Nanomagnetic logic, incorporating logic bits in the magnetization orientations of single-domain nanomagnets, has garnered attention as an alternative to transistor-based logic due to its non-volatility and unprecedented energy-efficiency. The energy efficiency of this scheme is determined by the method used to flip the magnetization orientations of the nanomagnets in response to one or more inputs and produce the desired output. Unfortunately, the large dissipative losses that occur when nanomagnets are switched with a magnetic field or spin-transfer-torque inhibit the promised energy-efficiency. Another technique offering superior energy efficiency, “straintronics”, involves the application of a voltage to a piezoelectric layer to generate a strain which is transferred to an elastically coupled magnetrostrictive layer, causing magnetization rotation. The functionality of this scheme can be enhanced further by introducing magnetocrystalline anisotropy in the magnetostrictive layer, thereby generating four stable magnetization states (instead of the two stable directions produced by shape anisotropy in ellipsoidal nanomagnets). Numerical simulations were performed to implement a low-power universal logic gate (NOR) using such 4-state magnetostrictive/piezoelectric nanomagnets (Ni/PZT) by clocking the piezoelectric layer with a small electrostatic potential (~0.2 V) to switch the magnetization of the magnetic layer. Unidirectional and reliable logic propagation in this system was also demonstrated theoretically. Besides doubling the logic density (4-state versus 2-state) for logic applications, these four-state nanomagnets can be exploited for higher order applications such as image reconstruction and recognition in the presence of noise, associative memory and neuromorphic computing. Experimental work in strain-based switching has been limited to magnets that are multi-domain or magnets where strain moves domain walls. In this work, we also demonstrate strain-based switching in 2-state single-domain ellipsoidal magnetostrictive nanomagnets of lateral dimensions ~200 nm fabricated on a piezoelectric substrate (PMN-PT) and studied using Magnetic Force Microscopy (MFM). A nanomagnetic Boolean NOT gate and unidirectional bit information propagation through a finite chain of dipole-coupled nanomagnets are also shown through strain-based "clocking". This is the first experimental demonstration of strain-based switching in nanomagnets and clocking of nanomagnetic logic (Boolean NOT gate), as well as logic propagation in an array of nanomagnets.

Excessive energy dissipation in CMOS devices during switching is the primary threat to continued downscaling of computing devices in accordance with Moore’s law. In the quest for alternatives to traditional transistor based electronics, nanomagnet-based computing [1, 2] is emerging as an attractive alternative since: (i) nanomagnets are intrinsically more energy-efficient than transistors due to the correlated switching of spins [3], and (ii) unlike transistors, magnets have no leakage and hence have no standby power dissipation. However, large energy dissipation in the clocking circuit appears to be a barrier to the realization of ultra low power logic devices with such nanomagnets. To alleviate this issue, we propose the use of a hybrid spintronics-straintronics or straintronic nanomagnetic logic (SML) paradigm. This uses a piezoelectric layer elastically coupled to an elliptically shaped magnetostrictive nanomagnetic layer for both logic [4-6] and memory [7-8] and other information processing [9-10] applications that could potentially be 2-3 orders of magnitude more energy efficient than current CMOS based devices. This dissertation focuses on studying the feasibility, performance and reliability of such nanomagnetic logic circuits by simulating the nanoscale magnetization dynamics of dipole coupled nanomagnets clocked by stress. Specifically, the topics addressed are: 1. Theoretical study of multiferroic nanomagnetic arrays laid out in specific geometric patterns to implement a “logic wire” for unidirectional information propagation and a universal logic gate [4-6]. 2. Monte Carlo simulations of the magnetization trajectories in a simple system of dipole coupled nanomagnets and NAND gate described by the Landau-Lifshitz-Gilbert (LLG) equations simulated in the presence of random thermal noise to understand the dynamics switching error [11, 12] in such devices. 3. Arriving at a lower bound for energy dissipation as a function of switching error [13] for a practical nanomagnetic logic scheme. 4. Clocking of nanomagnetic logic with surface acoustic waves (SAW) to drastically decrease the lithographic burden needed to contact each multiferroic nanomagnet while maintaining pipelined information processing. 5. Nanomagnets with four (or higher states) implemented with shape engineering. Two types of magnet that encode four states: (i) diamond, and (ii) concave nanomagnets are studied for coherence of the switching process.

The successful era of CMOS technology is coming to an end. The limit on minimum fabrication dimensions of transistors and the increasing leakage power hinder the technological scaling that has characterized the last decades. In several different ways, this problem has been addressed changing the architectures implemented in CMOS, adopting parallel processors and thus increasing the throughput at the same operating frequency. However, architectural alternatives cannot be the definitive answer to a continuous increase in performance dictated by Moore’s law. This problem must be addressed from a technological point of view. Several alternative technologies that could substitute CMOS in next years are currently under study. Among them, magnetic technologies such as NanoMagnet Logic (NML) are interesting because they do not dissipate any leakage power. More- over, magnets have memory capability, so it is possible to merge logic and memory in the same device. However, magnetic circuits, and NML in this specific research, have also some important drawbacks that need to be addressed: first, the circuit clock frequency is limited to 100 MHz, to avoid errors in data propagation; second, there is a connection between circuit layout and timing, and in particular, longer wires will have longer latency. These drawbacks are intrinsic to the technology and for this reason they cannot be avoided. The only chance is to limit their impact from an architectural point of view. The first step followed in the research path of this thesis is indeed the choice and optimization of architectures able to deal with the problems of NML. Systolic Ar- rays are identified as an ideal solution for this technology, because they are regular structures with local interconnections that limit the long latency of wires; more- over they are composed of several Processing Elements that work in parallel, thus exploit parallelization to increase throughput (limiting the impact of the low clock frequency). Through the analysis of Systolic Arrays for NML, several possible im- provements have been identified and addressed: 1) it has been defined a rigorous way to increase throughput with interleaving, providing equations that allow to esti- mate the number of operations to be interleaved and the rules to provide inputs; 2) a latency insensitive circuit has been designed, that exploits a data communication protocol between processing elements to avoid data synchronization problems. This feature has been exploited to design a latency insensitive Systolic Array that is able to execute the Floyd-Steinberg dithering algorithm. All the improvements presented in this framework apply to Systolic Arrays implemented in any technology. So, they can also be exploited to increase performance of today’s CMOS parallel circuits. This research path is presented in Chapter 3. While Systolic Arrays are an interesting solution for NML, their usage could be quite limited because they are normally application-specific. The second re- search path addresses this problem. A Reconfigurable Systolic Array is presented, that can be programmed to execute several algorithms. This architecture has been tested implementing many algorithms, including FIR and IIR filters, Discrete Cosine Transform and Matrix Multiplication. This research path is presented in Chapter 4. In common Von Neumann architectures, the logic part of the circuit and the memory one are separated. Today bus communication between logic and memory represents the bottleneck of the system. This problem is addressed presenting Logic- In-Memory (LIM), an architecture where memory elements are merged in logic ones. This research path aims at defining a real LIM architectures. This has been done in two steps. The first step is represented by an architecture composed of three layers: memory, routing and logic. In the second step instead the routing plane is no more present, and its features are inherited by the memory plane. In this solution, a pyramidal memory model is used, where memories near logic elements contain the most probably used data, and other memory layers contain the remaining data and instruction set. This circuit has been tested with odd-even sort algorithms and it has been benchmarked against GPUs and ASIC. This research path is presented in Chapter 5. MagnetoElastic NML (ME-NML) is a technological improvement of the NML principle, proposed by researchers of Politecnico di Torino, where the clock system is based on the induced stretch of a piezoelectric substrate when a voltage is ap- plied to its boundaries. The main advantage of this solution is that it consumes much less power than the classic clock implementation. This technology has not yet been investigated from an architectural point of view and considering complex circuits. In this research field, a standard methodology for the design of ME-NML circuits has been proposed. It is based on a Standard Cell Library and an enhanced VHDL model. The effectiveness of this methodology has been proved designing a Galois Field Multiplier. Moreover the serial-parallel trade-off in ME-NML has been investigated, designing three different solutions for the Multiply and Accumulate structure. This research path is presented in Chapter 6. While ME-NML is an extremely interesting technology, it needs to be combined with other faster technologies to have a real competitive system. Signal interfaces between NML and other technologies (mainly CMOS) have been rarely presented in literature. A mixed-technology multiplexer is designed and presented as the basis for a CMOS to NML interface. The reverse interface (from ME-NML to CMOS) is instead based on a sensing circuit for the Faraday effect: a change in the polarization of a magnet induces an electric field that can be used to generate an input signal for a CMOS circuit. This research path is presented in Chapter 7. The research work presented in this thesis represents a fundamental milestone in the path towards nanotechnologies. The most important achievement is the de- sign and simulation of complex circuits with NML, benchmarking this technology with real application examples. The characterization of a technology considering complex functions is a major step to be performed and that has not yet been ad- dressed in literature for NML. Indeed, only in this way it is possible to intercept in advance any weakness of NanoMagnet Logic that cannot be discovered consid- ering only small circuits. Moreover, the architectural improvements introduced in this thesis, although technology-driven, can be actually applied to any technology. We have demonstrated the advantages that can derive applying them to CMOS cir- cuits. This thesis represents therefore a major step in two directions: the first is the enhancement of NML technology; the second is a general improvement of parallel architectures and the development of the new Logic-In-Memory paradigm.

A recent International Technology Roadmap for Semiconductors (ITRS) report (2.0, 2015 edition) has shown that Moore’s law is unlikely to hold beyond 2028. There is a need for alternate devices to replace CMOS based devices, if further miniaturization and high energy efficiency is desired. The goal of this dissertation is to experimentally demonstrate the feasibility of nanomagnetic memory and logic devices that can be clocked with acoustic waves in an extremely energy efficient manner. While clocking nanomagnetic logic by stressing the magnetostrictive layer of a multiferroic logic element with with an electric field applied across the piezoelectric layer is known to be an extremely energy-efficient clocking scheme, stressing every nanomagnet separately requires individual contacts to each one of them that would necessitate cumbersome lithography. On the other hand, if all nanomagnets are stressed simultaneously with a global voltage, it will eliminate the need for individual contacts, but such a global clock makes the architecture non-pipelined (the next input bit cannot be written till the previous bit has completely propagated through the chain) and therefore, unacceptably slow and error prone. Use of global acoustic wave, that has in-built granularity, would offer the best of both worlds. As the crest and the trough propagate in space with a velocity, nanomagnets that find themselves at a crest are stressed in tension while those in the trough are compressed. All other magnets are relaxed (no stress). Thus, all magnets are not stressed simultaneously but are clocked in a sequentially manner, even though the clocking agent is global. Finally, the acoustic wave energy is distributed over billions of nanomagnets it clocks, which results in an extremely small energy cost per bit per nanomagnet. In summary, acoustic clocking of nanomagnets can lead to extremely energy efficient nanomagnetic computing devices while also eliminating the need for complex lithography. The dissertation work focuses on the following two topics: Acoustic Waves, generated by IDTs fabricated on a piezoelectric lithium niobate substrate, can be utilized to manipulate the magnetization states in elliptical Co nanomagnets. The magnetization switches from its initial single-domain state to a vortex state after SAW stress cycles propagate through the nanomagnets. The vortex states are stable and the magnetization remains in this state until it is ‘reset’ by an external magnetic field. 2. Acoustic Waves can also be utilized to induce 1800 magnetization switching in dipole coupled elliptical Co nanomagnets. The magnetization switches from its initial single-domain ‘up’ state to a single-domain ‘down’ state after SAW tensile/compressive stress cycles propagate through the nanomagnets. The switched state is stable and non-volatile. These results show the effective implementation of a Boolean NOT gate. Ultimately, the advantage of this technology is that it could also perform higher order information processing (not discussed here) while consuming extremely low power. Finally, while we have demonstrated acoustically clocked nanomagnetic memory and logic schemes with Co nanomagnets, materials with higher magnetostriction (such as FeGa) may ultimately improve the switching reliability of such devices. With this in mind we prepared and studied FeGa films using a ferromagnetic resonance (FMR) technique to extract properties of importance to magnetization dynamics in such materials that could have higher magneto elastic coupling than either Co or Ni.

Even though silicon technology is dominant today, the physics (quantum electron tunneling effect), design (power dissipation, wire delays) and the manufacturing (lithography resolution) limitations of CMOS technology are pushed towards the scaling end. These issues motivated us towards a new paradigm that contributes to a continued advancement in terms of performance, density, and cost. The magnetic field coupled computing (MFC) paradigm, which is one of the regimes where we leverage and utilize the neighbor interaction of the nanomagnets to order the single-domain magnetic cells to perform computational tasks. The most important and attractive features of this technology are: 1) room temperature operation, which has been a limitation in electrostatic field coupled devices, 2) high density and nonetheless 3) low static power dissipation. It will be intriguing to address queries like, what are the challenges posed by the technology with such exotic features? Answer to such questions would become the focus of this doctoral research. The fundamental problem with magnetic field coupled devices is the directional flow of information from input to output. In this work, we have proposed a novel spatially moving Landauer clock system for MFC nanomagnet array which has an advantage over existing adiabatic clock system. Extensive simulation studies were done to model and validate the clock for different length, size, and shape of nanomagnet array. Another key challenge is the manufacturing defect, which leads to uncertainty and unreliability issues. We studied the different dominant types of geometric defects (missing material, missing cell, spacing, bulge, and merging) in array (used as interconnects) based on our fabrication experiments. We also studied effect of these defects on different segments (locations) of the array with spatially moving clock. The study concluded that a spatially moving clock scheme constitutes a robust MFC architecture as location of defect and length of arrays does not play any role in error masking as opposed to conventional clock. Finally, the work presents the study on the 2D nanomagnet array for boolean logic computation and vision logic computation. The effect of dipole-dipole interaction on magnetization state transition in closely spaced 2D array of ferromagnetic circular nanomagnet was explored. The detailed design space to demarcate the boundary between single domain state and vortex state reveals that the single domain state space is desirable for Boolean logic computation while the space around the boundary would be appropriate for vision logic computing.

Since its inception, Moore's Law has been a reliable predictor of computational power. This steady increase in computational power has been due to the ability to fit increasing numbers of transistors in a single chip. A consequence of increasing the number of transistors is also increasing the power consumption. The physical properties of CMOS technologies will make this powerwall unavoidable and will result in severe restrictions to future progress and applications. A potential solution to the problem of rising power demands is to investigate alternative low power nanotechnologies for implementing logic circuits. The intrinsic properties of these emerging nanotechnologies result in them being low power in nature when compared to current CMOS technologies. This thesis specifically highlights quantum dot celluar automata (QCA) and nanomagnetic logic (NML) as just two possible technologies. Designs in NML and QCA are explored for simple arithmetic units such as full adders and subtractors. A new multilayer 5-input majority gate design is proposed for use in NML. Designs of reversible adders are proposed which are easily testable for unidirectional stuck at faults.

Complementary metal-oxide semiconductor (CMOS) technology has driven the electronic scenario for the last 40 years. The exponential grow of computing power implicates technological challenges, such as scaling transistor sizes, increasing clock frequency and reducing the power consumption. These goals raise dramatically the manufacturing cost with every new technology node. The projections of the ITRS roadmap report tell us that the scaling will be also influenced by fundamental physical limits. These observations have stimulated researchers from industry and academia to investigate possible feasible alternatives to CMOS technology. Since at the time of writing is difficult to find a clear winner, many possibilities are studied. They are based on different computational variables such as charge controlled (i.e. transistors) or magnetic field controlled devices. But, all of them have three aspects in common: i) the manufacturing process is still not mature, so they have to deal with a high defect rate; ii) the high density expected from these new devices arise problems related to the design automation field; iii) currently no tools, specifically targeted for emerging devices, are available on the market that allow researchers to investigate these technologies. In fact, it is rather difficult to find a toolchain of existing software able to provide a complete design flow from nanodevice simulation to floorplanning, place and route, and nanoarchitecture simulation and evaluation, able to handle emerging devices related constraints. This manuscript focuses on the development of a CAD tool for nanotechnologies, named ToPoliNano. It has the ability, starting from the VHDL description of the circuit, to automatically generate the physical layout choosing a target nanotechnology. At the time of writing two technologies are supported: silicon nanorrays and in-plane NanoMagnetic Logic. After the layout phase, the user can simulate the circuit behavior with an integrated simulation engine. In this work, three beyond CMOS technologies are investigated and analyzed from an architectural point of view. The first one is based on silicon nanoarrays, the last two come from the Quantum dot Cellular Automata (QCA) family, the in-plane Nano Magnetic Logic (iNML) and the perpendicular Nano Magnetic Logic (pNML). The aim of this thesis is to analyze the layout constrains of these emerging technologies making an architectural exploration. The investigation and the benchmarking is enabled thanks to ToPoliNano, which has been enriched, during my PhD, of a place and route engine and a fault injection mechanism to verify circuits robustness. These features implementation will be discussed more in detail respectively in part 2 and 1. After a brief technological background provided in the introduction, the thesis is divided in three main parts dedicated to the three technologies analyzed: silicon nanoarray, iNML and pNML. In part 1 the high defect rate of silicon nanoarray technology is discussed and analyzed in order to find a method to design more reliable circuits. A new methodology has been developed and tested through our CAD tool ToPoliNano. Fault tolerant circuits have been tested injecting different fault maps and evaluating the output error rate and yield. In part 2, the main working structure of the layout engine and the layout constraints of iNML technology are introduced. In part 2, first the main working principle and the layout constrains are presented to the reader. Then, a detailed description of the design flow implemented in ToPoliNano will be presented. The place and route engine implemented in ToPoliNano will be analyzed and described in detail with examples. The algorithms are compared and results are provided in the last part of this section. In the last part, the pNML technology will be analyzed. In particular, this work has been done in collaboration with the Lehrstuhl für Technische Elektronik (LTE) institute at the Technical University of Munich (TUM). Here, after a brief introduction about the up to date fabrication process, some experimental data are presented in order to extract useful information for developing a drawing tool. The idea is to design a drawing tool that enables the final user to design 3D pNML based circuits. The tool should embed data collected from experiments and it should able to automatically export the VHDL file that described the drawn architecture. In this way, the behavior and the correctness of the circuit can be verified using Modelsim simulator from Mentor Graphics. However, this part of the thesis in currently under development. Thus, only an overview of the whole flow will be provided.

Research in future generation computing is focused on reducing energy dissipation while maintaining the switching speed in a binary operation to continue the current trend of increasing transistor-density according to Moore’s law. Unlike charge-based CMOS technology, spin-based nanomagnetic technology, based on switching bistable magnetization of single domain shape-anisotropic nanomagnets, has the potential to achieve ultralow energy dissipation due to the fact that no charge motion is directly involved in switching. However, switching of magnetization has not been any less dissipative than switching transistors because most magnet switching schemes involve generating a current to produce a magnetic field, or spin transfer torque or domain wall motion to switch magnetization. Current-induced switching invariably dissipates an exorbitant amount of energy in the switching circuit that nullifies any energy advantage that a magnet may have over a transistor. Magnetoelastic switching (switching the magnetization of a magnetostrictive magnet with voltage generated stress) is an unusual switching paradigm where the dissipation turns out to be merely few hundred kT per switching event – several orders of magnitude less than that encountered in current-based switching. A fundamental obstacle, though, is to deterministically switch the magnetization of a nanomagnet between two stable states that are mutually anti-parallel with stress alone. In this work, I have investigated ways to mitigate this problem. One popular approach to flip the magnetizations of a nanomagnet is to pass a spin polarized current through it that transfers spin angular moment from the current to the electrons in the magnet, thereby switching their spins and ultimately the magnet’s magnetization. This approach – known as spin transfer torque (STT) – is very dissipative because of the enormous current densities needed to switch magnets, We, therefore, devised a mixed mode technique to switch magnetization with a combination of STT and stress to gain both energy efficiency from stress and deterministic 180o switching from STT. This approach reduces the total energy dissipation by roughly one order of magnitude. We then extended this idea to find a way to deterministically flip magnetization with stress alone. Sequentially applying stresses along two skewed axes, a complete 180o switching can be achieved. These results have been verified with stochastic Landau-Lifshitz-Gilbert simulation in the presence of thermal noise. The 180o switching makes it possible to develop a genre of magneto-elastic memory where bits are written entirely with voltage generated stress with no current flow. They are extremely energy-efficient. In addition to memory devices, a universal NAND logic device has been proposed which satisfies all the essential characteristics of a Boolean logic gate. It is non-volatile unlike transistor based logic gates in the sense that that gate can process binary inputs and store the output (result) in the magnetization states of magnets, thereby doubling as both logic and memory. Such dual role elements can spawn non-traditional non-von-Neumann architectures without the processor and memory partition that reduces energy efficiency and introduces additional errors. A bit comparator is also designed, which happens to be all straintronic, yet reconfigurable. Moreover, a straintronic spin neuron is designed for neural computing architecture that dissipates orders of magnitude less energy than its CMOS based counterparts. Finally, an experiment has been performed to demonstrate a complete 180o switching of magnetization in a shape anisotropic magnetostrictive Co nanomagnet using voltage generated stress. The device is synthesized with nano-fabrication techniques namely electron beam lithography, electron beam evaporation, and lift off. The experimental results vindicate our proposal of applying sequential stress along two skewed axes to reverse magnetization with stress and therefore, provide a firm footing to magneto-elastic memory technology.

For many years, the transistors placement was not limited by interconnections thanks to the Digital Integrated Circuits market that is changing from a situation where CMOS technology was the reference (microelectronics era) to a plurality of emerging technologies (nanoelectronics era). The costs of optics photolithography needed to produce the recent CMOS technologies are increasing to such an extent as to make interesting the exploration of nanoelectronics alternative solutions. These technologies are called beyond CMOS technologies. Among the application fields, Information Security is one of the most pioneering rising market: several application areas need to ensure confidentiality and authenticity of data through cryptographic solutions. In some cases, cryptographic primitives can benefit a strong hardware acceleration. Unfortunately, CMOS based systems are vulnerable to ageing factors, such as Electromigration which decreases the reliability of certain security properties, and to Side-Channel attacks, where an attacker can retrieve confidential information by observing the power consumption. In this scenario, it is possible to speculate that emerging nanotechnologies can be exploited to cover the gaps left uncovered by CMOS technologies. A sub-class of circuits based on this novel techno- logical approach are called Dynamically-Coupled Systems (DCS). These novel technologies go beyond the transistor-interconnection dichotomy: elaboration, storage and transmission functions are all performed by the same device. DCS building blocks are called Processing Elements (PE). Interconnections are replaced with PE chains that are intrinsically pipelined. Ideally, it is possible to divide DCS technologies in two conventional sub-classes: Electrical-Coupled Technologies (ECT) where information propagation is due to electrons flow across ohmic paths and Field-Coupled Technologies (FCT). In FCT both the propagation and the elaboration of data depends on the electromagnetic field in- teractions (coupling) among PEs. An interesting possibility is offered by the use of single domain nanomagnets. Rectangular shaped magnets, with sizes smaller than 100nm, demonstrate a bistable behavior. This principle has been exploited to design digital logic circuits, leading to the so-called NanoMagnet Logic. The energy landscape of a single domain nanomagnet has two minimums corresponding to the magnetization vector aligned along the longer magnet side. If an ideal magnet is forced in the metastable state (i.e. the peak in the energy landscape), the probability that the magnet will reach one of the two stable states is exactly 0.5. The presented work proposes a plurality of development environments employable to study and design Dynamical-Coupled Nanocomputing digital circuits based on both a bottom-up approach for “fast prototyping” and a top-down one for complex circuits development environment. By means of the presented tools, it has been possible to study a series of Arithmetic and Cryptographic architectures, to perform circuit performance analysis and to highlight how the Modular Arithmetic offers a substantial contribution to the Field-Coupled Nanotechnologies interconnections overhead issue.

Thesis (Ph. D.)--University of Notre Dame, 2005.
Thesis directed by Wolfgang Porod and Gary H. Bernstein for the Department of Electrical Engineering. "April 2005." Includes bibliographical references (leaves 93-97).

With the aggressive scaling of complementary metal-oxide semiconductor (CMOS) nearing an inevitable physical limit and its well-known power crisis, the quest for an alternative/augmenting technology that surpasses the current semiconductor electronics is needed for further technological progress. Spintronic devices emerge as prime candidates for Beyond CMOS era by utilizing the electron spin as an extra degree of freedom to decrease the power consumption and overcome the velocity limit connected with the charge. By using the nonvolatility nature of magnetization along with its direction to represent a bit of information and then manipulating it by spin-polarized currents, routes are opened for combined memory and logic. This would not have been possible without the recent discoveries in the physics of nanomagnetism such as spin-transfer torque (STT) whereby a spin-polarized current can excite magnetization dynamics through the transfer of spin angular momentum. STT have expanded the available means of switching the magnetization of magnetic layers beyond old classical techniques, promising to fulfill the need for a new generation of dense, fast, and nonvolatile logic and storage devices. All-spin logic (ASL) is among the most promising spintronic logic switches due to its low power consumption, logic-in-memory structure, and operation on pure spin currents. The device is based on a lateral nonlocal spin valve and STT switching. It utilizes two nanomagnets (whereby information is stored) that communicate with pure spin currents through a spin-coherent nonmagnetic channel. By using the well-known spin physics and the recently proposed four-component spin circuit formalism, ASL can be thoroughly studied and simulated. Previous attempts to model ASL in the linear and diffusive regime either neglect the dynamic characteristics of transport or do not provide a scalable and robust platform for full micromagnetic simulations and inclusion of other effects like spin Hall effect and spin-orbit torque. In this thesis, we propose an improved stochastic magnetization dynamics/time-dependent spin transport model based on a finite-difference scheme of both the temporal and spatial derivatives to capture the key features of ASL. The approach yields new finite-difference conductance matrices, which, in addition to recovering the steady-state results, captures the dynamic behavior. The new conductance matrices are general in that the discretization framework can be readily applied and extended to other spintronic devices. Also, we provide a stable algorithm that can be used to simulate a generic ASL switch using the developed model.