Relevant bibliographies by topics / NanoMagnets Logic

Academic literature on the topic 'NanoMagnets Logic'

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Published: 14 March 2023

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Journal articles on the topic "NanoMagnets Logic"

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Xueming Ju, S. Wartenburg, J. Rezgani, M. Becherer, J. Kiermaier, S. Breitkreutz, D. Schmitt-Landsiedel, W. Porod, P. Lugli, and G. Csaba. "Nanomagnet Logic from Partially Irradiated Co/Pt Nanomagnets." IEEE Transactions on Nanotechnology 11, no. 1 (January 2012): 97–104. http://dx.doi.org/10.1109/tnano.2011.2157974.

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Atulasimha, J., and S. Bandyopadhyay. "Bennett clocking of nanomagnetic logic using multiferroic single-domain nanomagnets." Applied Physics Letters 97, no. 17 (October 25, 2010): 173105. http://dx.doi.org/10.1063/1.3506690.

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Luo, Zhaochu, Trong Phuong Dao, Aleš Hrabec, Jaianth Vijayakumar, Armin Kleibert, Manuel Baumgartner, Eugenie Kirk, et al. "Chirally coupled nanomagnets." Science 363, no. 6434 (March 28, 2019): 1435–39. http://dx.doi.org/10.1126/science.aau7913.

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Magnetically coupled nanomagnets have multiple applications in nonvolatile memories, logic gates, and sensors. The most effective couplings have been found to occur between the magnetic layers in a vertical stack. We achieved strong coupling of laterally adjacent nanomagnets using the interfacial Dzyaloshinskii-Moriya interaction. This coupling is mediated by chiral domain walls between out-of-plane and in-plane magnetic regions and dominates the behavior of nanomagnets below a critical size. We used this concept to realize lateral exchange bias, field-free current-induced switching between multistate magnetic configurations as well as synthetic antiferromagnets, skyrmions, and artificial spin ices covering a broad range of length scales and topologies. Our work provides a platform to design arrays of correlated nanomagnets and to achieve all-electric control of planar logic gates and memory devices.
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Li, Peng, Gyorgy Csaba, Vijay K. Sankar, Xueming Ju, Edit Varga, Paolo Lugli, X. Sharon Hu, Michael Niemier, Wolfgang Porod, and Gary H. Bernstein. "Direct Measurement of Magnetic Coupling Between Nanomagnets for Nanomagnetic Logic Applications." IEEE Transactions on Magnetics 48, no. 11 (November 2012): 4402–5. http://dx.doi.org/10.1109/tmag.2012.2202219.

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Lambson, Brian, Zheng Gu, Morgan Monroe, Scott Dhuey, Andreas Scholl, and Jeffrey Bokor. "Concave nanomagnets: investigation of anisotropy properties and applications to nanomagnetic logic." Applied Physics A 111, no. 2 (March 27, 2013): 413–21. http://dx.doi.org/10.1007/s00339-013-7654-y.

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Shah, Faisal A., Gyorgy Csaba, Katherine Butler, and Gary H. Bernstein. "Closely spaced nanomagnets by dual e-beam exposure for low-energy nanomagnet logic." Journal of Applied Physics 113, no. 17 (May 7, 2013): 17B904. http://dx.doi.org/10.1063/1.4794362.

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Ding, J., and A. O. Adeyeye. "Ni80Fe20/Ni binary nanomagnets for logic applications." Applied Physics Letters 101, no. 10 (September 3, 2012): 103117. http://dx.doi.org/10.1063/1.4751259.

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Arava, Hanu, Peter M. Derlet, Jaianth Vijayakumar, Jizhai Cui, Nicholas S. Bingham, Armin Kleibert, and Laura J. Heyderman. "Computational logic with square rings of nanomagnets." Nanotechnology 29, no. 26 (May 3, 2018): 265205. http://dx.doi.org/10.1088/1361-6528/aabbc3.

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Turvani, Giovanna, Laura D’Alessandro, and Marco Vacca. "Physical Simulations of High Speed and Low Power NanoMagnet Logic Circuits." Journal of Low Power Electronics and Applications 8, no. 4 (October 8, 2018): 37. http://dx.doi.org/10.3390/jlpea8040037.

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Among all “beyond CMOS” solutions currently under investigation, nanomagnetic logic (NML) technology is considered to be one of the most promising. In this technology, nanoscale magnets are rectangularly shaped and are characterized by the intrinsic capability of enabling logic and memory functions in the same device. The design of logic architectures is accomplished by the use of a clocking mechanism that is needed to properly propagate information. Previous works demonstrated that the magneto-elastic effect can be exploited to implement the clocking mechanism by altering the magnetization of magnets. With this paper, we present a novel clocking mechanism enabling the independent control of each single nanodevice exploiting the magneto-elastic effect and enabling high-speed NML circuits. We prove the effectiveness of this approach by performing several micromagnetic simulations. We characterized a chain of nanomagnets in different conditions (e.g., different distance among cells, different electrical fields, and different magnet geometries). This solution improves NML, the reliability of circuits, the fabrication process, and the operating frequency of circuits while keeping the energy consumption at an extremely low level.
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Yilmaz, Yalcin, and Pinaki Mazumder. "Nonvolatile Nanopipelining Logic Using Multiferroic Single-Domain Nanomagnets." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 21, no. 7 (July 2013): 1181–88. http://dx.doi.org/10.1109/tvlsi.2012.2205594.

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Dissertations / Theses on the topic "NanoMagnets Logic"

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VACCA, MARCO. "Emerging Technologies - NanoMagnets Logic (NML)." Doctoral thesis, Politecnico di Torino, 2013. http://hdl.handle.net/11583/2507366.

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In the last decades CMOS technology has ruled the electronic scenario thanks to the constant scaling of transistor sizes. With the reduction of transistor sizes circuit area decreases, clock frequency increases and power consumption decreases accordingly. However CMOS scaling is now approaching its physical limits and many believe that CMOS technology will not be able to reach the end of the Roadmap. This is mainly due to increasing difficulties in the fabrication process, that is becoming very expensive, and to the unavoidable impact of leakage losses, particularly thanks to gate tunnel current. In this scenario many alternative technologies are studied to overcome the limitations of CMOS transistors. Among these possibilities, magnetic based technologies, like NanoMagnet Logic (NML) are among the most interesting. The reason of this interest lies in their magnetic nature, that opens up entire new possibilities in the design of logic circuits, like the possibility to mix logic and memory in the same device. Moreover they have no standby power consumption and potentially a much lower power consumption of CMOS transistors. In literature NML logic is well studied and theoretical and experimental proofs of concept were already found. However two important points are not enough considered in the analysis approach followed by most of the work in literature. First of all, no complex circuits are analyzed. NML logic is very different from CMOS technologies, so to completely understand the potential of this technology it is mandatory to investigate complex architectures. Secondly, most of the solutions proposed do not take into account the constraints derived from fabrication process, making them unrealistic and difficult to be fabricated experimentally. This thesis focuses therefore on NML logic keeping into account these two important limitations in the research approach followed in literature. The aim is to obtain a complete and accurate overview of NML logic, finding realistic circuital solutions and trying to improve at the same time their performance. After a brief and complete introduction (Chapter 1), the thesis is divided in two parts, which cover the two fundamental points followed in this three years of research: A circuits architecture analysis and a technological analysis. In the architecture analysis first an innovative VHDL model is described in Chapter 2. This model is extensively used in the analysis because it allows fast simulation of complex circuits, with, at the same time, the possibility to estimate circuit per- formance, like area and power consumption. In Chapter 3 the problem of signals synchronization in complex NML circuits is analyzed and solved, using as benchmark a simple but complete NML microprocessor. Different solutions based on asynchronous logic are studied and a new asynchronous solution, specifically designed to exploit the potential of NML logic, is developed. In Chapter 4 the layout of NML circuits is studied on a more physical level, considering the limitations of fabrication processes. The layout of NML circuits is therefore changed accordingly to these constraints. Secondly CMOS circuits architectures are compared to more simple architectures, evaluating therefore which one is more suited for NML logic. Finally the problem of interconnections in NML technology is analyzed and solutions to improve it are found. In Chapter 5 the problem of feedback signals in heavy pipelined technologies, like NML, is studied. Solutions to improve performances and synchronize signals are developed. Systolic arrays are then analyzed as possible candidate to exploit NML potential. Finally in Chapter 6 ToPoliNano, a simulator dedicated to NML and other emerging technologies, that we are developing, is described. This simulator allows to follow the same top-down approach followed for CMOS technology. The layout generator and the simulation engine are detailed described. In the first chapter of the technological analysis (Chapter 7), the performance of NML logic is explored throughout low level simulations. The aim is to understand if these circuits can be fabricated with optical lithography, allowing therefore the commercial development of NML logic. Basic logic gates and the clock system are there analyzed from a low level perspective. In Chapter 8 an innovative electric clock system for NML technology is shown and the first experimental results are reported. This clock system allows to achieve true low power for NML technology, obtaining a reduction of power consumption of 20 times considering the best CMOS transistors available. This power consumption takes into account all the losses, also the clock system losses. Moreover the solution presented can be fabricated with current technological processes. The research work behind this thesis represents an important breakthrough in NML logic. The solutions here presented allow the design and fabrication of complex NML circuits, considering the particular characteristics of this technology and considerably improving the performance. Moreover the technological solutions here presented allow the design and fabrication of circuits with available fabrication process with a considerable advantage over CMOS in terms of power consumption. This thesis represents therefore a considerable step froward in the study and development of NML technology.
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D'Souza, Noel. "APPLICATIONS OF 4-STATE NANOMAGNETIC LOGIC USING MULTIFERROIC NANOMAGNETS POSSESSING BIAXIAL MAGNETOCRYSTALLINE ANISOTROPY AND EXPERIMENTS ON 2-STATE MULTIFERROIC NANOMAGNETIC LOGIC." VCU Scholars Compass, 2014. http://scholarscompass.vcu.edu/etd/3539.

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Nanomagnetic logic, incorporating logic bits in the magnetization orientations of single-domain nanomagnets, has garnered attention as an alternative to transistor-based logic due to its non-volatility and unprecedented energy-efficiency. The energy efficiency of this scheme is determined by the method used to flip the magnetization orientations of the nanomagnets in response to one or more inputs and produce the desired output. Unfortunately, the large dissipative losses that occur when nanomagnets are switched with a magnetic field or spin-transfer-torque inhibit the promised energy-efficiency. Another technique offering superior energy efficiency, “straintronics”, involves the application of a voltage to a piezoelectric layer to generate a strain which is transferred to an elastically coupled magnetrostrictive layer, causing magnetization rotation. The functionality of this scheme can be enhanced further by introducing magnetocrystalline anisotropy in the magnetostrictive layer, thereby generating four stable magnetization states (instead of the two stable directions produced by shape anisotropy in ellipsoidal nanomagnets). Numerical simulations were performed to implement a low-power universal logic gate (NOR) using such 4-state magnetostrictive/piezoelectric nanomagnets (Ni/PZT) by clocking the piezoelectric layer with a small electrostatic potential (~0.2 V) to switch the magnetization of the magnetic layer. Unidirectional and reliable logic propagation in this system was also demonstrated theoretically. Besides doubling the logic density (4-state versus 2-state) for logic applications, these four-state nanomagnets can be exploited for higher order applications such as image reconstruction and recognition in the presence of noise, associative memory and neuromorphic computing. Experimental work in strain-based switching has been limited to magnets that are multi-domain or magnets where strain moves domain walls. In this work, we also demonstrate strain-based switching in 2-state single-domain ellipsoidal magnetostrictive nanomagnets of lateral dimensions ~200 nm fabricated on a piezoelectric substrate (PMN-PT) and studied using Magnetic Force Microscopy (MFM). A nanomagnetic Boolean NOT gate and unidirectional bit information propagation through a finite chain of dipole-coupled nanomagnets are also shown through strain-based "clocking". This is the first experimental demonstration of strain-based switching in nanomagnets and clocking of nanomagnetic logic (Boolean NOT gate), as well as logic propagation in an array of nanomagnets.
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Fashami, Mohammad Salehi. "MULTIFERROIC NANOMAGNETIC LOGIC: HYBRID SPINTRONICS-STRAINTRONIC PARADIGM FOR ULTRA-LOW ENERGY COMPUTING." VCU Scholars Compass, 2014. http://scholarscompass.vcu.edu/etd/3520.

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Excessive energy dissipation in CMOS devices during switching is the primary threat to continued downscaling of computing devices in accordance with Moore’s law. In the quest for alternatives to traditional transistor based electronics, nanomagnet-based computing [1, 2] is emerging as an attractive alternative since: (i) nanomagnets are intrinsically more energy-efficient than transistors due to the correlated switching of spins [3], and (ii) unlike transistors, magnets have no leakage and hence have no standby power dissipation. However, large energy dissipation in the clocking circuit appears to be a barrier to the realization of ultra low power logic devices with such nanomagnets. To alleviate this issue, we propose the use of a hybrid spintronics-straintronics or straintronic nanomagnetic logic (SML) paradigm. This uses a piezoelectric layer elastically coupled to an elliptically shaped magnetostrictive nanomagnetic layer for both logic [4-6] and memory [7-8] and other information processing [9-10] applications that could potentially be 2-3 orders of magnitude more energy efficient than current CMOS based devices. This dissertation focuses on studying the feasibility, performance and reliability of such nanomagnetic logic circuits by simulating the nanoscale magnetization dynamics of dipole coupled nanomagnets clocked by stress. Specifically, the topics addressed are: 1. Theoretical study of multiferroic nanomagnetic arrays laid out in specific geometric patterns to implement a “logic wire” for unidirectional information propagation and a universal logic gate [4-6]. 2. Monte Carlo simulations of the magnetization trajectories in a simple system of dipole coupled nanomagnets and NAND gate described by the Landau-Lifshitz-Gilbert (LLG) equations simulated in the presence of random thermal noise to understand the dynamics switching error [11, 12] in such devices. 3. Arriving at a lower bound for energy dissipation as a function of switching error [13] for a practical nanomagnetic logic scheme. 4. Clocking of nanomagnetic logic with surface acoustic waves (SAW) to drastically decrease the lithographic burden needed to contact each multiferroic nanomagnet while maintaining pipelined information processing. 5. Nanomagnets with four (or higher states) implemented with shape engineering. Two types of magnet that encode four states: (i) diamond, and (ii) concave nanomagnets are studied for coherence of the switching process.
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CAUSAPRUNO, GIOVANNI. "Architectural Solutions for NanoMagnet Logic." Doctoral thesis, Politecnico di Torino, 2016. http://hdl.handle.net/11583/2643285.

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The successful era of CMOS technology is coming to an end. The limit on minimum fabrication dimensions of transistors and the increasing leakage power hinder the technological scaling that has characterized the last decades. In several different ways, this problem has been addressed changing the architectures implemented in CMOS, adopting parallel processors and thus increasing the throughput at the same operating frequency. However, architectural alternatives cannot be the definitive answer to a continuous increase in performance dictated by Moore’s law. This problem must be addressed from a technological point of view. Several alternative technologies that could substitute CMOS in next years are currently under study. Among them, magnetic technologies such as NanoMagnet Logic (NML) are interesting because they do not dissipate any leakage power. More- over, magnets have memory capability, so it is possible to merge logic and memory in the same device. However, magnetic circuits, and NML in this specific research, have also some important drawbacks that need to be addressed: first, the circuit clock frequency is limited to 100 MHz, to avoid errors in data propagation; second, there is a connection between circuit layout and timing, and in particular, longer wires will have longer latency. These drawbacks are intrinsic to the technology and for this reason they cannot be avoided. The only chance is to limit their impact from an architectural point of view. The first step followed in the research path of this thesis is indeed the choice and optimization of architectures able to deal with the problems of NML. Systolic Ar- rays are identified as an ideal solution for this technology, because they are regular structures with local interconnections that limit the long latency of wires; more- over they are composed of several Processing Elements that work in parallel, thus exploit parallelization to increase throughput (limiting the impact of the low clock frequency). Through the analysis of Systolic Arrays for NML, several possible im- provements have been identified and addressed: 1) it has been defined a rigorous way to increase throughput with interleaving, providing equations that allow to esti- mate the number of operations to be interleaved and the rules to provide inputs; 2) a latency insensitive circuit has been designed, that exploits a data communication protocol between processing elements to avoid data synchronization problems. This feature has been exploited to design a latency insensitive Systolic Array that is able to execute the Floyd-Steinberg dithering algorithm. All the improvements presented in this framework apply to Systolic Arrays implemented in any technology. So, they can also be exploited to increase performance of today’s CMOS parallel circuits. This research path is presented in Chapter 3. While Systolic Arrays are an interesting solution for NML, their usage could be quite limited because they are normally application-specific. The second re- search path addresses this problem. A Reconfigurable Systolic Array is presented, that can be programmed to execute several algorithms. This architecture has been tested implementing many algorithms, including FIR and IIR filters, Discrete Cosine Transform and Matrix Multiplication. This research path is presented in Chapter 4. In common Von Neumann architectures, the logic part of the circuit and the memory one are separated. Today bus communication between logic and memory represents the bottleneck of the system. This problem is addressed presenting Logic- In-Memory (LIM), an architecture where memory elements are merged in logic ones. This research path aims at defining a real LIM architectures. This has been done in two steps. The first step is represented by an architecture composed of three layers: memory, routing and logic. In the second step instead the routing plane is no more present, and its features are inherited by the memory plane. In this solution, a pyramidal memory model is used, where memories near logic elements contain the most probably used data, and other memory layers contain the remaining data and instruction set. This circuit has been tested with odd-even sort algorithms and it has been benchmarked against GPUs and ASIC. This research path is presented in Chapter 5. MagnetoElastic NML (ME-NML) is a technological improvement of the NML principle, proposed by researchers of Politecnico di Torino, where the clock system is based on the induced stretch of a piezoelectric substrate when a voltage is ap- plied to its boundaries. The main advantage of this solution is that it consumes much less power than the classic clock implementation. This technology has not yet been investigated from an architectural point of view and considering complex circuits. In this research field, a standard methodology for the design of ME-NML circuits has been proposed. It is based on a Standard Cell Library and an enhanced VHDL model. The effectiveness of this methodology has been proved designing a Galois Field Multiplier. Moreover the serial-parallel trade-off in ME-NML has been investigated, designing three different solutions for the Multiply and Accumulate structure. This research path is presented in Chapter 6. While ME-NML is an extremely interesting technology, it needs to be combined with other faster technologies to have a real competitive system. Signal interfaces between NML and other technologies (mainly CMOS) have been rarely presented in literature. A mixed-technology multiplexer is designed and presented as the basis for a CMOS to NML interface. The reverse interface (from ME-NML to CMOS) is instead based on a sensing circuit for the Faraday effect: a change in the polarization of a magnet induces an electric field that can be used to generate an input signal for a CMOS circuit. This research path is presented in Chapter 7. The research work presented in this thesis represents a fundamental milestone in the path towards nanotechnologies. The most important achievement is the de- sign and simulation of complex circuits with NML, benchmarking this technology with real application examples. The characterization of a technology considering complex functions is a major step to be performed and that has not yet been ad- dressed in literature for NML. Indeed, only in this way it is possible to intercept in advance any weakness of NanoMagnet Logic that cannot be discovered consid- ering only small circuits. Moreover, the architectural improvements introduced in this thesis, although technology-driven, can be actually applied to any technology. We have demonstrated the advantages that can derive applying them to CMOS cir- cuits. This thesis represents therefore a major step in two directions: the first is the enhancement of NML technology; the second is a general improvement of parallel architectures and the development of the new Logic-In-Memory paradigm.
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Sampath, Vimal G. "ULTRA–LOW POWER STRAINTRONIC NANOMAGNETIC COMPUTING WITH SAW WAVES: AN EXPERIMENTAL STUDY OF SAW INDUCED MAGNETIZATION SWITCHING AND PROPERTIES OF MAGNETIC NANOSTRUCTURES." VCU Scholars Compass, 2016. http://scholarscompass.vcu.edu/etd/4617.

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A recent International Technology Roadmap for Semiconductors (ITRS) report (2.0, 2015 edition) has shown that Moore’s law is unlikely to hold beyond 2028. There is a need for alternate devices to replace CMOS based devices, if further miniaturization and high energy efficiency is desired. The goal of this dissertation is to experimentally demonstrate the feasibility of nanomagnetic memory and logic devices that can be clocked with acoustic waves in an extremely energy efficient manner. While clocking nanomagnetic logic by stressing the magnetostrictive layer of a multiferroic logic element with with an electric field applied across the piezoelectric layer is known to be an extremely energy-efficient clocking scheme, stressing every nanomagnet separately requires individual contacts to each one of them that would necessitate cumbersome lithography. On the other hand, if all nanomagnets are stressed simultaneously with a global voltage, it will eliminate the need for individual contacts, but such a global clock makes the architecture non-pipelined (the next input bit cannot be written till the previous bit has completely propagated through the chain) and therefore, unacceptably slow and error prone. Use of global acoustic wave, that has in-built granularity, would offer the best of both worlds. As the crest and the trough propagate in space with a velocity, nanomagnets that find themselves at a crest are stressed in tension while those in the trough are compressed. All other magnets are relaxed (no stress). Thus, all magnets are not stressed simultaneously but are clocked in a sequentially manner, even though the clocking agent is global. Finally, the acoustic wave energy is distributed over billions of nanomagnets it clocks, which results in an extremely small energy cost per bit per nanomagnet. In summary, acoustic clocking of nanomagnets can lead to extremely energy efficient nanomagnetic computing devices while also eliminating the need for complex lithography. The dissertation work focuses on the following two topics: Acoustic Waves, generated by IDTs fabricated on a piezoelectric lithium niobate substrate, can be utilized to manipulate the magnetization states in elliptical Co nanomagnets. The magnetization switches from its initial single-domain state to a vortex state after SAW stress cycles propagate through the nanomagnets. The vortex states are stable and the magnetization remains in this state until it is ‘reset’ by an external magnetic field. 2. Acoustic Waves can also be utilized to induce 1800 magnetization switching in dipole coupled elliptical Co nanomagnets. The magnetization switches from its initial single-domain ‘up’ state to a single-domain ‘down’ state after SAW tensile/compressive stress cycles propagate through the nanomagnets. The switched state is stable and non-volatile. These results show the effective implementation of a Boolean NOT gate. Ultimately, the advantage of this technology is that it could also perform higher order information processing (not discussed here) while consuming extremely low power. Finally, while we have demonstrated acoustically clocked nanomagnetic memory and logic schemes with Co nanomagnets, materials with higher magnetostriction (such as FeGa) may ultimately improve the switching reliability of such devices. With this in mind we prepared and studied FeGa films using a ferromagnetic resonance (FMR) technique to extract properties of importance to magnetization dynamics in such materials that could have higher magneto elastic coupling than either Co or Ni.
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Kiermaier, Josef [Verfasser]. "Integrated Nanomagnetic Logic System in Perpendicular Magnetic Media / Josef Kiermaier." Aachen : Shaker, 2014. http://d-nb.info/1049380894/34.

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Kumari, Anita. "Design Issues in Magnetic Field Coupled Array: Clock Structure, Fabrication Defects and Dipolar Coupling." Scholar Commons, 2011. http://scholarcommons.usf.edu/etd/3194.

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Even though silicon technology is dominant today, the physics (quantum electron tunneling effect), design (power dissipation, wire delays) and the manufacturing (lithography resolution) limitations of CMOS technology are pushed towards the scaling end. These issues motivated us towards a new paradigm that contributes to a continued advancement in terms of performance, density, and cost. The magnetic field coupled computing (MFC) paradigm, which is one of the regimes where we leverage and utilize the neighbor interaction of the nanomagnets to order the single-domain magnetic cells to perform computational tasks. The most important and attractive features of this technology are: 1) room temperature operation, which has been a limitation in electrostatic field coupled devices, 2) high density and nonetheless 3) low static power dissipation. It will be intriguing to address queries like, what are the challenges posed by the technology with such exotic features? Answer to such questions would become the focus of this doctoral research. The fundamental problem with magnetic field coupled devices is the directional flow of information from input to output. In this work, we have proposed a novel spatially moving Landauer clock system for MFC nanomagnet array which has an advantage over existing adiabatic clock system. Extensive simulation studies were done to model and validate the clock for different length, size, and shape of nanomagnet array. Another key challenge is the manufacturing defect, which leads to uncertainty and unreliability issues. We studied the different dominant types of geometric defects (missing material, missing cell, spacing, bulge, and merging) in array (used as interconnects) based on our fabrication experiments. We also studied effect of these defects on different segments (locations) of the array with spatially moving clock. The study concluded that a spatially moving clock scheme constitutes a robust MFC architecture as location of defect and length of arrays does not play any role in error masking as opposed to conventional clock. Finally, the work presents the study on the 2D nanomagnet array for boolean logic computation and vision logic computation. The effect of dipole-dipole interaction on magnetization state transition in closely spaced 2D array of ferromagnetic circular nanomagnet was explored. The detailed design space to demarcate the boundary between single domain state and vortex state reveals that the single domain state space is desirable for Boolean logic computation while the space around the boundary would be appropriate for vision logic computing.
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Becherer, Markus [Verfasser]. "Nanomagnetic Logic in Focused Ion Beam Engineered Co/Pt Multilayer Films / Markus Becherer." Aachen : Shaker, 2011. http://d-nb.info/1072592673/34.

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GNOLI, LUCA. "Exploring logic-in-memory architectures with skyrmion technology." Doctoral thesis, Politecnico di Torino, 2021. http://hdl.handle.net/11583/2945181.

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Labrado, Carson. "Exploration of Majority Logic Based Designs for Arithmetic Circuits." UKnowledge, 2017. http://uknowledge.uky.edu/ece_etds/102.

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Since its inception, Moore's Law has been a reliable predictor of computational power. This steady increase in computational power has been due to the ability to fit increasing numbers of transistors in a single chip. A consequence of increasing the number of transistors is also increasing the power consumption. The physical properties of CMOS technologies will make this powerwall unavoidable and will result in severe restrictions to future progress and applications. A potential solution to the problem of rising power demands is to investigate alternative low power nanotechnologies for implementing logic circuits. The intrinsic properties of these emerging nanotechnologies result in them being low power in nature when compared to current CMOS technologies. This thesis specifically highlights quantum dot celluar automata (QCA) and nanomagnetic logic (NML) as just two possible technologies. Designs in NML and QCA are explored for simple arithmetic units such as full adders and subtractors. A new multilayer 5-input majority gate design is proposed for use in NML. Designs of reversible adders are proposed which are easily testable for unidirectional stuck at faults.
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Book chapters on the topic "NanoMagnets Logic"

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Luis, Fernando, Olivier Roubeau, and Guillem Aromí. "Artificial Molecular Nanomagnets as Spin-Based Quantum Logic Gates." In Architecture and Design of Molecule Logic Gates and Atom Circuits, 249–66. Berlin, Heidelberg: Springer Berlin Heidelberg, 2012. http://dx.doi.org/10.1007/978-3-642-33137-4_19.

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Porod, Wolfgang, Gary H. Bernstein, György Csaba, Sharon X. Hu, Joseph Nahas, Michael T. Niemier, and Alexei Orlov. "Nanomagnet Logic (NML)." In Field-Coupled Nanocomputing, 21–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-43722-3_2.

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Porod, Wolfgang, Gary H. Bernstein, György Csaba, Sharon X. Hu, Joseph Nahas, Michael T. Niemier, and Alexei Orlov. "Nanomagnet Logic (NML)." In Field-Coupled Nanocomputing, 21–32. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-45908-9_2.

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Becherer, Markus. "3D Nanomagnetic Logic." In Emerging Non-volatile Memory Technologies, 259–96. Singapore: Springer Singapore, 2021. http://dx.doi.org/10.1007/978-981-15-6912-8_8.

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Vacca, Marco, Mariagrazia Graziano, Juanchi Wang, Fabrizio Cairo, Giovanni Causapruno, Gianvito Urgese, Andrea Biroli, and Maurizio Zamboni. "NanoMagnet Logic: An Architectural Level Overview." In Field-Coupled Nanocomputing, 223–56. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-43722-3_10.

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Vacca, Marco, Mariagrazia Graziano, Alessandro Chiolerio, Andrea Lamberti, Marco Laurenti, Davide Balma, Emanuele Enrico, et al. "Electric Clock for NanoMagnet Logic Circuits." In Field-Coupled Nanocomputing, 73–110. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-43722-3_5.

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Vacca, Marco, Mariagrazia Graziano, Juanchi Wang, Fabrizio Cairo, Giovanni Causapruno, Gianvito Urgese, Andrea Biroli, and Maurizio Zamboni. "NanoMagnet Logic: An Architectural Level Overview." In Field-Coupled Nanocomputing, 223–56. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-45908-9_10.

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Vacca, Marco, Mariagrazia Graziano, Alessandro Chiolerio, Andrea Lamberti, Marco Laurenti, Davide Balma, Emanuele Enrico, et al. "Electric Clock for NanoMagnet Logic Circuits." In Field-Coupled Nanocomputing, 73–110. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-45908-9_5.

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Riente, Fabrizio, Markus Becherer, and Gyorgy Csaba. "Nanomagnetic Logic: From Devices to Systems." In Emerging Computing: From Devices to Systems, 107–43. Singapore: Springer Nature Singapore, 2022. http://dx.doi.org/10.1007/978-981-16-7487-7_5.

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Vacca, Marco, Stefano Frache, Mariagrazia Graziano, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, and Maurizio Zamboni. "ToPoliNano: NanoMagnet Logic Circuits Design and Simulation." In Field-Coupled Nanocomputing, 274–306. Berlin, Heidelberg: Springer Berlin Heidelberg, 2014. http://dx.doi.org/10.1007/978-3-662-43722-3_12.

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Conference papers on the topic "NanoMagnets Logic"

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D’Souza, Noel M., Jayasimha Atulasimha, and Supriyo Bandyopadhyay. "Four-State Straintronics: Extremely Low Power Nanomagnetic Logic Using Multiferroics With Biaxial Anisotropy." In ASME 2011 Conference on Smart Materials, Adaptive Structures and Intelligent Systems. ASMEDC, 2011. http://dx.doi.org/10.1115/smasis2011-5242.

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Abstract:
The authors had previously theoretically demonstrated that multiferroic nanomagnetic logic can be clocked in ∼1 GHz with few 100 kT/bit power dissipation which is ∼3 orders of magnitude more energy efficient than current CMOS transistor technology that dissipates several 100,000 kT/bit.. In this work, we propose the more novel concept of 4-state logic by numerically demonstrating the feasibity of an ultra low-power 4-state NOR logic gate using multiferroic nanomagnets with biaxial magnetocrystalline anisotropy. Here, the logic bits are encoded in the magnetization orientation of a nanoscale magnetostrictive layer elastically coupled to a piezoelectric layer. The piezoelectric layer can be clocked with a small electrostatic potential (∼0.2 V) to switch the magnetization of the magnetic layer. We also address logic propagation, where the accurate and unidirectional transfer of data from an input nanomagnet along an array of nanomagnets is needed. This is accomplished by devising an effective clocking scheme to the nanomagnet array, which allows for the realization of feasible logic circuits. Ultimately, this technology would enable higher order information processing, such as pattern recognition, to be performed in parallel at very high speeds while consuming extremely low power. Potential applications include high-density logic circuits, associative memory and neuromorphic computing.
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Imre, Alexandra, Gyorgy Csaba, Lili Ji, Alexei Orlov, Gary H. Bernstein, Vitali Metlushko, and Wolfgang Porod. "Field-coupled nanomagnets for logic applications." In Microtechnologies for the New Millennium 2005, edited by Paolo Lugli, Laszlo B. Kish, and Javier Mateos. SPIE, 2005. http://dx.doi.org/10.1117/12.613974.

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Ju, Xueming, Josef Kiermaier, Andrea Savo, Markus Becherer, Stephan Breitkreutz, Irina Eichwald, Doris Schmitt-Landsiedel, Wolfgang Porod, Paolo Lugli, and Gyorgy Csaba. "Modeling interaction between Co/Pt nanomagnets and Permalloy domain wall for Nanomagnet Logic." In 2012 IEEE 12th International Conference on Nanotechnology (IEEE-NANO). IEEE, 2012. http://dx.doi.org/10.1109/nano.2012.6322193.

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Imre, A., L. Ji, G. Csaba, A. Orlov, G. H. Bernstein, and W. Porod. "Magnetic Logic based on Field-Coupled Nanomagnets." In 2007 International Conference on Electromagnetics in Advanced Applications. IEEE, 2007. http://dx.doi.org/10.1109/iceaa.2007.4387371.

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D'Souza, Noel, Mohammad Salehi-Fashami, Supriyo Bandyopadhyay, and Jayasimha Atulasimha. "Hybrid spintronics-straintronic nanomagnetic logic with two-state elliptical and four-state concave magnetostrictive nanomagnets." In 2014 72nd Annual Device Research Conference (DRC). IEEE, 2014. http://dx.doi.org/10.1109/drc.2014.6872321.

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Carlton, David, Brian Lambson, Zheng Gu, Scott Dhuey, Li Gao, Brian Hughes, Deirdre Olynick, et al. "Signal propagation in dipole coupled nanomagnets for logic applications." In SPIE NanoScience + Engineering, edited by Henri-Jean Drouhin, Jean-Eric Wegrowe, and Manijeh Razeghi. SPIE, 2012. http://dx.doi.org/10.1117/12.930776.

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Johnson, Mark, Jindong Song, Jinki Hong, and Joonyeon Chang. "Magnetic field controlled reconfigurable logic gates with integrated nanomagnets." In SPIE NanoScience + Engineering, edited by Henri-Jean Drouhin, Jean-Eric Wegrowe, and Manijeh Razeghi. SPIE, 2013. http://dx.doi.org/10.1117/12.2024409.

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Ahmad, H., A. K. Biswas, J. Atulasimha, and S. Bandyopadhyay. "Straintronics: Strain-switched multiferroic nanomagnets for extremely low energy logic/memory." In 2015 IEEE Nanotechnology Materials and Devices Conference (NMDC). IEEE, 2015. http://dx.doi.org/10.1109/nmdc.2015.7439253.

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Alam, M. T., S. Kurtz, M. T. Niemier, S. X. Hu, G. H. Bernstein, and W. Porod. "Magnetic Logic Based on Coupled Nanomagnets: Clocking Structures and Power Analysis." In 2008 8th IEEE Conference on Nanotechnology (NANO). IEEE, 2008. http://dx.doi.org/10.1109/nano.2008.192.

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Kaiser, W., M. Kiechle, G. Ziemys, D. Schmitt-Landsiedel, and S. Breitkreutz-v. Gamm. "Engineering the switching behavior of nanomagnets for logic computation using 3-dimensional modeling and simulation." In 2016 IEEE Conference on Electromagnetic Field Computation (CEFC). IEEE, 2016. http://dx.doi.org/10.1109/cefc.2016.7815977.

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