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1
Rao, Wenjing. "Towards reliable nanoelectronic systems." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2008. http://wwwlib.umi.com/cr/ucsd/fullcit?p3291919.
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Thesis (Ph. D.)--University of California, San Diego, 2008.<br>Title from first page of PDF file (viewed March 18, 2008). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 193-199).
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Chiu, Pit Ho Patrio 1977. "Bismuth based nanoelectronic devices." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=100337.
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Bismuth (Bi) is a unique electronic material with small effective mass (∼0.001me) and long carrier mean free path (100 nm at 300K). It is particularly suitable for studying nano scale related phenomena such as size effect and energy level spacing. In this thesis work, bismuth based nanoelectronic devices were studied. Devices were fabricated using a combination of electron beam (e-beam) writing and thermal evaporation techniques. Dimensions of the fabricated devices were in the order of 100 rim. All structures were optimized for individual electrical characterization. Three types of devices were studied: Bi nanowires, Bi nanowires with dual side-gate structures and Bi nanodot structures. In the study of Bi nanowires, metal-to-semiconductor transition phenomenon and size effect were observed. The conduction behavior of Bi nanowires changed from metallic to semiconductor when the device's critical dimension was reduced to below 50 nm. It is a solid experimental evidence of the quantum confinement-induced bandgap theory. Additionally, it has been found in the present work that resistivity of individual Bi nanowire increased as linewidth decreased indicating size effect occurred in the Bi nanowires. Dual side-gate structures were formed adjacent to the Bi nanowires in an attempt to modulate the current. Measurements showed a 7% of current modulation. The small current modulation suggested the high carrier density in the nanowire which has prevented the full depletion of free carriers. 100 nm-diameter Bi nanodot structures were fabricated utilizing proximity effect of e-beam writing. Precise control of electron doses and process conditions led to the successful fabrication of sub-nanometer tunneling junctions to the nanodots. Significant non-linear current-voltage (I-V) characteristic was observed at low temperatures. The step like I-V characteristic was a strong indication of energy level spacing in the zero-dimensional nanodot structure. The successful observation of energy level spacing in a relatively large nanodot is due to the small effective mass of bismuth material which leads to a measurable energy level spacing.
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Blackburn, A. M. "Multiple-gate vacuum nanoelectronic devices." Thesis, University of Cambridge, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.596691.
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This thesis introduces novel multiple-gate vacuum nanoelectronic devices, presenting details of their theoretical and experimental characterization, and of the methods that have been established for their fabrication. These devices, based upon the nanotriode of Driskill-Smith et al, have multiple-gates placed within an anode-cathode vacuum gap of only a few hundred nanometres, permitting a wide range of potential-energy landscapes to be created in front of its tungsten-nanopillar field-emitting cathode. The current transport in such devices is suggested to be influenced by quantum interference of the electron wave function in the anode-cathode gap, and this work seeks to control this effect. The device fabrication and electrical characterisation focuses on a pentode device, which has an integrated anode and tungsten-nanopillar cathode structure and three gate-electrodes with aperture-diameters of less than 100 nm; the fabrication can readily be adapted to devices with fewer gates. A calculation of the transmission probability for electrons through the entire pentode anode-cathode gap shows resonances at certain gate-voltage arrangements, strengthening the possibility of observing quantum interference effects in these devices. A study of the tungsten nanopillar formation-process gives new information upon their geometry and formation. The details of the process required to form nanopillars in the pentode chamber are suggested to differ from those required on large area samples. Thus, the observed pentode device characteristics are best explained by dielectric leakage mechanisms, which were also evident in the nanotriode work. However, the reliable range of field emission observation, in two-terminal devices where field emission was observed, has been increased in comparison to the nanotriode by using a tungsten pedestal cathode structure. In response to the pentode characteristics, an alternative cathode structure was fabricated, based upon carbon contaminated scanning electron microscope deposited tips.
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Maassen, Jesse. "First principles simulations of nanoelectronic devices." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106463.
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As the miniaturization of devices begins to reveal the atomic nature of materials, where chemical bonding and quantum effects are important, one must resort to a parameter-free theory for predictions. This thesis theoretically investigates the quantum transport properties of nanoelectronic devices using atomistic first principles. Our theoretical formalism employs density functional theory (DFT) in combination with Keldysh nonequilibrium Green's functions (NEGF). Self-consistently solving the DFT Hamiltonian with the NEGF charge density provides a way to simulate nonequilibrium systems without phenomenological parameters. This state-of-the-art technique was used to study three problems related to the field of nanoelectronics. First, we investigated the role of metallic contacts (Cu, Ni and Co) on the transport characteristics of graphene devices. With Cu, the graphene is simply electron-doped (Fermi level shift of −0.7 eV) which creates a unique signature in the conduction profile allowing one to extract the doping level. With Ni and Co, spin-dependent band gaps are formed in graphene's linear dispersion bands, thus leading to the prediction of high spin injection efficiencies reaching 60% and 80%, respectively. Second, we studied how controlled doping distributions in nano-scale Si transistors could suppress OFF-state leakage currents. By assuming the dopants (B and P) are confined in 1.1 nm regions in the channel, we discovered large conductance variations (Gmax/Gmin ~ 10^5) as a function of the doping location. The largest fluctuations arise when the dopants are in the vicinity of the electrodes. Our results indicate that if the dopants are located away from the leads, a distance equal to 20% of the channel length, the tunneling current can be suppressed by a factor of 2 when compared to the case of uniform doping. Thus, controlled doping engineering is found to suppress device-to-device variations and lower the undesirable leakage current. Finally, we incorporated a dephasing model into our ab initio transport formalism, which was used to study the effect of phase-breaking scattering in three different systems. Our calculations revealed the complex role of dephasing, where conduction increased or decreased depending on the system under consideration. We demon- strated that the backscattering component of this dephasing scheme also allows one to retrieve Ohm's law.<br>Comme la miniaturisation des dispositifs commence à révéler la nature atomique des matériaux, où les liaisons chimiques et les effets quantiques sont importants, nous devons recourir à une théorie sans paramètre pour obtenir des prédictions. Cette thèse étudie les propriétés de transport quantique des dispositifs nanoélectroniques en utilisant des méthodes ab initio atomiques. Notre formalisme théorique combine la théorie de la fonctionnelle de la densité (DFT) avec les fonctions de Green hors-équilibres (NEGF). Résoudre l'Hamiltonien DFT de manière auto-consistante avec la densité de charge NEGF permet de simuler des systèmes hors-équilibres sans utiliser des paramètres. Cette technique sophistiquée a été utilisée pour étudier trois problèmes liés au domaine de la nanoélectronique. Premièrement, nous avons étudié le rôle des contacts métalliques (Cu, Ni et Co) sur les caractéristiques de transport des dispositifs à base de graphène. Dans le cas du Cu, le graphène est simplement dopé en électrons (décalage du niveau de Fermi = −0.7 eV) ce qui crée une signature unique dans le profil de conduction permettant d'extraire le niveau de dopage. Avec Ni et Co, la formation de bandes interdites dépendantes du spin détruit la dispersion linéaire des états du graphène ce qui permet d'atteindre une efficacité d'injection de spin de 60% et 80%, respectivement. Deuxièmement, nous avons étudié comment des distributions de dopage contrôlées dans les nano-transistors en Si pourraient supprimer les courants de fuite à l'état OFF. En supposant que les dopants (B et P) sont confinés dans des régions de 1.1 nm dans le canal, nous avons découvert de grandes variations de conductances (Gmax/Gmin ~ 10^5) en fonction de l'emplacement du dopage. Les plus grandes fluctuations surviennent lorsque les dopants sont à proximité des électrodes. Nos résultats indiquent que si les dopants sont éloignés des électrodes, d'une distance égale à 20% de la longueur du canal, le courant tunnel peut être supprimé par un facteur de 2 par rapport au dopage uniforme. Ainsi, l'ingénierie du dopage pourrait réduire les variations d'un dispositif à un autre et diminuer le courant de fuite. Dernièrement, nous avons intégré un modèle de déphasage dans notre théorie de transport ab initio qui a été utilisé pour étudier l'effet des collisions dans trois systèmes différents. Nos calculs ont révélé le rôle complexe du déphasage; parfois la conduction augmente ou diminue selon le système. Nous avons démontré que la rétrodiffusion, présent dans ce modèle, permet de récupérer la loi d'Ohm.
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Huang, Jun, and 黃俊. "Efficiency enhancement for nanoelectronic transport simulations." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/196031.
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Continual technology innovations make it possible to fabricate electronic devices on the order of 10nm. In this nanoscale regime, quantum physics becomes critically important, like energy quantization effects of the narrow channel and the leakage currents due to tunneling. It has also been utilized to build novel devices, such as the band-to-band tunneling field-effect transistors (FETs). Therefore, it presages accurate quantum transport simulations, which not only allow quantitative understanding of the device performances but also provide physical insight and guidelines for device optimizations.
However, quantum transport simulations usually require solving repeatedly the Green’s function or the wave function of the whole device region with open boundary treatment, which are computationally cumbersome. Moreover, to overcome the short-channel effects, modern devices usually employ multi-gate structures that are three-dimensional, making the computation very challenging. It is the major target of this thesis to enhance the simulation efficiency by proposing several fast numerical algorithms. The other target is to apply these algorithms to study the physics and performances of some emerging electronic devices.
First, an efficient method is implemented for real space simulations with the effective mass approximation. Based on the wave function approach, asymptotic waveform evaluation combined with a complex frequency hopping algorithm is successfully adopted to characterize electron conduction over a wide energy range. Good accuracy and efficiency are demonstrated by simulating several n-type multi-gate silicon FETs. This technique is valid for arbitrary potential distribution and device geometry, making it a powerful tool for studying n-type silicon nanowire (SiNW) FETs in the presence of charged impurity and surface roughness scattering.
Second, a model order reduction (MOR) method is proposed for multiband simulation of nanowire structures. Employing three- or six-band k.p Hamiltonian, the non-equilibrium Green’s function (NEGF) equations are projected into a much smaller subspace constructed by sampling the Bloch modes of each cross-section layer. Together with special sampling schemes and Krylov subspace methods for solving the eigenmodes, large cross-section p-type SiNW FETs can be simulated. A novel device, junctionless FET, is then investigated. It is found that its doping density, channel orientation, and channel size need to be carefully optimized in order to outperform the classical inversion-mode FET.
With a spurious band elimination process, the MOR method is subsequently extended to the eight-band k.p model, allowing simulation of band-to-band tunneling devices. In particular, tunneling FETs with indium arsenide (InAs) nanowire channel are studied, considering different channel orientations and configurations with source pockets. Results suggest that source pocket has no significant impact on the performances of the nanowire device due to its good electrostatic integrity.
At last, improvements are made for open boundary treatment in atomistic simulations. The trick is to condense the Hamiltonian matrix of the periodic leads before calculating the surface Green’s function. It is very useful for treating leads with long unit cells.<br>published_or_final_version<br>Electrical and Electronic Engineering<br>Doctoral<br>Doctor of Philosophy
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Mirza, Muhammad M. "Nanofabrication of silicon nanowires and nanoelectronic transistors." Thesis, University of Glasgow, 2015. http://theses.gla.ac.uk/6495/.
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This project developed a robust and reliable process to pattern < 5 nm features in negative tone Hydrogen silsesquioxane (HSQ) resist using high resolution electron beam lithography and developed a low damage reactive ion etch (RIE) process to fabricate silicon nanowires on degenerately doped n-type silicon-on-insulator (SOI) substrates. A process to thermally grow high quality silicon dioxide (SiO2) (between 5-15 nm) is also developed to passivate onto the etched silicon nanowire devices to serve the purposes of gate dielectric and a diffusion barrier to minimize the donor deactivation. The measured interface state trap density (Dit) of the 10 nm thermally grown oxide is 1.3x10^10 cm^−2 eV^−1 with a breakdown voltage of ~7 V. Using optimized processes for lithography, dry etch and thermal oxidation, Hall bar and Greek cross devices are fabricated with mean widths from 45 to 4 nm on SOI substrates with a doping density ~ 2x10^19, 4x10^19, 8x10^19 and 2x10^20 atoms/cm^3 and electronically characterized at room and cryogenic temperatures (from 1.4 to 300 K) to allow resistivity, mobility and carrier density to be extracted directly as a function of temperature. This allowed to probe electron transport and scattering mechanisms in degenerately doped silicon nanowires. The mean free path is theoretically calculated and directly compared with the widths of the nanowires by which it can be approximated that the electron transport is 3 dimensional (3D) for the 12 nm wide nanowire which has likely to be changed to 2D and 1D for the 7 nm and 4 nm wide nanowires respectively. Moreover the experimental mobility is directly compared with a number of theoretically calculated mobilities using Matthiessen’s rule, where it has been determined that the neutral impurity scattering is the dominant scattering mechanism limiting the performance of silicon nanowires. Using silicon nanowires, junctionless transistors are fabricated on SOI substrate with a doping density ~ 4x10^19 atoms/cm^3 and electronically characterized at room and cryogenic temperatures (from 1.4 to 300 K). It was observed that reducing the width of channel from 24 to 8 nm, the transistor changed their operation from depletion to enhancement mode due to increase in the surface depletion at smaller length scales. Since the drain current in a junctionless transistor is proportional to the doping density, a high on-state drive current ~ 1.28 mA/µm has been observed with sub-threshold slope (SS) ~ 66 mV/decade at 300 K. Moreover temperature dependent measurements revealed a low SS ~ 39 mV/decade at 70 K and single electron oscillations at 1.4 K. Finally, independent arrays of 2 terminal nanowires devices with mean widths from 45 to 4 nm are fabricated on SOI substrate with a doping density ~ 8x10^19 atoms/cm^3 to detect polyoxometalate (POM) molecules [W18O54(SeO3)2]4−. A change in resistivity has been observed ~ 3.6 m ohm-cm (corresponds to ~ 13 % increase) when POM molecules are coated around the nanowires, shown n-type behaviour of molecules. POM molecules exhibit highly redox properties, therefore side-gated FETs with mean width ~ 4 nm were fabricated on SOI substrate with a doping density ~ 4x10^19 atoms/cm^3 where side-gate was used to apply alternative ± pulses of 20 V to charge and discharge the POM molecules to demonstrate flash memory operation. The average change in the threshold voltage was ~ 1.2 V between the charging (program) and the discharging (erase) cycles. The program/erase time is currently limited to 100 ms for a reasonable single-to-noise ratio. Moreover no significant decay in the stored charge has yet been measured over a period of 2 weeks (336 hours).
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Coker, Ayodeji. "Performance analysis of fault-tolerant nanoelectronic memories." [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2666.
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Sarsby, Matt. "Nanoelectronic and nanomechanical devices for low temperature applications." Thesis, Lancaster University, 2017. http://eprints.lancs.ac.uk/84447/.
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Cooling physical experiments to low temperatures removes thermal excitations to reveal quantum mechanical phenomena. The progression of nanotechnologies provides new and exciting research opportunities to probe nature at ever smaller length scales. The coupling of nanotechnologies and low temperature techniques has potential for scientific discoveries as well as real world applications. This work demonstrates techniques to further extend physical experimental research into the millikelvin-nanoscale domain. The challenge of thermometry becomes an increasingly complex problem as the temperature of a physical system lowers. We describe the development and methods for a specially modified Coulomb blockade thermometer to achieve electron thermometry below 4mK overcoming the challenge of electron thermalisation for on-chip devices. Mechanically vibrating devices can directly probe bulk and surface fluid properties. We developed practical measurement techniques and analysis methods to demonstrate the use of nanomechanical resonators, which for the first time were used to probe both the normal and the superfluid phases of helium-4. The doubly clamped beams had a cross section of 100nm by 100nm and were tested in length variants between 15um to 50um, The flexural resonance between 1MHz and 10MHz in response to the helium temperature dependent properties showed an encouraging agreement with established theories, providing experimental verification on a new smaller length scale. The smallest beams achieved a mass sensitivity in liquid of 10ag. We also created and analysed a new method of sampling peak-like functions that is applicable to many physical systems to provide around 20% improvements over the existing methods under certain situations. This was verified in ultra low temperature applications as a drop-in addition to accompany existing techniques.
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Jiang, Zhe. "Novel nanowire structures and devices for nanoelectronic bioprobes." Thesis, Harvard University, 2015. http://nrs.harvard.edu/urn-3:HUL.InstRepos:17467307.
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Semiconductor nanowire materials and devices provide unique opportunities in the frontier between nanoelectronics and biology. The bottom-up paradigm enables flexible synthesis and patterning of nanoscale building blocks with novel structures and properties, and nano-to-micro fabrication methods allow the advantages of functional nanowire elements to interface with biological systems in new ways. In this thesis, I will focus on the development of bottom-up nanoscience platforms, which includes rational synthesis and assembly of semiconductor nanowires with new capabilities, as well as design and fabrication of the first free-standing three-dimensional (3D) nanoprobes, with special focus on applications in intracellular recording and stimulation.
I will first introduce kinked p-n junction nanowires as a new and powerful family of high spatial resolution biological and chemical sensors with proof-of-concept applications. Next, I will discuss a variety of functional kinked nanowires with synthetically controlled properties and the potential of achieving more detailed and less invasive cellular studies. Furthermore, I will present a general shape-controlled deterministic nanowire assembly method to produce large-scale arrays of devices with well-defined geometry and position.
Then, I will present the design of a general method to fabricate these nanowire structures into free-standing 3D probes. I will show that free-standing nanowire bioprobes can be manipulated to target specific cells and record stable intracellular action potentials. I will demonstrate simultaneous measurements from the same cell using both kinked nanowire and patch-clamp probes. Moreover, I will discuss two strategies of multiplexed recording using free-standing probes.
Finally, I will report localized stimulation on single cells enabled by the unique properties of p-n kinked nanowires. I will show with simulation and electrical characterization that in reverse bias, localized electric field generated around the nanoscale p-n junction should exceed the threshold for opening voltage-gated sodium channels. Moreover, I will present measurements of localized cell stimulation using p-n nanowire free-standing probes. Together with the capability of stable intracellular recording, these results complete the two-way communication between semiconductor nanowire electronics and biological systems at a natural nanoscale, which can open up new directions in the fields ranging from cellular electrophysiology, brain activity mapping to brain-machine interface.<br>Chemistry and Chemical Biology
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Kim, Jungyup. "Effective germanium surface preparation methods for nanoelectronic applications /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.
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Hsueh, Yu-Ling. "Electron Spin Relaxation of Donors in Silicon Nanoelectronic Devices." Thesis, Purdue University, 2019. http://pqdtopen.proquest.com/#viewpdf?dispub=10638270.
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<p> The environment interacts with the electron and leads to electron relaxation pro cesses. To measure the relaxation rate the system is disturbed from equilibrium. <i> T</i><sub>1</sub> time characterizes the time for the system to restore equilibrium. </p><p> Understanding and controlling the spin-relaxation mechanism is crucial for real izing a spin-qubit based quantum computer. The spin-lattice relaxation time (<i>T</i><sub>1</sub>) is one of the two important timescales of a qubit, and in addition, it can provide valu able information about the qubit and its interaction with the device environment. Here, we investigate the <i>T</i><sub>1</sub> time of electronic spins bound to donors in silicon in a scanning tunneling microscopy (STM) fabricated device. A tight-binding treatment of the electron-phonon problem is being developed. Together with Fermi’s Golden rule the <i>T</i><sub>1</sub> time of the system can be obtained with atomic level details. This method is extended to treat the multi-electron system, where the electron-electron interaction is captured by atomistic con?guration interaction method. We also show that under applied gate bias, an unconventional spin-orbit coupling the external electric ?eld and magnetic ?eld dominates over Rashba spin-orbit for donors in Si. Various spin relaxation mechanisms are investigated, considering both the valley repopulation and single valley e?ects. We ?nd that <i>T</i><sub>1</sub> is strongly dependent on the directions of the external magnetic and electric ?elds relative to the crystalline directions. We show good agreements between this theory and recent experimental measurements.</p><p>
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Ye, Sheng. "Kelvin Probe Force Microscopy (KPFM) for nanoelectronic device characterisation." Thesis, University of Southampton, 2016. https://eprints.soton.ac.uk/419059/.
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This project is to develope a new method of characterization for Silicon-nano-wire (SiNW) FET and SET devices by using KPFM technology to derive the information of local surface potential change on the channel of SiNW devices. The surface potential is related to many important parameters on material's surface, e.g. fixed surface charge, doping profile variation, distribution of charge carriers under applied bias, and individual dopant atoms near the surface. Those parameters are strongly related to the characteristics of SiNW devices. The KPFM equipment is designed to extract the contact potential difference (CPD) between tip and sample. The change of CPD is related to the Fermi energy level in materials. Therefore any factors which induce Fermi energy level change inside material are detectable. The significantly improved lateral resolution (sub-nanometer) gives us confidence for the measurement of local surface potential variation. Much of the time has been dedicated for the KPFM equipment calibration and optimization. By the end of PhD project the surface potential characterisation of three different types of the silicon-nano-wire (SiNW) devices (uniformly doped SiNW, n-pn SiNW Field-Effect-Transistor (FET), and n-p-n-p-n SiNW Single-Electron-Transistor (SET)) has been achieved. By using surface potential information the surface traped charge and change in local resistivity in SiNW is successfully estimated and the result is confirmed well agreed with the characterisation of other conventional method. This characterisation result also suggest the accuracy of local surface potential measurement. In-situ potential mapping and proling of n-p-n FET channel under device operation has been successfully performed. By comparing the data with simulation and electrical characterisation of the same device, correspondence between the line-shape of the surface potential and electrical field profiles and device parameters has been clarified for the first time. An attempt has been made to observe the surface potential of the channel of SET devices which have shown clear Coulomb oscillation at low temperature (5K). The formation of a conductive channel in 330-nm-wide SiNW channel by the side gate modulation is successfully observed. Four main achievements can be claimed at the end of this project. First, the metallurgic p-n junction in thin (50nm) SOI has been first time ever detected by Ex curve extraction from measured potential profile and the Ex curve was used to study the charge transport in the n-p-n structure under different biasing condition. Secondary, the novel single side gate doping modulated single electron transistors was fabricated and shown Coulomb oscillations which was consistent with theoretical predictions. Furthermore, the operation of FET/SET was investigated by scanned high resolution surface potential profile which revealed the status of p-n junction under biasing. In the end, this study discovered a new method to investigate nano-electronic devices by KPFM scan and more information such as change in build-in voltage at low temperature, and charge in charge state of island can be extracted if the high vacuum and low temperature is applied.
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MIRYALA, SANDEEP. "CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems." Doctoral thesis, Politecnico di Torino, 2014. http://hdl.handle.net/11583/2539691.
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As an answer to More Moore paradigm, Complementary Metal Oxide Semiconductor (CMOS) technology is continuously scaled to nanometer lengths and the silicon channel has reached its physical limit. It is time for the industry to explore novel material based devices that support future integrated circuits. Graphene is a two dimensional material which can be patterned through existing lithography process, therefore representing the most interesting material for concurrent, single-layer integration of devices and interconnects. Moreover, it shows unique mechanical properties alowing for the growth of new smart devices (e.g. wearable computing).
In this dissertation, we focus on a novel device called as multi function reconfigurable gate proposed by IBM. This device consists of coplanar split gates underneath a large graphene sheet. A thin dielectric oxide layer separates the gates and the graphene sheet. Three metal-graphene contacts are present on top of the graphene sheet, called as front metal-graphene contacts. The co-planar gates dope the graphene electrostatically by using bipolar voltages. Here, we define logic ‘0’
as negative voltage (-Vdd/2) and logic ‘1’ (+Vdd/2) as positive voltage. The gates are connected to ‘0’ and ‘1’ making the graphene region above the gates p-type and n-type, respectively. The device do not rely on patterning the graphene sheet into nanoribbons. Advanced CMOS lithography techniques can be efficiently used for the gate patterning to achieve high density integration. Thus, this device is feasible for manufacturing and does not introduce any edge effects on the carriers. Using the above mentioned multi function reconfigurable gate, with appropriate terminal connections, a graphene 2:1 multiplexer is realized. An equivalent electrical model (also verilog-A model) is developed which is integrated with commercial SPICE simulators. With appropriate signals at the data inputs of the graphene 2:1 multiplexer, several other basic boolean logic gates (Inv, AND, OR etc) are realized. Some of these gates (like AND etc) have multiple architectures and a thorough comparison in terms of power and performance is presented. For the graphene reconfigurable gate based logic gates, we identify the possible timing arcs. The timing arc is defined from the input node to the output node. Only those input node which is responsible for a signal transition at the output terminal are considered. Two classes of timing arcs are identified, one from back gate terminals to output terminal termed as back-to-out transition, second from
front contact terminal to the output terminal termed as front-to-out transition. An analytical model for delay and power for each of these timing arcs are presented and validated through SPICE simulator. The model validation is done for a range of input transition time and output load capacitance. The next step is to build integrated circuits with these graphene based gates. This is termed as synthesis and is present in the initial stage of the traditional IC design flow. There are various synthesis methods for designing conventional CMOS based circuits. These methods (namely Standard Cell Mapping (STC), Binary Decision Diagrams (BDD) and Look Up Table (LUT)) can be adopted for graphene RG based gates too. Various benchmark circuits implemented with these methods are
characterized for power, area and performance. This helps designers in identifying the best implementation style for low power and high performance circuit. From testability perspective, the effect of various physical defects such as Short circuit between device terminals and open terminals on the graphene RG based logic gates is presented in this thesis. The electrical behavior of faulty devices, obtained through the emulation of physical failures at the SPICE-level, have been analyzed and mapped at a higher level of abstraction using proper fault models. Finally, in this thesis we propose ultra low power graphene logic gates, based on Adiabatic Computing. We design graphene pn-junction based adiabatic logic gates (INV/AND/OR) and are characterized for power and performance. A comparison between the graphene pn-junction based adiabatic logic gates and non adiabatic graphene logic gates is drawn and the adiabatic gates proved to have significant power savings.
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Escott, Christopher Colin Electrical Engineering & Telecommunications Faculty of Engineering UNSW. "Modelling of phosphorus-donor based silicon qubit and nanoelectronic devices." Publisher:University of New South Wales. Electrical Engineering & Telecommunications, 2008. http://handle.unsw.edu.au/1959.4/41470.
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Modelling of phosphorus donor-based silicon (Si:P) qubit devices and mesoscopic single-electron devices is presented in this thesis. This theoretical analysis is motivated by the use of Si:P devices for scalable quantum computing. Modelling of Si:P single-electron devices (SEDs) using readily available simulation tools is presented. The mesoscopic properties of single and double island devices with source-drain leads is investigated through ion implantation simulation (using Crystal-TRIM), 3D capacitance extraction (FastCap) and single-electron circuit simulation (SIMON). Results from modelling two generations of single and double island Si:P devices are given, which are shown to accurately capture their charging behaviour. The trends extracted are used to forecast limits to the reduction in size of this Si:P architecture. Theoretical analysis of P2+:Si charge qubits is then presented. Calculations show large ranges for the SET measurement signal, Δq, and geometric ratio factor, α, are possible given the 'top-down' fabrication procedure. The charge qubit energy levels are calculated using the atomistic simulator NEMO 3-D coupled to TCAD calculations of the electrostatic potential distribution, further demonstrating the precise control required over the position of the donors. Theory has also been developed to simulate the microwave spectroscopy of P2+:Si charge qubits in a decohering environment using Floquet theory. This theory uses TCAD finite-volume modelling to incorporate realistic fields from actual device gate geometries. The theory is applied to a specific P2+:Si charge qubit device design to study the effects of fabrication variations on the measurement signal. The signal is shown to be a sensitive function of donor position. Design and analysis of two different spin qubit architectures concludes this thesis. The first uses a high-barrier Schottky contact, SET and an implanted P donor to create a double-well suitable for implementation as a qubit. The second architecture is a MOS device that combines an electron reservoir and SET into a single structure, formed from a locally depleted accumulation layer. The design parameters of both architectures are explored through capacitance modelling, TCAD simulation, tunnel barrier transmission and NEMO 3-D calculations. The results presented strengthen the viability of each architecture, and show a large Δq (> 0.1e) can be expected.
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Joshi, Shital. "Analysis and Optimization of Graphene FET based Nanoelectronic Integrated Circuits." Thesis, University of North Texas, 2016. https://digital.library.unt.edu/ark:/67531/metadc849755/.
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Like cell to the human body, transistors are the basic building blocks of any electronics circuits. Silicon has been the industries obvious choice for making transistors. Transistors with large size occupy large chip area, consume lots of power and the number of functionalities will be limited due to area constraints. Thus to make the devices smaller, smarter and faster, the transistors are aggressively scaled down in each generation. Moore's law states that the transistors count in any electronic circuits doubles every 18 months. Following this Moore's law, the transistor has already been scaled down to 14 nm. However there are limitations to how much further these transistors can be scaled down. Particularly below 10 nm, these silicon based transistors hit the fundamental limits like loss of gate control, high leakage and various other short channel effects. Thus it is not possible to favor the silicon transistors for future electronics applications. As a result, the research has shifted to new device concepts and device materials alternative to silicon.
Carbon is the next abundant element found in the Earth and one of such carbon based nanomaterial is graphene. Graphene when extracted from Graphite, the same material used as the lid in pencil, have a tremendous potential to take future electronics devices to new heights in terms of size, cost and efficiency. Thus after its first experimental discovery of graphene in 2004, graphene has been the leading research area for both academics as well as industries. This dissertation is focused on the analysis and optimization of graphene based circuits for future electronics.
The first part of this dissertation considers graphene based transistors for analog/radio frequency (RF) circuits. In this section, a dual gate Graphene Field Effect Transistor (GFET) is considered to build the case study circuits like voltage controlled oscillator (VCO) and low noise amplifier (LNA). The behavioral model of the transistor is modeled in different tools: well accepted EDA (electronic design automation) and a non-EDA based tool i.e. \simscape. This section of the dissertation addresses the application of non-EDA based concepts for the analysis of new device concepts, taking LC-VCO and LNA as a case study circuits. The non-EDA based approach is very handy for a new device material when the concept is not matured and the model files are not readily available from the fab. The results matches very well with that of the EDA tools. The second part of the section considers application of multiswarm optimization (MSO) in an EDA tool to explore the design space for the design of LC-VCO. The VCO provides an oscillation frequency at 2.85 GHz, with phase noise of less than -80 dBc/Hz and power dissipation less than 16 mW. The second part of this dissertation considers graphene nanotube field effect transistors (GNRFET) for the application of digital domain. As a case study, static random access memory (SRAM) hs been design and the results shows a very promising future for GNRFET based SRAM as compared to silicon based transistor SRAM. The power comparison between the two shows that GNRFET based SRAM are 93% more power efficient than the silicon transistor based SRAM at 45 nm.
In summary, the dissertation is to expected to aid the state of the art in following ways:
1) A non-EDA based tool has been used to characterize the device and measure the circuit performance. The results well matches to that obtained from the EDA tools. This tool becomes very handy for new device concepts when the simulation needs to be fast and accuracy can be tradeoff with.
2)Since an analog domain lacks well-design design paradigm, as compared to digital domain, this dissertation considers case study circuits to design the circuits and apply optimization.
3) Performance comparison of GNRFET based SRAM to the conventional silicon based SRAM shows that with maturation of the fabrication technology, graphene can be very useful for digital circuits as well.
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PENAZZI, GABRIELE. "Development of an atomistic/continous simulation tool for nanoelectronic devices." Doctoral thesis, Università degli Studi di Roma "Tor Vergata", 2010. http://hdl.handle.net/2108/1335.
Full textAbstract:
La simulazione dei moderni dispositivi elettronici
è una grande sfida per la comunità ingegneristica.
L'enorme progresso nei processi di fabbricazione
ha permesso una riduzione della dimensione dei
dispositivi talmente spinta che fenomeni tipici
della scala di lunghezza nanometrica giocano un ruolo
cruciale. Inoltre stiamo assistendo a un grande sforzo
teso ad esplorare soluzioni tecnologiche alternatice
ai tradizionali dispositivi a semiconduttore. Questo
sforzo è rivolto verso la frontiera dell'elettronica molecolare,
dei polimeri semiconduttori, delle strutture autoassemblanti,
dei materiali quasi-unidimensionali e bidimensionali.
In uno scenario simile è cruciale sviluppare strumenti di
simulazione modulari, capaci di connettere modelli fisici differenti
su scale geometriche differenti. Gli effetti quantistici
giocano un ruolo fondamentale ed è necessario includere
modelli che li descrivano, evitando però la tipica esplosione
di complessità nell'implementazione di suddetti modelli.
Per realizzare ciò è necessario andare verso un approccio multiscala,
approccio già utilizzato con successo in meccanica statica.
Lo scopo di questo lavoro è includere descrizioni e modelli
atomistici in TiberCAD, un codice TCAD per la simulazione
di dispositivi optoelettronici che può vantare eccellenti strumenti
per interfacciare diversi modelli fisici in un ambiente multifisica/multiscala.
I modelli atomistici inclusi sono utili al calcolo delle deformazioni
elastiche, della geometria della struttura e degli stati elettronici.
Infine, viene presentata anche una tecnica inedita
per una descrizione quantistica efficiente del trasporto di carica.
Questo lavoro vuole contrubuire a rendere TiberCAD
uno strumento di riferimento per la simulazione di dispositivi
optoelettronici su nanoscala.<br>The simulation of novel optoelectronic devices
is a great challenge for the engineering community.
The enoromous progress in device fabrication technology
allowed such a massive downscaling that geometrical
feature in the nanoscale play a crucial role.
Furthermore we have a great effort in exploring
alternative solutions respect to more traditional
semiconductor devices. It involves molecular
electronic, semiconductive polymers,
self-assembled structures, quasi-one dimensional
and two dimensional materials. In such scenario
it's crucial to develop modular simulation tools
able to connect different physical models
on different length scales. Quantum effect
play an important role and we need to take
them into account, avoiding anyway an explosion of the
computational complexity. Thus it's needed
to go in the direction of a multiscale approach,
which is already applied with success in
mechanical science.
The goal of this work is to include atomistic
description and atomistic models in TiberCAD,
a Technology CAD code for simulation of optoelectronic
devices which can rely on excellent instruments
for interfacing different models in a multyphisics/multiscale
environment. Atomistic models for the calculation
of strain, structure geometry and electronic states
have been included.
A novel technique for describing quantum
transport with an efficient algorithm is also presented.
These work wants to push TiberCAD
to be a reference tool for calculation of complex
optoeletronic devices at the nanoscale.
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Landauer, Gerhard Martin. "Opportunities for radio frequency nanoelectronic integrated circuits using carbon-based technologies." Doctoral thesis, Universitat Politècnica de Catalunya, 2014. http://hdl.handle.net/10803/145982.
Full textAbstract:
This thesis presents a body of work on the modeling of and performance predictions for carbon nanotube field-effect transistors (CNFET) and graphene field-effect transistors (GFET). While conventional silicon-based CMOS is expected to reach its ultimate scaling limits during the next decade, these two novel technologies are promising candidates for future high-performance electronics. The main goal of this work is to investigate
on the opportunities of using such carbon-based electronics for RF integrated circuits.
This thesis addresses 1) the modeling of noise and process variability in CNFETs, 2) RF performance predictions for CNFETs, and 3) an accurate GFET compact model. This work proposes the first CNFET noise compact model. Noise is of primary importance for RF applications and its description significantly increases the insight gained from simulation studies. Furthermore, a CNFET variability model is presented, which handles tube synthesis and metal tube removal imperfections. These two model extensions have been added to the Stanford CNFET compact model and allow for the variability-aware RF performance assessment of the CNFET technology.
In continuation, comprehensive RF performance projections for CNFETs are provided both on the device and circuit level. The overall set of ITRS RF-CMOS technology requirement FoMs is determined and shows that the CNFET performs excellently in terms of speed, gain, and minimum noise figure. Furthermore, for the first time FoMs are reported for the basic RF building blocks low-noise amplifier and oscillator. In addition, it is shown that CNFET downscaling yields significant performance improvements. Based on these analyses it is confirmed that the CNFET has the potential to outperform Si-CMOS in RF applications.
A third key contribution of this thesis is the development of an accurate GFET compact model. Previous compact models simplify several physical aspects, which can cause erroneous simulation results. Here, an accurate yet simple mathematical description of the GFET’s current-voltage relation is proposed and implemented in Verilog-A. Comprehensive error analyses are done in order to highlight the advantages of the new approach.
Furthermore, the model is verified against measurement results. The developed GFET model is an important step towards better understanding the characteristics and opportunities of graphene-based analog circuitry.
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Di, Giacomo Sandro John. "Development of silicon germanium-based quantum dots for nanoelectronic device applications." The Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=osu1406719133.
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Dai, Xiaochuan. "Multifunctional Three-Dimensional Nanoelectronic Networks for Smart Materials and Cyborg Tissues." Thesis, Harvard University, 2015. http://nrs.harvard.edu/urn-3:HUL.InstRepos:23845480.
Full textAbstract:
Nanomaterials provide unique opportunities at the interface between nanoelectronics and biology. “Bottom-up” synthesized nanowire(NW) with defined functionality can be assembled and enabled into three-dimensional(3D) flexible nanoelectronic networks. The micro- to nanoscale electronic units blur the distinction between electronics and cells/tissue in terms of length scale and mechanical stiffness. These unconventional 3D nanoelectronic networks can thus provide a path towards truly seamless integration of non-living electronics and living systems. In this thesis, I will introduce a general method for fabricating 3D macroporous NW nanoelectronic networks and their integration with hydrogel, elastomer and living tissues, with an emphasis on the realization of two-way communication between active nanoelectronics and the passive or living systems in which they are embedded.
First, fabrication of 3D macroporous NW nanoelectronic networks will be described. Examples showing hundreds of individually addressable, multifunctional nanodevices fully distributed and interconnected throughout 3D networks will be illustrated. Proof-of-concept studies of macroporous nanoelectronic networks embedded through hydrogels and polymers demonstrate the ability for dynamically mapping pH gradients and strain fields.
Second, a universal method to improve the long-term stability of semiconductor NWs in physiological environments using atomic layer deposition(ALD) of dielectric metal oxides shells on NW cores will be introduced. Long-term stability improvement by ALD of Al2O3 shells with different shell thickness and annealing conditions will be described and discussed. In addition, studies of semiconductor NW nanodevices with multilayer Al2O3/HfO2 shells indicates stability for up to two years in physiological solutions at 37◦C.
Third, 3D macroporous nanoelectronic networks were integrated with synthetic cardiac tissues to build “cyborg” cardiac tissues. Spatiotemporal mapping of action potential(AP) propagating throughout 3D cardiac tissue was carried out with sub-millisecond time resolution, allowing investigation of cardiac tissue development and responses to pharmacological agents. These results have promised the applications of cyborg tissues in the fields ranging from fundamental electrophysiology and regenerative medicine to pharmacological studies.
Finally, multifunctionallities of nanoelectronic devices for applications at the bio/nano interface will be discussed. Incorporation of NW field-effect-transistor(FET) and electrical stimulators in macroporous nanoelectronic networks demonstrates simultaneous recording and regulation of AP propagation in cyborg cardiac tissues. In addition, a convexed-NW FET bioprobe has been developed for simultaneous detection of AP and contraction force from individual cardiomyocyte. These explorations on the nanoelectronics functionalities highlight the capability to enable new communication modes between electronics and living tissues.<br>Chemistry and Chemical Biology
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Pawar, M. "Growth of two dimensional (2D) materials and its applications in nanoelectronic devices." Thesis(Ph.D.), CSIR-National Chemical Laboratory, Pune, 2021. http://dspace.ncl.res.in:8080/xmlui/handle/20.500.12252/6013.
Full textAbstract:
The 2D materials like Graphene and MoS2 are widely studied over the last decade due to their unique structural, mechanical, electrical and optical properties for nanoelectronics device applications. There are many other materials from 2D family possess similar properties as that of MoS2 but are less explored by the researchers. In the present thesis, various 2D materials such as V2O5, Black Phosphorous, SnSe2, PtSe2 and CdMoS4 are synthesized using top down and bottom up approaches. The structural, morphological and optical investigations were carried out using microscopic and spectroscopic techniques. Based on the characterization analysis these materials are utilized for fabricating nanoelectronic devices including Field Effect Transistor, photodetector, humidity sensor and gas sensor. Our results reveals that these 2D materials can be potential candidate in next generation nanoelectronic devices.<br>AcSIR
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Souza, Aldilene Saraiva. "Electronic Transport in Molecular Systems." reponame:Repositório Institucional da UFC, 2012. http://www.repositorio.ufc.br/handle/riufc/12671.
Full textAbstract:
SOUZA, Aldilene Saraiva. Electronic Transport in Molecular Systems. 2012. 107 f. Tese (Doutorado em Física) - Programa de Pós-Graduação em Física, Departamento de Física, Centro de Ciências, Universidade Federal do Ceará, Fortaleza, 2012.<br>Submitted by Edvander Pires (edvanderpires@gmail.com) on 2015-06-08T19:17:13Z
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Previous issue date: 2012<br>Nesta tese apresentamos o estudo teórico de transporte eletrônico de dispositivos moleculares em dois problemas distintos. No primeiro, comparamos medidas via microscopia de tunelamento (STM) com cálculos de primeiros princípios onde a tensão aplicada em uma mono camada de moléculas auto-montadas, denominadas: 5-(4-piridina)-1,3,4-oxadiazol-2-tiol (HPYT) e 5-(4-fenil)-1,3,4-oxadiazol-2-tiol (HPOT) mostram a distribuição local de carga. Essas moléculas são depositadas sobre um substrato de ouro tipo (1 1 1). A formação destas camadas moleculares foi confirmada por medidas de STM. Cálculos baseados na teoria do funcional da densidade (DFT) foram realizados para obter a conformação mais estável da interação molécula/substrato. Verificamos uma grande semelhança entre os resultados teóricos e as medidas de imagem de STM. A partir desta comparação, sugerimos que o átomo de enxofre na molécula HPYT e HPOT está ligado à superfície de ouro por uma ligação direta à um único átomo de ouro. Para descrever a corrente de tunelamento ao longo da mono camada molecular sobre a superfície de Au (1 1 1) foi proposto um modelo quântico baseado na técnica de equação mestra. Nós investigamos também, propriedades de transporte de spin em uma cadeia de poliacetileno (como ponte) acoplada à uma nano fita de carbono tipo zigue-zague (ZGNRs) funcionando como eletrodos. Os cálculos de transporte foram efetuados usando técnica de funções de Green fora do equilíbrio (NEGF), combinada com a teoria do funcional da densidade (DFT). Trabalhos anteriores demonstraram que as ZGNRs exibem um ordenamento antiferromagnético (AF) e meia-metalicidade nos estados provenientes da borda, que podem ser destruídos com aplicação de um forte campo elétrico externo. Neste trabalho, nós demonstramos que a ligação entre a ponte molecular e átomos não-equivalentes de carbono (A/B) na sub rede de grafeno ZGNRs pode ocorrer de duas formas produzindo um sistema metálico ou semicondutor fortemente dependente do acoplamento local. Ao considerar o anel de carbono onde a cadeia está ligada, uma ligação se assemelha a uma ligação para no benzeno, enquanto a outra ligação é semelhante a uma ligação meta. Estas geometrias geram transmissão eletrônica distinta, que pode ser controlada sob um campo elétrico transversal.
22
Pan, Chenyun. "A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53931.
Full textAbstract:
A fast and efficient hierarchical optimization engine was developed to benchmark and optimize various emerging device and interconnect technologies and system-level innovations at the early design stage. As the semiconductor industry approaches sub-20nm technology nodes, both devices and interconnects are facing severe physical challenges. Many novel device and interconnect concepts and system integration techniques are proposed in the past decade to reinforce or even replace the conventional Si CMOS technology and Cu interconnects. To efficiently benchmark and optimize these emerging technologies, a validated system-level design methodology is developed based on the compact models from all hierarchies, starting from the bottom material-level, to the device- and interconnect-level, and to the top system-level models. Multiple design parameters across all hierarchies are co-optimized simultaneously to maximize the overall chip throughput instead of just the intrinsic delay or energy dissipation of the device or interconnect itself. This optimization is performed under various constraints such as the power dissipation, maximum temperature, die size area, power delivery noise, and yield. For the device benchmarking, novel graphen PN junction devices and InAs nanowire FETs are investigated for both high-performance and low-power applications. For the interconnect benchmarking, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed, and emerging multi-layer graphene interconnects are also investigated, and compared with the conventional Cu interconnects. For the system-level analyses, the benefits of the systems implemented with 3D integration and heterogeneous integration are analyzed. In addition, the impact of the power delivery noise and process variation for both devices and interconnects are quantified on the overall chip throughput.
23
Tomlinson, Christopher David. "A highly parallel image processing computer architecture suitable for implementation in nanotechnology." Thesis, University College London (University of London), 1999. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.313616.
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Nominé, Anna V. "Synthesis of Bi₂O₂CO₃ nanosheets by electrical discharges in liquids for photocatalytic and nanoelectronic applications." Electronic Thesis or Diss., Université de Lorraine, 2023. http://www.theses.fr/2023LORR0357.
Full textAbstract:
Ce travail fournit des informations sur la synthèse de feuillets nanométriques ultrafins composés de Bi₂O₂CO₃, ci-après dénommé BOC. La synthèse est réalisée par une technique rapide et simple connue sous le signe EDDL correspondant au procédé de décharges électriques dans les liquides diélectriques. Pour assurer la reproductibilité de la synthèse, une méthode de prétraitement impliquant la gravure d'électrodes de bismuth avec du Nital a été employée. Le processus choisi consiste à initier des décharges électriques entre ces électrodes alors qu'elles sont immergées soit dans l'azote liquide, soit dans l'eau. Fait remarquable, les deux liquides conduisent à des nanostructures identiques, une similitude validée par spectroscopie d'émission optique, technique qui a permis de confirmer la nature métallique de la décharge dans les deux milieux. Après cette étape, les nanofeuillets subissent une oxydation et une carbonatation rapides lorsqu'ils sont exposés à l'air. Le mécanisme de croissance proposé est étroitement lié au mécanisme connu sous le nom de « ledge mechanism », en raison de la présence de « kinks » et de « jogs » clairement visibles le long des bords des nanofeuillets. Ces nanostructures bidimensionnelles émergent d'abord à la surface de la cathode et croissent ensuite verticalement. Cette croissance anisotrope est rendue possible par l'assistance ionique dans les régions qui ressemblent à des motifs en forme de peigne formés pendant l'étape de gravure chimique, condition préalable nécessaire à une forte reproductibilité du processus de croissance. La caractérisation cristallographique détaillée des nanofeuillets de BOC a été réalisée à l'aide d'une série de techniques, notamment la microscopie électronique en transmission (TEM), la microscopie électronique en transmission à balayage (STEM), la microscopie électronique en transmission à haute résolution (HRTEM), la spectroscopie de rayons X à dispersion d'énergie (EDX), la diffraction d'électrons en aire sélectionnée (SAED), la diffraction d'électrons en faisceau convergent (CBED), la microscopie électronique en transmission filtrée en énergie (EFTEM) et la spectroscopie de perte d'énergie des électrons (EELS). L'étude révèle que la structure cristallographique du BOC est conforme au groupe spatial I4/mmm, avec des paramètres de réseau a=3,91 Å et c=13,77 Å, une détermination qui a été confirmée par diffraction des rayons X (DRX). L'étude clarifie également l'origine potentielle des taches satellites qui sont régulièrement observées dans les motifs SAED le long de l'axe de zone [001]. Dans cette étude, ces taches ont été principalement attribuées à deux phénomènes : la diffraction multiple et les transformations locales ordre-désordre qui se produisent dans la structure cristalline du BOC. Cette transformation implique une transition d'une structure quadratique centrée vers un réseau primitif de Bravais. Afin d'évaluer leur utilité pratique, nous avons mesuré la performance photocatalytique des nanofeuillets de BOC synthétisés à l'aide de la méthode EDDL et nous avons constaté qu'elle était comparable à elle de BOCs obtenus par d'autres méthodes. En outre, nous avons évalué la performance électronique des BOC dans le but de découvrir leur potentiel dans les applications liées à des nanodispositifs<br>This work provides information on the synthesis of ultrathin nanosheets composed of Bi₂O₂CO₃, hereafter referred to as BOC. The synthesis is achieved through the rapid and straightforward technique known as Electrical Discharges in Dielectric Liquids (EDDL). To ensure the reproducibility of the synthesis, a pre-treatment method involving the etching of bismuth electrodes with Nital was employed. The chosen process entails initiating electrical discharges between these electrodes while submerged in either liquid nitrogen or water. Remarkably, both liquids produced identical nanostructures, a similarity validated by optical emission spectroscopy, which confirmed the metallic nature of the discharge in both environments. Following this stage, the nanosheets undergo rapid oxidation and carbonation upon exposure to air. The proposed growth mechanism is closely linked to the ledge mechanism, considering the presence of clearly visible kinks and jogs along the edges of the nanosheets. These two-dimensional nanostructures first emerge on the cathode's surface and then grow vertically. This anisotropic growth is made possible by ion assistance in regions that exhibit comb-like patterns formed during the chemical etching step, which is a necessary precondition for high reproducibility of the discharge process. Detailed crystallographic characterization of BOC nanosheets was achieved through a range of techniques, including Transmission Electron Microscopy (TEM), Scanning Transmission Electron Microscopy (STEM), High-Resolution TEM Transmission Electron Microscopy (HRTEM), Energy-Dispersive X-ray Spectroscopy (EDX), Selected Area Electron Diffraction (SAED), Convergent Beam Electron Diffraction (CBED), Energy Filtered Transmission Electron Microscopy (EFTEM), and Electron Energy-Loss Spectroscopy (EELS). The investigation reveals that the crystallographic structure of BOC conforms to the space group I4/mmm, with lattice parameters a=3.91 Å and c=13.77 Å, a determination that was confirmed by X-ray Diffraction (XRD). The study also clarifies the potential origin of satellite spots that are consistently observed in SAED patterns along the [001] zone axis. In this research, these spots were primarily attributed to two phenomena: multiple diffraction and local disorder-to-order transformations occurring within the BOC crystal structure. This transformation entails a transition from a body-centered tetragonal structure to a primitive Bravais lattice. To gauge their practical usefulness, we assessed the photocatalytic performance of BOC nanosheets synthesized using the EDDL method and found it to be consistent with BOC obtained through alternative methods. Furthermore, we explored the electronic performance of BOC with the goal of uncovering their potential in nanodevice applications
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FRACHE, STEFANO. "Massively Parallel Nanoarchitectures: structures, algorithms and simulation tools." Doctoral thesis, Politecnico di Torino, 2013. http://hdl.handle.net/11583/2518616.
Full textAbstract:
The exponential growth of computing power that we have been used-to since years is about to face new challenges, most notably for technical and economical reasons. It is highly debated when it will be time to go past traditional CMOS technology, but from ITRS data we know that traditional ultra-deep submicron devices are approaching fundamental physical limits. From an economical point of view, the extremely high costs of chip masks and production plants are posing substantial limitations to the development margins.
The end of a remarkably successful era in computing is approaching then. It’s the era where Moore’s Law reigns and processing power per dollar doubles every year. A new era, though, is on the horizon [52]: the nanoelectronics era, with ever smaller devices and higher densities, to keep up with pace.
Among the envisaged solutions to these arising problems, alternatives to traditional computation have been proposed, in the form of numerous so-called disruptive nanotechnologies. Some of the proposals innovate also the technological approach, moving from the conventional top-down process to a chemical self-assembly process. None of these effort is mature to the point to substitute CMOS any time soon, but this is the right time to be deeply involved in their study and contribute to their progress towards the moment when some of these will provide a valid alternative. The risk, else, would be to miss not just the next evolutionary step, but a revolution in the approach to computation.
The fact that a clear winner is far and away from being declared among the competitors stresses the need to study different technology proposals. The scaling of the featured size of devices in disruptive nanotechnologies also requires to deal with added complexity, that is the price to pay for a great density advantage.
Many nanotechnologies, and for sure the ones based on chemical self-assembly, suffer from two problems. First, the self-assembly nature of the process renders almost impossible to replicate complex aperiodic structures, as in the CMOS case. Then, the thermodynamical nature of the assembly makes structures sensitive to temperature variations. To put it more simply, disruptive nanotechnologies suffer from greater defect rates with respect to CMOS. Fault-tolerance techniques must be applied to fabrics, irrespective to the architecture of choice.
The net gain, we said, on one side is the prospected density advantage, estimated in up to three orders of magnitude with respect to the limits traced by IRTS, plus a ultra-low power consumption: these are among the main reasons driving computational research in the field in this direction.
This doctoral work focuses on the need to address specific questions that apply to many disruptive nanotechnologies.
• Is it possible to cope with high defect rates?
• How to interconnect nanoscale devices or logic blocks?
• Which architectures are best fit for these high density devices?
These questions are just an exemplification of the many questions that researchers are trying to answer. In our view, there is a methodological problem that has to be solved first and foremost. The problem is about which approach is scientifically sound to get data to answer the aforementioned question. It is our believe that building analytical models first, to study different technologies, would lead to conclusions that could hardly be considered convincing. In [27] we showed how an analytical model, despite its intricacy, is far from close to model the complexity of the system it mimics, and so are the attained results.
From a methodological point of view, then, we argue that numerical simulations are needed to tackle the great complexity of these systems, irrespective of technology at hand, and this requires CAD tools specifically designed to study the nascent problems of emerging technology. Unfortunately, to the best of our knowledge, no such tool was developed before this work.
Why, then, we observed a tendency to exploit existing tools to cross the bridge between nanotechnologies and nanoarchitectures? Was this due to the fact that existing tools were good at solving the new challenges as well? This could hardly be the reason why. In fact, it is rather difficult, if possible, to put up a toolchain of existing softwares, able to provide a complete workflow from nanodevice simulation to floorplanning, place and route, and nanoarchitecture simulation and evaluation, able to handle nanotechnology-related constraints.
This work focuses on the development of such a tool, ToPoliNano. The software functionalities are described in details, alongside with attained results. It has the ability, starting from a circuit by parsing its VHDL description, to target different disruptive nanotechnologies (different Nanoarray-based architectures [143] and NanoMagneticLogics (NML), also known as Magnetic QCA (M-QCA) [76] supported at present time), to place and route it on a floorplan and then simulate it, in an integrated fashion. The tool has been used to study specific architectures devised to exploit the power of emerging technologies.
ToPoliNano tool covers a broad range of abstraction levels, from the device level, to the circuit level, up to the architectural level. It is then possible to draw conclusions at architectural level starting from modeling at device level. This is critical to trust architectural results, usually prone to huge errors.
Massively parallel architectures were studied to exploit regularity of these fabrics; this approach seems more promising than massive data parallelism. Logic and timing simulations have been performed, and results published in International Journals and Conferences [25, 26, 27, 32, 65, 77].
The organization of this document is as follows.
Part I consists in Chapter 1, which is introductory to the technologies handled by ToPoliNano, providing background and state-of-the art information on the subject.
Part II opens with Chapter 2, which is about general organization of the application, providing an overview of the specifications and of the most advanced characteristics of the ToPoliNano software. Chapter 3 provides information about the software at two levels of detail: introductory, if the subject is further developed in other parts of the work, informative else. Chapter 4 deals with details of the VHDL parsing module. Chapter 5 deals with details of the Input Stimuli Generator, while Chapter 6 thoroughly details implementation and results of the Simulation Engine(s) of the software. In Chapter 7 a key component for ToPoliNano’s flexibility in dealing with different nanotechnologies is described: the Library Generator. Part II is closed by Chapter 8, in which a case study is presented, with an architecture proposal for biosequence analysis and simulation results.
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Sangtarash, Sara. "Theory of mid-gap quantum transport through single molecule : new approach to transport modeling of nanoelectronic devices." Thesis, Lancaster University, 2017. http://eprints.lancs.ac.uk/88312/.
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Molecules due to their very small sizes, possess discrete energy levels and electrons can transmit from one side of the molecule to the other with high probability if their energy coincides with molecular energy levels. In the weak coupling limit such on-resonance electron transport is described by the simple Lorentzian-shaped Breit-Wigner formula. On the other hand, electrons with energy different than the molecular energy levels have to tunnel through the energy gap between two molecular energy levels (off resonance transmission). Consequently the electron transmission probability is much smaller than on resonance regime. Interesting phenomena including quantum interference could be observed in this regime at room temperature. In this thesis, I discuss both regimes though, my main aim is to introduce a new theory called ”mid- gap theory” to predict the conductance ratio between different connectivities driven by quantum interference (QI) in the tunneling regime. Both theory and experiment have focused primarily on elucidating the conditions for the appearance of constructive or destructive interference. In the simplest case, where electrons are injected at the Fermi energy EF of the electrodes, constructive QI arises when EF coincides with a delocalized energy level En of the molecule. Similarly a simple form of destructive QI occurs when EF coincides with the energy Eb of a bound state located on a pendant moiety. Unless energy levels are tuned by electrostatic, electrochemical or mechanical gating, molecules located within a junction rarely exhibit these types of QI, because EF is usually located in the HOMO-LUMO (H-L) gap. Furthermore few analytic formulas are available, which means that pre-screening of molecules often requires expensive numerical simulations. For this reason, discussions have often focused on conditions for destructive or constructive QI when EF is located at the centre of the H-L gap. In this thesis, based on a simple description of connectivity, I demonstrate that the conductance ratio between two different connectivities of a core molecule could be predicted simply by using the ratio between two magic numbers of the core molecule. This will be discussed in the chapters 4-6. This simple theory not only predicts conductance ratios, but it could be used also to propose new strategies for molecular electronic design and applications such as single molecule switches and thermoelectricity. In this thesis after an introduction to nano and molecular electronics, I discuss general ideas about nanoscale transport and the methods which could be applied to model nano and molecular scale devices. In chapter 3, on resonance transport is discussed. For a wide variety of molecules, the conductance G decays with length L as Aexp(−βL) and it is widely accepted that the attenuation coefficient β is determined by position of the Fermi energy of the electrodes relative to the energy gap of the molecular bridge, whereas the terminal anchor groups which bind the molecule to the electrodes contribute to A. In contrast with this expectation, in chapter 3, I demonstrate that gateway orbitals located on the anchor groups can significantly decrease the value of β, thereby creating a new design strategy for realizing low-conductance molecular wires. In chapters 4-6, I introduce mid-gap theory and drive a mid-gap ratio rule (MRR) which is an exact formula for conductance ratios of tight-binding representations of molecules in the weak coupling limit, when the Fermi energy is located at the centre of the HOMO-LUMO (H-L) gap. It does not depend on the size of the H-L gap and is independent of asymmetries in the contacts. I also show how conductance ratios change, when one of the carbon atoms within the parent polycyclic aromatic hydrocarbons (PAH) core is replaced by a heteroatom to yield a daughter molecule. I show that this heteroatom substitution could be used to enhance the conductance in a PAH molecule by several orders of magnitude. A good agreement between this new simple theory and experiment shows that, the MRR provides a useful tool to predict the conductances of PAH molecules prior to synthesis. Therefore it could be used to design molecules with desirable properties or to propose new molecular devices.
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Chung, Chia-Ling. "Study of DNA- SWNT conjugation for nanoelectronic purposes : realisation of transistors and SWNT positioning in DNA T scaffold." Paris 11, 2010. http://www.theses.fr/2010PA112033.
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Dans cette thèse l’ADN a été envisagé comme un matériau de choix pour l’auto-assemblage de circuits à base de SWNTS. Afin de réaliser cette vision ambitieuse, plusieurs étapes sont nécessaires et dans cette thèse nous nous intéressons à trois d’entre elles : l’assemblage de l’ADN sur nanotubes. Nous avons exploré deux approches : l’approche covalente (chapitre 2) et l’approche non covalente ( chapitre 3). Les résultats obtenus nous ont servi à évaluer quelle méthode était la plus pertinente pour la fabrication de transistors. La conclusion de ces études a été que l’approche non covalente basée sur le système biotin-streptavidine est plus appropriée pour la fabrication de SWNT-FET en raison de son rendement plus élevé. (II) La fabrication d’une nanostructure d’ADN en forme de T, l’idée était ici de créer un échafaudage d’ADN imitant la géométrie d’un transistor a grille individuel. Nos résultats démontrent qu’il est possible de définir le design d’une structure d’ADN pour une fonction donnée et de le positionner sélectivement et spécifiquement un nanotube sur cette structure a trois branches. (III) Finalement nous décrivons la fabrication de dispositifs à base de nanotubes et d’ADN (chapitre 5). Nous avons réalisé des transistors par assemblage biorigide en utilisant les étapes suivantes : A) formation d’un complexe ADN-nanotubes, B) Métallisation sélective de l’ADN, C) fabrication des électrodes sur l’ADN métallisé par lithographie électronique et D) mesure des caractéristiques I/V. Les résultats démontrent la faisabilité des dispositifs, les transistors obtenus présentent un comportement de type P classique pour les nanotubes de carbone<br>In this thesis DNA has been envisioned as a scaffold for self assembly of SWNTS circuits on a substrate to realise this ambitious vision, several steps are needed and we address three of them in this thesis : I) DNA SWNT conjugation experiments. We test two approaches: covalent Approach (chapter2) and non –convalent approach (chapter 3). In order to evaluate which approach is suitable to fabricate DNA assembled SWNT-FET. Our results reveal that non-convalent approach by biotin-streptavidin system is the more appropriate for our DNA-based SWNT-FET fabrication, because of its superior linkage yield. (II) The assembly of a T-Shape DNA scaffold. In chapiter 4, we present a three branched DNA scaffold which can be the template of a SWNT field effect transistor. We design an artificial three branched DNA structure that mimics the geometry of an individual gated transistor. Our results demonstrate that it is possible to design sub-micrometric branched DNA structures for a given function, and directly an specifically localize one SWNT onto a three armed functionalized DNA template. (III) Finally, the fabrication of bio-directed SWNT-FET (chapter 5) through the following steps : (A) formation of DNA SWNT complexes using biotin-streptavidin system, (B) selective DNA metallization, (C) fabrication of electrode contacts on the metallized DNA strand by lithography and (D) the conductivity measurement the results reveal, the feasibility of the approach ant that our bio-directed SWNT-FET presents the typical P type SWNT-FET
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Chouard, Florian Raoul Verfasser], Doris [Akademischer Betreuer] [Schmitt-Landsiedel, and Sebastian M. [Akademischer Betreuer] Sattler. "Device Aging in Analog Circuits for Nanoelectronic CMOS Technologies / Florian Raoul Chouard. Gutachter: Sebastian M. Sattler ; Doris Schmitt-Landsiedel. Betreuer: Doris Schmitt-Landsiedel." München : Universitätsbibliothek der TU München, 2012. http://d-nb.info/1024355020/34.
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Krüger, Justus [Verfasser], Gianaurelio [Akademischer Betreuer] Cuniberti, Gianaurelio [Gutachter] Cuniberti, and Lukas [Gutachter] Eng. "On-surface synthesis of acenes – : organic nanoelectronic materials explored at a single-molecule level / Justus Krüger ; Gutachter: Gianaurelio Cuniberti, Lukas Eng ; Betreuer: Gianaurelio Cuniberti." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2018. http://d-nb.info/1151046957/34.
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Krüger, Justus [Verfasser], Gianaurelio [Akademischer Betreuer] Cuniberti, Gianaurelio Gutachter] Cuniberti, and Lukas [Gutachter] [Eng. "On-surface synthesis of acenes – : organic nanoelectronic materials explored at a single-molecule level / Justus Krüger ; Gutachter: Gianaurelio Cuniberti, Lukas Eng ; Betreuer: Gianaurelio Cuniberti." Dresden : Saechsische Landesbibliothek- Staats- und Universitaetsbibliothek Dresden, 2018. http://nbn-resolving.de/urn:nbn:de:bsz:14-qucosa-232078.
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Hutjens, Charles Michael. "Morphology Control for Model Block Copolymer/Nanoparticle Thin Film Nano-Electronic Devices on Conductive Substrates." University of Akron / OhioLINK, 2013. http://rave.ohiolink.edu/etdc/view?acc_num=akron1374496041.
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McCaughan, Adam Nykoruk. "Superconducting thin film nanoelectronics." Thesis, Massachusetts Institute of Technology, 2015. http://hdl.handle.net/1721.1/101576.
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Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.<br>Cataloged from PDF version of thesis.<br>Includes bibliographical references (pages 163-171).<br>Superconducting devices have found application in a diverse set of fields due to their unique properties which cannot be reproduced in normal materials. Although many of these devices rely on the properties of bulk superconductors, superconducting devices based on thin films are finding increasing application, especially in the realms of sensing and amplification. With recent advances in electron-beam lithography, superconducting thin films can be patterned into geometries with feature sizes at or below the characteristic length scales of the superconducting state. By patterning 2D geometries with features smaller than these characteristic length scales, we were able to use nanoscale phenomena which occur in thin superconducting films to create superconducting devices which performed useful tasks such as sensor amplification, logical processing, and fluxoid state sensing. In this thesis, I describe the development, characterization, and application of three novel superconducting nanoelectronic devices: the nTron, the yTron, and the current-controlled nanoSQUID. These devices derive their functionality from the exploitation of nanoscale superconducting effects such as kinetic inductance, electrothermal suppression, and current-crowding. Patterning these devices from superconducting thin-films has allowed them to be integrated monolithically with each other and other thin-film superconducting devices such as the superconducting nanowire single-photon detector.<br>by Adam Nykoruk McCaughan.<br>Ph. D.
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Echtermeyer, Tim Joachim. "Graphene nanoelectronics and optoelectronics." Thesis, University of Cambridge, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.648171.
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Kulmala, Tero Samuli. "Nanowires and graphene nanoelectronics." Thesis, University of Cambridge, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.608195.
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Fasoli, Andrea. "Nanowires and nanoribbons nanoelectronics." Thesis, University of Cambridge, 2010. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.608660.
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Lombardo, Antonio. "Graphene nanoelectronics and optoelectronics." Thesis, University of Cambridge, 2014. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.648601.
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Conrad, Brad Richard. "Interface effects on nanoelectronics." College Park, Md.: University of Maryland, 2009. http://hdl.handle.net/1903/9154.
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Thesis (Ph. D.) -- University of Maryland, College Park, 2009.<br>Thesis research directed by: Dept. of Physics. Title from t.p. of PDF. Includes bibliographical references. Published by UMI Dissertation Services, Ann Arbor, Mich. Also available in paper.
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Spagocci, S. "Fault tolerance issues in nanoelectronics." Thesis, University College London (University of London), 2008. http://discovery.ucl.ac.uk/14227/.
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The astonishing success story of microelectronics cannot go on indefinitely. In fact, once devices reach the few-atom scale (nanoelectronics), transient quantum effects are expected to impair their behaviour. Fault tolerant techniques will then be required. The aim of this thesis is to investigate the problem of transient errors in nanoelectronic devices. Transient error rates for a selection of nanoelectronic gates, based upon quantum cellular automata and single electron devices, in which the electrostatic interaction between electrons is used to create Boolean circuits, are estimated. On the bases of such results, various fault tolerant solutions are proposed, for both logic and memory nanochips. As for logic chips, traditional techniques are found to be unsuitable. A new technique, in which the voting approach of triple modular redundancy (TMR) is extended by cascading TMR units composed of nanogate clusters, is proposed and generalised to other voting approaches. For memory chips, an error correcting code approach is found to be suitable. Various codes are considered and a lookup table approach is proposed for encoding and decoding. We are then able to give estimations for the redundancy level to be provided on nanochips, so as to make their mean time between failures acceptable. It is found that, for logic chips, space redundancies up to a few tens are required, if mean times between failures have to be of the order of a few years. Space redundancy can also be traded for time redundancy. As for memory chips, mean times between failures of the order of a few years are found to imply both space and time redundancies of the order of ten.
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Semple, James. "High-throughput large-area plastic nanoelectronics." Thesis, Imperial College London, 2016. http://hdl.handle.net/10044/1/39573.
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Large-area electronics (LAE) manufacturing has been a key focus of both academic and industrial research, especially within the last decade. The growing interest is born out of the possibility of adding attractive properties (flexibility, light weight or minimal thickness) at low cost to well-established technologies, such as photovoltaics, displays, sensors or enabling the realisation of emerging technologies such as wearable devices and the Internet of Things. As such there has been great progress in the development of materials specifically designed to be employed in solution processed (plastic) electronics, including organic, transparent metal oxide and nanoscale semiconductors, as well as progress in the deposition methods of these materials using low-cost high-throughput printing techniques, such as gravure printing, inkjet printing, and roll-to-roll vacuum deposition. Meanwhile, industry innovation driven by Moore's law has pushed conventional silicon-based electronic components to the nanoscale. The processes developed for LAE must strive to reach these dimensions. Given that the complex and expensive patterning techniques employed by the semiconductor industry so far are not compatible with LAE, there is clearly a need to develop large-area high throughput nanofabrication techniques. This thesis presents progress in adhesion lithography (a-Lith), a nanogap electrode fabrication process that can be applied over large areas on arbitrary substrates. A-Lith is a self-alignment process based on the alteration of surface energies of a starting metal electrode which allows the removal of any overlap of a secondary metal electrode. Importantly, it is an inexpensive, scalable and high throughput technique, and, especially if combined with low temperature deposition of the active material, it is fundamentally compatible with large-area fabrication of nanoscale electronic devices on flexible (plastic) substrates. Herein, I present routes towards process optimisation with a focus on gap size reduction and yield maximisation. Asymmetric gaps with sizes below 10 nm and yields of > 90 % for hundreds of electrode pairs generated on a single substrate are demonstrated. These large width electrode nanogaps represent the highest aspect ratio nanogaps (up to 108) fabricated to date. As a next step, arrays of Schottky nanodiodes are fabricated by deposition of a suitable semiconductor from solution into the nanogap structures. Of principal interest is the wide bandgap transparent semiconductor, zinc oxide (ZnO). Lateral ZnO Schottky diodes show outstanding characteristics, with on-off ratios of up to 106 and forward current values up to 10 mA for obtained upon combining a-Lith with low-temperature solution processing. These unique devices are further investigated for application in rectifier circuits, and in particular for potential use in radio frequency identification (RFID) tag technology. The ZnO diodes are found to surpass the 13.56 MHz frequency bernchmark used in commercial applications and approach the ultra-high frequency (UHF) band (hundreds of megahertz), outperforming current state of the art printed diodes. Solution processed fullerene (C60) is also shown to approach the UHF band in this co-planar device configuration, highlighting the viability of a-Lith for enabling large-area flexible radio frequency nanoelectronics. Finally, resistive switching memory device arrays based on a-Lith patterned nanogap aluminium symmetric electrodes are demonstrated for the first time. These devices are based either on empty aluminium nanogap electrodes, or with the gap filled with a solution-processed semiconductor, the latter being ZnO, the semiconducting polymer poly(9,9-dioctylfluorene-alt-benzothiadiazole) (F8BT) or carbon nanotube/polyfluorene blends. The switching mechanism, retention time and switching speed are investigated and compared with published data. The fabrication of arrays of these devices illustrates the potential of a-Lith as a simple technique for the realisation of large-area high-density memory applications.
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Hutchinson, G. D. "Superconducting nanoelectronics using controllable Josephson junctions." Thesis, University of Cambridge, 2006. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.604859.
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This dissertation describes the fabrication, measurement and modelling for a micrometer sized direct-current superconducting quantum interference device (DC-SQID), which had its critical current controlled by a process of non-equilibrium phonon (hot-phonon) irradiation from a nanofabricated gated structure. The method of control was achieved via close proximity, normal-metal constrictions that injected hot-phonons on the Dayem bridge Josephson junctions in the DC-SQUID. A hot electron population created these hot-phonons in the control layer’s normal-metal constrictions when a bias current was applied whilst the device was immersed in liquid helium. This hot-phonon injection layer was produced from a multi-layer fabrication technique that allowed for the creation of an in-line structure; a structure fabrication through a reactive-ion etch process performed on a top-down, nano-lithographically defined constriction geometry. The controlled microSQUID device was created using an inner loop size less than a micrometer and contained two Dayem bridge Josephson junctions with a width and length of approximately 100 and 200 nanometres respectively, in a 50 nanometre thick niobium thin-film. The 70 nanometre thick chromium/titanium normal-metal constructions and the weak link Josephson junction were in thermal contact, but in electrical isolation, due to a 30 nanometre silicon dioxide dielectric layer. The device was measured at a temperature of 4.2 degrees Kelvin, and the manipulation of the critical current oscillations of the microSQUID was performed. The critical current control mechanism, utilised in this device, demonstrated a technique where the magnetic hysteresis was eliminated, and the thermal hysteresis in the current-voltage characteristics of the microSQUID was reduced. An observed characteristic of the controlled reduction of the critical current in this device, illustrated by the one-dimensional microSQUID model presented in this dissertation, was the change in the effective length of the Dayem bridge Josephson junctions. This manifested itself through the shortening of the Cooper pair coherence length in the niobium thin-film under the hot-photon irradiation. The experimental data presented in this dissertation, and its interpretation in relation to the microSQUID model, confirms that this technique, based on hot-phonon irradiation for controlling the critical current in Dayem bridge Josephson Junctions, is compatible with the Josephson effect. Therefore, my dissertation shows a feasible method for post-fabrication parameter control in superconducting circuits using Dayem bridge Josephson junctions.
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Tan, Yong-Tsong. "Nanoelectronics using polycrystalline and nanocrystalline silicon." Thesis, University of Cambridge, 2001. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.621321.
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ROTTA, DAVIDE. "Emerging devices and materials for nanoelectronics." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2015. http://hdl.handle.net/10281/76048.
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Questa tesi analizza la possibile implementazione di due tipologie di dispositivi elettronici con funzionalità innovative: dispositivi per la computazione quantistica e transistors a film sottile. Negli ultimi decenni l’industria dei semiconduttori ha portato alla realizzazione di circuiti integrati con milioni di transistors e performance sempre migliori a costi contenuti. Tuttavia, questo processo di miniaturizzazione è giunto a un punto tale che i dispositivi elettronici sono ora composti da pochissimi atomi e ridurne ulteriormente le dimensioni sta diventando sempre più difficile. L’International Technology Roadmap of Semiconductors (ITRS) suggerisce due vie alternative per migliorare le caratteristiche dei dispositivi a partire dalla Front-End-Of-Line. La prima si avvale di nuovi dispositivi sulla base di architetture innovative o dell’utilizzo di diverse variabili di stato (Emerging Research Devices), mentre la seconda punta all’utilizzo di nuovi materiali (Emerging Research Materials).
Questa tesi esamina due possibili candidati in questa ottica: i dispositivi per la computazione quantistica su architettura Complementary Metal-Oxide-Semiconductor (CMOS) e i transistors a film sottile basati su un semiconduttore bidimensionale come il MoS2. Da un lato, l’integrazione della computazione quantistica su Si sfrutterebbe il background tecnologico dell’industria dei semiconduttori per implementare su larga scala un nuovo protocollo di computazione dotato di un potenziale enorme e ancora inesplorato. D’altra parte il di-solfuro di molibdeno (MoS2) è intrinsecamente scalabile, in quanto può essere esfoliato fino allo spessore di un singolo strato atomico. Per questo motivo potrebbe essere un semiconduttore ideale per dispositivi elettronici ultrascalati, così come per applicazioni nella sensoristica, nell’optoelettronica e nell’elettronica flessibile.
Questo lavoro mostra l’attività svolta al Laboratorio MDM-IMM-CNR nell’ambito del corso di dottorato in Nanostrutture e Nanotecnologie all’Università di Milano Bicocca. Lo sviluppo e l’utilizzo di processi di fabbricazione della nanoelettronica, in particolare la litografia a fascio elettronico (EBL), sono stati parte integrante dell’attività sperimentale dedicata alla realizzazione di dispositivi CMOS-compatibili per la computazione quantistica e per l’integrazione di film sottili di MoS2 in strutture Metal-Oxide-Semiconductor Field-Effect-Transistor (MOS FET).
I necessari passi di processo sono stati adeguatamente calibrati e ottimizzati in modo da ottenere dispositivi quantistici basati su Quantum Dots (QD) con dimensioni caratteristiche inferiori a 50 nm. Tali dispositivi sono stati sviluppati con tecnologia Silicon-On-Insulator (SOI), mantenendo così la compatibilità con lo standard della tecnologia CMOS.
Dispositivi a singolo donore e con QD di silicio sono stati poi caratterizzati elettricamente a temperature criogeniche (fino a 300 mK). Impulsando i potenziali di gate in modo controllato, è stato possibile studiare fenomeni di tunneling di singoli elettroni su un donore in alti campi magnetici (8T). In modo analogo è stato dimostrato il controllo dello stato di carica di QDs di Si. In particolare, si è osservato l’insorgere di rumore telegrafico associato al movimento di un singolo elettrone tra due QDs. Infine è stato condotto uno studio di fattibilità per l’integrazione su larga scala di un’architettura di computazione quantistica (il cosiddetto hybrid spin qubit) basata su doppi QDs di Si.
Sul secondo fronte sono stati realizzati dei MOS FETs a film sottile basati su frammenti di MoS2, ottenuti per esfoliazione meccanica e contattati elettricamente tramite litografia EBL. Tali transistors sono poi stati caratterizzati elettricamente, con particolare attenzione alle proprietà di trasporto di carica e alla spettroscopia delle trappole all’interfaccia con l’ossido.<br>This work of thesis explores two emerging research device concepts as possible platforms for novel integrated circuits with unconventional functionalities. Nowadays integrated circuits with advanced performances are available at affordable costs, thanks to the progressive miniaturization of electronic components in the last decades. However, bare geometrical scaling is no more a practical way to improve the device performances and alternative strategies must be considered to achieve an equivalent scaling of the functionalities. The introduction of conceptually new devices and paradigms of information processing (Emerging Research Devices) or new materials with unconventional properties (Emerging Research Materials) are viable approaches, as indicated by the International Technology Roadmap of Semiconductors (ITRS), to enhance the functionalities of integrated circuits at the Front-End-Of-Line. The two options investigated to this respect are silicon devices for quantum computation based on a classical Complementary Metal-Oxide-Semiconductor (CMOS) platform and standard Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) based on MoS2 thin film. In particular, the integration of Quantum Information Processing (QIP) in Si would take advantage of Si-based technology to introduce a completely new paradigm of information processing that has the potential to outperform classical computers in some computational tasks, like prime number factoring and the search in a big database. MoS2, conversely, can be exfoliated up to the single layer thickness. Such intrinsic and extreme scalability makes this material suitable for end-of-roadmap ultrascaled electronic devices as well as for other applications in the fields of sensors, optoelectronics and flexible electronics. This work reports on the experimental activity carried out at Laboratory MDM-IMM-CNR in the framework of the PhD school on Nanostructures and Nanotechnology at Università di Milano Bicocca. Electron Beam Lithography (EBL) and mainstream clean-room processing techniques have been intensively utilized to fabricate CMOS devices for QIP on the one hand and to integrate mechanically exfoliated MoS2 flakes in a conventional FET structure on the other hand. After a careful calibration and optimization of the process parameters, several different Quantum Dot (QD) configurations were designed and fully realized, achieving critical dimensions under 50 nm. Such device architectures were developed on a Silicon-On-Insulator (SOI) platform, in order to eventually access a straightforward integration into the CMOS mainstream technology. Si-QDs and donor-based devices have been then tested by electrical characterization techniques at cryogenic temperatures down to 300 mK. In detail, single electron tunneling events on a donor atom have been controlled by pulsed-gate techniques in high magnetic fields up to 8T, providing a preliminary characterization for the initialization procedure of donor qubits. The control of the charge states of Si-QDs have been also demonstrated by means of stability diagrams as well as the analysis of random telegraph noise arising from single electron tunneling between two QDs. Finally, a feasibility study for the large scale integration of quantum information processing was done based on a double QD hybrid qubit architecture. On the other side, MoS2 thin film transistors have been made by mechanical exfoliation of crystalline MoS2 and electrodes definition by EBL. Electrical characterization was performed on such devices, with a particular focus on the electrical transport in a FET device and on the spectroscopy of interface traps, that turns out to be a limiting factor for the logic operation.
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Rice, John S. "Future satellite technology the role of nanoelectronics." Thesis, Monterey, Calif. : Springfield, Va. : Naval Postgraduate School ; Available from National Technical Information Service, 1998. http://handle.dtic.mil/100.2/ADA355660.
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Thesis (M.S. in Applied Physics) Naval Postgraduate School, September 1998.<br>Thesis advisor(s): James Luscombe, Robert Armstead. "September 1998." Includes bibliographical references (p. 49-51). Also available online.
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Ayhan, Pinar. "Probabilistic CMOS (PCMOS) in the Nanoelectronics Regime." Diss., Georgia Institute of Technology, 2007. http://hdl.handle.net/1853/19877.
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Motivated by the necessity to consider probabilistic approaches to future designs, the main objective of this thesis was to develop and characterize energy efficient probabilistic CMOS (PCMOS) circuits that can be used to implement low energy computing platforms. The simplest circuit characterized was a PCMOS inverter (switch). An analytical model relating the energy consumption per switching (E) of this switch to its probability of correctness, p was derived. This characterization can also be used to evaluate the energy and performance savings that are achieved by PCMOS switch based computing platforms. The characterization of a PCMOS inverter was also extended to larger circuits whose probabilistic behavior was analyzed by first developing probability models of primitive gates, which were then input to a graph-based model to find the probabilities of larger circuits. The analysis of larger probabilistic circuits provides a basis for analyzing probabilistic behaviors due to noise in future technologies, and can be used in probabilistic design and synthesis methods to improve circuit reliability. Another important design criterion is the speed of a PCMOS circuit. The trade-offs between the energy, speed, and p of PCMOS circuits were also analyzed. Based on this study, various methods were proposed to optimize energy delay product (EDP) and p under given constraints on p, performance, and EDP. The sensitivity of the analysis with respect to variations in temperature, supply voltage, and threshold voltage was also considered.
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Ingram, Ian David Victor. "New materials and processes for flexible nanoelectronics." Thesis, University of Manchester, 2013. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.588129.
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Planar electronic devices represent an attractive approach towards roll-to-roll printed electronics without the need for the sequential, precisely aligned, patterning steps inherent in the fabrication of conventional ‘3D’ electronic devices. Self-switching diodes (SSDs) and in-plane-gate field-effect transistors (IPG-FETs) can be patterned using a single process into a substrate precoated with semiconductor.These devices function in depletion mode, requiring the semiconductor to be doped in order for the devices to function. To achieve this, a reliable and controllable method was developed for doping organic semiconducting polymers by the immersion of optimally deposited films in a solution of dopant. The process was shown to apply both semicrystalline and air-stable, amorphous materials indicating that the approach is broadly applicable to a wide range of organic semiconductors.Simultaneously with the development of the doping protocol specialised hot-embossing equipment was designed and constructed and a high-yielding method of patterning the structures of IPG-FETs and SSDs was arrived at. This method allowed for consistent and reliable patterning of features with a minimum line-width of 200nm.Following the development of these doping and patterning processes these were combined to fabricate controllably doped, functioning planar devices. SSDs showed true zero-threshold rectification behaviour with no observed breakdown in the reverse direction up to 100 V. IPG-FETs showed switching behaviour in response to an applied gate potential and were largely free of detectable gate leakage current, verifying the quality of the patterning process.Furthermore, high-performance semiconducting polymer PAAD was synthesised and characterised in field-effect transistors as steps towards its use in planar electronic devices. It was also shown that this material could be doped using the developed immersion doping protocol and that this protocol was compatible with top-gated device architectures and the use of fluoropolymer CYTOP as a dielectric.
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Gaury, Benoit. "Emerging concepts in time-resolved quantum nanoelectronics." Thesis, Grenoble, 2014. http://www.theses.fr/2014GRENY026/document.
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Grâce aux progrès techniques récents, les sources d'électrons uniques sontpassées de la théorie au laboratoire. Des expériencesconceptuellement nouvelles où l'on sonde directement la dynamique quantiqueinterne des systèmes sont désormais possibles. Dans cette thèse nousdéveloppons les outils analytiques et numériques pour analyser et comprendre cesproblèmes. Les simulations requièrent une résolution spatiale appropriée pourles systèmes, et des temps simulés suffisament longs pour sonder leurs tempscaractéristiques. Jusqu'à présent l'approche théorique standard utilisée pour traiter de tels problèmes numériquement---connue sous les dénominations de formalisme Keldysh ou NEGF (Fonctions de Green Hors Equilibre)---n'a pas été très fructueuse, principalement à cause du coût en temps de calcul prohibitif. Nous proposons une reformulation decette technique sous la forme des fonctions d'onde électroniques du système dansune représentation énergie--temps. Le coût de calcul de notre algorithmenumérique est maintenant linéaire avec le temps simulé et le volume du système,rendant possible la simulation de système contenant $10^5-10^6$ atomes/sites.Nous utilisons cet outil pour proposer de nouveaux effets intrigants ainsi quedes expériences. Nous introduisons la modification dynamique du motifd'interférence d'un système quantique. Nous montrons, par exemple, que la montéed'une tension DC $V$ sur un interféromètre électronique produit un régimetransitoire où le courant oscille comme $cos(eVt/hbar)$. Nous prévoyons unegrande variété d'effets nouveaux lorsque les circuits de nanoélectronique sontsondés très rapidement. Les outils et concepts développés dans cette thèseauront un rôle clé dans l'analyse et les propositions des expériences à venir<br>With the recent technical progress, single electron sources have moved fromtheory to the lab. Conceptually new types of experiments where one probesdirectly the internal quantum dynamics of the devices are within grasp. In thisthesis we develop the analytical and numerical tools for handling suchsituations. The simulations require appropriate spatial resolution for thesystems, and simulated times long enough so that one can probe their internalcharacteristic times. So far the standard theoretical approach used to treatsuch problems numerically---known as Keldysh or NEGF (Non Equilibrium Green'sFunctions) formalism---has not been very successful mainly because of aprohibitive computational cost. We propose a reformulation of the NEGFtechnique in terms of the electronic wave functions of the system in anenergy--time representation. The numerical algorithm we obtain scales nowlinearly with the simulated time and the volume of the system, and makessimulation of systems with $10^5-10^6$ atoms/sites feasible. We leverage thistool to propose new intriguing effects and experiments. In particular weintroduce the concept of dynamical modification of interference pattern of aquantum system. For instance, we show that when raising a DC voltage $V$ to anelectronic interferometer, the transient current responseoscillates as $cos(eVt/hbar)$. We expect a wealth of new effects whennanoelectronic circuits are probed fast enough. The tools and conceptsdeveloped in this work shall play a key role in the analysis and proposal ofupcoming experiments
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Weston, Joseph. "Numerical methods for time-resolved quantum nanoelectronics." Thesis, Université Grenoble Alpes (ComUE), 2016. http://www.theses.fr/2016GREAY040/document.
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De récents progrès dans la nanoélectronique quantique ont donné lieu à denouvelles expériences avec des sources cohérentes d'électrons unique. Lorsqu'undispositif électronique quantique est manipulé sur une échelle de temps pluscourte que le temps de vol caractéristique d'un électron à travers ledispositif, toute une gamme de possibilités qui sont conceptuellement nouvellesdeviennent possible. Pour traiter de telles situations physiques, des avancéescorrespondantes sont nécessaires dans les techniques de simulation, pour aiderà comprendre, ainsi qu'à concevoir, la prochaine génération d'expériences dansce domaine.Les techniques les plus avancées pour simuler ce genre de physique nécessitentun temps de calcul qui croît de linéairement avec la taille dusystème, mais de manière quadratique avec la durée simulée.Ceci est particulièrement problématique pour les cas où un électron restedans le dispositif pendant une durée beaucoup plus longue que le temps devol balistique. Dans cette thèse on propose d'améliorer un algorithmeexistant, basé sur des fonctions d'onde, pour traiter le transport quantiquerésolu en temps dont le temps de calcul croît linéairement avec la taille du système ainsique la durée simulée. Par la suite on exploite cet algorithme pour étudierplusieurs systèmes physiques intéressants. En particulier on trouve quel'application d'un train d'impulsions de tension à un interféromètre à électronspeut stabiliser la modification dynamique du schéma d'interférence.On exploite cet effet pour faire de la spectroscopied'états d'Andreev et de Majorana existant dans des structure hybridessupraconducteur-nanofil.Les algorithmes numériques sont implémentés en tant qu'extension du logicielde transport quantique Kwant. Cette implémentation est utilisée pour tousles résultats numériques présentés dans la thèse, ainsi que d'autres projetsde recherche couvrants une grande gamme de physique: effet Hall quantique,isolants topologiques de Floquet, interféromètres de type Fabry-Pérot, etjonctions supraconductrices<br>Recent technical progress in the field of quantum nanoelectronics have lead toexciting new experiments involving coherent single electron sources.When quantum electronic devices are manipulated on time scales shorterthan the characteristic time of flight of electrons through the device, a wholeclass of conceptually new possibilities become available. In order totreat such physical situations, corresponding advances in numerical techniquesand their software implementation are required both as a tool to aidunderstanding, and also to help when designing the next generation ofexperiments in this domain.Recent advances in numerical methods have lead to techniques for which thecomputation times scales linearly with the system volume, but as thesquare of the simulation time desired. This is particularly problematicfor cases where the characteristic dwell time of electrons in the centraldevice is much longer than the ballistic time of flight. Here, we proposean improvement to an existing wavefunction based algorithm fortreating time-resolved quantum transport which scales linearly in both thesystem volume and desired simulation time. We use this technique tostudy a number of interesting physical cases. In particular we find that theapplication of a train of voltage pulses to an electronic interferometercan be used to stabilise the dynamical modification of the interferencethat was recently proposed. We use this to perform spectroscopy on Majoranaand Andreev resonances in hybrid superconductor-nanowire structures.The numerical algorithms are implemented as an extension to the Kwantquantum transport software. This implementation is used for all the numericalresults presented here, in addition to other work, covering a wide varietyof physical applications: quantum Hall effect, Floquet topological insulators,Fabry-Perot interferometers and superconducting junction
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Rossignol, Benoît. "Time-resolved quantum nanoelectronics in electromagnetic environments." Thesis, Université Grenoble Alpes, 2020. http://www.theses.fr/2020GRALY004.
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La nanoélectronique quantique est dans une phase de grande expansion, soutenue principalement par le développement de l'informatique quantique. Une grande précision est nécessaire pour atteindre les objectifs actuels, mais d'un autre côté, les expériences sont aussi plus complexes que jamais. Les outils numériques semblent nécessaires pour réaliser la compréhension exigée tout en traitant une telle complexité. Les échelles de temps concernées sont de plus en plus courtes et se rapprochent des échelles de temps quantiques intrinsèques de l'appareil, comme le temps de vol. Les travaux antérieurs de notre groupe ont simulé le transport d'électrons en fonction du temps à une échelle quantique. Cette thèse vise à améliorer les algorithmes précédents pour obtenir une plus grande précision et une meilleure description des systèmes en incluant l'environnement électronique.Ce travail est divisé en trois domaines principaux. Tout d'abord, nous améliorons les outils de simulation numérique en fonction du temps pour prendre en compte un environnement électronique d'une manière cohérente. Le nouvel algorithme peut atteindre une précision arbitraire d'une manière contrôlée. Deuxièmement, le nouvel algorithme est utilisé pour démontrer l'existence de nouveaux phénomènes physiques. Nous étudions les jonctions Josephson dans différents environnements pour mettre en valeur le rôle des quasi-particules, l'effet d'une impulsion très courte, et pour étudier les techniques de caractérisation de la jonction topologique.Enfin, différents développements sont à l'étude afin d'intégrer le phénomène de décohérence et le bruit quantique dans les simulations<br>Quantum nanoelectronics is in a phase of great expansion, supported mainlyby the development of quantum computing. A high degree of precision isrequired to achieve current objectives, but on the other hand, the experi-ences are also more complex than ever. Nuremical tools seem necessary toachieve the required understanding while dealing with such complexity. Thetime scales involved are getting shorter and are getting closer to the intrinsicquantum time scales of the device, such as time of flight. Our group’s pre-vious work has simulated time-dependent electron transport on a quantumscale. This thesis aims to improve the previous algorithms to obtain greateraccuracy and a better description of the systems by including the electronicenvironment. This work is divided into three main areas. First, we improveof numerical time-dependent simulation tools to take into account an elec-tronic environment in a self-consistent way. The new algorithm can achievearbitrary accuracy in a controlled way. Second, the new algorithm is used todemonstrate the existence of new physical phenomena. We study Josephsonjunctions in different environments to enhance the role of quasi-particles, theeffect of a very short pulse, and to study topological junction characteriza-tion techniques. Finally, various developments are being studied to integratethe phenomenon of decoherence and quantum noise into the simulations
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Vodenicarevic, Damir. "Rhythms and oscillations : a vision for nanoelectronics." Thesis, Université Paris-Saclay (ComUE), 2017. http://www.theses.fr/2017SACLS518/document.
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Avec l'avènement de l'"intelligence artificielle", les ordinateurs, appareils mobiles et objets connectés sont amenés à dépasser les calculs arithmétiques et logiques pour lesquels ils ont été optimisés durant des décennies, afin d'effectuer des tâches "cognitives" telles que la traduction automatique ou la reconnaissance d'images et de voix, et pour lesquelles ils ne sont pas adaptés. Ainsi, un super-calculateur peut-il consommer des mégawatts pour effectuer des tâches que le cerveau humain traite avec 20 watt. Par conséquent, des système de calcul alternatifs inspirés du cerveau font l'objet de recherches importantes. En particulier, les oscillations neurales semblant être liées à certains traitements de données dans le cerveau ont inspiré des approches détournant la physique complexe des réseaux d'oscillateurs couplés pour effectuer des tâches cognitives efficacement. Cette thèse se fonde sur les avancées récentes en nano-technologies permettant la fabrication de nano-oscillateurs hautement intégrables pour proposer et étudier de nouvelles architectures neuro-inspirées de classification de motifs exploitant la dynamique des oscillateurs couplés et pouvant être implémentées sur puce<br>With the advent of "artificial intelligence", computers, mobile devices and other connected objects are being pushed beyond the realm of arithmetic and logic operations, for which they have been optimized over decades, in order to process "cognitive" tasks such as automatic translation and image or voice recognition, for which they are not the ideal substrate. As a result, supercomputers may require megawatts to process tasks for which the human brain only needs 20 watt. This has revived interest into the design of alternative computing schemes inspired by the brain. In particular, neural oscillations that appear to be linked to computational activity in the brain have inspired approaches leveraging the complex physics of networks of coupled oscillators in order to process cognitive tasks efficiently. In the light of recent advances in nano-technology allowing the fabrication of highly integrable nano-oscillators, this thesis proposes and studies novel neuro-inspired oscillator-based pattern classification architectures that could be implemented on chip
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Liu, Jia. "Biomimetics through nanoelectronics: development of three-dimensional macroporous nanoelectronics for building smart materials, cyborg tissues and injectable biomedical electronics." Thesis, Harvard University, 2014. http://dissertations.umi.com/gsas.harvard:11510.
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Nanoscale materials enable unique opportunities at the interface between physical and life sciences. The interface between nanoelectronic devices and biological systems makes possible communication between these two diverse systems at the length scale relevant to biological functions. The development of a bottom-up paradigm allows the nanoelectronic units to be synthesized and patterned on unconventional substrates. In this thesis, I will focus on the development of three-dimensional (3D) nanoelectronics, which mimics the structure of porous biomaterials to explore new methods for seamless integration of electronics with other materials, with a special focus on biological tissue.<br>Chemistry and Chemical Biology