Journal articles: 'Nanoelectronic device'

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Nikolić, K., M. Forshaw, and R. Compañó. "The Current Status of Nanoelectronic Devices." International Journal of Nanoscience 02, no. 01n02 (February 2003): 7–29. http://dx.doi.org/10.1142/s0219581x03001048.

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Over the last thirty years, many new physical phenomena have been discovered and suggested for use in data processing devices. Many, but not all, of these devices are described as "nanoelectronic", because one or more of their characteristic dimensions lie in the size range ≈1–100 nm. However, any new idea has a long way to go before it can achieve any practical value. It is necessary to develop and test a series of increasingly complicated structures. Starting from (1) the basic physical effect and its theoretical description, one must design and fabricate prototypes of (2) a single device, then (3) a simple circuit, then (4) functional units such as assemblies of logic gates or blocks of memory cells, and eventually (5) electronic chips. This article provides an overview of the development status of some of these device technologies.

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Kosina, Hans, and Siegfried Selberherr. "Device Simulation Demands of Upcoming Microelectronics Devices." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 115–36. http://dx.doi.org/10.1142/s0129156406003576.

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An overview of models for the simulation of current transport in micro- and nanoelectronic devices within the framework of TCAD applications is presented. Starting from macroscopic transport models, currently discussed enhancements are specifically addressed. This comprises the inclusion of higher-order moments into the transport models, the incorporation of quantum correction and tunneling models up to dedicated quantum-mechanical simulators, and mixed approaches which are able to account for both, quantum interference and scattering. Specific TCAD requirements are discussed from an engineer's perspective and an outlook on future research directions is given.

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White, Marvin H., Yu (Richard) Wang, Stephen J. Wrazien, and Yijie (Sandy) Zhao. "ADVANCEMENTS IN NANOELECTRONIC SONOS NONVOLATILE SEMICONDUCTOR MEMORY (NVSM) DEVICES AND TECHNOLOGY." International Journal of High Speed Electronics and Systems 16, no. 02 (June 2006): 479–501. http://dx.doi.org/10.1142/s0129156406003801.

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This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.

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Panfilov, Y. V., I. A. Rodionov, I. A. Ryzhikov, A. S. Baburin, D. O. Moskalev, and E. S. Lotkov. "Ultrathin film deposition for nanoelectronic device manucturing." IOP Conference Series: Materials Science and Engineering 781 (May 5, 2020): 012021. http://dx.doi.org/10.1088/1757-899x/781/1/012021.

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Saxena, Shubhangi, and Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node." ECS Transactions 107, no. 1 (April 24, 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.

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Since the last six decades, technology node has grown smaller from micrometer to nanometer dimensions. In continuation of Moore's Law, the research is going on for device/supply voltage shrinking to go beyond 22 nm CMOS technology node. However, many physical and quantum challenges appear at a smaller scale, which causes shrinking beyond 22 nm critical and needs innovative materials and devices for scaling in the nanometer regime. Incorporating nanoengineered materials to realize research achievements has shown timely development with significant influence in electronic industries. These new materials and devices hold promise as potential device candidates to be integrated onto the silicon platform to enhance semiconductor industry growth and extend Moore's Law. Here we address state–of–the–art research trends in nanomaterials and nanodevices for future technology node and discuss associated challenges.

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KOSINA, HANS. "NANOELECTRONIC DEVICE SIMULATION BASED ON THE WIGNER FUNCTION FORMALISM." International Journal of High Speed Electronics and Systems 17, no. 03 (September 2007): 475–84. http://dx.doi.org/10.1142/s0129156407004667.

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Coherent transport in mesoscopic devices is well described by the Schrödinger equation supplemented by open boundary conditions. When electronic devices are operated at room temperature, however, a realistic transport model needs to include carrier scattering. In this work the kinetic equation for the Wigner function is employed as a model for dissipative quantum transport. Carrier scattering is treated in an approximate manner through a Boltzmann collision operator. A Monte Carlo technique for the solution of this kinetic equation has been developed, based on an interpretation of the Wigner potential operator as a generation term for numerical particles. Including a multi-valley semiconductor model and a self-consistent iteration scheme, the described Monte Carlo simulator can be used for routine device simulations. Applications to single barrier and double barrier structures are presented. The limitations of the numerical Wigner function approach are discussed.

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Nidhi, Tashi Nautiyal, and Samaresh Das. "Large-Scale Synthesis of Nickel Sulfide for Electronic Device Applications." MRS Advances 5, no. 52-53 (2020): 2727–35. http://dx.doi.org/10.1557/adv.2020.339.

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AbstractSeveral techniques have been employed for large-scale synthesis of group 10 transition metal dichalcogenides (TMDCs) based on platinum and palladium for nano- and opto-electronic device applications. Nickel Sulphides (NixSy), belonging to group 10 TMDC family, have been widely explored in the field of energy storage devices such as batteries and supercapacitors, etc. and commonly synthesized through the solution process or hydrothermal methods. However, the high-quality thin film growth of NixSy for nanoelectronic applications remains a central challenge. Here, we report the chemical vapor deposition (CVD) growth of NiS2 thin film onto a two-inch SiO2/Si substrate, for the first time. Techniques such as X-ray photoelectron spectroscopy, X-ray Diffraction, Raman Spectroscopy, Scanning Electron Microscopy, have been used to analyse the quality of this CVD grown NiS2 thin film. A high-quality crystalline thin film of thickness up to a few nanometres (~28 nm) of NiS2 has been analysed here. We also fabricated a field-effect device based on NiS2 thin film using interdigitated electrodes by optical lithography. The electrical performance of the fabricated device is characterized at room temperature. On applying the drain voltage from -2 to +2 V, the device shows drain current in the range of 10-9 A before annealing and in the range of 10-6 A after annealing. This, being comparable to that from devices based on MoS2 and other two-dimensional materials, projects CVD grown NiS2 as a good alternative material for nanoelectronic devices.

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Liffmann, R., M. Homberger, M. Mennicken, S. Karthäuser, and U. Simon. "Polydiacetylene stabilized gold nanoparticles – extraordinary high stability and integration into a nanoelectrode device." RSC Advances 5, no. 125 (2015): 102981–92. http://dx.doi.org/10.1039/c5ra17545c.

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Janes, D. B., V. R. Kolagunta, M. Batistuta, B. L. Walsh, R. P. Andres, Jia Liu, J. Dicke, et al. "Nanoelectronic device applications of a chemically stable GaAs structure." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 17, no. 4 (1999): 1773. http://dx.doi.org/10.1116/1.590824.

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Müller, T., A. Lorke, Q. T. Do, F. J. Tegude, D. Schuh, and W. Wegscheider. "A three-terminal planar selfgating device for nanoelectronic applications." Solid-State Electronics 49, no. 12 (December 2005): 1990–95. http://dx.doi.org/10.1016/j.sse.2005.09.004.

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Bae, Choelhwyi, and Gerald Lucovsky. "Low temperature semiconductor surface passivation for nanoelectronic device applications." Surface Science 532-535 (June 2003): 759–63. http://dx.doi.org/10.1016/s0039-6028(03)00181-x.

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WONG, H. S. PHILIP. "NANOELECTRONICS – OPPORTUNITIES AND CHALLENGES." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 83–94. http://dx.doi.org/10.1142/s0129156406003540.

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As device sizes approach the nanoscale, new opportunities arise from harnessing the physical and chemical properties at the nanoscale. It is now feasible to contemplate new nanoelectronic systems based on new devices with completely new system architectures. This paper will give an overview of the materials, technology, and device opportunities in the nanoscale era. So far, much of the nanoscale sciences have been researched in the physics, chemistry, and materials science communities. While there have been plenty of good science in the nano world, nanotechnology is still at its infancy. The engineering community is poised to make a major impact in transforming good nanoscience into useful nanotechnology. The disciplined performance benchmarking against alternatives as practiced by the engineering community will prove to be invaluable to the development of new nanotechnologies. Examples of such performance benchmarking exercises will be shown and directions for future work will be suggested.

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Bondarev, A. V., and V. N. Efanov. "ANALYSIS OF DYNAMIC PROCESSES IN NANOELECTRONIC STRUCTURES BASED ON MEMRESISTIVE ELEMENTS." Izvestiya of Samara Scientific Center of the Russian Academy of Sciences 23, no. 2 (2021): 91–97. http://dx.doi.org/10.37313/1990-5378-2021-23-2-91-97.

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The emergence of recently a wide range of nanoelectronic components is expanding the possibilities of information and computing systems. First of all, it concerns supercomputers with Petaflopovaya productivity. To achieve such performance on the basis of modern microelectronic devices, computing complexes are created, combining up to 100 thousand processors that consume about 100 megawatts of electrical energy and occupy about 300 square meters. A significant increase in productivity, reduction of energy consumption and a decrease in mass-dimensional indicators can be ensured in the transition from microelectronic to a nanoelectronic element base. For such promising nanoelectronic components include memristors. A memristor (from memory — memory, and resistor-electrical resistance) is a passive element in microelectronics that can change its resistance depending on the charge flowing through it. For a long time, the memristor was considered a theoretical model [7], which cannot be implemented in practice, until the first sample of the element demonstrating the properties of the memristor was created in 2008 by a team of scientists led by R. S. Williams in the research laboratory of Hewlett-Packard. The device does not store charge like a capacitor, does not support magnetic flux like an inductor. The change in the properties of the device is provided by chemical reactions in a thin two-layer film of titanium dioxide (5 nm). One layer of the device film is slightly depleted of oxygen and oxygen vacancies migrate between the layers when the voltage changes. This implementation of the memristor belongs to the class of nanoion devices. The observed phenomenon of hysteresis in the memristor allows it to be used, among other things, as a memory cell [9, 10-15, 20-21]. The already studied properties of memristors allow us to say that on their basis it is possible to create computers of a fundamentally new architecture, significantly exceeding semiconductor ones in performance. Due to the regular structure of intersecting nanowires, memristor fabrication is quite simple, especially in comparison with the complex structure of modern processors based on CMOS technology. As a result, the write / read time in the memristor memory cell does not exceed 5 ns. The number of read / write cycles exceeds 1012, and the storage time of information is more than 10 years. All this suggests that memristor memory will become the only type of computer memory. However, the use of such elements in real-life conditions leads to the fact that the electrical parameters of these devices vary over a wide range. This uncertainty in characteristics complicates circuit analysis and the entire design process for electronic devices that include memristor components. In this regard, the problem of assessing the stability of nanoelectronic structures based on memresistive elements under conditions of uncertain external influences is urgent.

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Mennicken, Max, Sophia Katharina Peter, Corinna Kaulen, Ulrich Simon, and Silvia Karthäuser. "Impact of device design on the electronic and optoelectronic properties of integrated Ru-terpyridine complexes." Beilstein Journal of Nanotechnology 13 (February 15, 2022): 219–29. http://dx.doi.org/10.3762/bjnano.13.16.

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The performance of nanoelectronic and molecular electronic devices relies strongly on the employed functional units and their addressability, which is often a matter of appropriate interfaces and device design. Here, we compare two promising designs to build solid-state electronic devices utilizing the same functional unit. Optically addressable Ru-terpyridine complexes were incorporated in supramolecular wires or employed as ligands of gold nanoparticles and contacted by nanoelectrodes. The resulting small-area nanodevices were thoroughly electrically characterized as a function of temperature and light exposure. Differences in the resulting device conductance could be attributed to the device design and the respective transport mechanism, that is, thermally activated hopping conduction in the case of Ru-terpyridine wire devices or sequential tunneling in nanoparticle-based devices. Furthermore, the conductance switching of nanoparticle-based devices upon 530 nm irradiation was attributed to plasmon-induced metal-to-ligand charge transfer in the Ru-terpyridine complexes used as switching ligands. Finally, our results reveal a superior device performance of nanoparticle-based devices compared to molecular wire devices based on Ru-terpyridine complexes as functional units.

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Vahapoglu, Ensar, James P. Slack-Smith, Ross C. C. Leon, Wee Han Lim, Fay E. Hudson, Tom Day, Tuomo Tanttu, et al. "Single-electron spin resonance in a nanoelectronic device using a global field." Science Advances 7, no. 33 (August 2021): eabg9158. http://dx.doi.org/10.1126/sciadv.abg9158.

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Spin-based silicon quantum electronic circuits offer a scalable platform for quantum computation, combining the manufacturability of semiconductor devices with the long coherence times afforded by spins in silicon. Advancing from current few-qubit devices to silicon quantum processors with upward of a million qubits, as required for fault-tolerant operation, presents several unique challenges, one of the most demanding being the ability to deliver microwave signals for large-scale qubit control. Here, we demonstrate a potential solution to this problem by using a three-dimensional dielectric resonator to broadcast a global microwave signal across a quantum nanoelectronic circuit. Critically, this technique uses only a single microwave source and is capable of delivering control signals to millions of qubits simultaneously. We show that the global field can be used to perform spin resonance of single electrons confined in a silicon double quantum dot device, establishing the feasibility of this approach for scalable spin qubit control.

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Lei, Wen, Bo Cai, Huanfu Zhou, Gunter Heymann, Xin Tang, Shengli Zhang, and Xing Ming. "Ferroelastic lattice rotation and band-gap engineering in quasi 2D layered-structure PdSe2 under uniaxial stress." Nanoscale 11, no. 25 (2019): 12317–25. http://dx.doi.org/10.1039/c9nr03101d.

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The quasi 2D layered-structure PdSe₂ is predicted to be an intrinsic ferroelastic material with a stress-driven 90° lattice rotation, which is a promising material for perspective applications in microelectromechanical and nanoelectronic device.

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Fedoseyev, Alexander I., Marek Turowski, and Marek S. Wartak. "Kinetic and Quantum Models for Nanoelectronic and Optoelectronic Device Simulation." Journal of Nanoelectronics and Optoelectronics 2, no. 3 (December 1, 2007): 234–56. http://dx.doi.org/10.1166/jno.2007.303.

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Muhonen, Juha T., Juan P. Dehollain, Arne Laucht, Fay E. Hudson, Rachpon Kalra, Takeharu Sekiguchi, Kohei M. Itoh, et al. "Storing quantum information for 30 seconds in a nanoelectronic device." Nature Nanotechnology 9, no. 12 (October 12, 2014): 986–91. http://dx.doi.org/10.1038/nnano.2014.211.

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Sajjad, Muhammad, Gerardo Morell, and Peter Feng. "Advance in Novel Boron Nitride Nanosheets to Nanoelectronic Device Applications." ACS Applied Materials & Interfaces 5, no. 11 (May 23, 2013): 5051–56. http://dx.doi.org/10.1021/am400871s.

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Rose, G. S., M. M. Ziegler, and M. R. Stan. "Large-signal two-terminal device model for nanoelectronic circuit analysis." IEEE Transactions on Very Large Scale Integration (VLSI) Systems 12, no. 11 (November 2004): 1201–8. http://dx.doi.org/10.1109/tvlsi.2004.836291.

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Petrakov, Dmitry S., Dmitry I. Smirnov, Nikolay N. Gerasimenko, Nurlan A. Medetov, and Azamat A. Jikeev. "Implementation of software for data processing of X-ray optical measurements for the analysis of structural parameters." Journal of Applied Crystallography 52, no. 1 (February 1, 2019): 186–92. http://dx.doi.org/10.1107/s1600576718016837.

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The development of semiconductor nanoelectronic technology requires the use of new approaches to metrological control of critically important stages of device structure formation. The development and use of complex measurement methods based on various physical principles allowing one to obtain exhaustive information about the features of real structures, including the existence of hidden and unaccounted layers in transition areas, are of special interest. This paper presents the idea of implementing a complex approach to X-ray optical studies for a two-wavelength measurement scheme, including the methods of relative X-ray reflectometry, refractometry and diffuse X-ray scattering, and its application to the analysis of dimensional parameters of thin-film structures. The study was carried out with the help of a software package for analysing TiN diffusion-barrier layers. A comparison of the results obtained with the results of one-wavelength methods shows the high efficiency of the implemented approach for performing various tasks of metrological control of nanoelectronic devices.

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Abderrahmane, Abdelkader, Changlim Woo, and Pil-Ju Ko. "Low Power Consumption Gate-Tunable WSe2/SnSe2 van der Waals Tunnel Field-Effect Transistor." Electronics 11, no. 5 (March 7, 2022): 833. http://dx.doi.org/10.3390/electronics11050833.

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Two-dimensional (2D) transition-metal dichalcogenides (TMDCs) have attracted attention as promising next-generation electronic devices and sensors. In this study, we fabricated a novel nanoelectronic device based on a black-phosphorus-gated WSe2/SnSe2 van der Waals (vdW) tunnel field-effect transistor (TFET), where hexagonal boron nitride (h-BN) was used as the gate insulator. We performed morphological, electrical, and optoelectronic characterizations. The p-WSe2/n-SnSe2 heterostructure-based TFET exhibited p-type behavior with a good dependence on the gate voltage. The TFET device showed a trend toward negative differential resistance (NDR) originating from band-to-band tunneling, which can be tuned by applying a gate voltage. The optoelectronic performance of the TFET device was low, with a maximum photoresponsivity of 11 mA W−1, owing to the large device length. The results obtained herein promote the integration of black phosphorus into low-energy-consumption 2D vdW TFETs.

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Le, Ha-Linh Thi, Fatme Jardali, and Holger Vach. "Deposition of hydrogenated silicon clusters for efficient epitaxial growth." Physical Chemistry Chemical Physics 20, no. 23 (2018): 15626–34. http://dx.doi.org/10.1039/c8cp00764k.

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Epitaxial silicon thin films grown from the deposition of plasma-born hydrogenated silicon nanoparticles using plasma-enhanced chemical vapor deposition have widely been investigated due to their potential applications in photovoltaic and nanoelectronic device technologies. Here, molecular dynamics simulations are presented to predict the optimal deposition conditions.

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Li, Chao, Bo Lei, Wendy Fan, Daihua Zhang, M. Meyyappan, and Chongwu Zhou. "Molecular Memory Based on Nanowire–Molecular Wire Heterostructures." Journal of Nanoscience and Nanotechnology 7, no. 1 (January 1, 2007): 138–50. http://dx.doi.org/10.1166/jnn.2007.18011.

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This article reviews the recent research of molecular memory based on self-assembled nanowire–molecular wire heterostructures. These devices exploit a novel concept of using redox-active molecules as charge storage flash nodes for nanowire transistors, and thus boast many advantages such as room-temperature processing and nanoscale device area. Various key elements of this technology will be reviewed, including the synthesis of the nanowires and molecular wires, and fabrication and characterization of the molecular memory devices. In particular, multilevel memory has been demonstrated using In2O3 nanowires with self-assembled Fe-bis(terpyridine) molecules, which serve to multiple the charge storage density without increasing the device size. Furthermore, in-depth studies on memory devices made with different molecules or with different functionalization techniques will be reviewed and analyzed. These devices represent a conceptual breakthrough in molecular memory and may work as building blocks for future beyond-CMOS nanoelectronic circuits.

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Schuerle, Simone, Manish K. Tiwari, Kaiyu Shou, Dimos Poulikakos, and Bradley J. Nelson. "Fabricating devices with dielectrophoretically assembled, suspended single walled carbon nanotubes for improved nanoelectronic device characterization." Microelectronic Engineering 88, no. 8 (August 2011): 2740–43. http://dx.doi.org/10.1016/j.mee.2011.01.008.

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Yue, Chenxi, Shuye Jiang, Hao Zhu, Lin Chen, Qingqing Sun, and David Zhang. "Device Applications of Synthetic Topological Insulator Nanostructures." Electronics 7, no. 10 (October 1, 2018): 225. http://dx.doi.org/10.3390/electronics7100225.

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This review briefly describes the development of synthetic topological insulator materials in the application of advanced electronic devices. As a new class of quantum matter, topological insulators with insulating bulk and conducting surface states have attracted attention in more and more research fields other than condensed matter physics due to their intrinsic physical properties, which provides an excellent basis for novel nanoelectronic, optoelectronic, and spintronic device applications. In comparison to the mechanically exfoliated samples, the newly emerging topological insulator nanostructures prepared with various synthetical approaches are more intriguing because the conduction contribution of the surface states can be significantly enhanced due to the larger surface-to-volume ratio, better manifesting the unique properties of the gapless surface states. So far, these synthetic topological insulator nanostructures have been implemented in different electrically accessible device platforms via electrical, magnetic and optical characterizations for material investigations and device applications, which will be introduced in this review.

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Chen, An. "(Invited, Digital Presentation) Emerging Materials and Devices for Energy-Efficient Computing." ECS Meeting Abstracts MA2022-01, no. 19 (July 7, 2022): 1073. http://dx.doi.org/10.1149/ma2022-01191073mtgabs.

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As the CMOS scaling driven by the Moore’s Law approaching the fundamental limits, high energy consumption and heat dissipation have been recognized as the most critical device challenges. Novel switching devices with significantly lower power based on unconventional mechanisms have been explored to replace CMOS in various research programs, e.g., Nanoelectronics Research Initiative (NRI). The major categories of these devices include steep-slope transistors, spintronic devices, ferroelectric devices, and van der Waals devices [1]. These devices are often implemented on emerging materials with unique properties. As the foundation of nanoelectronic devices and systems, novel materials (including dielectrics) present both great challenges and promising opportunities. For example, dielectric layers for gating and electrical insulation are critical for low-dimension devices; magnetic insulators are promising for low-power high-efficiency spintronic devices; ferroelectric materials have been utilized to realize “negative-capacitance” transistors with steep subthreshold slope. Despite abundant scientific breakthroughs achieved on these emerging devices, comprehensive benchmarking has revealed that most of them do not outperform CMOS for Boolean logic and von Neumann architectures [2]. Therefore, the focus of emerging materials and devices has increasingly shifted toward novel computing paradigms. Novel computing paradigms beyond Boolean logic and von Neumann architectures may provide solutions for energy-efficient computing. For example, in-memory computing reduces data movement between computing and memory units, and exploits the intrinsic parallelism in memory arrays. Neural-inspired computing implements cognitive and intelligent functions through a wide range of approaches, e.g., deep neural network, spiking neural network, hyperdimensional computing, probabilistic network, dynamic systems, etc. Although many of these approaches can be implemented in CMOS technologies, more efficient solutions may originate from the engineering and optimization of materials and devices that could enable native implementations of novel computing paradigms. For example, ferroelectric materials, binary and complex oxides, and chalcogenides have been utilized in a wide range of nonvolatile memories and analog devices, which may enable highly efficient in-memory computing and analog computing solutions. At the same time, stringent requirements exist for emerging devices to significantly outperform CMOS in novel computing paradigms, e.g., high density, fast speed, low power, high endurance, long retention, wide analog tunability, asymmetry, etc. [3] Specific requirements vary from application to application. Therefore, device-architecture co-design and co-optimization are important to address these requirements. A holistic approach from basic material exploration to device engineering and further up to architecture co-design has been adopted in more recent research programs, e.g., Energy-Efficient Computing from Devices to Architectures (E2CDA) [4]. This presentation will review the opportunities and challenges of emerging materials and devices for energy-efficient nanoelectronics, and highlight the approaches and perspectives of the E2CDA program. References: K. Bernstein, R.K. Cavin, W. Porod, A. Seabaugh, and J. Welser, “Device and architecture outlook for beyond CMOS switches,” IEEE Proc. 98(12), 2169-2184 (2010). C. Pan and A. Naeemi, “Non-Boolean computing benchmarking for beyond-CMOS devices based on cellular neural network,” IEEE J. Explor. Solid-State Comp. Dev. & Circ 2, 36-43 (2016). G.W. Burr, et al, “Neuromorphic computing using non-volatile memory,” Advances in Physics: X, 2(1), 89-124 (2017). A. Chen, “New directions of nanoelectronics research for computing,” 14th IEEE ICSICT (2018).

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El Sachat, Alexandros, Francesc Alzina, Clivia M. Sotomayor Torres, and Emigdio Chavez-Angel. "Heat Transport Control and Thermal Characterization of Low-Dimensional Materials: A Review." Nanomaterials 11, no. 1 (January 13, 2021): 175. http://dx.doi.org/10.3390/nano11010175.

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Heat dissipation and thermal management are central challenges in various areas of science and technology and are critical issues for the majority of nanoelectronic devices. In this review, we focus on experimental advances in thermal characterization and phonon engineering that have drastically increased the understanding of heat transport and demonstrated efficient ways to control heat propagation in nanomaterials. We summarize the latest device-relevant methodologies of phonon engineering in semiconductor nanostructures and 2D materials, including graphene and transition metal dichalcogenides. Then, we review recent advances in thermal characterization techniques, and discuss their main challenges and limitations.

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Prasad, Vikash, and Debaprasad Das. "A Review on MOSFET-Like CNTFETs." Science & Technology Journal 4, no. 2 (July 1, 2016): 124–29. http://dx.doi.org/10.22232/stj.2016.04.02.06.

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Carbon Nanotube Field Effect Transistor (CNTFET) is one of the promising devices for future nanoscale technologies. In this paper, we have studied the drain characteristics of MOSFET-like CNTFETs for different device parameters like, channel length, diameter of CNT, and number of tubes. It is shown that these device parameters can be used to make important design decisions while designing nanoelectronic circuits. A buffer and ring oscillator circuits are designed using the MOSFET-like CNTFET and propagation delay, power, and power-delay-product (PDP) values are calculated and compared with the CMOS based designs. Also, the CNTFET technology based SRAM cell is compared with CMOS technology based SRAM in term of power consumption. We have shown that CNTFET can exhibit better performance in the nanoscale regime as compared to its CMOS counterparts.

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TERANISHI, Toshiharu, and Masayuki KANEHARA. "Strategy to Fabricate Small Gold Nanoparticle Superlattices and Application to Nanoelectronic Device." Journal of the Vacuum Society of Japan 51, no. 11 (2008): 731–36. http://dx.doi.org/10.3131/jvsj2.51.731.

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Haley, Benjamin P., Sunhee Lee, Mathieu Luisier, Hoon Ryu, Faisal Saied, Steve Clark, Hansang Bae, and Gerhard Klimeck. "Advancing nanoelectronic device modeling through peta-scale computing and deployment on nanoHUB." Journal of Physics: Conference Series 180 (July 1, 2009): 012075. http://dx.doi.org/10.1088/1742-6596/180/1/012075.

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Kumar, S. Bala, S. G. Tan, M. B. A. Jalil, P. Q. Cheung, and Yong Jiang. "Nanoelectronic logic device based on the manipulation of magnetic and electric barriers." Journal of Applied Physics 103, no. 5 (March 2008): 054310. http://dx.doi.org/10.1063/1.2838211.

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Kang, Jeong Won, and Ho Jung Hwang. "Model schematics of a nanoelectronic device based on multi-endo-fullerenes electromigration." Physica E: Low-dimensional Systems and Nanostructures 27, no. 1-2 (March 2005): 245–52. http://dx.doi.org/10.1016/j.physe.2004.11.014.

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Gan, C. L., E. K. Ng, B. L. Chan, U. Hashim, and F. C. Classe. "Technical Barriers and Development of Cu Wirebonding in Nanoelectronics Device Packaging." Journal of Nanomaterials 2012 (2012): 1–7. http://dx.doi.org/10.1155/2012/173025.

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Bondpad cratering, Cu ball bond interface corrosion, IMD (intermetal dielectric) cracking, and uncontrolled post-wirebond staging are the key technical barriers in Cu wire development. This paper discusses the UHAST (unbiased HAST) reliability performance of Cu wire used in fine-pitch BGA package. In-depth failure analysis has been carried out to identify the failure mechanism under various assembly conditions. Obviously green mold compound, low-halogen substrate, optimized Cu bonding parameters, assembly staging time after wirebonding, and anneal baking after wirebonding are key success factors for Cu wire development in nanoelectronic packaging. Failure mechanisms of Cu ball bonds after UHAST test and CuAl IMC failure characteristics have been proposed and discussed in this paper.

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Vaknin, Yonatan, Ronen Dagan, and Yossi Rosenwaks. "Pinch-Off Formation in Monolayer and Multilayers MoS2 Field-Effect Transistors." Nanomaterials 9, no. 6 (June 14, 2019): 882. http://dx.doi.org/10.3390/nano9060882.

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The discovery of layered materials, including transition metal dichalcogenides (TMD), gives rise to a variety of novel nanoelectronic devices, including fast switching field-effect transistors (FET), assembled heterostructures, flexible electronics, etc. Molybdenum disulfide (MoS2), a transition metal dichalcogenides semiconductor, is considered an auspicious candidate for the post-silicon era due to its outstanding chemical and thermal stability. We present a Kelvin probe force microscopy (KPFM) study of a MoS2 FET device, showing direct evidence for pinch-off formation in the channel by in situ monitoring of the electrostatic potential distribution along the conducting channel of the transistor. In addition, we present a systematic comparison between a monolayer MoS2 FET and a few-layer MoS2 FET regarding gating effects, electric field distribution, depletion region, and pinch-off formation in such devices.

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36

Bayan, Sayan, and Dambarudhar Mohanta. "Significant Fowler–Nordheim tunneling across ZnO – Nanorod based nanojunctions for nanoelectronic device applications." Current Applied Physics 13, no. 4 (June 2013): 705–9. http://dx.doi.org/10.1016/j.cap.2012.11.009.

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Yang, Xiaonian, Qiang Li, Guofeng Hu, Zegao Wang, Zhenyu Yang, Xingqiang Liu, Mingdong Dong, and Caofeng Pan. "Controlled synthesis of high-quality crystals of monolayer MoS2 for nanoelectronic device application." Science China Materials 59, no. 3 (March 2016): 182–90. http://dx.doi.org/10.1007/s40843-016-0130-1.

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Chuan, Mu Wen, Muhammad Amirul Irfan Misnon, Nurul Ezaila Alias, and Michael Loong Peng Tan. "Device Performance of Double-Gate Schottky-Barrier Graphene Nanoribbon Field-Effect Transistors with Physical Scaling." Journal of Nanotechnology 2023 (January 16, 2023): 1–7. http://dx.doi.org/10.1155/2023/1709570.

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Moore’s law is approaching its limit due to various challenges, especially the size limit of the transistors. The International Roadmap for Devices and Systems (IRDS), the successor of International Technology Roadmap for Semiconductors (ITRS), has included 2D materials as an alternative approach for the More-than-Moore nanoelectronic applications. Among the 2D materials, graphene nanoribbons (GNRs) have been widely used as the alternative channel materials of field-effect transistors (FETs). In this paper, the impacts of physical scaling on the device performance of double-gate Schottky-barrier GNR FETs (DG-SB-GNRFETs) are investigated by using NanoTCAD ViDES simulation tool based on the tight-binding Hamiltonian and self-consistent solutions of 3D Poisson and Schrödinger equations with open boundary conditions within the nonequilibrium Green’s function formalism. The extracted device performance parameters include the subthreshold swing and on-to-off current ratio. The results suggest that the performances of DG-SB-GNRFETs are strongly dependent on their physical parameters, especially the widths of the GNRs.

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Cao, Liemao, Xiaohui Deng, Zhenkun Tang, Guanghui Zhou, and Yee Sin Ang. "Designing high-efficiency metal and semimetal contacts to two-dimensional semiconductor γ-GeSe." Applied Physics Letters 121, no. 11 (September 12, 2022): 113104. http://dx.doi.org/10.1063/5.0117670.

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Forming a low-resistance semiconductor–metal contact is a critical step to achieve a high-performance two-dimensional (2D) semiconductor nanoelectronic device. Motivated by the recent discovery of monolayer γ-GeSe with exceptional high electrical conductivity reaching 105 S/m, we computationally investigate the interface contact properties of γ-GeSe with four representative classes of metallic systems, including 2D semimetal (graphene), 2D metal (NbS2), 3D semimetal (Bi), and 3D metal (Au) using first-principle density functional theory simulations. We found that these metals exhibit rich contact formation physics with 2D γ-GeSe, yielding contacts of heterostructures with weak and moderate couplings. Importantly, γ-GeSe/NbS2 is an Ohmic contact while γ-GeSe/Bi is an n-type Schottky contact with an ultralow barrier height of 0.07 eV. For γ-GeSe/graphene contact, the electronic properties can be adjusted via the interlayer distance or via an external electric field. Finally, we show that the contact properties can also be further controlled using layer-number engineering of γ-GeSe. Our findings provide a useful guideline for designing high-performance 2D nanoelectronics based on 2D γ-GeSe.

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Yue, Dewu, Ximing Rong, Shun Han, Peijiang Cao, Yuxiang Zeng, Wangying Xu, Ming Fang, Wenjun Liu, Deliang Zhu, and Youming Lu. "High Photoresponse Black Phosphorus TFTs Capping with Transparent Hexagonal Boron Nitride." Membranes 11, no. 12 (December 1, 2021): 952. http://dx.doi.org/10.3390/membranes11120952.

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Black phosphorus (BP), a single elemental two-dimensional (2D) material with a sizable band gap, meets several critical material requirements in the development of future nanoelectronic applications. This work reports the ambipolar characteristics of few-layer BP, induced using 2D transparent hexagonal boron nitride (h-BN) capping. The 2D h-BN capping have several advantages over conventional Al2O3 capping in flexible and transparent 2D device applications. The h-BN capping technique was used to achieve an electron mobility in the BP devices of 73 cm2V−1s−1, thereby demonstrating n-type behavior. The ambipolar BP devices exhibited ultrafast photodetector behavior with a very high photoresponsivity of 1980 mA/W over the ultraviolet (UV), visible, and infrared (IR) spectral ranges. The h-BN capping process offers a feasible approach to fabricating n-type behavior BP semiconductors and high photoresponse BP photodetectors.

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Wang, Hui, Xin Wang, Chuandong Li, and Ling Chen. "SPICE Mutator Model for Transforming Memristor into Meminductor." Abstract and Applied Analysis 2013 (2013): 1–5. http://dx.doi.org/10.1155/2013/281675.

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The memristor (resistor with memory), as the fourth fundamental circuit element, is a nonvolatile nanoelectronic device and holds great promise for VLSI applications. It was suggested that the meminductor (ML, inductor with memory) circuit can be built by memristor emulators. This paper further addresses the transformation mechanism in terms of constitutive relation from the memristor to the meminductor and then designs an MR-ML mutator to achieve MR-ML transformation. We also present the mutator’s SPICE model and analyze the simulation results.

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Бондарев, А. В., and В. Н. Ефанов. "Investigation of Robustness of Nanoelectronic Structures Based on Resonant Tunneling Elements." Proceedings of Universities. Electronics 26, no. 6 (December 2021): 491–507. http://dx.doi.org/10.24151/1561-5405-2021-26-6-491-507.

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Multi-input logic gates based on two-level logic cells MOBILE have short (picosecond) switching times and higher functionality due to the ability to implement logic functions with fewer gates. This creates good prospects for the development of ultra-high-speed FPGAs with a high degree of integration, which are required for organizing high-performance computing. However, the extremely high sensitivity of resonant tunneling elements to changes in the energies of quantum states requires an assessment of the stability of such structures to external influences in real operation. In this work, the problem of assessing the stability of nanoelectronic structures that include resonant tunneling elements is considered. The method for studying the robustness of logic cells MOBILE based on a resonant tunneling diode and an НВТ transistor was proposed, making it possible to find an external interval estimate of the output voltage of the device under study for given interval models of the initial components. The technique is based on the use of systems of topological and parametric equations written in finite increments. It was shown that the proposed decomposition principle for the initial interval model ensures the algorithmic solvability of the problem posed. A computational algorithm for calculating processes in a two-level logical cell MOBILE has been developed. The algorithm provides for step-by-step integration of interval differential equations and solution of interval nonlinear algebraic equations at each step of integration using Kaucher interval arithmetic. The obtained results of the study of processes in a two-level logic cell MOBILE create prerequisites for expanding the field of application of resonant tunneling devices in high-speed monolithic integrated circuits.

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Wagner, Tino, Hannes Beyer, Patrick Reissner, Philipp Mensch, Heike Riel, Bernd Gotsmann, and Andreas Stemmer. "Kelvin probe force microscopy for local characterisation of active nanoelectronic devices." Beilstein Journal of Nanotechnology 6 (November 23, 2015): 2193–206. http://dx.doi.org/10.3762/bjnano.6.225.

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Frequency modulated Kelvin probe force microscopy (FM-KFM) is the method of choice for high resolution measurements of local surface potentials, yet on coarse topographic structures most researchers revert to amplitude modulated lift-mode techniques for better stability. This approach inevitably translates into lower lateral resolution and pronounced capacitive averaging of the locally measured contact potential difference. Furthermore, local changes in the strength of the electrostatic interaction between tip and surface easily lead to topography crosstalk seen in the surface potential. To take full advantage of the superior resolution of FM-KFM while maintaining robust topography feedback and minimal crosstalk, we introduce a novel FM-KFM controller based on a Kalman filter and direct demodulation of sidebands. We discuss the origin of sidebands in FM-KFM irrespective of the cantilever quality factor and how direct sideband demodulation enables robust amplitude modulated topography feedback. Finally, we demonstrate our single-scan FM-KFM technique on an active nanoelectronic device consisting of a 70 nm diameter InAs nanowire contacted by a pair of 120 nm thick electrodes.

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Saga, Koichiro, and Takeshi Hattori. "Wafer Cleaning Using Supercritical CO₂ in Semiconductor and Nanoelectronic Device Fabrication." Solid State Phenomena 134 (November 2007): 97–103. http://dx.doi.org/10.4028/www.scientific.net/ssp.134.97.

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Davidson, J. L., W. P. Kang, K. Subramanian, and Y. M. Wong. "Forms and behaviour of vacuum emission electronic devices comprising diamond or other carbon cold cathode emitters." Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences 366, no. 1863 (November 19, 2007): 281–93. http://dx.doi.org/10.1098/rsta.2007.2154.

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Nanocarbon-derived electron emission devices, specifically nanodiamond lateral field emission (FE) diodes and gated carbon nanotube (CNT) triodes, are new configurations for robust nanoelectronic devices. These novel micro/nanostructures provide an alternative and efficient means of accomplishing electronics that are impervious to temperature and radiation. For example, nitrogen-incorporated nanocrystalline diamond has been lithographically micropatterned to use the material as an electron field emitter. Arrays of laterally arranged ‘finger-like’ nanodiamond emitters constitute the cathode in a versatile diode configuration with a small interelectrode separation. A low diode turn-on voltage of 7 V and a high emission current of 90 μA at an anode voltage of 70 V (electric field of approx. 7 V μm −1 ) are reported for the nanodiamond lateral device. Also, a FE triode amplifier based on aligned CNTs with a low turn-on voltage and a small gate leakage current has been developed.

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Venkataraman, Anusha, Eberechukwu Amadi, and Chris Papadopoulos. "Molecular-Scale Hardware Encryption Using Tunable Self-Assembled Nanoelectronic Networks." Micro 2, no. 3 (June 21, 2022): 361–68. http://dx.doi.org/10.3390/micro2030024.

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Nanomaterials are promising alternatives for creating hardware security primitives that are considered more robust and less susceptible to physical attacks compared to standard CMOS-based approaches. Here, nanoscale electronic circuits composed of tunable ratios of molecules and colloidal nanoparticles formed via self-assembly on silicon wafers are investigated for information and hardware security by utilizing device-level physical variations induced during fabrication. Two-terminal electronic transport measurements show variations in current through different parts of the nanoscale network, which are used to define electronic physically unclonable functions. By comparing different current paths, arrays of binary bits are generated that can be used as encryption keys. Evaluation of the keys using Hamming inter-distance values indicates that performance is improved by varying the ratio of molecules to nanoparticles in the network, which demonstrates self-assembly as a potential path toward implementing molecular-scale hardware security primitives. These nanoelectronic networks thus combine facile fabrication with a large variety of possible network building blocks, enabling their utilization for hardware security with additional degrees of freedom that is difficult to achieve using conventional systems.

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Majidi, Mohammad, Mohammad Taghi Ahmadi, and Meisam Rahmani. "Analytical Modeling of Carbon Nanoparticle-Based Symmetric p–n Junction." Advanced Science, Engineering and Medicine 11, no. 11 (November 1, 2019): 1031–35. http://dx.doi.org/10.1166/asem.2019.2446.

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Outstanding physical and electrical properties such as quantum transport, high carrier mobility, excellent electrical and thermal conductivity, high surface area, good optical transparency, strong mechanical strength and easy fabrication make carbon nanoparticles appropriate on nanoelectronic applications. Carbon nanoparticle based p–n junction, as a fundamental structure of nanoscale devices, is analytically presented in this study. The carbon nanoparticle p–n interface reveals an improved transport along the junction in comparison with the conventional p–n junction. Controlling the doping of p–n junction based device partially permit the foundation of carbon nanoparticle based bipolar technology and can overcome application of current in silicon based technology. This paper analytically demonstrates findings on electric field, space charge region width, scalar potential, built-in potential and transport along carbon nanoparticle based p–n junction. The uniqueness of this method is to create a well identified carbon nanoparticle based p–n junction which opens new opportunities for researching high field transport limit in nanoscale devices.

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Al-mashaal, Asaad K. Edaan, and Rebecca Cheung. "Delamination of polyimide in hydrofluoric acid." Acta Polytechnica 61, no. 6 (December 31, 2021): 684–88. http://dx.doi.org/10.14311/ap.2021.61.0684.

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Wet etching is a critical fabrication step for the mass production of micro and nanoelectronic devices. However, when an extremely corrosive acid such as hydrofluoric (HF) acid are used during etching, an undesirable damage might occur if the device includes a material that is not compatible with the acid. Polyimide thin films can serve as sacrificial/structural layers to fabricate freestanding or flexible devices. The importance of polyimide in microelectronics is due to its relatively low stress and compatibility with standard micromachining processes. In this work, a fast delamination process of a 4-μm-thin film of polyimide from a silicon substrate has been demonstrated. The films’ detachment has been performed using a wet-based etchant of HF acid. Specifically, the effect of HF concentration on the delamination time required to detach the polyimide film from the substrate has been investigated. This study is intended to provide the information on the compatibility of using polyimide films with HF, which can help in the design and fabrication of polyimide-based devices.

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Cui, Huanqing, Li Cai, Sen Wang, Xiaoqiang Liu, and Xiaokuo Yang. "Accurate reliability analysis method for quantum-dot cellular automata circuits." International Journal of Modern Physics B 29, no. 29 (November 13, 2015): 1550203. http://dx.doi.org/10.1142/s0217979215502033.

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Probabilistic transfer matrix (PTM) is a widely used model in the reliability research of circuits. However, PTM model cannot reflect the impact of input signals on reliability, so it does not completely conform to the mechanism of the novel field-coupled nanoelectronic device which is called quantum-dot cellular automata (QCA). It is difficult to get accurate results when PTM model is used to analyze the reliability of QCA circuits. To solve this problem, we present the fault tree models of QCA fundamental devices according to different input signals. After that, the binary decision diagram (BDD) is used to quantitatively investigate the reliability of two QCA XOR gates depending on the presented models. By employing the fault tree models, the impact of input signals on reliability can be identified clearly and the crucial components of a circuit can be found out precisely based on the importance values (IVs) of components. So this method is contributive to the construction of reliable QCA circuits.

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Kelly, Thomas F., Keith Thompson, Emmanuelle A. Marquis, and David J. Larson. "Atom Probe Tomography Defines Mainstream Microscopy at the Atomic Scale." Microscopy Today 14, no. 4 (July 2006): 34–41. http://dx.doi.org/10.1017/s1551929500050264.

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When making a sculpture, it is the eyes that guide the hands and tools and perceive the outcome. In simple words, “in order to make, you must be able to see.” So too, when making a nanoelectronic device, it is the microscope (eyes) that guides the process equipment (hands and tools) and perceives the outcome. As we emerge into the century of nanotechnology, it is imperative that the eyes on the nanoworld provide an adequate ability to “see.” We have microscopies that resolve 0.02 nm on a surface (scanning tunneling microscope (STM)) or single atoms in a specimen (atom probe tomographs (APT) and transmission electron microscopes (TEM)).

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Journal articles on the topic 'Nanoelectronic device'

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