Relevant bibliographies by topics / Nanoelectronic device

Academic literature on the topic 'Nanoelectronic device'

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Published: 14 March 2023

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Journal articles on the topic "Nanoelectronic device"

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Nikolić, K., M. Forshaw, and R. Compañó. "The Current Status of Nanoelectronic Devices." International Journal of Nanoscience 02, no. 01n02 (February 2003): 7–29. http://dx.doi.org/10.1142/s0219581x03001048.

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Over the last thirty years, many new physical phenomena have been discovered and suggested for use in data processing devices. Many, but not all, of these devices are described as "nanoelectronic", because one or more of their characteristic dimensions lie in the size range ≈1–100 nm. However, any new idea has a long way to go before it can achieve any practical value. It is necessary to develop and test a series of increasingly complicated structures. Starting from (1) the basic physical effect and its theoretical description, one must design and fabricate prototypes of (2) a single device, then (3) a simple circuit, then (4) functional units such as assemblies of logic gates or blocks of memory cells, and eventually (5) electronic chips. This article provides an overview of the development status of some of these device technologies.
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Kosina, Hans, and Siegfried Selberherr. "Device Simulation Demands of Upcoming Microelectronics Devices." International Journal of High Speed Electronics and Systems 16, no. 01 (March 2006): 115–36. http://dx.doi.org/10.1142/s0129156406003576.

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An overview of models for the simulation of current transport in micro- and nanoelectronic devices within the framework of TCAD applications is presented. Starting from macroscopic transport models, currently discussed enhancements are specifically addressed. This comprises the inclusion of higher-order moments into the transport models, the incorporation of quantum correction and tunneling models up to dedicated quantum-mechanical simulators, and mixed approaches which are able to account for both, quantum interference and scattering. Specific TCAD requirements are discussed from an engineer's perspective and an outlook on future research directions is given.
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White, Marvin H., Yu (Richard) Wang, Stephen J. Wrazien, and Yijie (Sandy) Zhao. "ADVANCEMENTS IN NANOELECTRONIC SONOS NONVOLATILE SEMICONDUCTOR MEMORY (NVSM) DEVICES AND TECHNOLOGY." International Journal of High Speed Electronics and Systems 16, no. 02 (June 2006): 479–501. http://dx.doi.org/10.1142/s0129156406003801.

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This paper describes the recent advancements in the development of nanoelectronic SONOS nonvolatile semiconductor memory (NVSM) devices and technology, which are employed in both embedded applications, such as microcontrollers, and 'stand-alone', high-density, memory applications, such as cell phones and memory 'sticks'. Multi-dielectric devices, such as the MNOS devices, were among the first NVSM; however, over the ensuing years the double polysilicon, floating-gate device has become the dominant semiconductor NVSM technology. Today, however, questions arise as to future scaling and cost effectiveness of floating gate technology – questions, which have sparked renewed interest in SONOS technology. The latter offers a single polysilicon device structure with reduced lithography steps together with compact cell layouts - compatible with 'standard' CMOS technology for cost effectiveness. In addition, SONOS technology offers performance features, such as reduced erase and write voltage levels to ease the design of peripheral memory circuits with a decrease in electric fields and localized charge storage for improved reliability and multi-bit storage, and ease of memory testing. A special feature of SONOS technology is radiation hardness, which makes this technology ideal for advanced Space and Military systems. SONOS devices use ultra-thin tunnel oxides (2nm) and operate with 'modified' Fowler-Nordheim and 'direct' tunneling in both erase and write (program) modes. A thicker tunnel oxide SONOS device (5nm), called the NROM™ device, uses 'hot electron injection for programming and 'hot hole band-to-band tunneling' for erase. The NROM™ device provides spatially isolated, two-bit storage with the possibility of multi-level charge (MLC) storage at each bit location. This paper describes the physical electronics for these device structures and their erase/write, retention and endurance characteristics. In addition, several novel SONOS device structures are discussed as potential candidates for future NVSM.
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Panfilov, Y. V., I. A. Rodionov, I. A. Ryzhikov, A. S. Baburin, D. O. Moskalev, and E. S. Lotkov. "Ultrathin film deposition for nanoelectronic device manucturing." IOP Conference Series: Materials Science and Engineering 781 (May 5, 2020): 012021. http://dx.doi.org/10.1088/1757-899x/781/1/012021.

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Saxena, Shubhangi, and Kamsali Manjunathachari. "Novel Nanoelectronic Materials and Devices: For Future Technology Node." ECS Transactions 107, no. 1 (April 24, 2022): 15701–11. http://dx.doi.org/10.1149/10701.15701ecst.

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Since the last six decades, technology node has grown smaller from micrometer to nanometer dimensions. In continuation of Moore's Law, the research is going on for device/supply voltage shrinking to go beyond 22 nm CMOS technology node. However, many physical and quantum challenges appear at a smaller scale, which causes shrinking beyond 22 nm critical and needs innovative materials and devices for scaling in the nanometer regime. Incorporating nanoengineered materials to realize research achievements has shown timely development with significant influence in electronic industries. These new materials and devices hold promise as potential device candidates to be integrated onto the silicon platform to enhance semiconductor industry growth and extend Moore's Law. Here we address state–of–the–art research trends in nanomaterials and nanodevices for future technology node and discuss associated challenges.
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KOSINA, HANS. "NANOELECTRONIC DEVICE SIMULATION BASED ON THE WIGNER FUNCTION FORMALISM." International Journal of High Speed Electronics and Systems 17, no. 03 (September 2007): 475–84. http://dx.doi.org/10.1142/s0129156407004667.

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Coherent transport in mesoscopic devices is well described by the Schrödinger equation supplemented by open boundary conditions. When electronic devices are operated at room temperature, however, a realistic transport model needs to include carrier scattering. In this work the kinetic equation for the Wigner function is employed as a model for dissipative quantum transport. Carrier scattering is treated in an approximate manner through a Boltzmann collision operator. A Monte Carlo technique for the solution of this kinetic equation has been developed, based on an interpretation of the Wigner potential operator as a generation term for numerical particles. Including a multi-valley semiconductor model and a self-consistent iteration scheme, the described Monte Carlo simulator can be used for routine device simulations. Applications to single barrier and double barrier structures are presented. The limitations of the numerical Wigner function approach are discussed.
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Nidhi, Tashi Nautiyal, and Samaresh Das. "Large-Scale Synthesis of Nickel Sulfide for Electronic Device Applications." MRS Advances 5, no. 52-53 (2020): 2727–35. http://dx.doi.org/10.1557/adv.2020.339.

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AbstractSeveral techniques have been employed for large-scale synthesis of group 10 transition metal dichalcogenides (TMDCs) based on platinum and palladium for nano- and opto-electronic device applications. Nickel Sulphides (NixSy), belonging to group 10 TMDC family, have been widely explored in the field of energy storage devices such as batteries and supercapacitors, etc. and commonly synthesized through the solution process or hydrothermal methods. However, the high-quality thin film growth of NixSy for nanoelectronic applications remains a central challenge. Here, we report the chemical vapor deposition (CVD) growth of NiS2 thin film onto a two-inch SiO2/Si substrate, for the first time. Techniques such as X-ray photoelectron spectroscopy, X-ray Diffraction, Raman Spectroscopy, Scanning Electron Microscopy, have been used to analyse the quality of this CVD grown NiS2 thin film. A high-quality crystalline thin film of thickness up to a few nanometres (~28 nm) of NiS2 has been analysed here. We also fabricated a field-effect device based on NiS2 thin film using interdigitated electrodes by optical lithography. The electrical performance of the fabricated device is characterized at room temperature. On applying the drain voltage from -2 to +2 V, the device shows drain current in the range of 10-9 A before annealing and in the range of 10-6 A after annealing. This, being comparable to that from devices based on MoS2 and other two-dimensional materials, projects CVD grown NiS2 as a good alternative material for nanoelectronic devices.
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Liffmann, R., M. Homberger, M. Mennicken, S. Karthäuser, and U. Simon. "Polydiacetylene stabilized gold nanoparticles – extraordinary high stability and integration into a nanoelectrode device." RSC Advances 5, no. 125 (2015): 102981–92. http://dx.doi.org/10.1039/c5ra17545c.

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Janes, D. B., V. R. Kolagunta, M. Batistuta, B. L. Walsh, R. P. Andres, Jia Liu, J. Dicke, et al. "Nanoelectronic device applications of a chemically stable GaAs structure." Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures 17, no. 4 (1999): 1773. http://dx.doi.org/10.1116/1.590824.

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Müller, T., A. Lorke, Q. T. Do, F. J. Tegude, D. Schuh, and W. Wegscheider. "A three-terminal planar selfgating device for nanoelectronic applications." Solid-State Electronics 49, no. 12 (December 2005): 1990–95. http://dx.doi.org/10.1016/j.sse.2005.09.004.

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Dissertations / Theses on the topic "Nanoelectronic device"

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Ye, Sheng. "Kelvin Probe Force Microscopy (KPFM) for nanoelectronic device characterisation." Thesis, University of Southampton, 2016. https://eprints.soton.ac.uk/419059/.

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This project is to develope a new method of characterization for Silicon-nano-wire (SiNW) FET and SET devices by using KPFM technology to derive the information of local surface potential change on the channel of SiNW devices. The surface potential is related to many important parameters on material's surface, e.g. fixed surface charge, doping profile variation, distribution of charge carriers under applied bias, and individual dopant atoms near the surface. Those parameters are strongly related to the characteristics of SiNW devices. The KPFM equipment is designed to extract the contact potential difference (CPD) between tip and sample. The change of CPD is related to the Fermi energy level in materials. Therefore any factors which induce Fermi energy level change inside material are detectable. The significantly improved lateral resolution (sub-nanometer) gives us confidence for the measurement of local surface potential variation. Much of the time has been dedicated for the KPFM equipment calibration and optimization. By the end of PhD project the surface potential characterisation of three different types of the silicon-nano-wire (SiNW) devices (uniformly doped SiNW, n-pn SiNW Field-Effect-Transistor (FET), and n-p-n-p-n SiNW Single-Electron-Transistor (SET)) has been achieved. By using surface potential information the surface traped charge and change in local resistivity in SiNW is successfully estimated and the result is confirmed well agreed with the characterisation of other conventional method. This characterisation result also suggest the accuracy of local surface potential measurement. In-situ potential mapping and proling of n-p-n FET channel under device operation has been successfully performed. By comparing the data with simulation and electrical characterisation of the same device, correspondence between the line-shape of the surface potential and electrical field profiles and device parameters has been clarified for the first time. An attempt has been made to observe the surface potential of the channel of SET devices which have shown clear Coulomb oscillation at low temperature (5K). The formation of a conductive channel in 330-nm-wide SiNW channel by the side gate modulation is successfully observed. Four main achievements can be claimed at the end of this project. First, the metallurgic p-n junction in thin (50nm) SOI has been first time ever detected by Ex curve extraction from measured potential profile and the Ex curve was used to study the charge transport in the n-p-n structure under different biasing condition. Secondary, the novel single side gate doping modulated single electron transistors was fabricated and shown Coulomb oscillations which was consistent with theoretical predictions. Furthermore, the operation of FET/SET was investigated by scanned high resolution surface potential profile which revealed the status of p-n junction under biasing. In the end, this study discovered a new method to investigate nano-electronic devices by KPFM scan and more information such as change in build-in voltage at low temperature, and charge in charge state of island can be extracted if the high vacuum and low temperature is applied.
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Di, Giacomo Sandro John. "Development of silicon germanium-based quantum dots for nanoelectronic device applications." The Ohio State University, 2005. http://rave.ohiolink.edu/etdc/view?acc_num=osu1406719133.

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PENAZZI, GABRIELE. "Development of an atomistic/continous simulation tool for nanoelectronic devices." Doctoral thesis, Università degli Studi di Roma "Tor Vergata", 2010. http://hdl.handle.net/2108/1335.

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La simulazione dei moderni dispositivi elettronici è una grande sfida per la comunità ingegneristica. L'enorme progresso nei processi di fabbricazione ha permesso una riduzione della dimensione dei dispositivi talmente spinta che fenomeni tipici della scala di lunghezza nanometrica giocano un ruolo cruciale. Inoltre stiamo assistendo a un grande sforzo teso ad esplorare soluzioni tecnologiche alternatice ai tradizionali dispositivi a semiconduttore. Questo sforzo è rivolto verso la frontiera dell'elettronica molecolare, dei polimeri semiconduttori, delle strutture autoassemblanti, dei materiali quasi-unidimensionali e bidimensionali. In uno scenario simile è cruciale sviluppare strumenti di simulazione modulari, capaci di connettere modelli fisici differenti su scale geometriche differenti. Gli effetti quantistici giocano un ruolo fondamentale ed è necessario includere modelli che li descrivano, evitando però la tipica esplosione di complessità nell'implementazione di suddetti modelli. Per realizzare ciò è necessario andare verso un approccio multiscala, approccio già utilizzato con successo in meccanica statica. Lo scopo di questo lavoro è includere descrizioni e modelli atomistici in TiberCAD, un codice TCAD per la simulazione di dispositivi optoelettronici che può vantare eccellenti strumenti per interfacciare diversi modelli fisici in un ambiente multifisica/multiscala. I modelli atomistici inclusi sono utili al calcolo delle deformazioni elastiche, della geometria della struttura e degli stati elettronici. Infine, viene presentata anche una tecnica inedita per una descrizione quantistica efficiente del trasporto di carica. Questo lavoro vuole contrubuire a rendere TiberCAD uno strumento di riferimento per la simulazione di dispositivi optoelettronici su nanoscala.
The simulation of novel optoelectronic devices is a great challenge for the engineering community. The enoromous progress in device fabrication technology allowed such a massive downscaling that geometrical feature in the nanoscale play a crucial role. Furthermore we have a great effort in exploring alternative solutions respect to more traditional semiconductor devices. It involves molecular electronic, semiconductive polymers, self-assembled structures, quasi-one dimensional and two dimensional materials. In such scenario it's crucial to develop modular simulation tools able to connect different physical models on different length scales. Quantum effect play an important role and we need to take them into account, avoiding anyway an explosion of the computational complexity. Thus it's needed to go in the direction of a multiscale approach, which is already applied with success in mechanical science. The goal of this work is to include atomistic description and atomistic models in TiberCAD, a Technology CAD code for simulation of optoelectronic devices which can rely on excellent instruments for interfacing different models in a multyphisics/multiscale environment. Atomistic models for the calculation of strain, structure geometry and electronic states have been included. A novel technique for describing quantum transport with an efficient algorithm is also presented. These work wants to push TiberCAD to be a reference tool for calculation of complex optoeletronic devices at the nanoscale.
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Pan, Chenyun. "A hierarchical optimization engine for nanoelectronic systems using emerging device and interconnect technologies." Diss., Georgia Institute of Technology, 2015. http://hdl.handle.net/1853/53931.

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A fast and efficient hierarchical optimization engine was developed to benchmark and optimize various emerging device and interconnect technologies and system-level innovations at the early design stage. As the semiconductor industry approaches sub-20nm technology nodes, both devices and interconnects are facing severe physical challenges. Many novel device and interconnect concepts and system integration techniques are proposed in the past decade to reinforce or even replace the conventional Si CMOS technology and Cu interconnects. To efficiently benchmark and optimize these emerging technologies, a validated system-level design methodology is developed based on the compact models from all hierarchies, starting from the bottom material-level, to the device- and interconnect-level, and to the top system-level models. Multiple design parameters across all hierarchies are co-optimized simultaneously to maximize the overall chip throughput instead of just the intrinsic delay or energy dissipation of the device or interconnect itself. This optimization is performed under various constraints such as the power dissipation, maximum temperature, die size area, power delivery noise, and yield. For the device benchmarking, novel graphen PN junction devices and InAs nanowire FETs are investigated for both high-performance and low-power applications. For the interconnect benchmarking, a novel local interconnect structure and hybrid Al-Cu interconnect architecture are proposed, and emerging multi-layer graphene interconnects are also investigated, and compared with the conventional Cu interconnects. For the system-level analyses, the benefits of the systems implemented with 3D integration and heterogeneous integration are analyzed. In addition, the impact of the power delivery noise and process variation for both devices and interconnects are quantified on the overall chip throughput.
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Chouard, Florian Raoul Verfasser], Doris [Akademischer Betreuer] [Schmitt-Landsiedel, and Sebastian M. [Akademischer Betreuer] Sattler. "Device Aging in Analog Circuits for Nanoelectronic CMOS Technologies / Florian Raoul Chouard. Gutachter: Sebastian M. Sattler ; Doris Schmitt-Landsiedel. Betreuer: Doris Schmitt-Landsiedel." München : Universitätsbibliothek der TU München, 2012. http://d-nb.info/1024355020/34.

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Chiu, Pit Ho Patrio 1977. "Bismuth based nanoelectronic devices." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=100337.

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Bismuth (Bi) is a unique electronic material with small effective mass (∼0.001me) and long carrier mean free path (100 nm at 300K). It is particularly suitable for studying nano scale related phenomena such as size effect and energy level spacing. In this thesis work, bismuth based nanoelectronic devices were studied. Devices were fabricated using a combination of electron beam (e-beam) writing and thermal evaporation techniques. Dimensions of the fabricated devices were in the order of 100 rim. All structures were optimized for individual electrical characterization. Three types of devices were studied: Bi nanowires, Bi nanowires with dual side-gate structures and Bi nanodot structures. In the study of Bi nanowires, metal-to-semiconductor transition phenomenon and size effect were observed. The conduction behavior of Bi nanowires changed from metallic to semiconductor when the device's critical dimension was reduced to below 50 nm. It is a solid experimental evidence of the quantum confinement-induced bandgap theory. Additionally, it has been found in the present work that resistivity of individual Bi nanowire increased as linewidth decreased indicating size effect occurred in the Bi nanowires. Dual side-gate structures were formed adjacent to the Bi nanowires in an attempt to modulate the current. Measurements showed a 7% of current modulation. The small current modulation suggested the high carrier density in the nanowire which has prevented the full depletion of free carriers. 100 nm-diameter Bi nanodot structures were fabricated utilizing proximity effect of e-beam writing. Precise control of electron doses and process conditions led to the successful fabrication of sub-nanometer tunneling junctions to the nanodots. Significant non-linear current-voltage (I-V) characteristic was observed at low temperatures. The step like I-V characteristic was a strong indication of energy level spacing in the zero-dimensional nanodot structure. The successful observation of energy level spacing in a relatively large nanodot is due to the small effective mass of bismuth material which leads to a measurable energy level spacing.
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Blackburn, A. M. "Multiple-gate vacuum nanoelectronic devices." Thesis, University of Cambridge, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.596691.

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This thesis introduces novel multiple-gate vacuum nanoelectronic devices, presenting details of their theoretical and experimental characterization, and of the methods that have been established for their fabrication. These devices, based upon the nanotriode of Driskill-Smith et al, have multiple-gates placed within an anode-cathode vacuum gap of only a few hundred nanometres, permitting a wide range of potential-energy landscapes to be created in front of its tungsten-nanopillar field-emitting cathode. The current transport in such devices is suggested to be influenced by quantum interference of the electron wave function in the anode-cathode gap, and this work seeks to control this effect. The device fabrication and electrical characterisation focuses on a pentode device, which has an integrated anode and tungsten-nanopillar cathode structure and three gate-electrodes with aperture-diameters of less than 100 nm; the fabrication can readily be adapted to devices with fewer gates. A calculation of the transmission probability for electrons through the entire pentode anode-cathode gap shows resonances at certain gate-voltage arrangements, strengthening the possibility of observing quantum interference effects in these devices. A study of the tungsten nanopillar formation-process gives new information upon their geometry and formation. The details of the process required to form nanopillars in the pentode chamber are suggested to differ from those required on large area samples. Thus, the observed pentode device characteristics are best explained by dielectric leakage mechanisms, which were also evident in the nanotriode work. However, the reliable range of field emission observation, in two-terminal devices where field emission was observed, has been increased in comparison to the nanotriode by using a tungsten pedestal cathode structure. In response to the pentode characteristics, an alternative cathode structure was fabricated, based upon carbon contaminated scanning electron microscope deposited tips.
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Maassen, Jesse. "First principles simulations of nanoelectronic devices." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106463.

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As the miniaturization of devices begins to reveal the atomic nature of materials, where chemical bonding and quantum effects are important, one must resort to a parameter-free theory for predictions. This thesis theoretically investigates the quantum transport properties of nanoelectronic devices using atomistic first principles. Our theoretical formalism employs density functional theory (DFT) in combination with Keldysh nonequilibrium Green's functions (NEGF). Self-consistently solving the DFT Hamiltonian with the NEGF charge density provides a way to simulate nonequilibrium systems without phenomenological parameters. This state-of-the-art technique was used to study three problems related to the field of nanoelectronics. First, we investigated the role of metallic contacts (Cu, Ni and Co) on the transport characteristics of graphene devices. With Cu, the graphene is simply electron-doped (Fermi level shift of −0.7 eV) which creates a unique signature in the conduction profile allowing one to extract the doping level. With Ni and Co, spin-dependent band gaps are formed in graphene's linear dispersion bands, thus leading to the prediction of high spin injection efficiencies reaching 60% and 80%, respectively. Second, we studied how controlled doping distributions in nano-scale Si transistors could suppress OFF-state leakage currents. By assuming the dopants (B and P) are confined in 1.1 nm regions in the channel, we discovered large conductance variations (Gmax/Gmin ~ 10^5) as a function of the doping location. The largest fluctuations arise when the dopants are in the vicinity of the electrodes. Our results indicate that if the dopants are located away from the leads, a distance equal to 20% of the channel length, the tunneling current can be suppressed by a factor of 2 when compared to the case of uniform doping. Thus, controlled doping engineering is found to suppress device-to-device variations and lower the undesirable leakage current. Finally, we incorporated a dephasing model into our ab initio transport formalism, which was used to study the effect of phase-breaking scattering in three different systems. Our calculations revealed the complex role of dephasing, where conduction increased or decreased depending on the system under consideration. We demon- strated that the backscattering component of this dephasing scheme also allows one to retrieve Ohm's law.
Comme la miniaturisation des dispositifs commence à révéler la nature atomique des matériaux, où les liaisons chimiques et les effets quantiques sont importants, nous devons recourir à une théorie sans paramètre pour obtenir des prédictions. Cette thèse étudie les propriétés de transport quantique des dispositifs nanoélectroniques en utilisant des méthodes ab initio atomiques. Notre formalisme théorique combine la théorie de la fonctionnelle de la densité (DFT) avec les fonctions de Green hors-équilibres (NEGF). Résoudre l'Hamiltonien DFT de manière auto-consistante avec la densité de charge NEGF permet de simuler des systèmes hors-équilibres sans utiliser des paramètres. Cette technique sophistiquée a été utilisée pour étudier trois problèmes liés au domaine de la nanoélectronique. Premièrement, nous avons étudié le rôle des contacts métalliques (Cu, Ni et Co) sur les caractéristiques de transport des dispositifs à base de graphène. Dans le cas du Cu, le graphène est simplement dopé en électrons (décalage du niveau de Fermi = −0.7 eV) ce qui crée une signature unique dans le profil de conduction permettant d'extraire le niveau de dopage. Avec Ni et Co, la formation de bandes interdites dépendantes du spin détruit la dispersion linéaire des états du graphène ce qui permet d'atteindre une efficacité d'injection de spin de 60% et 80%, respectivement. Deuxièmement, nous avons étudié comment des distributions de dopage contrôlées dans les nano-transistors en Si pourraient supprimer les courants de fuite à l'état OFF. En supposant que les dopants (B et P) sont confinés dans des régions de 1.1 nm dans le canal, nous avons découvert de grandes variations de conductances (Gmax/Gmin ~ 10^5) en fonction de l'emplacement du dopage. Les plus grandes fluctuations surviennent lorsque les dopants sont à proximité des électrodes. Nos résultats indiquent que si les dopants sont éloignés des électrodes, d'une distance égale à 20% de la longueur du canal, le courant tunnel peut être supprimé par un facteur de 2 par rapport au dopage uniforme. Ainsi, l'ingénierie du dopage pourrait réduire les variations d'un dispositif à un autre et diminuer le courant de fuite. Dernièrement, nous avons intégré un modèle de déphasage dans notre théorie de transport ab initio qui a été utilisé pour étudier l'effet des collisions dans trois systèmes différents. Nos calculs ont révélé le rôle complexe du déphasage; parfois la conduction augmente ou diminue selon le système. Nous avons démontré que la rétrodiffusion, présent dans ce modèle, permet de récupérer la loi d'Ohm.
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ROSATI, ROBERTO. "Microscopic modeling of energy dissipation and decoherence in nanoscale materials and devices." Doctoral thesis, Politecnico di Torino, 2015. http://hdl.handle.net/11583/2599755.

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Primary goal of this thesis work is to develop and implement microscopic modeling strategies able to describe semiconductor-based nanomaterials and nanodevices, overcoming both the intrinsic limits of the semiclassical transport theory and the huge computational costs of non Markovian approaches. The progressive reduction of modern optoelectronic devices space-scales, triggered by the evolution on semiconductor heterostructures at the nanoscale, together with the decrease of the typical time-scales involved, pushes device miniaturization toward limits where the application of the traditional Boltzmann transport theory becomes questionable, and a comparison with more rigorous quantum transport approaches is imperative. In spite of the quantum-mechanical nature of electron and photon dynamics in the core region of typical solid-state nanodevices, the overall behavior of such quantum systems is often governed by a highly non-trivial interplay between phase coherence and dissipation/dephasing. To this aim, the crucial step is to adopt a quantum mechanical description of the carrier subsystem; this can be performed at different levels, ranging from phenomenological dissipation/decoherence models to quantum-kinetic treatments. However, due to their high computational cost, non-Markovian Green’ s-function as well as density-matrix approaches like quantum Monte Carlo techniques or quantum-kinetics are currently unsuitable for the design and optimization of new-generation nanodevices. On the other end, the Wigner-function technique is a widely used approach which, in principle, is well suited to describe an interplay between coherence and dissipation: in fact it can be regarded both as a phase space formulation of the electronic density matrix and a quantum equivalent of the classical distribution function. The evolution of this quasi-distribution function is governed by the Wigner-equation, which is usually solved by applying local spatial boundary conditions. However, such a scheme has recently shown some intrinsic limits. In this thesis work we analyze both the reasons for these unphysical features –pointing out the needing of different and purely quantum approaches– and the limits in which they should not appear, thus justifying why these problems had not been encountered in numerous quantum-transport simulations based on this procedure. For these reasons here we present a novel single-particle simulation strategy able to describe the interplay between coherence and dissipation/dephasing. In the presence of one- as well as two-body scattering mechanisms, we apply the mean-field approximation to the many-body Lindblad-type (hence, positive-definite) scattering superoperators provided by a recently proposed Markov approach, and we derive a closed equation of motion for the electronic single-particle density matrix. Although the resulting scattering superoperator turns out to be, at finite or high carrier densities, nonlinear and non-Lindblad, we prove that it is able to guarantee the positivity of the evolution (in striking contrast with conventional Markov approaches) independently of the scattering mechanisms, an essential prerequisite of any reliable kinetic treatment of semiconductor quantum devices; furthermore, it may be extended to the cases of quantum systems with open spatial boundaries (in this regard, it provides a formal derivation of a recently proposed Lindblad-like device-reservoir scattering superoperator). The proposed theoretical scheme is able, one the one hand, to recover the space-dependent Boltzmann equation and, on the other, to point out the regimes where a relevant role may be played by scattering-nonlocality effects, e.g. scattering-induced variations of the spatial charge-density which may not be provided by semiclassical treatments. Supplementing our analytical investigation with a number of simulated experiments in homogeneous as well as inhomogeneous GaN-based systems, we provide a rigorous treatment of scattering nonlocality in semiconductor nanostructures: in particular, we show how the scattering-nonlocality effects (i) are particularly significant in the presence of a carrier localization on the nanometric space scale, (ii) cause a speedup of the diffusion and (iii) in superlattice structures induce, with respect to scattering-free evolutions, a suppression of coherent oscillations between adjacent wells. These genuine quantum effects may be predicted also by other simplified treatments of the dissipation/decoherence like, e.g., the Relaxation Time Approximation: the latter however turns out to be, contrary to the proposed microscopic theoretical scheme, totally nonlocal, e.g. it is unable to recover the local character of the Boltzmann collision term in the semiclassical limit and it leads, especially for the case of quasielastic dissipation processes, to a significant overestimation of the diffusion speedup.
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ROTTA, DAVIDE. "Emerging devices and materials for nanoelectronics." Doctoral thesis, Università degli Studi di Milano-Bicocca, 2015. http://hdl.handle.net/10281/76048.

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Questa tesi analizza la possibile implementazione di due tipologie di dispositivi elettronici con funzionalità innovative: dispositivi per la computazione quantistica e transistors a film sottile. Negli ultimi decenni l’industria dei semiconduttori ha portato alla realizzazione di circuiti integrati con milioni di transistors e performance sempre migliori a costi contenuti. Tuttavia, questo processo di miniaturizzazione è giunto a un punto tale che i dispositivi elettronici sono ora composti da pochissimi atomi e ridurne ulteriormente le dimensioni sta diventando sempre più difficile. L’International Technology Roadmap of Semiconductors (ITRS) suggerisce due vie alternative per migliorare le caratteristiche dei dispositivi a partire dalla Front-End-Of-Line. La prima si avvale di nuovi dispositivi sulla base di architetture innovative o dell’utilizzo di diverse variabili di stato (Emerging Research Devices), mentre la seconda punta all’utilizzo di nuovi materiali (Emerging Research Materials). Questa tesi esamina due possibili candidati in questa ottica: i dispositivi per la computazione quantistica su architettura Complementary Metal-Oxide-Semiconductor (CMOS) e i transistors a film sottile basati su un semiconduttore bidimensionale come il MoS2. Da un lato, l’integrazione della computazione quantistica su Si sfrutterebbe il background tecnologico dell’industria dei semiconduttori per implementare su larga scala un nuovo protocollo di computazione dotato di un potenziale enorme e ancora inesplorato. D’altra parte il di-solfuro di molibdeno (MoS2) è intrinsecamente scalabile, in quanto può essere esfoliato fino allo spessore di un singolo strato atomico. Per questo motivo potrebbe essere un semiconduttore ideale per dispositivi elettronici ultrascalati, così come per applicazioni nella sensoristica, nell’optoelettronica e nell’elettronica flessibile. Questo lavoro mostra l’attività svolta al Laboratorio MDM-IMM-CNR nell’ambito del corso di dottorato in Nanostrutture e Nanotecnologie all’Università di Milano Bicocca. Lo sviluppo e l’utilizzo di processi di fabbricazione della nanoelettronica, in particolare la litografia a fascio elettronico (EBL), sono stati parte integrante dell’attività sperimentale dedicata alla realizzazione di dispositivi CMOS-compatibili per la computazione quantistica e per l’integrazione di film sottili di MoS2 in strutture Metal-Oxide-Semiconductor Field-Effect-Transistor (MOS FET). I necessari passi di processo sono stati adeguatamente calibrati e ottimizzati in modo da ottenere dispositivi quantistici basati su Quantum Dots (QD) con dimensioni caratteristiche inferiori a 50 nm. Tali dispositivi sono stati sviluppati con tecnologia Silicon-On-Insulator (SOI), mantenendo così la compatibilità con lo standard della tecnologia CMOS. Dispositivi a singolo donore e con QD di silicio sono stati poi caratterizzati elettricamente a temperature criogeniche (fino a 300 mK). Impulsando i potenziali di gate in modo controllato, è stato possibile studiare fenomeni di tunneling di singoli elettroni su un donore in alti campi magnetici (8T). In modo analogo è stato dimostrato il controllo dello stato di carica di QDs di Si. In particolare, si è osservato l’insorgere di rumore telegrafico associato al movimento di un singolo elettrone tra due QDs. Infine è stato condotto uno studio di fattibilità per l’integrazione su larga scala di un’architettura di computazione quantistica (il cosiddetto hybrid spin qubit) basata su doppi QDs di Si. Sul secondo fronte sono stati realizzati dei MOS FETs a film sottile basati su frammenti di MoS2, ottenuti per esfoliazione meccanica e contattati elettricamente tramite litografia EBL. Tali transistors sono poi stati caratterizzati elettricamente, con particolare attenzione alle proprietà di trasporto di carica e alla spettroscopia delle trappole all’interfaccia con l’ossido.
This work of thesis explores two emerging research device concepts as possible platforms for novel integrated circuits with unconventional functionalities. Nowadays integrated circuits with advanced performances are available at affordable costs, thanks to the progressive miniaturization of electronic components in the last decades. However, bare geometrical scaling is no more a practical way to improve the device performances and alternative strategies must be considered to achieve an equivalent scaling of the functionalities. The introduction of conceptually new devices and paradigms of information processing (Emerging Research Devices) or new materials with unconventional properties (Emerging Research Materials) are viable approaches, as indicated by the International Technology Roadmap of Semiconductors (ITRS), to enhance the functionalities of integrated circuits at the Front-End-Of-Line. The two options investigated to this respect are silicon devices for quantum computation based on a classical Complementary Metal-Oxide-Semiconductor (CMOS) platform and standard Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs) based on MoS2 thin film. In particular, the integration of Quantum Information Processing (QIP) in Si would take advantage of Si-based technology to introduce a completely new paradigm of information processing that has the potential to outperform classical computers in some computational tasks, like prime number factoring and the search in a big database. MoS2, conversely, can be exfoliated up to the single layer thickness. Such intrinsic and extreme scalability makes this material suitable for end-of-roadmap ultrascaled electronic devices as well as for other applications in the fields of sensors, optoelectronics and flexible electronics. This work reports on the experimental activity carried out at Laboratory MDM-IMM-CNR in the framework of the PhD school on Nanostructures and Nanotechnology at Università di Milano Bicocca. Electron Beam Lithography (EBL) and mainstream clean-room processing techniques have been intensively utilized to fabricate CMOS devices for QIP on the one hand and to integrate mechanically exfoliated MoS2 flakes in a conventional FET structure on the other hand. After a careful calibration and optimization of the process parameters, several different Quantum Dot (QD) configurations were designed and fully realized, achieving critical dimensions under 50 nm. Such device architectures were developed on a Silicon-On-Insulator (SOI) platform, in order to eventually access a straightforward integration into the CMOS mainstream technology. Si-QDs and donor-based devices have been then tested by electrical characterization techniques at cryogenic temperatures down to 300 mK. In detail, single electron tunneling events on a donor atom have been controlled by pulsed-gate techniques in high magnetic fields up to 8T, providing a preliminary characterization for the initialization procedure of donor qubits. The control of the charge states of Si-QDs have been also demonstrated by means of stability diagrams as well as the analysis of random telegraph noise arising from single electron tunneling between two QDs. Finally, a feasibility study for the large scale integration of quantum information processing was done based on a double QD hybrid qubit architecture. On the other side, MoS2 thin film transistors have been made by mechanical exfoliation of crystalline MoS2 and electrodes definition by EBL. Electrical characterization was performed on such devices, with a particular focus on the electrical transport in a FET device and on the spectroscopy of interface traps, that turns out to be a limiting factor for the logic operation.
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Books on the topic "Nanoelectronic device"

1

Chen, An, James Hutchby, Victor Zhirnov, and George Bourianoff, eds. Emerging Nanoelectronic Devices. Chichester, United Kingdom: John Wiley & Sons Ltd, 2014. http://dx.doi.org/10.1002/9781118958254.

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Evtukh, Anatoliy, Hans Hartnagel, Oktay Yilmazoglu, Hidenori Mimura, and Dimitris Pavlidis. Vacuum Nanoelectronic Devices. Chichester, UK: John Wiley & Sons, Ltd, 2015. http://dx.doi.org/10.1002/9781119037989.

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Sarkar, Angsuman, and Arpan Deyasi. Low-Dimensional Nanoelectronic Devices. Boca Raton: Apple Academic Press, 2022. http://dx.doi.org/10.1201/9781003277378.

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Labbé, Christophe, Subhananda Chakrabarti, Gargi Raina, and B. Bindu, eds. Nanoelectronic Materials and Devices. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7191-1.

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Nanoelectronics: Principles and devices. Boston, MA: Artech House, 2005.

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Dragoman, Mircea. Nanoelectronics: Principles and devices. 2nd ed. Boston: Artech House, 2009.

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Dragoman, Mircea. Nanoelectronics: Principles and devices. Boston, MA: Artech House, 2005.

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Joodaki, Mojtaba. Selected Advances in Nanoelectronic Devices. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31350-9.

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Microelectronics to nanoelectronics: Materials, devices & manufacturability. Boca Raton, FL: Taylor & Francis, 2012.

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Raj, Balwinder, and Arun Kumar Singh. Nanoelectronic Devices for Hardware and Software Security. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003126645.

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Book chapters on the topic "Nanoelectronic device"

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Martini, I., M. Kamp, and A. Forchel. "Combined Approaches for Nanoelectronic Device Fabrication." In Alternative Lithography, 235–48. Boston, MA: Springer US, 2003. http://dx.doi.org/10.1007/978-1-4419-9204-8_12.

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Kumar, Arun, and Pramod Kumar Tiwari. "Silicon Nanotube FETs: From Device Concept to Analytical Model Development." In Low-Dimensional Nanoelectronic Devices, 153–71. Boca Raton: Apple Academic Press, 2022. http://dx.doi.org/10.1201/9781003277378-6.

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Kunduru, Vindhya, Yamini Yadav, and Shalini Prasad. "Characteristics of Carbon Nanotubes for Nanoelectronic Device Applications." In Nanopackaging, 345–75. Boston, MA: Springer US, 2008. http://dx.doi.org/10.1007/978-0-387-47325-3_16.

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Liu, Z. "Novel Nanoelectronic Device Applications of Nanocrystals and Nanoparticles." In Semiconductor Nanocrystals and Metal Nanoparticles, 461–500. Taylor & Francis Group, 6000 Broken Sound Parkway NW, Suite 300, Boca Raton, FL 33487-2742: CRC Press, 2016. http://dx.doi.org/10.1201/9781315374628-14.

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Shanmugam, Nandhinee Radha, and Shalini Prasad. "Characteristics of Carbon Nanotubes for Nanoelectronic Device Applications." In Nanopackaging, 597–628. Cham: Springer International Publishing, 2018. http://dx.doi.org/10.1007/978-3-319-90362-0_18.

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Querlioz, Damien, Philippe Dollfus, and Mireille Mouis. "Particle-based Monte Carlo Approach to Wigner-Boltzmann Device Simulation." In The Wigner Monte Carlo Method for Nanoelectronic Devices, 57–88. Hoboken, NJ USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118618479.ch2.

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Saga, Koichiro, and Takeshi Hattori. "Wafer Cleaning Using Supercritical CO2 in Semiconductor and Nanoelectronic Device Fabrication." In Solid State Phenomena, 97–103. Stafa: Trans Tech Publications Ltd., 2007. http://dx.doi.org/10.4028/3-908451-46-9.97.

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Jayalakshmi, R., and M. Senthil Kumaran. "Modeling of Potentially Implementable Configurable Logic Block in Quantum Dot Cellular Automata for Nanoelectronic Device Architecture." In Springer Proceedings in Materials, 611–17. Singapore: Springer Singapore, 2020. http://dx.doi.org/10.1007/978-981-15-6267-9_69.

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Kuzmin, Andrey, Mathieu Luisier, and Olaf Schenk. "Fast Methods for Computing Selected Elements of the Green’s Function in Massively Parallel Nanoelectronic Device Simulations." In Euro-Par 2013 Parallel Processing, 533–44. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-40047-6_54.

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Raushan, Mohd Adil, Naushad Alam, and Mohd Jawaid Siddiqui. "Emerging Nanoelectronic Devices." In Nanoelectronic Devices for Hardware and Software Security, 1–32. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003126645-1.

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Conference papers on the topic "Nanoelectronic device"

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NOVIK, E. G., I. V. SHEREMET, S. S. IVASHKEVICH, and I. I. ABRAMOV. "NANOELECTRONIC DEVICE SIMULATOR NANODEV." In Reviews and Short Notes to Nanomeeting '97. WORLD SCIENTIFIC, 1997. http://dx.doi.org/10.1142/9789814503938_0069.

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"Nanoelectronic Devices II." In 2006 64th Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/drc.2006.305076.

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Huo, Dennis, Qiaoyan Yu, and Paul Ampadu. "A ballistic nanoelectronic device simulator." In 2007 IEEE International Symposium on Nanoscale Architectures. IEEE, 2007. http://dx.doi.org/10.1109/nanoarch.2007.4400856.

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"Solid State and Nanoelectronic Devices -- Novel Device Technologies." In 2006 International Electron Devices Meeting. IEEE, 2006. http://dx.doi.org/10.1109/iedm.2006.346981.

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Ceze, L., J. Hasler, K. K. Likharev, J. s. Seo, T. Sherwood, D. Strukov, Y. Xie, and S. Yu. "Nanoelectronic neurocomputing: Status and prospects." In 2016 74th Annual Device Research Conference (DRC). IEEE, 2016. http://dx.doi.org/10.1109/drc.2016.7548506.

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Richter, Curt A., Joseph J. Kopanski, Chong Jiang, Yicheng Wang, M. Yaqub Afridi, Xiaoxiao Zhu, D. E. Ioannou, et al. "Advanced Capacitance Metrology for Nanoelectronic Device Characterization." In FRONTIERS OF CHARACTERIZATION AND METROLOGY FOR NANOELECTRONICS: 2009. AIP, 2009. http://dx.doi.org/10.1063/1.3251244.

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Luisier, M., and A. Szabo. "Paving the way for ultimate device scaling through nanoelectronic device simulations." In 2013 14th International Conference on Ultimate Integration on Silicon (ULIS 2013). IEEE, 2013. http://dx.doi.org/10.1109/ulis.2013.6523489.

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Han, Kyungsup, Yong-Jin Yoon, Jack Sheng Kee, and Mi Kyoung Park. "Enhancement of nanoelectronic sensor performance with microfluidic device." In 2013 IEEE International Nanoelectronics Conference (INEC). IEEE, 2013. http://dx.doi.org/10.1109/inec.2013.6465987.

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Abramov, I. I., A. L. Baranoff, I. A. Goncharenko, N. V. Kolomejtseva, Y. L. Bely, and I. Y. Shcherbakova. "A nanoelectronic device simulation software system NANODEV: new opportunities." In International Conference on Micro- and Nano-Electronics 2009, edited by Kamil A. Valiev and Alexander A. Orlikovsky. SPIE, 2009. http://dx.doi.org/10.1117/12.853521.

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Zhou, Guanyu, Tian Sun, Rehan Younas, and Christopher L. Hinkle. "Materials and Device Strategies for Nanoelectronic 3D Heterogeneous Integration." In 2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD). IEEE, 2021. http://dx.doi.org/10.1109/sispad54002.2021.9592592.

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Reports on the topic "Nanoelectronic device"

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Brinker, C. Jeffrey, Darren Robert Dunphy, Carlee E. Ashley, Hongyou Fan, DeAnna Lopez, Regina Lynn Simpson, David Robert Tallant, et al. Cell-directed assembly on an integrated nanoelectronic/nanophotonic device for probing cellular responses on the nanoscale. Office of Scientific and Technical Information (OSTI), January 2006. http://dx.doi.org/10.2172/883480.

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Liu, Jie, and Mark W. Grinstaff. DNA for the Assembly of Nanoelectronic Devices Biotechnology and Nanoelectronics. Fort Belvoir, VA: Defense Technical Information Center, April 2005. http://dx.doi.org/10.21236/ada433496.

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Rodriguez, Rene, Joshua Pak, Andrew Holland, Alan Hunt, Thomas Bitterwolf, You Qiang, Leah Bergman, Christine Berven, Alex Punnoose, and Dmitri Tenne. Incorporation of Novel Nanostructured Materials into Solar Cells and Nanoelectronic Devices. Office of Scientific and Technical Information (OSTI), November 2011. http://dx.doi.org/10.2172/1029119.

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Waitz, Anthony, Jerzy Bernholc, and Kurt Stokbro. Tools for Modeling & Simulation of Molecular and Nanoelectronics Devices. Fort Belvoir, VA: Defense Technical Information Center, June 2012. http://dx.doi.org/10.21236/ada577319.

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Ajayan, Pulickel M. Scaled up Fabrication of High-Throughout SWNT Nanoelectronics and Nanosensor Devices. Fort Belvoir, VA: Defense Technical Information Center, April 2007. http://dx.doi.org/10.21236/ada482306.

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Ham, Donhee, Xiaofeng Li, and William Andress. Nanoelectronic Initiative - GHz & THz Amplifier and Oscillator Circuits With ID Nanoscale Devices for Multispectral Heterodyning Detector Arrays. Fort Belvoir, VA: Defense Technical Information Center, October 2009. http://dx.doi.org/10.21236/ada510610.

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