Relevant bibliographies by topics / Nanoelectronic

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers
  6. Reports

Academic literature on the topic 'Nanoelectronic'

Author: Grafiati
Published: 4 June 2021
Last updated: 9 June 2025

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Journal articles on the topic "Nanoelectronic"

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He, Qianxi. "Characteristics and Improvement Methods of Carbon Nanodevices." Highlights in Science, Engineering and Technology 106 (July 16, 2024): 94–100. http://dx.doi.org/10.54097/8s3ra054.

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Whether the trend of increasing integration density of integrated circuits indicated by Moore's Law can continue to develop, especially now that feature sizes have entered the nanometer range, shrinking sizes face greater challenges. Since entering the "post-Moore" era, the development of carbon-based nanoelectronics has attracted attention. This paper explores the application of carbon-based nanomaterials in carbon-based nanoelectronic devices and integrated circuits. It introduces the structure, properties, and preparation methods of single-walled carbon nanotubes and graphene, demonstrating their importance to carbon-based nanoelectronic devices and integrated circuits. The synthesis methods of carbon nanotubes mainly include arc discharge method, laser ablation method, and chemical vapor deposition metho. Subsequently, it summarizes the advantages, applications, and challenges of carbon-based nanoelectronic devices. The applications of carbon-based nanoelectronic devices and integrated circuits include digital integrated circuits, optoelectronic integrated circuits, electrochemical sensors, carbon-based radio frequency devices, and smart integrated systems. Furthermore, starting from the preparation methods, improvement methods are summarized, focusing on chemical vapor deposition, to optimize carbon nanomaterials for application in carbon nanodevices. It elucidates the promising prospects of carbon-based nanoelectronics.
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Mishra, Manoj, and Shil Ja. "Germanium Nanowires (GeNW): Synthesis, Structural Properties, and Electrical Characterization for Advanced Nanoelectronic Devices." Migration Letters 20, S13 (December 20, 2023): 236–45. http://dx.doi.org/10.59670/ml.v20is13.6289.

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The exponential progress of nanoelectronic devices necessitates the development of novel materials and production methodologies to fulfill the escalating demands for enhanced performance. This research aims to answer the current need for high-performance materials by proposing a revolutionary approach known as Germanium Nanowires for Advanced Nanoelectronic Devices (GeNW-ANED). GeNW-ANED achieves the integration of GeNW growth with advanced nanoelectronic applications. The system has several distinctive attributes, such as meticulous regulation of nanowire fabrication, adjustable electrical characteristics, and improved thermal qualities. The GeNW-ANED method exhibits exceptional performance across multiple experimental metrics, encompassing Electrical Conductivity (1.70 S/cm), Carrier Mobility (1685.83 cm²/Vs), Dielectric Constant (4.73), Specific Capacity (325.00 mAh/g), Growth Rate (5.93 nm/s), and Thermal Conductivity (3.47 W/mK). The impressive results achieved by GeNW-ANED establish it as a prospective contender for advanced nanoelectronic devices, offering the potential for improved performance and increased adaptability. The presented approach exhibits promise in influencing the trajectory of nanoelectronics, as it provides a sturdy basis for advancing the creation of forthcoming devices that possess enhanced electrical, thermal, and energy storage properties.
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S, Anusankari, and Rajabrundha A. "MODELING, VERIFICATION AND TESTING TECHNIQUES IN NANOELECTRONICS INSTRUMENTATION FOR ENHANCED PRECISION AND RELIABILITY." ICTACT Journal on Microelectronics 10, no. 3 (October 1, 2024): 1854–61. https://doi.org/10.21917/ijme.2024.0319.

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In the field of nanoelectronics, achieving high precision and reliability is critical for advancing technologies in diverse applications, such as sensors, biomedical devices, and quantum computing. Nanoelectronics instrumentation faces unique challenges due to the scaling of devices to nanometer dimensions, which results in increased susceptibility to noise, variability, and failure. Traditional verification and testing methods often fall short in ensuring the precision and reliability required at such scales. To address these challenges, advanced modeling, verification, and testing techniques have been developed to enhance the performance of nanoelectronic systems. This paper explores state-of-the-art techniques for modeling, verification, and testing that cater specifically to nanoelectronics. The proposed method combines physics-based modeling with statistical approaches to account for process variations and device imperfections. Formal verification methods are employed to ensure that the system meets stringent performance specifications, while accelerated stress testing techniques, such as temperature and voltage scaling, are used to simulate long-term reliability. Results from a case study demonstrate that by applying these techniques, a 15% improvement in precision was achieved, reducing measurement errors from 5% to 2.5%. Furthermore, reliability was enhanced, with a 20% increase in the mean time to failure (MTTF) for the nanoelectronic system. These results highlight the effectiveness of combining advanced modeling with rigorous verification and testing approaches in nanoelectronics, offering a pathway to more robust and reliable systems.
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HULL, ROBERT, RICHARD MARTEL, and J. M. XU. "NANOELECTRONICS: SOME CURRENT ASPECTS AND PROSPECTS." International Journal of High Speed Electronics and Systems 12, no. 02 (June 2002): 353–64. http://dx.doi.org/10.1142/s0129156402001174.

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A brief summary is provided of selected current activities in the field of nanoelectronics, which is taken here to mean the fabrication and integration of active microelectronic components with feature dimensions of tens of nanometers or less. Particular emphasis is placed upon the classes of nanoelectronic devices that were discussed at the 2002 WOFE Conference.
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Snider, G., P. Kuekes, T. Hogg, and R. Stanley Williams. "Nanoelectronic architectures." Applied Physics A 80, no. 6 (March 2005): 1183–95. http://dx.doi.org/10.1007/s00339-004-3154-4.

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Csurgay, Árpád I., and Wolfgang Porod. "Nanoelectronic Circuits." International Journal of Circuit Theory and Applications 38, no. 9 (September 15, 2010): 881–82. http://dx.doi.org/10.1002/cta.727.

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Melnyk, Oleksandr, and Viktoriia Kozarevych. "SIMULATION OF PROGRAMMABLE SINGLE-ELECTRON NANOCIRCUITS." Bulletin of the National Technical University "KhPI". Series: Mathematical modeling in engineering and technologies, no. 1 (March 5, 2021): 64–68. http://dx.doi.org/10.20998/2222-0631.2020.01.05.

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The speed and specializations of large-scale integrated circuits always contradict their versatility, which expands their range and causes the rise in price of electronic devices. It is possible to eliminate the contradictions between universality and specialization by developing programmable nanoelectronic devices, the algorithms of which are changed at the request of computer hardware developers, i.e. by creating arithmetic circuits with programmable characteristics. The development of issues of theory and practice of the majority principle is now an urgent problem, since the nanoelectronic execution of computer systems with programmable structures will significantly reduce their cost and significantly simplify the design stage of automated systems. Today there is an important problem of developing principles for building reliable computer equipment. The use of mathematical and circuit modeling along with computer-aided design systems (CAD) can significantly increase the reliability of the designed devices. The authors prove the advantages of creating programmable nanodevices to overcome the physical limitations of micro-rominiatization. This continuity contributes to the accelerated introduction of mathematical modeling based on programmable nanoelectronics devices. The simulation and computer-aided design of reliable programmable nanoelectronic devices based on the technology of quantum automata is described. While constructing single-electron nanocircuits of combinational and sequential types the theory of majority logic is used. The order of construction and programming of various types of arithmetic-logic units is analyzed.
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Sha, Junjiang, Chong Xu, and Ke Xu. "Progress of Research on the Application of Nanoelectronic Smelling in the Field of Food." Micromachines 13, no. 5 (May 18, 2022): 789. http://dx.doi.org/10.3390/mi13050789.

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In the past 20 years, the development of an artificial olfactory system has made great progress and improvements. In recent years, as a new type of sensor, nanoelectronic smelling has been widely used in the food and drug industry because of its advantages of accurate sensitivity and good selectivity. This paper reviews the latest applications and progress of nanoelectronic smelling in animal-, plant-, and microbial-based foods. This includes an analysis of the status of nanoelectronic smelling in animal-based foods, an analysis of its harmful composition in plant-based foods, and an analysis of the microorganism quantity in microbial-based foods. We also conduct a flavor component analysis and an assessment of the advantages of nanoelectronic smelling. On this basis, the principles and structures of nanoelectronic smelling are also analyzed. Finally, the limitations and challenges of nanoelectronic smelling are summarized, and the future development of nanoelectronic smelling is proposed.
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Wang, Yanfeng, Haoping Ji, and Junwei Sun. "Design and Control for Four-Variable Chaotic Nanoelectronic Circuits Based on DNA Reaction Networks." Journal of Nanoelectronics and Optoelectronics 16, no. 8 (August 1, 2021): 1248–62. http://dx.doi.org/10.1166/jno.2021.3062.

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Control of chaotic nanoelectronic circuit is a typical nonlinear problem. In this paper, we present a four-variable chaotic oscillatory nanoelectronic circuit by the cascade of multiplication, adjustment and elimination DNA chemical reaction modules. Furthermore, a proportional integral (PI) controller of four-variable nonlinear chaotic nanoelectronic circuit is realized based on catalysis and annihilation DNA chemical reaction modules. These DNA modules are realized by a series of DNA strand displacement (DSD) reactions and simulated by Visual DSD. Oscillatory time domain waveforms of four-variable chaotic oscillatory nanoelectronic circuit could be generated by the designed chaotic oscillatory chemical reaction modules. The proposed PI controller could be added for chaotic nanoelectronic circuits to stabilize oscillatory signals and it has robustness to the initial value changes of chaotic nanoelectronic circuit.
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Sangwan, Vinod K., and Mark C. Hersam. "Neuromorphic nanoelectronic materials." Nature Nanotechnology 15, no. 7 (March 2, 2020): 517–28. http://dx.doi.org/10.1038/s41565-020-0647-z.

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Dissertations / Theses on the topic "Nanoelectronic"

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Rao, Wenjing. "Towards reliable nanoelectronic systems." Diss., Connect to a 24 p. preview or request complete full text in PDF format. Access restricted to UC campuses, 2008. http://wwwlib.umi.com/cr/ucsd/fullcit?p3291919.

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Thesis (Ph. D.)--University of California, San Diego, 2008.<br>Title from first page of PDF file (viewed March 18, 2008). Available via ProQuest Digital Dissertations. Vita. Includes bibliographical references (p. 193-199).
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Chiu, Pit Ho Patrio 1977. "Bismuth based nanoelectronic devices." Thesis, McGill University, 2005. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=100337.

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Bismuth (Bi) is a unique electronic material with small effective mass (&sim;0.001me) and long carrier mean free path (100 nm at 300K). It is particularly suitable for studying nano scale related phenomena such as size effect and energy level spacing. In this thesis work, bismuth based nanoelectronic devices were studied. Devices were fabricated using a combination of electron beam (e-beam) writing and thermal evaporation techniques. Dimensions of the fabricated devices were in the order of 100 rim. All structures were optimized for individual electrical characterization. Three types of devices were studied: Bi nanowires, Bi nanowires with dual side-gate structures and Bi nanodot structures. In the study of Bi nanowires, metal-to-semiconductor transition phenomenon and size effect were observed. The conduction behavior of Bi nanowires changed from metallic to semiconductor when the device's critical dimension was reduced to below 50 nm. It is a solid experimental evidence of the quantum confinement-induced bandgap theory. Additionally, it has been found in the present work that resistivity of individual Bi nanowire increased as linewidth decreased indicating size effect occurred in the Bi nanowires. Dual side-gate structures were formed adjacent to the Bi nanowires in an attempt to modulate the current. Measurements showed a 7% of current modulation. The small current modulation suggested the high carrier density in the nanowire which has prevented the full depletion of free carriers. 100 nm-diameter Bi nanodot structures were fabricated utilizing proximity effect of e-beam writing. Precise control of electron doses and process conditions led to the successful fabrication of sub-nanometer tunneling junctions to the nanodots. Significant non-linear current-voltage (I-V) characteristic was observed at low temperatures. The step like I-V characteristic was a strong indication of energy level spacing in the zero-dimensional nanodot structure. The successful observation of energy level spacing in a relatively large nanodot is due to the small effective mass of bismuth material which leads to a measurable energy level spacing.
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Blackburn, A. M. "Multiple-gate vacuum nanoelectronic devices." Thesis, University of Cambridge, 2005. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.596691.

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This thesis introduces novel multiple-gate vacuum nanoelectronic devices, presenting details of their theoretical and experimental characterization, and of the methods that have been established for their fabrication. These devices, based upon the nanotriode of Driskill-Smith et al, have multiple-gates placed within an anode-cathode vacuum gap of only a few hundred nanometres, permitting a wide range of potential-energy landscapes to be created in front of its tungsten-nanopillar field-emitting cathode. The current transport in such devices is suggested to be influenced by quantum interference of the electron wave function in the anode-cathode gap, and this work seeks to control this effect. The device fabrication and electrical characterisation focuses on a pentode device, which has an integrated anode and tungsten-nanopillar cathode structure and three gate-electrodes with aperture-diameters of less than 100 nm; the fabrication can readily be adapted to devices with fewer gates. A calculation of the transmission probability for electrons through the entire pentode anode-cathode gap shows resonances at certain gate-voltage arrangements, strengthening the possibility of observing quantum interference effects in these devices. A study of the tungsten nanopillar formation-process gives new information upon their geometry and formation. The details of the process required to form nanopillars in the pentode chamber are suggested to differ from those required on large area samples. Thus, the observed pentode device characteristics are best explained by dielectric leakage mechanisms, which were also evident in the nanotriode work. However, the reliable range of field emission observation, in two-terminal devices where field emission was observed, has been increased in comparison to the nanotriode by using a tungsten pedestal cathode structure. In response to the pentode characteristics, an alternative cathode structure was fabricated, based upon carbon contaminated scanning electron microscope deposited tips.
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Maassen, Jesse. "First principles simulations of nanoelectronic devices." Thesis, McGill University, 2012. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=106463.

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As the miniaturization of devices begins to reveal the atomic nature of materials, where chemical bonding and quantum effects are important, one must resort to a parameter-free theory for predictions. This thesis theoretically investigates the quantum transport properties of nanoelectronic devices using atomistic first principles. Our theoretical formalism employs density functional theory (DFT) in combination with Keldysh nonequilibrium Green's functions (NEGF). Self-consistently solving the DFT Hamiltonian with the NEGF charge density provides a way to simulate nonequilibrium systems without phenomenological parameters. This state-of-the-art technique was used to study three problems related to the field of nanoelectronics. First, we investigated the role of metallic contacts (Cu, Ni and Co) on the transport characteristics of graphene devices. With Cu, the graphene is simply electron-doped (Fermi level shift of −0.7 eV) which creates a unique signature in the conduction profile allowing one to extract the doping level. With Ni and Co, spin-dependent band gaps are formed in graphene's linear dispersion bands, thus leading to the prediction of high spin injection efficiencies reaching 60% and 80%, respectively. Second, we studied how controlled doping distributions in nano-scale Si transistors could suppress OFF-state leakage currents. By assuming the dopants (B and P) are confined in 1.1 nm regions in the channel, we discovered large conductance variations (Gmax/Gmin ~ 10^5) as a function of the doping location. The largest fluctuations arise when the dopants are in the vicinity of the electrodes. Our results indicate that if the dopants are located away from the leads, a distance equal to 20% of the channel length, the tunneling current can be suppressed by a factor of 2 when compared to the case of uniform doping. Thus, controlled doping engineering is found to suppress device-to-device variations and lower the undesirable leakage current. Finally, we incorporated a dephasing model into our ab initio transport formalism, which was used to study the effect of phase-breaking scattering in three different systems. Our calculations revealed the complex role of dephasing, where conduction increased or decreased depending on the system under consideration. We demon- strated that the backscattering component of this dephasing scheme also allows one to retrieve Ohm's law.<br>Comme la miniaturisation des dispositifs commence à révéler la nature atomique des matériaux, où les liaisons chimiques et les effets quantiques sont importants, nous devons recourir à une théorie sans paramètre pour obtenir des prédictions. Cette thèse étudie les propriétés de transport quantique des dispositifs nanoélectroniques en utilisant des méthodes ab initio atomiques. Notre formalisme théorique combine la théorie de la fonctionnelle de la densité (DFT) avec les fonctions de Green hors-équilibres (NEGF). Résoudre l'Hamiltonien DFT de manière auto-consistante avec la densité de charge NEGF permet de simuler des systèmes hors-équilibres sans utiliser des paramètres. Cette technique sophistiquée a été utilisée pour étudier trois problèmes liés au domaine de la nanoélectronique. Premièrement, nous avons étudié le rôle des contacts métalliques (Cu, Ni et Co) sur les caractéristiques de transport des dispositifs à base de graphène. Dans le cas du Cu, le graphène est simplement dopé en électrons (décalage du niveau de Fermi = −0.7 eV) ce qui crée une signature unique dans le profil de conduction permettant d'extraire le niveau de dopage. Avec Ni et Co, la formation de bandes interdites dépendantes du spin détruit la dispersion linéaire des états du graphène ce qui permet d'atteindre une efficacité d'injection de spin de 60% et 80%, respectivement. Deuxièmement, nous avons étudié comment des distributions de dopage contrôlées dans les nano-transistors en Si pourraient supprimer les courants de fuite à l'état OFF. En supposant que les dopants (B et P) sont confinés dans des régions de 1.1 nm dans le canal, nous avons découvert de grandes variations de conductances (Gmax/Gmin ~ 10^5) en fonction de l'emplacement du dopage. Les plus grandes fluctuations surviennent lorsque les dopants sont à proximité des électrodes. Nos résultats indiquent que si les dopants sont éloignés des électrodes, d'une distance égale à 20% de la longueur du canal, le courant tunnel peut être supprimé par un facteur de 2 par rapport au dopage uniforme. Ainsi, l'ingénierie du dopage pourrait réduire les variations d'un dispositif à un autre et diminuer le courant de fuite. Dernièrement, nous avons intégré un modèle de déphasage dans notre théorie de transport ab initio qui a été utilisé pour étudier l'effet des collisions dans trois systèmes différents. Nos calculs ont révélé le rôle complexe du déphasage; parfois la conduction augmente ou diminue selon le système. Nous avons démontré que la rétrodiffusion, présent dans ce modèle, permet de récupérer la loi d'Ohm.
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Huang, Jun, and 黃俊. "Efficiency enhancement for nanoelectronic transport simulations." Thesis, The University of Hong Kong (Pokfulam, Hong Kong), 2013. http://hdl.handle.net/10722/196031.

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Continual technology innovations make it possible to fabricate electronic devices on the order of 10nm. In this nanoscale regime, quantum physics becomes critically important, like energy quantization effects of the narrow channel and the leakage currents due to tunneling. It has also been utilized to build novel devices, such as the band-to-band tunneling field-effect transistors (FETs). Therefore, it presages accurate quantum transport simulations, which not only allow quantitative understanding of the device performances but also provide physical insight and guidelines for device optimizations. However, quantum transport simulations usually require solving repeatedly the Green’s function or the wave function of the whole device region with open boundary treatment, which are computationally cumbersome. Moreover, to overcome the short-channel effects, modern devices usually employ multi-gate structures that are three-dimensional, making the computation very challenging. It is the major target of this thesis to enhance the simulation efficiency by proposing several fast numerical algorithms. The other target is to apply these algorithms to study the physics and performances of some emerging electronic devices. First, an efficient method is implemented for real space simulations with the effective mass approximation. Based on the wave function approach, asymptotic waveform evaluation combined with a complex frequency hopping algorithm is successfully adopted to characterize electron conduction over a wide energy range. Good accuracy and efficiency are demonstrated by simulating several n-type multi-gate silicon FETs. This technique is valid for arbitrary potential distribution and device geometry, making it a powerful tool for studying n-type silicon nanowire (SiNW) FETs in the presence of charged impurity and surface roughness scattering. Second, a model order reduction (MOR) method is proposed for multiband simulation of nanowire structures. Employing three- or six-band k.p Hamiltonian, the non-equilibrium Green’s function (NEGF) equations are projected into a much smaller subspace constructed by sampling the Bloch modes of each cross-section layer. Together with special sampling schemes and Krylov subspace methods for solving the eigenmodes, large cross-section p-type SiNW FETs can be simulated. A novel device, junctionless FET, is then investigated. It is found that its doping density, channel orientation, and channel size need to be carefully optimized in order to outperform the classical inversion-mode FET. With a spurious band elimination process, the MOR method is subsequently extended to the eight-band k.p model, allowing simulation of band-to-band tunneling devices. In particular, tunneling FETs with indium arsenide (InAs) nanowire channel are studied, considering different channel orientations and configurations with source pockets. Results suggest that source pocket has no significant impact on the performances of the nanowire device due to its good electrostatic integrity. At last, improvements are made for open boundary treatment in atomistic simulations. The trick is to condense the Hamiltonian matrix of the periodic leads before calculating the surface Green’s function. It is very useful for treating leads with long unit cells.<br>published_or_final_version<br>Electrical and Electronic Engineering<br>Doctoral<br>Doctor of Philosophy
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Mirza, Muhammad M. "Nanofabrication of silicon nanowires and nanoelectronic transistors." Thesis, University of Glasgow, 2015. http://theses.gla.ac.uk/6495/.

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This project developed a robust and reliable process to pattern < 5 nm features in negative tone Hydrogen silsesquioxane (HSQ) resist using high resolution electron beam lithography and developed a low damage reactive ion etch (RIE) process to fabricate silicon nanowires on degenerately doped n-type silicon-on-insulator (SOI) substrates. A process to thermally grow high quality silicon dioxide (SiO2) (between 5-15 nm) is also developed to passivate onto the etched silicon nanowire devices to serve the purposes of gate dielectric and a diffusion barrier to minimize the donor deactivation. The measured interface state trap density (Dit) of the 10 nm thermally grown oxide is 1.3x10^10 cm^−2 eV^−1 with a breakdown voltage of ~7 V. Using optimized processes for lithography, dry etch and thermal oxidation, Hall bar and Greek cross devices are fabricated with mean widths from 45 to 4 nm on SOI substrates with a doping density ~ 2x10^19, 4x10^19, 8x10^19 and 2x10^20 atoms/cm^3 and electronically characterized at room and cryogenic temperatures (from 1.4 to 300 K) to allow resistivity, mobility and carrier density to be extracted directly as a function of temperature. This allowed to probe electron transport and scattering mechanisms in degenerately doped silicon nanowires. The mean free path is theoretically calculated and directly compared with the widths of the nanowires by which it can be approximated that the electron transport is 3 dimensional (3D) for the 12 nm wide nanowire which has likely to be changed to 2D and 1D for the 7 nm and 4 nm wide nanowires respectively. Moreover the experimental mobility is directly compared with a number of theoretically calculated mobilities using Matthiessen’s rule, where it has been determined that the neutral impurity scattering is the dominant scattering mechanism limiting the performance of silicon nanowires. Using silicon nanowires, junctionless transistors are fabricated on SOI substrate with a doping density ~ 4x10^19 atoms/cm^3 and electronically characterized at room and cryogenic temperatures (from 1.4 to 300 K). It was observed that reducing the width of channel from 24 to 8 nm, the transistor changed their operation from depletion to enhancement mode due to increase in the surface depletion at smaller length scales. Since the drain current in a junctionless transistor is proportional to the doping density, a high on-state drive current ~ 1.28 mA/µm has been observed with sub-threshold slope (SS) ~ 66 mV/decade at 300 K. Moreover temperature dependent measurements revealed a low SS ~ 39 mV/decade at 70 K and single electron oscillations at 1.4 K. Finally, independent arrays of 2 terminal nanowires devices with mean widths from 45 to 4 nm are fabricated on SOI substrate with a doping density ~ 8x10^19 atoms/cm^3 to detect polyoxometalate (POM) molecules [W18O54(SeO3)2]4−. A change in resistivity has been observed ~ 3.6 m ohm-cm (corresponds to ~ 13 % increase) when POM molecules are coated around the nanowires, shown n-type behaviour of molecules. POM molecules exhibit highly redox properties, therefore side-gated FETs with mean width ~ 4 nm were fabricated on SOI substrate with a doping density ~ 4x10^19 atoms/cm^3 where side-gate was used to apply alternative ± pulses of 20 V to charge and discharge the POM molecules to demonstrate flash memory operation. The average change in the threshold voltage was ~ 1.2 V between the charging (program) and the discharging (erase) cycles. The program/erase time is currently limited to 100 ms for a reasonable single-to-noise ratio. Moreover no significant decay in the stored charge has yet been measured over a period of 2 weeks (336 hours).
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Coker, Ayodeji. "Performance analysis of fault-tolerant nanoelectronic memories." [College Station, Tex. : Texas A&M University, 2008. http://hdl.handle.net/1969.1/ETD-TAMU-2666.

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Sarsby, Matt. "Nanoelectronic and nanomechanical devices for low temperature applications." Thesis, Lancaster University, 2017. http://eprints.lancs.ac.uk/84447/.

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Cooling physical experiments to low temperatures removes thermal excitations to reveal quantum mechanical phenomena. The progression of nanotechnologies provides new and exciting research opportunities to probe nature at ever smaller length scales. The coupling of nanotechnologies and low temperature techniques has potential for scientific discoveries as well as real world applications. This work demonstrates techniques to further extend physical experimental research into the millikelvin-nanoscale domain. The challenge of thermometry becomes an increasingly complex problem as the temperature of a physical system lowers. We describe the development and methods for a specially modified Coulomb blockade thermometer to achieve electron thermometry below 4mK overcoming the challenge of electron thermalisation for on-chip devices. Mechanically vibrating devices can directly probe bulk and surface fluid properties. We developed practical measurement techniques and analysis methods to demonstrate the use of nanomechanical resonators, which for the first time were used to probe both the normal and the superfluid phases of helium-4. The doubly clamped beams had a cross section of 100nm by 100nm and were tested in length variants between 15um to 50um, The flexural resonance between 1MHz and 10MHz in response to the helium temperature dependent properties showed an encouraging agreement with established theories, providing experimental verification on a new smaller length scale. The smallest beams achieved a mass sensitivity in liquid of 10ag. We also created and analysed a new method of sampling peak-like functions that is applicable to many physical systems to provide around 20% improvements over the existing methods under certain situations. This was verified in ultra low temperature applications as a drop-in addition to accompany existing techniques.
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Jiang, Zhe. "Novel nanowire structures and devices for nanoelectronic bioprobes." Thesis, Harvard University, 2015. http://nrs.harvard.edu/urn-3:HUL.InstRepos:17467307.

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Semiconductor nanowire materials and devices provide unique opportunities in the frontier between nanoelectronics and biology. The bottom-up paradigm enables flexible synthesis and patterning of nanoscale building blocks with novel structures and properties, and nano-to-micro fabrication methods allow the advantages of functional nanowire elements to interface with biological systems in new ways. In this thesis, I will focus on the development of bottom-up nanoscience platforms, which includes rational synthesis and assembly of semiconductor nanowires with new capabilities, as well as design and fabrication of the first free-standing three-dimensional (3D) nanoprobes, with special focus on applications in intracellular recording and stimulation. I will first introduce kinked p-n junction nanowires as a new and powerful family of high spatial resolution biological and chemical sensors with proof-of-concept applications. Next, I will discuss a variety of functional kinked nanowires with synthetically controlled properties and the potential of achieving more detailed and less invasive cellular studies. Furthermore, I will present a general shape-controlled deterministic nanowire assembly method to produce large-scale arrays of devices with well-defined geometry and position. Then, I will present the design of a general method to fabricate these nanowire structures into free-standing 3D probes. I will show that free-standing nanowire bioprobes can be manipulated to target specific cells and record stable intracellular action potentials. I will demonstrate simultaneous measurements from the same cell using both kinked nanowire and patch-clamp probes. Moreover, I will discuss two strategies of multiplexed recording using free-standing probes. Finally, I will report localized stimulation on single cells enabled by the unique properties of p-n kinked nanowires. I will show with simulation and electrical characterization that in reverse bias, localized electric field generated around the nanoscale p-n junction should exceed the threshold for opening voltage-gated sodium channels. Moreover, I will present measurements of localized cell stimulation using p-n nanowire free-standing probes. Together with the capability of stable intracellular recording, these results complete the two-way communication between semiconductor nanowire electronics and biological systems at a natural nanoscale, which can open up new directions in the fields ranging from cellular electrophysiology, brain activity mapping to brain-machine interface.<br>Chemistry and Chemical Biology
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Kim, Jungyup. "Effective germanium surface preparation methods for nanoelectronic applications /." May be available electronically:, 2007. http://proquest.umi.com/login?COPT=REJTPTU1MTUmSU5UPTAmVkVSPTI=&clientId=12498.

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Books on the topic "Nanoelectronic"

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Madkour, Loutfy H. Nanoelectronic Materials. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-21621-4.

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Jha, Niraj K., and Deming Chen, eds. Nanoelectronic Circuit Design. New York, NY: Springer New York, 2011. http://dx.doi.org/10.1007/978-1-4419-7609-3.

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Chen, An, James Hutchby, Victor Zhirnov, and George Bourianoff, eds. Emerging Nanoelectronic Devices. Chichester, United Kingdom: John Wiley & Sons Ltd, 2014. http://dx.doi.org/10.1002/9781118958254.

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Evtukh, Anatoliy, Hans Hartnagel, Oktay Yilmazoglu, Hidenori Mimura, and Dimitris Pavlidis. Vacuum Nanoelectronic Devices. Chichester, UK: John Wiley & Sons, Ltd, 2015. http://dx.doi.org/10.1002/9781119037989.

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Jha, Niraj K., and Deming Chen. Nanoelectronic circuit design. New York: Springer, 2011.

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Jha, Niraj K., and Deming Chen. Nanoelectronic circuit design. New York: Springer, 2011.

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Sarkar, Angsuman, and Arpan Deyasi. Low-Dimensional Nanoelectronic Devices. Boca Raton: Apple Academic Press, 2022. http://dx.doi.org/10.1201/9781003277378.

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Labbé, Christophe, Subhananda Chakrabarti, Gargi Raina, and B. Bindu, eds. Nanoelectronic Materials and Devices. Singapore: Springer Singapore, 2018. http://dx.doi.org/10.1007/978-981-10-7191-1.

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ter Maten, E. Jan W., Hans-Georg Brachtendorf, Roland Pulch, Wim Schoenmaker, and Herbert De Gersem, eds. Nanoelectronic Coupled Problems Solutions. Cham: Springer International Publishing, 2019. http://dx.doi.org/10.1007/978-3-030-30726-4.

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Joodaki, Mojtaba. Selected Advances in Nanoelectronic Devices. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-31350-9.

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Book chapters on the topic "Nanoelectronic"

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Raushan, Mohd Adil, Naushad Alam, and Mohd Jawaid Siddiqui. "Emerging Nanoelectronic Devices." In Nanoelectronic Devices for Hardware and Software Security, 1–32. Boca Raton: CRC Press, 2021. http://dx.doi.org/10.1201/9781003126645-1.

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Fossum, J. G. "Teaching Nanoelectronic Devices." In Microelectronics Education, 117. Dordrecht: Springer Netherlands, 2004. http://dx.doi.org/10.1007/978-1-4020-2651-5_20.

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Oates, Anthony S., and K. P. Cheung. "Reliability of Nanoelectronic Devices." In Nanoelectronics, 317–30. Weinheim, Germany: Wiley-VCH Verlag GmbH & Co. KGaA, 2017. http://dx.doi.org/10.1002/9783527800728.ch13.

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Hutchby, James. "The Nanoelectronics Roadmap." In Emerging Nanoelectronic Devices, 1–14. Chichester, United Kingdom: John Wiley & Sons Ltd, 2014. http://dx.doi.org/10.1002/9781118958254.ch01.

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Chen, An, James Hutchby, Victor V. Zhirnov, and George Bourianoff. "Outlook for Nanoelectronic Devices." In Emerging Nanoelectronic Devices, 511–28. Chichester, United Kingdom: John Wiley & Sons Ltd, 2014. http://dx.doi.org/10.1002/9781118958254.ch26.

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Stanisavljevic, Milos, Alexandre Schmid, and Yusuf Leblebici. "Reliability of Nanoelectronic VLSI." In Advanced Circuits for Emerging Technologies, 463–81. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2012. http://dx.doi.org/10.1002/9781118181508.ch18.

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Kelly, M. J. "Manufacturability and Nanoelectronic Performance." In Future Trends in Microelectronics, 133–38. Hoboken, NJ, USA: John Wiley & Sons, Inc., 2013. http://dx.doi.org/10.1002/9781118678107.ch10.

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Chen, Deming, and Niraj K. Jha. "Introduction to Nanotechnology." In Nanoelectronic Circuit Design, 1–22. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7609-3_1.

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Mohanram, Kartik, and Xuebei Yang. "Graphene Transistors and Circuits." In Nanoelectronic Circuit Design, 349–76. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7609-3_10.

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Koo, Kyung-Hoae, and Krishna C. Saraswat. "Study of Performances of Low-k Cu, CNTs, and Optical Interconnects." In Nanoelectronic Circuit Design, 377–407. New York, NY: Springer New York, 2010. http://dx.doi.org/10.1007/978-1-4419-7609-3_11.

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Conference papers on the topic "Nanoelectronic"

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Skorek, Adam W., Anna Gryko-Nikitin, and Joanicjusz Nazarko. "Genetic Algorithm for Nanoscale Electro-Thermal Optimization." In ASME 2007 InterPACK Conference collocated with the ASME/JSME 2007 Thermal Engineering Heat Transfer Summer Conference. ASMEDC, 2007. http://dx.doi.org/10.1115/ipack2007-33827.

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Abstract:
In this paper, we are presenting a genetic algorithm adopted for electro-thermal optimization in nanoelectronics devices and systems. The model of nanoelectronic system is simplified. Each heat source will be approximated by a specific function. The presented optimization strategy is designated for any system containing a number N of nanoelectronic elements. Optimization for the overall structure of the system will be performed in conformity with the temperature minimization criteria in the chosen areas of the system. Regarding others non unexpected modifications of the optimization algorithm, we are using a modified complex objective function.
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"Nanoelectronic Devices II." In 2006 64th Device Research Conference. IEEE, 2006. http://dx.doi.org/10.1109/drc.2006.305076.

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"Session: Nanoelectronic devices." In 2014 IEEE 29th International Conference on Microelectronics (MIEL). IEEE, 2014. http://dx.doi.org/10.1109/miel.2014.6842093.

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Hagouel, P. I., and I. G. Karafyllidis. "Nanoelectronic graphene devices." In 2017 IEEE 30th International Conference on Microelectronics (MIEL). IEEE, 2017. http://dx.doi.org/10.1109/miel.2017.8190069.

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Yilmazoglu, O. "THz technology with nanoelectronic and vacuum nanoelectronic devices, a tutorial." In 2017 30th International Vacuum Nanoelectronics Conference (IVNC). IEEE, 2017. http://dx.doi.org/10.1109/ivnc.2017.8051529.

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Takaura, Norikatsu, and Dirk Wouters. "Solid-State and Nanoelectronic Devices - Phase Change Memory and New Approaches for Nanoelectronics." In 2007 IEEE International Electron Devices Meeting. IEEE, 2007. http://dx.doi.org/10.1109/iedm.2007.4418929.

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Wang, George T., Keshab R. Sapkota, Barbara A. Kazanowska, A. Alec Talin, Francois Leonard, Brendan P. Gunning, and Kevin S. Jones. "GaN vacuum nanoelectronic devices." In Low-Dimensional Materials and Devices 2020, edited by Nobuhiko P. Kobayashi, A. Alec Talin, Albert V. Davydov, and M. Saif Islam. SPIE, 2020. http://dx.doi.org/10.1117/12.2570577.

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NOVIK, E. G., I. V. SHEREMET, S. S. IVASHKEVICH, and I. I. ABRAMOV. "NANOELECTRONIC DEVICE SIMULATOR NANODEV." In Reviews and Short Notes to Nanomeeting '97. WORLD SCIENTIFIC, 1997. http://dx.doi.org/10.1142/9789814503938_0069.

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Wang, George T., Keshab R. Sapkota, A. Alec T. Talin, Francois Leonard, Gyorgy Vizkelethy, and Brendan P. Gunning. "GaN vacuum nanoelectronic devices." In Low-Dimensional Materials and Devices 2022, edited by Nobuhiko P. Kobayashi, A. Alec Talin, Albert V. Davydov, and M. Saif Islam. SPIE, 2022. http://dx.doi.org/10.1117/12.2638041.

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Aldridge, J. S., Andrew N. Cleland, R. Knobel, D. R. Schmidt, and C. S. Yung. "Nanoelectronic and nanomechanical systems." In International Symposium on Microelectronics and MEMS, edited by Neil W. Bergmann, Derek Abbott, Alex Hariz, and Vijay K. Varadan. SPIE, 2001. http://dx.doi.org/10.1117/12.449143.

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Reports on the topic "Nanoelectronic"

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Liu, Jie, and Mark W. Grinstaff. DNA for the Assembly of Nanoelectronic Devices Biotechnology and Nanoelectronics. Fort Belvoir, VA: Defense Technical Information Center, April 2005. http://dx.doi.org/10.21236/ada433496.

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Peatman, William C. Nanoelectronic Modeling Software Development. Fort Belvoir, VA: Defense Technical Information Center, March 1998. http://dx.doi.org/10.21236/ada340531.

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Rodriguez, Rene, Joshua Pak, Andrew Holland, Alan Hunt, Thomas Bitterwolf, You Qiang, Leah Bergman, Christine Berven, Alex Punnoose, and Dmitri Tenne. Incorporation of Novel Nanostructured Materials into Solar Cells and Nanoelectronic Devices. Office of Scientific and Technical Information (OSTI), November 2011. http://dx.doi.org/10.2172/1029119.

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Brinker, C. Jeffrey, Darren Robert Dunphy, Carlee E. Ashley, Hongyou Fan, DeAnna Lopez, Regina Lynn Simpson, David Robert Tallant, et al. Cell-directed assembly on an integrated nanoelectronic/nanophotonic device for probing cellular responses on the nanoscale. Office of Scientific and Technical Information (OSTI), January 2006. http://dx.doi.org/10.2172/883480.

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Ham, Donhee, Xiaofeng Li, and William Andress. Nanoelectronic Initiative - GHz & THz Amplifier and Oscillator Circuits With ID Nanoscale Devices for Multispectral Heterodyning Detector Arrays. Fort Belvoir, VA: Defense Technical Information Center, October 2009. http://dx.doi.org/10.21236/ada510610.

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Lawrence R. Sita. Ferrocene-Based Nanoelectronics. Office of Scientific and Technical Information (OSTI), February 2006. http://dx.doi.org/10.2172/876179.

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Pan, Wei, Taisuke Ohta, Laura Butler Biedermann, Carlos Gutierrez, C. M. Nolen, Stephen Wayne Howell, Thomas Edwin Beechem Iii, Kevin F. McCarty, and Anthony Joseph, III Ross. Enabling graphene nanoelectronics. Office of Scientific and Technical Information (OSTI), September 2011. http://dx.doi.org/10.2172/1029775.

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Kiv, A., V. Soloviev, and Yu Shunin. Economic problems of nanoelectronics. Брама-Україна, May 2014. http://dx.doi.org/10.31812/0564/1281.

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Knight, Stephen, Joaquin V. Martinez de Pinillos, and Michele Buckley. Semiconductor microelectronics and nanoelectronics programs. Gaithersburg, MD: National Institute of Standards and Technology, 2003. http://dx.doi.org/10.6028/nist.ir.7010.

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Knight, Stephen, Joaquin V. Martinez de Pinillos, and Michele Buckley. Semiconductor microelectronics and nanoelectronics programs. Gaithersburg, MD: National Institute of Standards and Technology, 2004. http://dx.doi.org/10.6028/nist.ir.7121.

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