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Journal articles on the topic 'NAND SSD'

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Author: Grafiati

Published: 6 September 2023

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1

Hong, Duwon, Keonsoo Ha, Minseok Ko, Myoungjun Chun, Yoona Kim, Sungjin Lee, and Jihong Kim. "Reparo: A Fast RAID Recovery Scheme for Ultra-large SSDs." ACM Transactions on Storage 17, no. 3 (August 31, 2021): 1–24. http://dx.doi.org/10.1145/3450977.

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A recent ultra-large SSD (e.g., a 32-TB SSD) provides many benefits in building cost-efficient enterprise storage systems. Owing to its large capacity, however, when such SSDs fail in a RAID storage system, a long rebuild overhead is inevitable for RAID reconstruction that requires a huge amount of data copies among SSDs. Motivated by modern SSD failure characteristics, we propose a new recovery scheme, called reparo , for a RAID storage system with ultra-large SSDs. Unlike existing RAID recovery schemes, reparo repairs a failed SSD at the NAND die granularity without replacing it with a new SSD, thus avoiding most of the inter-SSD data copies during a RAID recovery step. When a NAND die of an SSD fails, reparo exploits a multi-core processor of the SSD controller in identifying failed LBAs from the failed NAND die and recovering data from the failed LBAs. Furthermore, reparo ensures no negative post-recovery impact on the performance and lifetime of the repaired SSD. Experimental results using 32-TB enterprise SSDs show that reparo can recover from a NAND die failure about 57 times faster than the existing rebuild method while little degradation on the SSD performance and lifetime is observed after recovery.

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2

Hung, Ji Jun, Kai Bu, Zhao Lin Sun, Jie Tao Diao, and Jian Bin Liu. "PCI Express-Based NVMe Solid State Disk." Applied Mechanics and Materials 464 (November 2013): 365–68. http://dx.doi.org/10.4028/www.scientific.net/amm.464.365.

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This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

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3

Kim, Jiho, Myoungsoo Jung, and John Kim. "Decoupled SSD: Reducing Data Movement on NAND-Based Flash SSD." IEEE Computer Architecture Letters 20, no. 2 (July 1, 2021): 150–53. http://dx.doi.org/10.1109/lca.2021.3118688.

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4

Gao, Congming, Min Ye, Chun Jason Xue, Youtao Zhang, Liang Shi, Jiwu Shu, and Jun Yang. "Reprogramming 3D TLC Flash Memory based Solid State Drives." ACM Transactions on Storage 18, no. 1 (February 28, 2022): 1–33. http://dx.doi.org/10.1145/3487064.

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NAND flash memory-based SSDs have been widely adopted. The scaling of SSD has evolved from plannar (2D) to 3D stacking. For reliability and other reasons, the technology node in 3D NAND SSD is larger than in 2D, but data density can be increased via increasing bit-per-cell. In this work, we develop a novel reprogramming scheme for TLCs in 3D NAND SSD, such that a cell can be programmed and reprogrammed several times before it is erased. Such reprogramming can improve the endurance of a cell and the speed of programming, and increase the amount of bits written in a cell per program/erase cycle, i.e., effective capacity. Our work is the first to perform a real 3D NAND SSD test to validate the feasibility of the reprogram operation. From the collected data, we derive the restrictions of performing reprogramming due to reliability challenges. Furthermore, a reprogrammable SSD (ReSSD) is designed to structure reprogram operations. ReSSD is evaluated in a case study in RAID 5 system (RSS-RAID). Experimental results show that RSS-RAID can improve the endurance by 35.7%, boost write performance by 15.9%, and increase effective capacity by 7.71%, with negligible overhead compared with conventional 3D SSD-based RAID 5 system.

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5

Yang, Yuan Hua, Xian Bin Xu, Shui Bing He, Fang Zhen, and Yu Ping Zhang. "WLVT: A Static Wear-Leveling Algorithm with Variable Threshold." Advanced Materials Research 756-759 (September 2013): 3131–35. http://dx.doi.org/10.4028/www.scientific.net/amr.756-759.3131.

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NAND flash memory has been successfully employed in storage system due to its advantages such as performance, resistance, and capacity. NAND flash memory based solid state disk (SSD) has started to replace disk in numerous environments. However, the poor endurance offered by these SSDs continues to be their key shortcoming. To improve SSD endurance, we propose a static wear-leveling algorithm with variable threshold (WLVT). In contrast with traditional algorithm with fixed threshold, WLVT adjusts the value of threshold, so that each block can simultaneously reach the erasure times that the manufacturer gives when life of SSD is over. Therefore, available erasure time of each block will be fully utilized when SSD fails. Experimental results show that the endurance of the SSD is significantly improved.

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6

Liu, Weihua, Fei Wu, Xiang Chen, Meng Zhang, Yu Wang, Xiangfeng Lu, and Changsheng Xie. "Characterization Summary of Performance, Reliability, and Threshold Voltage Distribution of 3D Charge-Trap NAND Flash Memory." ACM Transactions on Storage 18, no. 2 (May 31, 2022): 1–25. http://dx.doi.org/10.1145/3491230.

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Solid-state drive (SSD) gradually dominates in the high-performance storage scenarios. Three-dimension (3D) NAND flash memory owning high-storage capacity is becoming a mainstream storage component of SSD. However, the interferences of the new 3D charge-trap (CT) NAND flash are getting unprecedentedly complicated, yielding to many problems regarding reliability and performance. Alleviating these problems needs to understand the characteristics of 3D CT NAND flash memory deeply. To facilitate such understanding, in this article, we delve into characterizing the performance, reliability, and threshold voltage ( V th ) distribution of 3D CT NAND flash memory. We make a summary of these characteristics with multiple interferences and variations and give several new insights and a characterization methodology. Especially, we characterize the skewed ( V th ) distribution, ( V th ) shift laws, and the exclusive layer variation in 3D NAND flash memory. The characterization is the backbone of designing more reliable and efficient flash-based storage solutions.

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7

Bu, Kai, Hai Jun Liu, Hui Xu, and Zhao Lin Sun. "Lifetime-Aware Capacity Dynamic Adjusting for Solid State Disk." Applied Mechanics and Materials 513-517 (February 2014): 3630–33. http://dx.doi.org/10.4028/www.scientific.net/amm.513-517.3630.

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In this paper, we analyzed the endurance of Nand Flash memory and then proposed a level adjusting scheme to use the MLC Flash dynamically to storage different amount of data levels through the entire lifetime. The result shows that the MLC SSD adopting this method could be totally written 4.8X more data than conventional MLC SSD and 16.5% more than SLC SSD.

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8

Sassani (Sarrafpour), Bahman A., Mohammed Alkorbi, Noreen Jamil, M. Asif Naeem, and Farhaan Mirza. "Evaluating Encryption Algorithms for Sensitive Data Using Different Storage Devices." Scientific Programming 2020 (May 31, 2020): 1–9. http://dx.doi.org/10.1155/2020/6132312.

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Sensitive data need to be protected from being stolen and read by unauthorized persons regardless of whether the data are stored in hard drives, flash memory, laptops, desktops, and other storage devices. In an enterprise environment where sensitive data is stored on storage devices, such as financial or military data, encryption is used in the storage device to ensure data confidentiality. Nowadays, the SSD-based NAND storage devices are favored over HDD and SSHD to store data because they offer increased performance and reduced access latency to the client. In this paper, the performance of different symmetric encryption algorithms is evaluated on HDD, SSHD, and SSD-based NAND MLC flash memory using two different storage encryption software. Based on the experiments we carried out, Advanced Encryption Standard (AES) algorithm on HDD outperforms Serpent and Twofish algorithms in terms of random read speed and write speed (both sequentially and randomly), whereas Twofish algorithm is slightly faster than AES in sequential reading on SSHD and SSD-based NAND MLC flash memory. By conducting full range of evaluative tests across HDD, SSHD, and SSD, our experimental results can give better idea for the storage consumers to determine which kind of storage device and encryption algorithm is suitable for their purposes. This will give them an opportunity to continuously achieve the best performance of the storage device and secure their sensitive data.

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9

No, Jaechun, Sung-Soon Park, and Cheol-Su Lim. "ReHypar: A Recursive Hybrid Chunk Partitioning Method Using NAND-Flash Memory SSD." Scientific World Journal 2014 (2014): 1–9. http://dx.doi.org/10.1155/2014/658161.

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Due to the rapid development of flash memory, SSD is considered to be the replacement of HDD in the storage market. Although SSD retains several promising characteristics, such as high random I/O performance and nonvolatility, its high expense per capacity is the main obstacle in replacing HDD in all storage solutions. An alternative is to provide a hybrid structure where a small portion of SSD address space is combined with the much larger HDD address space. In such a structure, maximizing the space utilization of SSD in a cost-effective way is extremely important to generate high I/O performance. We developed ReHypar (recursive hybrid chunk partitioning) that enables improving the space utilization of SSD in the hybrid structure. The first objective of ReHypar is to mitigate the fragmentation overhead of SSD address space, by reusing the remaining free space of I/O units as much as possible. Furthermore, ReHypar allows defining several, logical data sections in SSD address space, with each of those sections being configured with the different I/O unit. We integrated ReHypar with ext2 and ext4 and evaluated it using two public benchmarks including IOzone and Postmark.

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10

Et.al, Ms Hepisuthar. "Comparative Analysis Study on SSD, HDD, and SSHD." Turkish Journal of Computer and Mathematics Education (TURCOMAT) 12, no. 3 (April 10, 2021): 3635–41. http://dx.doi.org/10.17762/turcomat.v12i3.1644.

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In the Current Century, permeant storage devices and methods of storing data changed from traditional HDD to SDD. In this document, we discuss the merge of HDD and SSD. The Abbreviation of SSHD is called the solid-state hybrid disk. A mixture of both secondary devices to enhance the performance of the system. Inside the SSD, data movement events occur without any user input. Recent research has suggested that SSD has only the Replacement of secondary storage. HDD is also good in life span with longer life. It’s more reliable for long time data contained in this. HDD storage has typical magnetic fields for store data. SSD contains NAND flash memory to write the data in the drive. Based on the method and material of storing different. HDD and SSD feature well to upgrade with technology in Computer filed. For enhancing computing speed and excellent processing SSHD good to use in computer.Ratio increase of SSHD usage in current laptop and in computer system.

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11

Choi, Gyu Sang, Ingyu Lee, Mankyu Sung, and Choongjae Im. "A hybrid SSD with PRAM and NAND Flash memory." Microprocessors and Microsystems 36, no. 3 (May 2012): 257–66. http://dx.doi.org/10.1016/j.micpro.2011.11.001.

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12

Ye, Xin, Zhengjun Zhai, and Xiaochang Li. "ZDC: A Zone Data Compression Method for Solid State Drive Based Flash Memory." Symmetry 12, no. 4 (April 15, 2020): 623. http://dx.doi.org/10.3390/sym12040623.

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Solid-state drive (SSD) with flash memory as the storage medium are being widely used in various data storage systems. SSD data compression means that data is compressed before it is written to Not-And (NAND) Flash. Data compression can reduce the amount of data written in NAND Flash and improve the performance and reliability of SSDs. At present, the main problem facing data compression of SSD is how to improve the efficiency of data compression and decompression. In order to improve the performance of data compression and decompression, this study proposes a method of SSD data deduplication based on zone division. First, this study divides the storage space of the SSD into zones and divides them into one hot zone and multiple cold zones according to the different erasing frequency. Second, the data in each zone is divided into hot data and cold data according to the number of erasures. At the same time, the address mapping table in the hot zone is loaded into the cache. Finally, when there is a write or read request, the SSD will selectively compress or decompress the data according to the type of different zones. Through simulation tests, the correctness and effectiveness of this study are verified. The research results show that the data compression rate of this research result can reach 70–95%. Compared with SSD without data compression, write amplification is reduced by 5 to 30%, and write latency is reduced by 5 to 25%. The research results have certain reference value for improving the performance and reliability of SSD.

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13

Deguchi, Yoshiaki, Toshiki Nakamura, Atsuna Hayakawa, and Ken Takeuchi. "3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition." IEEE Journal of Solid-State Circuits 54, no. 6 (June 2019): 1800–1811. http://dx.doi.org/10.1109/jssc.2019.2900866.

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14

Liu, Chao, Nan Li, and Xin Xu. "Research and Implementation of SSD Lifespan Protection Mechanism." Applied Mechanics and Materials 568-570 (June 2014): 1186–90. http://dx.doi.org/10.4028/www.scientific.net/amm.568-570.1186.

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With the continuous development of SSD, It becomes the commodity requirements of memory storage users especially in consumer application. NAND Flash lifespan limitation is the most concerns of every user in relation to the drive’s reliability. This paper explains three factors which embark from the basic principle effect of SSD lifespan and induced the reliability strategies/the method of SSD lifespan prediction during the SSD design and usage period. We have designed a SSD`s lifespan management software which predict and manage the SSD lifespan. It will enhance the safety of SSD usage.SSD lifespan mechanism analyzes how actively you use your solid-state drive and uses a special algorithm to calculate its estimated lifetime. Of course, the date of the lifetime expiration is corrected depending on how intensively you keep using your drive.

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15

Chang, Jieh-Ren, You-Shyang Chen, Chien-Ku Lin, and Ming-Fu Cheng. "Advanced Data Mining of SSD Quality Based on FP-Growth Data Analysis." Applied Sciences 11, no. 4 (February 14, 2021): 1715. http://dx.doi.org/10.3390/app11041715.

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Storage devices in the computer industry have gradually transformed from the hard disk drive (HDD) to the solid-state drive (SSD), of which the key component is error correction in not-and (NAND) flash memory. While NAND flash memory is under development, it is still limited by the “program and erase” cycle (PE cycle). Therefore, the improvement of quality and the formulation of customer service strategy are topics worthy of discussion at this stage. This study is based on computer company A as the research object and collects more than 8000 items of SSD error data of its customers, which are then calculated with data mining and frequent pattern growth (FP-Growth) of the association rule algorithm to identify the association rule of errors by setting the minimum support degree of 90 and the minimum trust degree of 10 as the threshold. According to the rules, three improvement strategies of production control are suggested: (1) use of the association rule to speed up the judgment of the SSD error condition by customer service personnel, (2) a quality strategy, and (3) a customer service strategy.

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16

Bu, Kai, Wei Yi, Hui Xu, Qi You Xie, and Jian Bin Liu. "A SSD-Aware Dynamic Stripe Method for High Reliable RAID." Applied Mechanics and Materials 380-384 (August 2013): 3421–24. http://dx.doi.org/10.4028/www.scientific.net/amm.380-384.3421.

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NAND Flash-based SSD has gained prevalence in enterprise and embedded system as storage device because its high I/O performance, low-power consumption, and Anti-vibration characteristics. RAID consisting of SSD can achieve higher performance. However, it brings new problems such as parity disks suffering from premature aging, data disk aging simultaneously. This paper based on the variation of SSDs reliability, design a new RAID-5 architecture with dynamic stripe length. It can effectively reduce the disk space overhead and improve the safety performance of the RAID.

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17

Chou, Wen Kuang, Tian Ming Yang, Ping Huang, and Hai Tao Wu. "Extending the lifetime of NAND flash-based SSD through compacted write." International Journal of Embedded Systems 13, no. 2 (2020): 129. http://dx.doi.org/10.1504/ijes.2020.10029449.

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18

Wu, Hai Tao, Tian Ming Yang, Ping Huang, and Wen Kuang Chou. "Extending the lifetime of NAND flash-based SSD through compacted write." International Journal of Embedded Systems 13, no. 2 (2020): 129. http://dx.doi.org/10.1504/ijes.2020.108859.

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19

Sun, Chao, Tomoko Ogura Iwasaki, Takahiro Onagi, Koh Johguchi, and Ken Takeuchi. "Cost, Capacity, and Performance Analyses for Hybrid SCM/NAND Flash SSD." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 8 (August 2014): 2360–69. http://dx.doi.org/10.1109/tcsi.2014.2309780.

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20

Wu, Guanying, Ping Huang, and Xubin He. "Reducing SSD access latency via NAND flash program and erase suspension." Journal of Systems Architecture 60, no. 4 (April 2014): 345–56. http://dx.doi.org/10.1016/j.sysarc.2013.12.002.

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21

Shin, Ilhoon. "Early Dirty Buffer Flush with Second Chance for SSDs." Micromachines 14, no. 4 (March 31, 2023): 796. http://dx.doi.org/10.3390/mi14040796.

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As high-performance server-based applications become more prevalent, there is a growing demand for high-performance storage solutions. In response, SSDs that use NAND flash memory as storage media are quickly replacing hard disks in the high-performance storage market. One way to improve SSD performance is to use an internal large-capacity memory as a buffer cache for NAND. Previous studies have shown that early flushing, which ensures sufficient clean buffers by flushing dirty buffers to NAND in advance when the ratio of dirty buffers exceeds a threshold, significantly reduces the average response time of I/O requests. However, the early flush can also have a negative side effect, namely an increase in NAND write operations. To address this problem, this study proposes a selective early flush policy. This policy evaluates the likelihood of a candidate dirty buffer being rewritten upon the early flush, and delays flushing if the candidate has a high rewrite likelihood. Through this selective early flush, the proposed policy reduces NAND write operations by up to 18.0% compared to the existing early flush policy in the mixed trace. Additionally, the response time of I/O requests is also improved in most of the considered configurations.

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22

No, Jaechun. "I/O Optimizations for Hybrid File System Integrated with NAND-Flash SSD." Advanced Science Letters 14, no. 1 (July 1, 2012): 413–18. http://dx.doi.org/10.1166/asl.2012.4095.

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23

Wang, Yufei, Xiaoshe Dong, Xingjun Zhang, and Longxiang Wang. "Measurement and Analysis of SSD Reliability Data Based on Accelerated Endurance Test." Electronics 8, no. 11 (November 16, 2019): 1357. http://dx.doi.org/10.3390/electronics8111357.

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In recent years, NAND Flash-based solid-state drives (SSDs) have become more widely used in data centers and consumer markets. Data centers generally choose to provide high-quality storage services by deploying a large number of SSDs, but there are no effective preventive measures to reduce the impact of SSD failures currently. Some existing studies have analyzed the relevant factors related to SSD failures from different angles, but the characteristics of reliability changes exhibited by SSD throughout the life cycle have not been explored in depth. On the other hand, although the 3D manufacturing process has increased the storage density of the SSD, the mutual influence between the flash units has also increased, resulting in severe degradation of the performance and lifetime of the SSD. Therefore, in order to fully understand the reliability varying process of SSD throughout the life cycle, we first designed an SSD lifetime endurance test method, then conducted the endurance test and collected the reliability data for the entire life cycle of the 3D TLC SSD in the laboratory environment with reference to the JEDEC standard. Through the analysis of experimental data and its statistical correlation, it is found that SSD will produce a large number of uncorrectable errors before reaching the endurance limit, and there will be a phenomenon of continuous high operating temperature, as well as showing some intrinsic relationships about SSD reliability data. The findings in this paper are valuable for identifying whether an SSD is going to fail.

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24

Kim, Jaeho, and Jung Kyu Park. "Building Reliable Massive Capacity SSDs through a Flash Aware RAID-Like Protection." Applied Sciences 10, no. 24 (December 21, 2020): 9149. http://dx.doi.org/10.3390/app10249149.

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The demand for mass storage devices has become an inevitable consequence of the explosive increase in data volume. The three-dimensional (3D) vertical NAND (V-NAND) and quad-level cell (QLC) technologies rapidly accelerate the capacity increase of flash memory based storage system, such as SSDs (Solid State Drives). Massive capacity SSDs adopt dozens or hundreds of flash memory chips in order to implement large capacity storage. However, employing such a large number of flash chips increases the error rate in SSDs. A RAID-like technique inside an SSD has been used in a variety of commercial products, along with various studies, in order to protect user data. With the advent of new types of massive storage devices, studies on the design of RAID-like protection techniques for such huge capacity SSDs are important and essential. In this paper, we propose a massive SSD-Aware Parity Logging (mSAPL) scheme that protects against n-failures at the same time in a stripe, where n is protection strength that is specified by the user. The proposed technique allows for us to choose the strength of protection for user data. We implemented mSAPL on a trace-based simulator and evaluated it with real-world I/O workload traces. In addition, we quantitatively analyze the error rates of a flash based SSD for different RAID-like configurations with analytic models. We show that mSAPL outperforms the state-of-the-art RAID-like technique in the performance and reliability.

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25

Takeuchi, K. "(Invited) Storage Class Memory and NAND Flash Memory Hybrid Solid-State Drives (SSD)." ECS Transactions 58, no. 5 (August 31, 2013): 3–8. http://dx.doi.org/10.1149/05805.0003ecst.

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26

TAKISHITA, Hirofumi, Shuhei TANAKAMARU, Sheyang NING, and Ken TAKEUCHI. "Variation of SCM/NAND Flash Hybrid SSD Performance, Reliability and Cost by Using Different SSD Configurations and Error Correction Strengths." IEICE Transactions on Electronics E99.C, no. 4 (2016): 444–51. http://dx.doi.org/10.1587/transele.e99.c.444.

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27

Ae, Jin, and Youpyo Hong. "Efficient Garbage Collection Algorithm for Low Latency SSD." Electronics 11, no. 7 (March 30, 2022): 1084. http://dx.doi.org/10.3390/electronics11071084.

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Solid-state drives (SSDs) are rapidly replacing hard disk drives (HDDs) in many applications owing to their numerous advantages such as higher speed, low power consumption, and small size. NAND flash memories, the memory devices used for SSDs, require garbage collection (GC) operations to reclaim wasted storage space due to obsolete data. The GC is the major source of performance degradation because it greatly increases the latency for SSDs. The latency for read or write operations is sometimes significantly long if the operations are requested by users while GC operations are in progress. Reducing the frequency of GC invocation while maintaining the storage space requirement may be an ideal solution to remedy this problem, but there is a minimal number of GC operations to reserve storage space. The other approach is to reduce the performance overhead due to GC rather than reducing GC frequency. In this paper, following the latter approach, we propose a new GC scheme that reduces GC overhead by intelligently controlling the priorities among read/write and GC operations. The experimental results show the proposed scheme consistently improve the overall latency for various workloads.

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28

Jung, Siu, Seungjin Lee, Jungwook Han, and Youngjae Kim. "Preemptive Zone Reset Design within Zoned Namespace SSD Firmware." Electronics 12, no. 4 (February 5, 2023): 798. http://dx.doi.org/10.3390/electronics12040798.

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Zoned Namespace (ZNS) SSDs address the disadvantages that come from supporting the block interface within conventional SSDs, granting more control over data management to host systems, while also relieving heavy duties from device firmware. However, with the removal of on-device garbage collection, host systems must explicitly send zone reset requests to free up storage space, which may incur multiple NAND block erase operations according to the configured zone size, resulting in increased tail latency. In this article, we propose a Preemptive Zone Reset scheduling design, which we implemented within the firmware of our ZNS SSD prototype, and compare it to an intuitive Zone Mapping Table method, which we consider as the state-of-the-art. The main idea is to service high priority foreground I/O requests while preempting block erase operations induced by zone resets. Our proposed approach, opposed to the baseline method, as much as halved tail latency for write-only workloads, and reduced read tail latency by up to 1.76 times in a mixed workload.

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Zambelli, Cristian, Lorenzo Zuolo, Luca Crippa, Rino Micheloni, and Piero Olivo. "Mitigating Self-Heating in Solid State Drives for Industrial Internet-of-Things Edge Gateways." Electronics 9, no. 7 (July 20, 2020): 1179. http://dx.doi.org/10.3390/electronics9071179.

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Data storage in the Industrial Internet-of-Things scenario presents critical aspects related to the necessity of bringing storage devices closer to the point where data are captured. Concerns on storage temperature are to be considered especially when Solid State Drives (SSD) based on 3D NAND Flash technology are part of edge gateway architectures. Indeed, self-heating effects caused by oppressive storage demands combined with harsh environmental conditions call for proper handling at multiple abstraction levels to minimize severe performance slow downs and reliability threats. In this work, with the help of a SSD co-simulation environment that is stimulated within a realistic Industrial Internet-of-Things (IIoT) workload, we explore a methodology orthogonal to performance throttling that can be applied in synergy with the operating system of the host. Results evidenced that by leveraging on the SSD micro-architectural parameters of the queuing system it is possible to reduce the Input/Output operations Per Second (IOPS) penalty due to temperature protection mechanisms with minimum effort by the system. The methodology presented in this work opens further optimization tasks and algorithmic refinements for SSD and system designers not only in the IIoT market segment, but generally in all areas where storage power consumption is a concern.

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Sayyad, R., and Sangram Redkar. "Failure Analysis and Reliability Study of NAND Flash-Based Solid State Drives." Indonesian Journal of Electrical Engineering and Computer Science 2, no. 2 (May 1, 2016): 315. http://dx.doi.org/10.11591/ijeecs.v2.i2.pp315-327.

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<p>The research focuses on conducting failure analysis and reliability study to understand and analyze the root cause of Quality, Endurance component Reliability Demonstration Test (RDT) failures and determine SSD performance capability. It addresses essential challenges in developing techniques that utilize solid-state memory technologies (with emphasis on NAND flash memory) from device, circuit, architecture, and system perspectives. These challenges include not only the performance degradation arising from the physical nature of NAND flash memory, e.g., the inability to modify data in-place read/write performance asymmetry, and slow and constrained erase functionality, but also the reliability drawbacks that limits Solid State Drives (SSDs) performance. In order to understand the nature of failures, a Fault Tree Analysis (FTA) was performed that identified the potential causes of component failures. In the course of this research, significant data gathering and analysis effort was carried out that led to a systematic evaluation of the components under consideration. </p>

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Kurinjimalar, Ramu, Selvam Manjula, M. Ramachandran, and RajKumar Sangeetha. "A Review on Solid state Drives transformer concept A new era in power supply." Electrical and Automation Engineering 2, no. 1 (March 1, 2023): 104–10. http://dx.doi.org/10.46632/eae/2/1/15.

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Solid State Drives (SSD) are single drive. The performance is greater than that produced by disks allow Their low latency and parallelism Possibilities for operations, operating system I/O Read data at speeds that break interfaces They also allow writing. In addition, their performance Characteristics in existing grading systems Reveal gaps. An SSD is more Efficiency, high activity rates and more to operate with minimum latency under demanding conditions We prove that it can. High efficiency SSDs with Future High-Performance Computing (HPC) Dramatic parallel I/O performance for systems This suggests that the method can be improved. our Instead of traditional hard drives in public laboratories Using solid-state drives, our Public perception of services How technology has had an immediate effect This article also explains. Solid State Drives (SSDs) are more popular now Dense and compact are NAND flash Due to the growth in the cost of memories widely is used.

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van Renen, Alexander, Lukas Vogel, Viktor Leis, Thomas Neumann, and Alfons Kemper. "Building blocks for persistent memory." VLDB Journal 29, no. 6 (September 23, 2020): 1223–41. http://dx.doi.org/10.1007/s00778-020-00622-9.

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AbstractI/O latency and throughput are two of the major performance bottlenecks for disk-based database systems. Persistent memory (PMem) technologies, like Intel’s Optane DC persistent memory modules, promise to bridge the gap between NAND-based flash (SSD) and DRAM, and thus eliminate the I/O bottleneck. In this paper, we provide the first comprehensive performance evaluation of PMem on real hardware in terms of bandwidth and latency. Based on the results, we develop guidelines for efficient PMem usage and four optimized low-level building blocks for PMem applications: log writing, block flushing, in-place updates, and coroutines for write latency hiding.

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Takeuchi, Ken. "Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)." IEEE Journal of Solid-State Circuits 44, no. 4 (April 2009): 1227–34. http://dx.doi.org/10.1109/jssc.2009.2014027.

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Kim, Dong-Ho, and Sun-Young Hwang. "An Efficient Wear-Leveling Algorithm for NAND Flash SSD with Multi-Channel and Multi-Way Architecture." Journal of Korea Information and Communications Society 39B, no. 7 (July 31, 2014): 425–32. http://dx.doi.org/10.7840/kics.2014.39b.7.425.

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Hatanaka, Teruyoshi, and Ken Takeuchi. "NAND Controller System With Channel Number Detection and Feedback for Power-Efficient High-Speed 3D-SSD." IEEE Journal of Solid-State Circuits 47, no. 6 (June 2012): 1460–68. http://dx.doi.org/10.1109/jssc.2012.2190187.

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Choi, Gi-Jae, Jeong-Hun Kim, and Tae-Hee Han. "BER-based Hybrid Partitioning Technique for Improving Lifetime and Write Performance of High-density NAND Flash SSD." Journal of the Institute of Electronics and Information Engineers 59, no. 12 (December 31, 2022): 48–55. http://dx.doi.org/10.5573/ieie.2022.59.12.48.

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Park, Se-Chun, You-Sung Kim, Ho-Youb Cho, Sung-Dae Choi, Mi-Sun Yoon, Tae-Yun Kim, Kun-Woo Park, Jongsun Park, and Soo-Won Kim. "Program Cache Busy Time Control Method for Reducing Peak Current Consumption of NAND Flash Memory in SSD Applications." ETRI Journal 36, no. 5 (October 1, 2014): 876–79. http://dx.doi.org/10.4218/etrij.14.0213.0537.

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Sun, Chao, Kousuke Miyaji, Koh Johguchi, and Ken Takeuchi. "A High Performance and Energy-Efficient Cold Data Eviction Algorithm for 3D-TSV Hybrid ReRAM/MLC NAND SSD." IEEE Transactions on Circuits and Systems I: Regular Papers 61, no. 2 (February 2014): 382–92. http://dx.doi.org/10.1109/tcsi.2013.2268111.

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Hatanaka, Teruyoshi, Koh Johguchi, and Ken Takeuchi. "Experimental Investigation of Program Voltage (20 V) Generation With Boost Converter for 3-D-Stacked NAND Flash SSD." IEEE Transactions on Components, Packaging and Manufacturing Technology 5, no. 2 (February 2015): 188–93. http://dx.doi.org/10.1109/tcpmt.2014.2381267.

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Ishida, Koichi, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, and Ken Takeuchi. "1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD." IEEE Journal of Solid-State Circuits 46, no. 6 (June 2011): 1478–87. http://dx.doi.org/10.1109/jssc.2011.2131810.

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Vohra, Adnan Asad, and Dr Srividya P. "Design and Implementation of Sequential Read Ahead in Zoned Namespaces for Solid State Drives." International Journal of Innovative Science and Research Technology 5, no. 5 (July 24, 2020): 1985–88. http://dx.doi.org/10.38124/ijisrt20may889.

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In the day and age of data and information, the ability to retrieve the information becomes of paramount importance. The cutting edge technology in terms of data storage is currently Solid State Devices which use NAND gates to store data. This relatively new method of storing data presents numerous avenues of research and breakthroughs. The concept of Zoned Namespaces in SSD firmware is one such major avenue of ongoing research. The objective of this paper is to understand the need for higher data accessing speeds and envisioning the advancements made possible by improving basic read and write speeds in SSD's. The goal is to allow for writing sequential data in namespaces where the data related to each other holds a granularity of a single zone. The idea is achieved by implementing sequential read ahead where the sequential data is read ahead of time by anticipating host read request to that data. This gives the host, cache hit on requested data which greatly improves performance. The pre-fetched data is cleared from cache once the data has been read or any disabling condition occurs thus not hampering normal functioning of the drive. The implementation was tested on a 8 TB form factor SSD. The results for reads were 70 MB/s for ZNS before SRA and 275 MB/s after SRA enablement. Thus a very significant increase is observed which proves that the objective was achieved.

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Miyaji, Kousuke, Shinji Noda, Teruyoshi Hatanaka, Mitsue Takahashi, Shigeki Sakai, and Ken Takeuchi. "A 1.0V power supply, 9.3GB/s write speed, Single-Cell Self-Boost program scheme for high performance ferroelectric NAND flash SSD." Solid-State Electronics 58, no. 1 (April 2011): 34–41. http://dx.doi.org/10.1016/j.sse.2010.11.028.

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Lim, Hyun Jo, Dongkun Shin, and Tae Hee Han. "Parallelism-Aware Channel Partition for Read/Write Interference Mitigation in Solid-State Drives." Electronics 11, no. 23 (December 6, 2022): 4048. http://dx.doi.org/10.3390/electronics11234048.

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The advancement of multi-level cell technology that enables storing multiple bits in a single NAND flash memory cell has increased the density and affordability of solid-state drives (SSDs). However, increased latency asymmetry between read and write (R/W) intensifies the severity of R/W interference, so reads cannot be processed for a long time owing to the extended flash memory resource occupancy of writing. Existing flash translation layer (FTL)-level mitigation techniques can allocate flash memory resources in a balanced manner taking R/W interference into account; however, due to the inefficient utilization of parallel flash memory resources, the effect on performance enhancement is restrictive. From the perspectives of the predicted access pattern and available concurrency of flash memory resources, we propose a parallelism-aware channel partition (PACP) scheme that prevents SSD performance degradation caused by R/W interference. Moreover, an additional performance improvement is achieved by reallocating interference-vulnerable page using leveraged garbage collection (GC) migration. The evaluation results showed that compared with the existing solution, PACP reduced the average read latency by 11.6% and average write latency by 6.0%, with a negligible storage overhead.

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TAKAI, Yoshiki, Mamoru FUKUCHI, Chihiro MATSUI, Reika KINOSHITA, and Ken TAKEUCHI. "Analysis on Hybrid SSD Configuration with Emerging Non-Volatile Memories Including Quadruple-Level Cell (QLC) NAND Flash Memory and Various Types of Storage Class Memories (SCMs)." IEICE Transactions on Electronics E103.C, no. 4 (April 1, 2020): 171–80. http://dx.doi.org/10.1587/transele.2019cdp0006.

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Nie, Shiqiang, Weiguo Wu, and Chi Zhang. "Data Pattern Aware Reliability Enhancement Scheme for 3D Solid-State Drives." ACM Transactions on Embedded Computing Systems 20, no. 5s (October 31, 2021): 1–20. http://dx.doi.org/10.1145/3477000.

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3D charge-trap (CT) NAND flash-based SSD has been used widely for its large capacity, low cost per bit, and high endurance. One-shot program (OSP) scheme, as a variation of incremental step pulse programming (ISPP) scheme, has been employed to program data for CT flash, whose program unit is the Word-Line (WL) instead of the page. The existing program optimization schemes either make trade-offs among program latency and reliability by adjusting the program step voltage on demand; or remap the most error-prone cell states to others by re-encoding programmed data. However, the data pattern, which represents the ratio of 1s in data values, has not been thoroughly studied. In this paper, we observe that most small files do not contain uniform 1s and 0s among these common file types (i.e., image, audio, text, executable file), leading to programming WL cells in different states unevenly. Some cell states dominate over the WL, while others are not. Based on this observation, we propose a flexible reliability enhancement scheme based on the OSP scheme. This scheme programs the cells into different states with varied , i.e., these cells in one state, whose number is the largest in one WL, are programmed with a fine-grained (namely slow write). In contrast, the minority are programmed with a coarse-grained (namely fast write). So the reliability is improved due to averaging the major enhanced cells with the minor degraded cells without program latency overhead. A series of experiments have been conducted, and the results indicate that the proposed scheme achieves 34% read performance improvement and 16% lifetime elongation on average.

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Park, Sungmin, and Sooyong Kang. "Considerations for Designing an Integrated Write Buffer Management Scheme for NAND-based Solid State Drives." Journal of Digital Contents Society 14, no. 2 (June 30, 2013): 215–22. http://dx.doi.org/10.9728/dcs.2013.14.2.215.

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47

Carles, A. B., and W. A. K. Kipngeno. "The effect of season and the introduction of rams on oestrous activity in Somali, Nandi, Merino, Karakul and New Zealand Romney Marsh ewes in Kenya." Animal Science 43, no. 3 (December 1986): 447–57. http://dx.doi.org/10.1017/s000335610000266x.

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ABSTRACTA study was made of the levels of oestrous activity of two indigenous breeds of sheep (Somali and Nandi) and three exotic breeds of sheep (Merino, Karakul and New Zealand Romney Marsh) over a period of 3 years, in an equatorial environment. Breed was the only significant source of variation for the length of the oestrous cycle (P < 0·01). The mean lengths of the oestrous cycle were 17·2 (s.d. 3·21), 17·5 (s.d. 2·24), 17·9 (s.d. 2·99), 17·5 (s.d. 2·57) and 16·5 (s.d. 3·41) days for the Somali, Nandi, Merino, Karakul and Romney Marsh breeds, respectively.The mean percentage of ewes of the different breeds showing oestrus in 20-day periods were 69·8 (s.d. 22·57), 49·9 (s.d. 18·67), 63·4 (s.d. 25·70), 79·2 (s.d. 20·30) and 33·2 (s.d. 23·50) % for the Somali, Nandi, Merino, Karakul and Romney Marsh breeds, respectively. Time-series analysis did not detect any evidence of seasonal variation in oestrous activity, although there was an indication that the Merino and Romney Marsh breeds showed a marked increase in oestrous activity following, the introduction of rams. It was concluded that the variation in level of oestrous activity was short term and random.

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Olawuyi, Odunayo Joseph, Juliet Ese Naworu, and Roseline Tolulope Feyisola. "Effect of sodium azide on Bambara groundnut (Vigna subterranean (L.) verdc.) as revealed by sodium dodecyl sulphate polyacrylamide gel electrophoresis (sds-page)." Scientia Africana 20, no. 1 (April 23, 2021): 183–94. http://dx.doi.org/10.4314/sa.v20i1.16.

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This study investigated the mutagenic effects of Sodium Azide (NaN3) on the agromorphological and protein content of eight Bambara groundnut genotypes. The seeds of six genotypes; TVSu-86, TVSu-91, TVSu-186, TVSu-235, TVSu-242, TVSu-350 were collected fromthe International Institute of Tropical Agriculture (IITA) and two landraces from Abia State and Enugu State North East, Nigeria local markets. The seeds were treated with five concentrations: 0.00%(control), 0.01%, 0.03%, 0.05% and 0.07% of NaN3 after pre-soakingfor 6hrs in distilled water and sown in pots arranged in a Complete Randomized Design with three replicates. There was reduction in germination percentage and growth characters as concentrations of NaN3 increases. Early flowering was recorded at 37 days mutated with 0.07% of NaN3 compared to control which flowered late at 42 days. NaN3 (0.07%) caused lethal effect on Abia and Enugu landraces. There was no significant (P>0.05) difference in yield traits among mutants and control. Mutant seeds significantly (P<0.05) increased protein content (19.12%) at 0.05% of NaN3 compared to control (18.5%). The number of seeds (0.99), seed yield (0.89) and pod yield (0.96) strongly correlated with seeds per pod (0.85). The SDS-PAGE revealed the presence of polypeptide bands in mutants compared to control. TVSu-235 and TVSu-350 genotypes had higher tolerance and yield traits to 0.01% concentration of NaN3, thuscould be further improved in subsequent breeding. Keywords: Bambara groundnut, Sodium azide, SDS-PAGE, polypeptide bands.

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Lai, Chun Chi, Yi Wen Lu, Hung Ju Chien, and Tzung Hua Ying. "Superior PSZ-SOD Gap-Fill Process Integration Using Ultra-Low Dispensation Amount in STI for 28 nm NAND Flash Memory and Beyond." Journal of Nanomaterials 2015 (2015): 1–7. http://dx.doi.org/10.1155/2015/910367.

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The gap-fill performance and process of perhydropolysilazane-based inorganic spin-on dielectric (PSZ-SOD) film in shallow trench isolation (STI) with the ultra-low dispensation amount of PSZ-SOD solution have been investigated in this study. A PSZ-SOD film process includes liner deposition, PSZ-SOD coating, and furnace curing. For liner deposition, hydrophilic property is required to improve the contact angle and gap-fill capability of PSZ-SOD coating. Prior to PSZ-SOD coating, the additional treatment on liner surface is beneficial for the fluidity of PSZ-SOD solution. The superior film thickness uniformity and gap-fill performance of PSZ-SOD film are achieved due to the improved fluidity of PSZ-SOD solution. Following that up, the low dispensation rate of PSZ-SOD solution leads to more PSZ-SOD filling in the trenches. After PSZ-SOD coating, high thermal curing process efficiently promotes PSZ-SOD film conversion into silicon oxide. Adequate conversion from PSZ-SOD into silicon oxide further increases the etching resistance inside the trenches. Integrating the above sequence of optimized factors, void-free gap-fill and well-controlled STI recess uniformity are achieved even when the PSZ-SOD solution dispensation volume is reduced 3 to 6 times compared with conventional condition for the 28 nm node NAND flash and beyond.

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Mareš, Petr. "History in the Service of the Story: Thoughts on Igor Lukeš's On the Edge of the Cold War." Soudobé dějiny 22, no. 3-4 (September 1, 2015): 504–23. http://dx.doi.org/10.51134/sod.2015.025.

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