Journal articles on the topic 'NAND Flash Interface'

NAND Flash Memory has replaced EEPROM and hard drives as Non-volatile. Data is stored in sequential order in NAND Flash Memory. NAND Memory is a type of flash memory widely used in mobile phones and System on Chips (SoC). The Memory controller supports an 8-bit NAND Flash interface and streaming interface towards АXI4. The data transfer between АXI4 and NAND Flash Memory is carried оut by using NAND Flash commands sequences. The AXI4 Interface enables the usage of various рrоtосоls. To improve the flash memory controller's data access speed. This project intends to design, develop, and integrate a NAND Flash memory controller using an AXI4 interface for an open POWER Processor A20 fabless SOC. The Flash Memory Controller includes Finite State Machines (FSM) and AXI4 bridge logic. Using Mentor Graphics® and Xilinx's Vivado design suite, the test results were based on behavioral simulation and synthesis

The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.

SPI NOR Flash is widely used in embedded system for its compact package and simple interface. It is suitable to medium scale data storage. Now, industry provides higher density NAND Flash with the same interface and package as SPI NOR Flash. But the erase/program circles of NAND Flash is less than that of NOR Flash. The lifetime of NAND Flash is becoming the critical issue. Wear leveling algorithms prevent NAND Flash from prematurely retiring by mapping the logical block to different physical blocks. To our knowledge, most wear leveling algorithms need several kilobytes of RAM for keeping the mapping data structures, which is costly for the resource constrained micro controller. This study first proposes a no RAM required design with presetting lifetime, and then presents an adaptive design which requires only 2 kilobytes RAM with elasticity lifetime. The proposed design can be adapted in most of embedded systems based on low cost micro controller.

This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.

Modern solid-state disks achieve high data transfer rates due to their massive internal parallelism. However, out-of-place updates for flash memory incur garbage collection costs when valid data needs to be copied during space reclamation. The root cause of this extra cost is that solid-state disks are not always able to accurately determine data lifetime and group together data that expires before the space needs to be reclaimed. Real-time systems found in autonomous vehicles, industrial control systems, and assembly-line robots store data from hundreds of sensors and often have predictable data lifetimes. These systems require guaranteed high storage bandwidth for read and write operations by mission-critical real-time tasks. In this article, we depart from the traditional block device interface to guarantee the high throughput needed to process large volumes of data. Using data lifetime information from the application layer, our proposed real-time design, called Telomere , is able to intelligently lay out data in NAND flash memory and eliminate valid page copies during garbage collection. Telomere’s real-time admission control is able to guarantee tasks their required read and write operations within their periods. Under randomly generated tasksets containing 500 tasks, Telomere achieves 30% higher throughput with a 5% storage cost compared to pre-existing techniques.

A die-stacking technology in a multi-chip package can effectively increase the capacity. However, long wire bonding for multi-chip stack, inter-symbol interference caused by large capacitive loading and I/O speed degradations due to simultaneous switching noise (SSN) and power consumption have become obstacles to optimize the internal NAND flash interface. In this paper, to overcome the inevitable challenge between larger storage capacity and higher I/O speed, we propose a new package structure with a frequency boosting interface chip (FBI-chip) for high speed and high density eStorage.

Now, the quality of higher speed and larger capacity are required to the real-time storage system. This paper designs a high-speed and large-capacity storage system which uses FPGA as the master of SOPC system controlling NAND Flash chips. This system puts forward an advanced storage structure which has several NAND Flashes with multi-buses, forming a parallel pipeline design. By using the key technologies of bad block management and the ECC algorithm, which greatly avoids the influence of the invalid block to the storage system and reduces the probability of error data as well. It can not only improve the storage bandwidth and capacity substantially, but also ensure the reliability of the storage system effectively. As a result, the storage system achieves the capacity of 1.5TB and the bandwidth of 1280MBps. Also, this system uses high-speed exchange interface to link to the external network, which achieve the real-time transmission and control of data, and make the storage system standard, universal, and scalable.

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

We studied the metal gate work function of different metal electrode and high-k dielectric combinations by monitoring the flat band voltage shift with dielectric thicknesses using capacitance–voltage measurements. We investigated the impact of different thermal treatments on the work function and linked any shift in the work function, leading to an effective work function, to the dipole formation at the metal/high-k and/or high-k/SiO2 interface. We corroborated the findings with the erase performance of metal/high-k/ONO/Si (MHONOS) capacitors that are identical to the gate stack in three-dimensional (3D) NAND flash. We demonstrate that though the work function extraction is convoluted by the dipole formation, the erase performance is not significantly affected by it.

This study focuses on the hardware architecture of a Raman scattering distributed optical fiber transducer platform, the principles of Raman scattering are analyzed, and the output 2 analog electrical signals are converted to digital signals at a 16-bit sampling rate by an Analog-to-Digital Converter (ADC). The system is implemented based on the FPGA. The integrated circuit is responsible for controlling the data acquisition process. The differential amplifier circuit, FPGA peripheral circuit, and CPU subsystem circuit, which takes ARM as the core, are separately designed. The composition of software includes a DDR2 (Double Data Rate 2) driver and central control logic. In this study, the optical fiber transducer platform has been tested. The CPU DDR2 is read/written by the test program respectively. According to the results, the program passes the read/write test. The NAND FLASH is tested. The results show that this program returns all operations successfully. The timing tests of the DDR2 interface and data latching are conducted. The results show that the read/write operations ensure that the clock and data curves are aligned. Therefore, the optical fiber transducer integrated platform designed in this study is effective.

A four-phase all-digital delay-locked loop (ADDLL) with a de-skew circuit for NAND Flash high-speed interfaces is proposed. The proposed de-skew circuit adopts a fall-edge-judgment phase adjuster and a three-stage digitally controlled delay line to align the system input clock and 0∘ output clock of the four-phase DLL over a wide frequency range, thus solving the four-phase offset caused by clock skew. A parallel-cascade configuration is proposed to solve the variable phase alignment problem caused by mode switching, thus effectively improving the phase-locked accuracy. The proposed circuit is fabricated in the 0.13 μm CMOS process with a 0.072 mm2 core area. The chip testing results show an operating frequency range from 26 MHz to 1.55 GHz and a typical alignment error of approximately 17 ps.

For improving the generality, expandability and accuracy, the general embedded intelligent monitoring system of tower crane is developed. The system can be applied to different kinds of tower cranes running at any lifting ratio, can be initialized using U disk with the information of tower crane, and fit the lifting torque curve automatically. In dangerous state, the system can sent out alarm signals with sounds and lights, and cut off power by sending signals to PLC through communication interface RS485. When electricity goes off suddenly, the system can record the real-time operating information automatically, and store them in a black box, which can be taken as the basis for confirming the accident responsibility.In recent years, tower cranes play a more and more important role in the construction of tall buildings, in other construction fields are also more widely used. For the safety of tower cranes, various monitors have been developed for monitoring the running information of crane tower [1-8]. These monitors can’t eliminate the errors caused by temperature variations automatically. The specific tower crane’s parameters such as geometric parameters, alarming parameters, lifting ratio, lifting torque should be embedded into the core program, so a monitor can only be applied to a specific type of tower crane, lack of generality and expansibility.For improving the defects of the existing monitors, a general intelligent monitoring modular system of tower crane with high precision is developed, which can initialize the system automatically, eliminate the temperature drift and creep effect of sensor, and store power-off data, which is the function of black box.Hardware design of the monitoring systemThe system uses modularized design mode. These modules include embedded motherboard module, sensor module, signal processing module, data acquisition module, power module, output control module, display and touch screen module. The hardware structure is shown in figure 1. Figure 1 Hardware structure of the monitoring systemEmbedded motherboard module is the core of the system. The motherboard uses the embedded microprocessor ARM 9 as MCU, onboard SDRAM and NAND Flash. Memory size can be chosen according to users’ needs. SDRAM is used for running procedure and cache data. NAND Flash is used to store embedded Linux operating system, applications and operating data of tower crane. Onboard clock with rechargeable batteries provides the information of year, month, day, hour, minute and second. This module provides time tag for real-time operating data. Most interfaces are taken out by the plugs on the embedded motherboard. They include I/O interface, RS232 interface, RS485 interface, USB interface, LCD interface, Audio interface, Touch Screen interface. Pull and plug structure is used between all interfaces and peripheral equipments, which not only makes the system to be aseismatic, but also makes its configuration flexible. Watch-dog circuit is designed on the embedded motherboard, which makes the system reset to normal state automatically after its crash because of interference, program fleet, or getting stuck in an infinite loop, so the system stability is improved greatly. In order to store operating data when power is down suddenly, the power-down protection circuit is designed. The saved data will be helpful to repeat the accident process later, confirm the accident responsibility, and provide the basis for structure optimization of tower crane.Sensor module is confirmed by the main parameters related to tower crane’s security, such as lifting weight, lifting torque, trolley luffing, lifting height, rotary angle and wind speed. Axle pin shear load cell is chosen to acquire lifting weight signals. Potentiometer accompanied with multi-stopper or incremental encoder is chosen to acquire trolley luffing and lifting height signals. Potentiometer accompanied with multi-stopper or absolute photoelectric encoder is chosen to acquire rotary angle signals. Photoelectric sensor is chosen to acquire wind speed signals. The output signals of these sensors can be 0~5V or 4~20mA analog signals, or digital signal from RS485 bus. The system can choose corresponding signal processing method according to the type of sensor signal, which increases the flexibility on the selection of sensors, and is helpful for the users to expand monitoring objects. If the acquired signal is analog signal, it will be processed with filtering, isolation, anti-interference processing by signal isolate module, and sent to A/D module for converting into digital signals, then transformed into RS485 signal by the communication protocol conversion device according to Modbus protocol. If the acquired signal is digital signal with RS485 interface, it can be linked to RS485 bus directly. All the acquired signals are sent to embedded motherboard for data processing through RS485 bus.The data acquisition module is linked to the data acquisition control module on embedded motherboard through RS485 interface. Under the control of program, the system inquires the sensors at regular intervals, and acquires the operating data of crane tower. Median filter technology is used to eliminate interferences from singularity signals. After analysis and processing, the data are stored in the database on ARM platform.Switch signal can be output to relay module or PLC from output control module through RS485 bus, then each actuator will be power on or power off according to demand, so the motion of tower crane will be under control.Video module is connected with motherboard through TFT interface. After being processed, real-time operating parameters are displayed on LCD. The working time, work cycle times, alarm, overweight and ultar-torque information will be stored into database automatically. For meeting the needs of different users, the video module is compatible with 5.7, 8.4 or 10.4 inches of color display.Touch screen is connected with embedded motherboard by touch screen interface, so human machine interaction is realized. Initialization, data download, alarm information inquire, parameter modification can be finished through touch screen.Speaker is linked with audio interface, thus alarm signals is human voice signal, not harsh buzz.USB interface can be linked to conventional U disk directly. Using U disk, users can upload basic parameters of tower crane, initialize system, download operating data, which provides the basis for the structural optimization and accident analysis. Software design of the monitoring systemAccording to the modular design principle, the system software is divided into grading encryption module, system update module, parameter settings module, calibration module, data acquisition and processor module, lifting parameters monitoring module, alarm query module, work statistics module.Alarm thresholds are guarantee for safety operation of the tower crane. Operating data of tower crane are the basis of service life prediction, structural optimization, accident analysis, accident responsibility confirmation. According to key field, the database is divided into different security levels for security requirements. Key fields are grade encryption with symmetrical encryption algorithm, and data keys are protected with elliptic curve encryption algorithm. The association is realized between the users’ permission and security grade of key fields, which will ensure authorized users with different grades to access the equivalent encrypted key fields. The user who meets the grade can access equivalent encrypted database and encrypted key field in the database, also can access low-grade encrypted key fields. This ensures the confidentiality and integrity of key data, and makes the system a real black box.The system is divided into operating mode and management mode in order to make the system toggle between the two states conveniently. The default state is operating mode. As long as the power is on, the monitoring system will be started by the system guide program, and monitor the operating state of the tower crane. The real-time operating data will be displayed on the display screen. At the dangerous state, warning signal will be sent to the driver through voice alarm and light alarm, and corresponding control signal will be output to execution unit to cut off relevant power for tower crane’s safety.By clicking at the mode switch button on the initial interface, the toggle can be finished between the management mode and the operating mode. Under the management mode, there are 4 grades encrypted modes, namely the system update, alarm query, parameter setting and data query. The driver only can browse relevant information. Ordinary administrator can download the alarm information for further analysis. Senior administrator can modify the alarm threshold. The highest administrator can reinitialize system to make it adapt to different types of tower crane. Only browse and download function are available in the key fields of alarm inquiry, anyone can't modify the data. The overload fields in alarm database are encrypted, only senior administrator can browse. The sensitive fields are prevented from being tampered to the great extent, which will provide the reliable basis for the structural optimization and accident analysis. The system can be initialized through the USB interface. Before initialization, type, structural parameters, alarm thresholds, control thresholds, lifting torque characteristics of tower crane should be made as Excel files and then converted to XML files by format conversion files developed specially, then the XML files are downloaded to U disk. The U disk is inserted into USB interface, then the highest administrator can initialize the system according to hints from system. After initialization, senior administrator can modify structural parameters, alarm thresholds, control thresholds by clicking on parameters setting menu. So long as users can make the corresponding excel form, the system initialization can be finished easily according to above steps and used for monitoring. This is very convenient for user.Tower crane belongs to mobile construction machinery. Over time, sensor signals may have some drift, so it is necessary to calibrate the system regularly for guaranteeing the monitoring accuracy. Considering the tower is a linear elastic structure, sensors are linear sensors,in calibration linear equation is used:y=kx+b (1)where x is sample value of sensor, y is actual value. k, b are calibration coefficients, and are calculated out by two-points method. At running mode, the relationship between x and y is:y=[(y1-y0)/(x1-x0)](x-x0)+y0 (2)After calibration, temperature drift and creep can be eliminated, so the monitoring accuracy is improved greatly.Lifting torque is the most important parameter of condition monitoring of tower crane. Comparing the real-time torque M(L) with rated torque Me(L), the movement of tower crane can be controlled under a safe status.M (L)= Q (L)×L (3)Where, Q(L)is actual lifting weight, L is trolley luffing. Me(L) = Qe(L)×L (4)Where, Q e(L) is rated lifting weight. The design values of rated lifting weight are discrete, while trolley luffing is continuous. Therefore there is a rated lifting weight in any position. According to the mechanical characteristics of tower crane, the rated lifting weight is calculated out at any point by 3 spline interpolation according to the rated lifting weight at design points.When lifting weight or lifting torque is beyond rated value, alarm signal and control signal will be sent out. The hoist motor with high, medium and low speed is controlled by the ratio of lifting weight Q and maximum lifting weight Qmax,so the hoisting speed can be controlled automatically by the lifting weight. The luffing motor with high and low speed is controlled by the ratio of lifting torque M and rated lifting torque Me. Thus the luffing speed can be controlled by the lifting torque automatically. The flow chart is shown in figure 2. Fig. 2 real-time control of lifting weight and lifting torqueWhen accidents take place, power will be off suddenly. It is vital for identifying accident liability to record the operating data at the time of power-off. If measures are not taken to save the operating data, the relevant departments is likely to shirk responsibility. In order to solve the problem, the power-off protection module is designed. The module can save the operating data within 120 seconds automatically before power is off suddenly. In this 120 seconds, data is recorded every 0.1 seconds, and stores in a 2D array with 6 rows 1200 columns in queue method. The elements of the first line are the recent time (year-month-day-hour-minute-second), the elements of the second line to sixth line are lifting weight, lifting torque, trolley luffing, lifting height and wind speed in turn. The initial values are zero, when a set of data are obtained, the elements in the first column are eliminated, the elements in the backward columns move frontwards, new elements are filled into the last column of the array, so the array always saves the operating data at the recent 120 seconds. In order to improve the real-time property of the response, and to extend the service life of the nonvolatile memory chip EEPROM-93C46, the array is cached in volatile flip SDRAM usually. So long as power-off signal produces, the array will be shift to EEPROM, at once.In order to achieve the task, the external interruption thread and the power-off monitoring thread of program is set up, the power-off monitoring thread of program is the highest priority. These two threads is idle during normal operation. When power is off, the power-off monitoring thread of program can be executed immediately. When power-off is monitored by power-off control circuit, the external interruption pins produces interrupt signal. The ARM microprocessor responds to external interrupt request, and wakes up the processing thread of external interruption, then sets synchronized events as informing state. After receiving the synchronized events, the data cached in SDRAM will be written to EEPROM in time.ConclusionThe general intelligence embedded monitoring system of tower crane, which can be applicable to various types of tower crane operating under any lifting rates, uses U disk with the information of the tower crane to finish the system initialization and fits the lifting torque curve automatically. In dangerous state, the system will give out the voice and light alarm, link with the relay or PLC by the RS485 communication interface, and cut off the power. When power is down suddenly, the instantaneous operating data can be recorded automatically, and stored in a black box, which can be taken as the proof for identifying accident responsibility. The system has been used to monitor the "JiangLu" series of tower cranes successfully, and achieved good social and economic benefits.AcknowledgementsThe authors wish to thank China Natural Science Foundation(50975289), China Postdoctoral Science Foundation(20100471229), Hunan science & technology plan, Jianglu Machinery & Electronics Co. Ltd for funding this work.Reference Leonard Bernold. Intelligent Technology for Crane Accident Prevention. Journal of Construction Engineering and Management. 1997, 9: 122~124.Gu Lichen,Lei Peng,Jia Yongfeng. Tower crane' monitor and control based on multi-sensor. Journal of Vibration, Measurement and Diagnosis. 2006, 26(SUPPL.): 174-178.Wang Ming,Zhang Guiqing,Yan Qiao,et, al. Development of a novel black box for tower crane based on an ARM-based embedded system. Proceedings of the IEEE International Conference on Automation and Logistics. 2007: 82-87.Wang Renqun, Yin Chenbo, Zhang Song, et, al. Tower Crane Safety Monitoring and Control System Based on CAN Bus. Instrument Techniques and Sensor. 2010(4): 48-51.Zheng Conghai,Li Yanming,Yang Shanhu,et, al. Intelligent Monitoring System for Tower Crane Based on BUS Architecture and Cut IEEE1451 Standard. Computer Measurement & Control. 2010, 18, (9): 1992-1995.Yang Yu,Zhenlian Zhao,Liang Chen. Research and Design of Tower Crane Condition Monitoring and Fault Diagnosis System. 2010 Proceedings of International Conference on Artificial Intelligence and Computational Intelligence. 2010: 405-408.Yu Yang, Chen Liang, Zhao Zhenlian. Research and design of tower crane condition monitoring and fault diagnosis system. International Conference on Artificial Intelligence and Computational Intelligence, 2010, 3: 405-408.Chen Baojiang, Zeng Xiaoyuan. Research on structural frame of the embedded monitoring and control system for tower crane. 2010 International Conference on Mechanic Automation and Control Engineering. 2010: 5374-5377.

Solid State Drives (SSD) are single drive. The performance is greater than that produced by disks allow Their low latency and parallelism Possibilities for operations, operating system I/O Read data at speeds that break interfaces They also allow writing. In addition, their performance Characteristics in existing grading systems Reveal gaps. An SSD is more Efficiency, high activity rates and more to operate with minimum latency under demanding conditions We prove that it can. High efficiency SSDs with Future High-Performance Computing (HPC) Dramatic parallel I/O performance for systems This suggests that the method can be improved. our Instead of traditional hard drives in public laboratories Using solid-state drives, our Public perception of services How technology has had an immediate effect This article also explains. Solid State Drives (SSDs) are more popular now Dense and compact are NAND flash Due to the growth in the cost of memories widely is used.

Silicon nitride (Si3N4) etching using CF4/O2 mixed with N2 has become very popular in 3D NAND flash structures. However, studies on Si3N4 dry etching based on optical emission spectroscopy (OES) are lacking; in particular, no study has reported the use of OES for analyzing N2-mixed CF4/O2 plasma. Thus, this study demonstrates an OES-based approach for analyzing a mixed-gas plasma for etching Si3N4 thin films. The state of each single gas plasma of CF4, O2, and N2 as well as that of mixed plasmas of heterogeneous gases CF4/O2, CF4/N2, and O2/N2 was investigated to analyze the mixed-gas plasma. Furthermore, the amount of N2 in the CF4/O2 plasma varied from 0 to 8 sccm. The relationship between the OES analysis results and the Si3N4 etch rate was subsequently established using Si3N4 film etching, and the explanation was verified through a chemical reaction modeling and surface reaction. Therefore, our study confirmed the alteration in chemical species and quantity that occurred when N2 was added to CF4/O2 plasma and the effect of the alteration on Si3N4 etch.

The ability to precisely form Si3N4 spacers is critical to the success of dynamic random-access memory and NAND (NOT AND) flash memory technology development. In this study, we investigated the mechanisms and process windows of an innovative two-step nitride (Si3N4) etch consisting of H2 plasma processing in an inductively coupled plasma chamber followed by either buffered oxide etch (BOE, a mix of NH4F and HF solution) wet clean or in situ NF3 plasma etch. We obtained layer–by-layer removal with each layer’s removal capable of more than 10 nm. We revealed that H can penetrate more than 20 nm deep into the nitride film to transform pristine Si3N4 into SiON after air exposure, which can be subsequently removed by BOE wet clean. The H2 and BOE steps do not need to run back-to-back; the modified SiON layer is stable enough to sustain elevated temperature processing and can be removed by BOE later down-the-line integration. We also demonstrated that using NF3 plasma can have highly selective etch of nitride over oxide due to the incubation time difference between these two types of films. It takes much longer time to initiate the chemical reaction for oxide compared with nitride. Critically, the role of H2 is not the key for high selectivity; instead, it provides an etch directionality and shortens the incubation time for both nitride and oxide.

Abstract This study investigates the effects of hydrogen post-treatment on 3D NAND flash memory. Hydrogen post-treatment annealing (PTA) is suggested to passivate the defects in the tunneling oxide/poly-Si interface and inside the poly-Si channel. However, excess hydrogen PTA can release hydrogen atoms from the passivated defects, which may degrade device performance. Therefore, it is important to determine the appropriate PTA condition for optimization of the device performance. Three different conditions for hydrogen PTA, namely Reference, H, and H++, are applied to observe the effects on device performance. The activation energy (Ea) of the device parameters was extracted according to the hydrogen PTA condition to analyze theeffects. The extracted Ea is about 74 meV for Reference, 53 meV for H, and 58 meV for H++conditions, with the best performance observed at the H condition. Optimal hydrogen PTAshows the best on-current (51% higher than Reference) and short-term retention (66% suppressed ΔVT than Reference) in 9X stacked 3D NAND flash memory.

AbstractBelow the 65-nm technology node, scaling of Flash memory, NAND, NOR or embedded, needs smart and heterogeneous integration of materials in the entire device structure. In addition to maintaining retention, in the order of importance, we need to continuously make functional density (bits/cm2) higher, cycling endurance longer, program/erase (P/E) voltage lower (negated by the read disturbance, multi-level possibility and noise margin), and P/E time faster (helped by inserting SRAM buffer at system interface). From both theory and experiments, we will compare the advantages and disadvantages in various material choices in view of 3D electrostatics, quantum transport and CMOS process compatibility.

Abstract Flash memory with high operation speed and stable retention performance is in great demand to meet the requirements of big data. In addition, the realisation of ultrafast flash memory with novel functions offers a means of combining heterogeneous components into a homogeneous device without considering impedance matching. This report proposes a 20 ns programme flash memory with 108 self-rectifying ratios based on a 0.65-nm-thick MoS2-channel transistor. A high-quality van der Waals heterojunction with a sharp interface is formed between the Cr/Au metal floating layer and h-BN tunnelling layer. In addition, the large rectification ratio and low ideality factor (n = 1.13) facilitate the application of the MoS2-channel flash memory as a bit-line select transistor. Finally, owing to the ultralow MoS2/h-BN heterojunction capacitance (50 fF), the memory device exhibits superior performance as a high-frequency (up to 1 MHz) sine signal rectifier. These results pave the way toward the potential utilisation of multifunctional memory devices in ultrafast two-dimensional NAND-flash applications.

AbstractThe nitride-based SONOS cell, for its excellent scalability and process simplicity, is the candidate to push the scaling roadmap for FLASH memories beyond the limit imposed on floating-gate memories by the electrostatic interference between adjacent cells. The traditional SONOS cell consists of a nitride layer (the storage element) encapsulated by two SiO2 layers which isolate the nitride layer from the Si substrate and the poly-Si gate (Poly-Si/SiO2/Si3N4/SiO2/c-Si). However, the thick tunnel oxide necessary to meet the retention requirements imposes a severe limit on the erase performance because of the erase saturation phenomenon. One possibility to guarantee both the erase and the retention performance is the replacement of the top SiO2 layer with materials of higher dielectric constant (high-k dielectric). The presence of a high-k dielectric reduces the electric field across the top dielectric, thus decreasing the unwanted parasitic electron injection from the gate during the erase operation. This will allow the cell to erase deep so to meet a basic requirement for Gigabit multilevel NAND memories. The introduction of high-k materials in the SONOS stack is unfortunately not straightforward. One problem is the Fermi-level pinning at the poly-Si/high-k interface. Another problem is the morphological changes the high-k material undergoes during the device fabrication thermal budget. These changes can modify the k-value and affect the band offset between gate and high-k material. The results may, in both cases, be the decrease of the barrier for electron injection from the gate and, as a consequence, the deterioration of the erase performance. In this paper we study the effect of gate material and of the morphological transformation associated with the high-k post deposition anneal on the erase and the retention behaviour of nitride-based cells. Two different high-k dielectrics are investigated: Al2O3 (which has already been found to be able to significantly improve the erase operation, guaranteeing at the same time excellent endurance and sufficient bake retention) and HfAlO. We show that both for Al2O3 and HfAlO a trade-off exists between erase and retention, higher PDA temperatures being beneficial for erase but detrimental for retention. We also discuss the effect of Fermi level pinning and poly-Si depletion on the erase behaviour and compare the erase performances of several PVD- and AVD-deposited metal gates.