Relevant bibliographies by topics / NAND Flash Interface

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  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'NAND Flash Interface'

Author: Grafiati
Published: 11 September 2023

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Journal articles on the topic "NAND Flash Interface"

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Myramuru, Shanmukha Sai Nikhil, Dr S. Chandra Mohan Reddy, and Dr Gannera Mamatha. "Design and Integration of NAND Flash Memory Controller for Open Power-based Fabless SoC." International Journal of Engineering and Advanced Technology 12, no. 2 (December 30, 2022): 137–44. http://dx.doi.org/10.35940/ijeat.d3470.1212222.

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NAND Flash Memory has replaced EEPROM and hard drives as Non-volatile. Data is stored in sequential order in NAND Flash Memory. NAND Memory is a type of flash memory widely used in mobile phones and System on Chips (SoC). The Memory controller supports an 8-bit NAND Flash interface and streaming interface towards АXI4. The data transfer between АXI4 and NAND Flash Memory is carried оut by using NAND Flash commands sequences. The AXI4 Interface enables the usage of various рrоtосоls. To improve the flash memory controller's data access speed. This project intends to design, develop, and integrate a NAND Flash memory controller using an AXI4 interface for an open POWER Processor A20 fabless SOC. The Flash Memory Controller includes Finite State Machines (FSM) and AXI4 bridge logic. Using Mentor Graphics® and Xilinx's Vivado design suite, the test results were based on behavioral simulation and synthesis
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Liu, Hai Ke, Shun Wang, Xin Gna Kang, and Jin Liang Wang. "Realization of NAND FLASH Control Glueless Interface Circuit." Advanced Materials Research 1008-1009 (August 2014): 659–62. http://dx.doi.org/10.4028/www.scientific.net/amr.1008-1009.659.

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The article realization of NAND FLASH control glueless interface circuit based on FPGA,comparing the advantages and disadvantages of the NAND Flash and analysising the function of control interface circuit. The control interface circuit can correct carry out the SRAM timing-input block erase, page reads, page programming, state read instructions into the required operation sequence of NAND Flash, greatly simplifies the NAND FLASH read and write timing control. According to the ECC algorithm,the realization method of ECC check code generation,error search,error correction is described.The function of operate instructions of the NAND Flash control interface circuit designed in this paper is verified on Xillinx Spartan-3 board, and the frequency can reach 100MHz.
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Liu, Gen Xian, and Dong Sheng Wang. "Low Cost Wear Leveling for High-Density SPI NAND Flash in Memory Constrained Embedded System." Applied Mechanics and Materials 427-429 (September 2013): 1277–80. http://dx.doi.org/10.4028/www.scientific.net/amm.427-429.1277.

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SPI NOR Flash is widely used in embedded system for its compact package and simple interface. It is suitable to medium scale data storage. Now, industry provides higher density NAND Flash with the same interface and package as SPI NOR Flash. But the erase/program circles of NAND Flash is less than that of NOR Flash. The lifetime of NAND Flash is becoming the critical issue. Wear leveling algorithms prevent NAND Flash from prematurely retiring by mapping the logical block to different physical blocks. To our knowledge, most wear leveling algorithms need several kilobytes of RAM for keeping the mapping data structures, which is costly for the resource constrained micro controller. This study first proposes a no RAM required design with presetting lifetime, and then presents an adaptive design which requires only 2 kilobytes RAM with elasticity lifetime. The proposed design can be adapted in most of embedded systems based on low cost micro controller.
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Hung, Ji Jun, Kai Bu, Zhao Lin Sun, Jie Tao Diao, and Jian Bin Liu. "PCI Express-Based NVMe Solid State Disk." Applied Mechanics and Materials 464 (November 2013): 365–68. http://dx.doi.org/10.4028/www.scientific.net/amm.464.365.

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This paper presents a new architecture SSD based on NVMe (Non-Volatile Memory express) protocol. The NVMe SSD promises to solve the conventional SATA and SAS interface bottleneck. Its aimed to present a PCIe NAND Flash memory card that uses NAND Flash memory chip as the storage media. The paper analyzes the PCIe protocol and the characteristics of SSD controller, and then gives the detailed design of the PCIe SSD. It mainly contains the PCIe port and Flash Translation Layer.
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Missimer, Katherine, Manos Athanassoulis, and Richard West. "Telomere: Real-Time NAND Flash Storage." ACM Transactions on Embedded Computing Systems 21, no. 1 (January 31, 2022): 1–24. http://dx.doi.org/10.1145/3479157.

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Modern solid-state disks achieve high data transfer rates due to their massive internal parallelism. However, out-of-place updates for flash memory incur garbage collection costs when valid data needs to be copied during space reclamation. The root cause of this extra cost is that solid-state disks are not always able to accurately determine data lifetime and group together data that expires before the space needs to be reclaimed. Real-time systems found in autonomous vehicles, industrial control systems, and assembly-line robots store data from hundreds of sensors and often have predictable data lifetimes. These systems require guaranteed high storage bandwidth for read and write operations by mission-critical real-time tasks. In this article, we depart from the traditional block device interface to guarantee the high throughput needed to process large volumes of data. Using data lifetime information from the application layer, our proposed real-time design, called Telomere , is able to intelligently lay out data in NAND flash memory and eliminate valid page copies during garbage collection. Telomere’s real-time admission control is able to guarantee tasks their required read and write operations within their periods. Under randomly generated tasksets containing 500 tasks, Telomere achieves 30% higher throughput with a 5% storage cost compared to pre-existing techniques.
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Yan, Chin-Rung, Jone F. Chen, Ya-Jui Lee, Yu-Jie Liao, Chung-Yi Lin, Chih-Yuan Chen, Yin-Chia Lin, and Huei-Haurng Chen. "Extraction and Analysis of Interface States in 50-nm nand Flash Devices." IEEE Transactions on Electron Devices 60, no. 3 (March 2013): 992–97. http://dx.doi.org/10.1109/ted.2013.2240458.

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Kim, Geukchan, Hyejin Kim, and Sunghoon Chun. "A New Package for High Speed and High Density eStorage Using the Frequency Boosting Chip." International Symposium on Microelectronics 2015, no. 1 (October 1, 2015): 000220–24. http://dx.doi.org/10.4071/isom-2015-wa22.

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A die-stacking technology in a multi-chip package can effectively increase the capacity. However, long wire bonding for multi-chip stack, inter-symbol interference caused by large capacitive loading and I/O speed degradations due to simultaneous switching noise (SSN) and power consumption have become obstacles to optimize the internal NAND flash interface. In this paper, to overcome the inevitable challenge between larger storage capacity and higher I/O speed, we propose a new package structure with a frequency boosting interface chip (FBI-chip) for high speed and high density eStorage.
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Li, Qing, Shan Qing Hu, Yang Feng, and Teng Long. "The Design and Implementation of a High-Speed and Large-Capacity NAND Flash Storage System." Applied Mechanics and Materials 543-547 (March 2014): 568–71. http://dx.doi.org/10.4028/www.scientific.net/amm.543-547.568.

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Now, the quality of higher speed and larger capacity are required to the real-time storage system. This paper designs a high-speed and large-capacity storage system which uses FPGA as the master of SOPC system controlling NAND Flash chips. This system puts forward an advanced storage structure which has several NAND Flashes with multi-buses, forming a parallel pipeline design. By using the key technologies of bad block management and the ECC algorithm, which greatly avoids the influence of the invalid block to the storage system and reduces the probability of error data as well. It can not only improve the storage bandwidth and capacity substantially, but also ensure the reliability of the storage system effectively. As a result, the storage system achieves the capacity of 1.5TB and the bandwidth of 1280MBps. Also, this system uses high-speed exchange interface to link to the external network, which achieve the real-time transmission and control of data, and make the storage system standard, universal, and scalable.
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Jeong, Jun-Kyo, Jae-Young Sung, Woon-San Ko, Ki-Ryung Nam, Hi-Deok Lee, and Ga-Won Lee. "Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory." Micromachines 12, no. 11 (November 15, 2021): 1401. http://dx.doi.org/10.3390/mi12111401.

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In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.
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Yi, Hyun Ju, and Tae Hee Han. "Adaptive Design Techniques for High-speed Toggle 2.0 NAND Flash Interface Considering Dynamic Internal Voltage Fluctuations." Journal of the Institute of Electronics Engineers of Korea 49, no. 9 (September 25, 2012): 251–58. http://dx.doi.org/10.5573/ieek.2012.49.9.251.

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Dissertations / Theses on the topic "NAND Flash Interface"

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Штогрин, Павло Петрович. "Мобільний додаток для моніторингу та прогнозування погодних умов у реальному часі." Bachelor's thesis, КПІ ім. Ігоря Сікорського, 2020. https://ela.kpi.ua/handle/123456789/34793.

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Кваліфікаційна робота включає пояснювальну записку (74 стор., 47 рис.). У бакалаврському проєкті реалізовано систему для моніторингу та прогнозування погодних умов у реальному часі. Система складається із пристрою для зчитування та передачі через bluetooth даних про погоду, серверної частини для обробки та передачі даних із погодних сервісів у мережі Internet, а також мобільного додатку для прийому, обробки та відображення інформації, отриманої із пристрою та сервера. Метою проєкту є створення пристрою, який міг би передавати дані про погодні умови безпосередньо у смартфон, а також мобільного додатку із зручним інтерфейсом, який міг би приймати, обробляти та відображати ці дані. У цьому проєкті було розроблено такі компоненти: – апаратний засіб на основі платформи Arduino, датчика та bluetooth-передавача; – сервер, створений мовою програмування Python на базі мікрофреймворку Flask та із використанням REST-архітектури; – мобільний додаток, створений мовою програмування Java для пристроїв з операційною системою Android; Результатом розробки є апаратний та програмний продукти, які дозволяють зручно відстежувати поточні погодні умови, а також формують прогноз для конкретної місцевості. Додаток має простий та зрозумілий інтерфейс, мінімальні системні вимоги (пристрій із операційною системою Android версії 4.4 чи вище, bluetooth-модуль та доступ до мережі Internet). Режим моніторингу може працювати без доступу до мережі Internet.
The bachelor's project implements a system for monitoring and forecasting weather conditions in real time. The system consists of a device for reading and transmitting weather data via bluetooth, a server part for processing and transmitting data from weather services on the Internet, and a mobile application for receiving, processing and displaying information received from the device and server. The aim of the project is to create a device that could transmit weather data directly to a smartphone and a mobile application with a user-friendly interface that could receive, process and display this data. The following components were developed in this project: − device based on Arduino platform, sensor and bluetooth transmitter; − a server which was created in the Python programming language, based on the Flask microframework and using the REST architecture; − mobile application created in the Java programming language for devices with the Android operating system; The result of the development is hardware and software products that allow conveniently track current weather conditions and form a forecast for a specific area. The application has a simple and clear interface, minimum system requirements (device with Android operating system version 4.4 or higher, bluetooth module and Internet access). The monitoring mode can work without Internet access.
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SINGH, PANKAJ. "DESIGNING A NAND FLASH INTERFACE I/O WHICH MEETS ALL THE SPECIFICATION OF ONFI 2.3." Thesis, 2016. http://dspace.dtu.ac.in:8080/jspui/handle/repository/14520.

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ABSTRACT An interface is a tool and concept that refers to a point of interaction between components, and is applicable at the level of both hardware and software. This allows a component, whether a piece of hardware such as a graphic card or a piece of software such as an internet browser, to function independently while using interfaces to communicate with other components via an input /output system and an associated protocol. The Open NAND Flash Interface Working Group (ONFI) is a consortium of technology companies working to develop open standards for NAND flash memory chips and devices that communicate with them. The formation of ONFI was announced at the Intel Developer Forum in March 2006. The ONFI Working Group is dedicated to simplifying integration of NAND Flash memory into consumer electronics (CE) applications and computing platforms. ONFI 2.3 standard specifications were ratified in 16 AUG 2010 which includes the EZNAND protocol. EZ-NAND, which stands for error correction code (ECC) Zero NAND, was designed to remove the burden of the host controller to keep pace with the fast changing ECC requirements of NAND technology. Here In this thesis work, I design a NAND Flash Interface I/O which meets all the specifications of ONFI 2.3. This I/O design is working for data rate of 200 MHz with I/O supply voltage of 1.8V. I tested my design in ADE using SPECTRE as simulator.
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Books on the topic "NAND Flash Interface"

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Zhou, Clarence. NAND Flash Interface with EBI on Cortex-M Based MCUs. Microchip Technology Incorporated, 2018.

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Aiyappa, Rekha. NAND Flash Interface with EBI on Cortex-M Based MCUs TB. Microchip Technology Incorporated, 2018.

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Book chapters on the topic "NAND Flash Interface"

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Silvagni, Andrea. "NAND DDR interface." In Inside NAND Flash Memories, 161–96. Dordrecht: Springer Netherlands, 2010. http://dx.doi.org/10.1007/978-90-481-9431-5_7.

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Conference papers on the topic "NAND Flash Interface"

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Hwang Huh, ChunWoo Jeon, CheolWoo Yang, JaeSeok Park, TaeHeui Kwon, TaiKyu Kang, ChangWon Yang, et al. "A 64Gb NAND Flash Memory with 800MB/s Synchronous DDR Interface." In 2012 4th IEEE International Memory Workshop (IMW). IEEE, 2012. http://dx.doi.org/10.1109/imw.2012.6213644.

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Lee, Daeyeal, Ik Joon Chang, Sang-Yong Yoon, Joonsuc Jang, Dong-Su Jang, Wook-Ghee Hahn, Jong-Yeol Park, et al. "A 64Gb 533Mb/s DDR interface MLC NAND Flash in sub-20nm technology." In 2012 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2012. http://dx.doi.org/10.1109/isscc.2012.6177077.

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Kim, Hyun-Jin, Jeong-Don Lim, Jang-Woo Lee, Dae-Hoon Na, Joon-Ho Shin, Chae-Hoon Kim, Seung-Woo Yu, et al. "7.6 1GB/s 2Tb NAND flash multi-chip package with frequency-boosting interface chip." In 2015 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2015. http://dx.doi.org/10.1109/isscc.2015.7062964.

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Ou, Yang, Nong Xiao, Fang Liu, and Zhiguang Chen. "PIFCard: A High Performance Flash Card Matching the Parallelism and Latency of NAND Flash with Those of PCI-E Interface." In 2013 8th ChinaGrid Annual Conference (ChinaGrid). IEEE, 2013. http://dx.doi.org/10.1109/chinagrid.2013.18.

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Nobunaga, Dean, Ebrahim Abedifard, Frankie Roohparvar, June Lee, Erwin Yu, Allahyar Vahidimowlavi, Michael Abraham, et al. "A 50nm 8Gb NAND Flash Memory with 100MB/s Program Throughput and 200MB/s DDR Interface." In 2008 International Solid-State Circuits Conference - (ISSCC). IEEE, 2008. http://dx.doi.org/10.1109/isscc.2008.4523239.

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Wang, Szu-Yu, Hang-Ting Lue, Tzu-Hsuan Hsu, Pei-Ying Du, Sheng-Chih Lai, Yi-Hsuan Hsiao, Shih-Ping Hong, et al. "A high-endurance (≫100K) BE-SONOS NAND flash with a robust nitrided tunnel oxide/si interface." In 2010 IEEE International Reliability Physics Symposium. IEEE, 2010. http://dx.doi.org/10.1109/irps.2010.5488698.

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Kim, Hyunggon, Jung-hoon Park, Ki-Tae Park, Pansuk Kwak, Ohsuk Kwon, Chulbum Kim, Younyeol Lee, et al. "A 159mm2 32nm 32Gb MLC NAND-flash memory with 200MB/s asynchronous DDR interface." In 2010 IEEE International Solid- State Circuits Conference - (ISSCC). IEEE, 2010. http://dx.doi.org/10.1109/isscc.2010.5433912.

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Gillingham, Peter, Jin-Ki Kim, Roland Schuetz, Hong-Beom Pyeon, HakJune Oh, Don Macdonald, Eric Choi, and David Chinn. "A 256Gb NAND Flash Memory Stack with 300MB/s HLNAND Interface Chip for Point-to-Point Ring Topology." In 2011 3rd IEEE International Memory Workshop (IMW). IEEE, 2011. http://dx.doi.org/10.1109/imw.2011.5873241.

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Park, Sang-ku, Seung-Hyun Kim, Sang-Ho Lee, Do-Bin Kim, Myung-Hyun Baek, and Byung-Gook Park. "Interface and oxide trap analysis at tunnel oxide of NAND flash memory with excluding the effect of floating gate." In 2016 IEEE Silicon Nanoelectronics Workshop (SNW). IEEE, 2016. http://dx.doi.org/10.1109/snw.2016.7577999.

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Cho, Jiho, D. Chris Kang, Jongyeol Park, Sang-Wan Nam, Jung-Ho Song, Bong-Kil Jung, Jaedoeg Lyu, et al. "30.3 A 512Gb 3b/Cell 7th -Generation 3D-NAND Flash Memory with 184MB/s Write Throughput and 2.0Gb/s Interface." In 2021 IEEE International Solid- State Circuits Conference (ISSCC). IEEE, 2021. http://dx.doi.org/10.1109/isscc42613.2021.9366054.

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