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Journal articles on the topic 'Multiprocessor machine'

Author: Grafiati

Published: 25 May 2024

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1

Averbuch, A., E. Gabber, S. Itzikowitz, and B. Shoham. "On the Parallel Elliptic Single/Multigrid Solutions about Aligned and Nonaligned Bodies Using the Virtual Machine for Multiprocessors." Scientific Programming 3, no. 1 (1994): 13–32. http://dx.doi.org/10.1155/1994/895737.

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Parallel elliptic single/multigrid solutions around an aligned and nonaligned body are presented and implemented on two multi-user and single-user shared memory multiprocessors (Sequent Symmetry and MOS) and on a distributed memory multiprocessor (a Transputer network). Our parallel implementation uses the Virtual Machine for Muli-Processors (VMMP), a software package that provides a coherent set of services for explicitly parallel application programs running on diverse multiple instruction multiple data (MIMD) multiprocessors, both shared memory and message passing. VMMP is intended to simplify parallel program writing and to promote portable and efficient programming. Furthermore, it ensures high portability of application programs by implementing the same services on all target multiprocessors. The performance of our algorithm is investigated in detail. It is seen to fit well the above architectures when the number of processors is less than the maximal number of grid points along the axes. In general, the efficiency in the nonaligned case is higher than in the aligned case. Alignment overhead is observed to be up to 200% in the shared-memory case and up to 65% in the message-passing case. We have demonstrated that when using VMMP, the portability of the algorithms is straightforward and efficient.

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2

Staunstrup, Jørgen, Jens Ove Jespersen, and Ole V. Johansen. "Physical datarepresentation in a multiprocessor database machine." Parallel Computing 2, no. 4 (December 1985): 335–43. http://dx.doi.org/10.1016/0167-8191(85)90032-8.

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3

Miya, E. N. "Multiprocessor/distributed processing bibliography (in machine-readable form)." ACM SIGARCH Computer Architecture News 13, no. 1 (March 1985): 27–29. http://dx.doi.org/10.1145/1296930.1296933.

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4

Sarkar, Susmit, Peter Sewell, Francesco Zappa Nardelli, Scott Owens, Tom Ridge, Thomas Braibant, Magnus O. Myreen, and Jade Alglave. "The semantics of x86-CC multiprocessor machine code." ACM SIGPLAN Notices 44, no. 1 (January 21, 2009): 379–91. http://dx.doi.org/10.1145/1594834.1480929.

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5

KELLERER, HANS. "Algorithms for multiprocessor scheduling with machine release times." IIE Transactions 30, no. 11 (November 1998): 991–99. http://dx.doi.org/10.1080/07408179808966555.

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6

Shachnai and Tamir. "Multiprocessor Scheduling with Machine Allotment and Parallelism Constraints." Algorithmica 32, no. 4 (April 2002): 651–78. http://dx.doi.org/10.1007/s00453-001-0098-3.

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7

Walter, Rico, and Alexander Lawrinenko. "A characterization of optimal multiprocessor schedules and new dominance rules." Journal of Combinatorial Optimization 40, no. 4 (August 12, 2020): 876–900. http://dx.doi.org/10.1007/s10878-020-00634-9.

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Abstract The paper on hand approaches the classical makespan minimization problem on identical parallel machines from a rather theoretical point of view. Using an approach similar to the idea behind inverse optimization, we identify a general structural pattern of optimal multiprocessor schedules. We also show how to derive new dominance rules from the characteristics of optimal solutions. Results of our computational study attest to the efficacy of the new rules. They are particularly useful in limiting the search space when each machine processes only a few jobs on average.

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8

Bogdanov, D. R., and O. V. Darintsev. "Multiprocessor systems based on FPGA for receiving and processing data from the position sensors of the manipulator elements with controlled bending." Proceedings of the Mavlyutov Institute of Mechanics 11, no. 1 (2016): 100–106. http://dx.doi.org/10.21662/uim2016.1.015.

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Key moments of technique of reception and processing of information from the MEMS position sensors in the information system of the manipulator built on the basis units with controlled bend is discussed in detail. The differences in the procedure for construction of multiprocessor information systems based on the new programmable logic integrated circuits large capacity which provide the use of soft-core processors is presented too. The results of qualitative comparison of the solutions obtained by use state machine circuits and schemes based on soft-processors is shown. As an example, consider the structure developed multiprocessor information system and variants of its hardware and structural implementation.

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Melikyan, V. SH, H. A. Petrosyan, S. H. Abovyan, L. H. Shakhbazyan, A. H. Stepanyan, and E. O. Musayelyan. "Statistical analysis of time delays multiprocessor systems." Electronics and Communications 15, no. 5 (March 29, 2010): 108–12. http://dx.doi.org/10.20535/2312-1807.2010.58.5.285076.

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In this paper a method of statistical static timing analysis (SSTA) for multicore processors is proposed. An effective method of timing analysis based on simultaneous application of usual static as well as statistical static timing analysis. At the first stage usual static timing analysis (STA) is applied and at the second stage - SSTA. The proposed method of analysis allows reaching of acceptable analysis results from the practical viewpoint of accuracy at considerably small expenses of machine runtime

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Kuruvilla, Abey, and Giuseppe Paletta. "Minimizing Makespan on Identical Parallel Machines." International Journal of Operations Research and Information Systems 6, no. 1 (January 2015): 19–29. http://dx.doi.org/10.4018/ijoris.2015010102.

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A heuristic algorithm that uses iteratively LPT and MF approaches on different job and machine sets constructed by using the current solution is developed to solve a classical multiprocessor scheduling problem with the objective of minimizing the makespan. Computational results indicate that the proposed algorithm is very competitive with respect to well-known constructive algorithms for a large number of benchmark instances.

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11

Vairam, Senthil, and V. Selladurai. "Parallel Machine Shop Scheduling Using Memetic Algorithm." Applied Mechanics and Materials 573 (June 2014): 362–67. http://dx.doi.org/10.4028/www.scientific.net/amm.573.362.

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Parallel machine shop scheduling problem can be stated as finding a schedule for a general task graph to execute on a customed flow so that the schedule length can be minimized. Parallel Flow Shop Scheduling with a case study has been . In this study we present an effective memetic algorithm to solve the problem. Also evaluating the performance of two algorithms (genetic algorithm and memetic algorithm) in terms of both the quality of the solutions produced and the efficiency. These results demonstrate that the memetic algorithm produces better and quality solutions and hence it is very efficient . KEY WORDS: Hybrid Flow Shop Scheduling, Multiprocessor, Memetic algorithm.

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12

Qadah, G. Z., and K. B. Irani. "The join algorithms on a shared-memory multiprocessor database machine." IEEE Transactions on Software Engineering 14, no. 11 (1988): 1668–83. http://dx.doi.org/10.1109/32.9054.

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13

Wang, Wencheng, and Xiaofei Liu. "A Combinatorial 2-Approximation Algorithm for the Parallel-Machine Scheduling with Release Times and Submodular Penalties." Mathematics 10, no. 1 (December 25, 2021): 61. http://dx.doi.org/10.3390/math10010061.

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In this paper, we consider parallel-machine scheduling with release times and submodular penalties (P|rj,reject|Cmax+π(R)), in which each job can be accepted and processed on one of m identical parallel machines or rejected, but a penalty must paid if a job is rejected. Each job has a release time and a processing time, and the job can not be processed before its release time. The objective of P|rj,reject|Cmax+π(R) is to minimize the makespan of the accepted jobs plus the penalty of the rejected jobs, where the penalty is determined by a submodular function. This problem generalizes a multiprocessor scheduling problem with rejection, the parallel-machine scheduling with submodular penalties, and the single machine scheduling problem with release dates and submodular rejection penalties. In this paper, inspired by the primal-dual method, we present a combinatorial 2-approximation algorithm to P|rj,reject|Cmax+π(R). This ratio coincides with the best known ratio for the parallel-machine scheduling with submodular penalties and the single machine scheduling problem with release dates and submodular rejection penalties.

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14

Alglave, Jade, Anthony Fox, Samin Ishtiaq, Magnus O. Myreen, Susmit Sarkar, Peter Sewell, and Francesco Zappa Nardelli. "The semantics of power and ARM multiprocessor machine code (abstract only)." ACM SIGPLAN Notices 44, no. 5 (May 6, 2009): 8. http://dx.doi.org/10.1145/1629635.1629638.

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Rashid, Richard, Avadis Tevanian, Michael Young, David Golub, Robert Baron, David Black, William Bolosky, and Jonathan Chew. "Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures." ACM SIGARCH Computer Architecture News 15, no. 5 (November 1987): 31–39. http://dx.doi.org/10.1145/36177.36181.

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Rashid, Richard, Avadis Tevanian, Michael Young, David Golub, Robert Baron, David Black, William Bolosky, and Jonathan Chew. "Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures." ACM SIGOPS Operating Systems Review 21, no. 4 (October 1987): 31–39. http://dx.doi.org/10.1145/36204.36181.

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Rashid, Richard, Avadis Tevanian, Michael Young, David Golub, Robert Baron, David Black, William Bolosky, and Jonathan Chew. "Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures." ACM SIGPLAN Notices 22, no. 10 (October 1987): 31–39. http://dx.doi.org/10.1145/36205.36181.

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18

Rashid, R., A. Tevanian, M. Young, D. Golub, R. Baron, D. Black, W. J. Bolosky, and J. Chew. "Machine-independent virtual memory management for paged uniprocessor and multiprocessor architectures." IEEE Transactions on Computers 37, no. 8 (1988): 896–908. http://dx.doi.org/10.1109/12.2242.

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19

Narayan, Ranjani, and V. Rajaraman. "Performance analysis of a multiprocessor machine based on data flow principles." Microprocessing and Microprogramming 30, no. 1-5 (August 1990): 601–8. http://dx.doi.org/10.1016/0165-6074(90)90306-t.

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20

Aerts, Joep, Jan Korst, and Wim Verhaegh. "Load balancing for redundant storage strategies: Multiprocessor scheduling with machine eligibility." Journal of Scheduling 4, no. 5 (2001): 245–57. http://dx.doi.org/10.1002/jos.81.

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21

Boctor, Fayez F., Jacques Renaud, Angel Ruiz, and Simon Tremblay. "Optimal and heuristic solution methods for a multiprocessor machine scheduling problem." Computers & Operations Research 36, no. 10 (October 2009): 2822–28. http://dx.doi.org/10.1016/j.cor.2008.12.017.

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22

Sagan, Jaroslaw. "Inter-thread communication efficiency." Annales Universitatis Mariae Curie-Sklodowska, sectio AI – Informatica 15, no. 1 (January 1, 2015): 12. http://dx.doi.org/10.17951/ai.2015.15.1.12-15.

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In this paper I compare inter-thread communication methods: blocking queue and LMAX Disruptor without synchronization according to a number of threads (CPU cores) and consumer rate. The research is carried out using a multiprocessor machine with Non Uniformed Memory and Oracle Java Runtime Environment. I determine if processing on many multi-core CPUs with NUMA is faster than on single multi-core CPU or vice versa.

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23

Baba, Yao, and Hevner. "Design of a Functionally Distributed, Multiprocessor Database Machine Using Data Flow Analysis." IEEE Transactions on Computers C-36, no. 6 (June 1987): 650–66. http://dx.doi.org/10.1109/tc.1987.1676959.

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24

Satpathy, Prativa, Kalyan Das, and Jagamohan Padhi. "Improved Rejection Penalty Algorithm with Multiprocessor Rejection Technique." International Journal of Electrical and Computer Engineering (IJECE) 5, no. 3 (June 1, 2015): 477. http://dx.doi.org/10.11591/ijece.v5i3.pp477-482.

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<p>This paper deals with multiprocessor scheduling with rejection technique where each job is provided with processing time and a given penalty cost. If the job satisfies the acceptance condition, it will schedule in the least loaded identical parallel machine else job is rejected. In this way its penalty cost is calculated. Our objective is to minimize the makespan of the scheduled job and to minimize the sum of the penalties of rejected jobs. We have merged ‘CHOOSE ‘and ‘REJECTION PENALTY’ algorithm to reduce the sum of penalties cost and makespan. Our proposed ‘Improved Reject penalty algorithm’ reduce competitive ratio, which in turn enhances the efficiency of the on-line algorithm. By applying our new on-line technique, we got the lower bound of our algorithm is is 1.286 which is far better from the existing algorithms whose competitive ratio is at 1.819. In our approach we have consider non-preemption scheduling technique.</p>

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25

Huang, Rong Hwa, Tung Han Yu, and Chang Lin Yang. "Multiprocessor Flow Shop Scheduling Problem with Common due Window." Applied Mechanics and Materials 284-287 (January 2013): 3712–16. http://dx.doi.org/10.4028/www.scientific.net/amm.284-287.3712.

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The objective of scheduling is to maximize capacity utilization, minimize work-in-process inventory and ensure timely delivery. The due windows problem proposes that jobs should only be finished within the time interval that meets customer needs. This research applies integer programming (IP) and ant colony optimization (ACO) to solve due window problems in a flow shop with multiprocessors (FSMP). To improve the performance of jobs within due windows, this research splits them into different numbers of processing lots so they can be processed on more than one machine simultaneously. This shortens the total weighted earliness and tardiness of the jobs. The ACO is applied as a heuristic tool for solving the scheduling problems, and the solution results show that ACO has good validity, robustness and effectiveness.

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26

H, Nirmala, and Girijamma H. A. "A Novel Scheduler for Task scheduling in Multiprocessor System using Machine Learning approach." International Journal of Computer Sciences and Engineering 7, no. 2 (February 28, 2019): 140–43. http://dx.doi.org/10.26438/ijcse/v7i2.140143.

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27

Veselovska, Nataliia. "DEVELOPMENT OF ALGORITHMIC SUPPORT FOR PRACTICAL IMPLEMENTATION OF TESTING AND DIAGNOSTIC COMPLEX OF CNC MACHINES." Vibrations in engineering and technology, no. 1(104) (April 29, 2022): 71–80. http://dx.doi.org/10.37128/2306-8744-2022-1-9.

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CNC machines, including multi-purpose machines (product processing centers), have been widely used in connection with the creation of flexible production systems and significant progress in developing and improving the reliability of multi-purpose freely programmable, multiprocessor and small numerical program control devices (CNC) , so the development of algorithmic software for the practical implementation of the test and diagnostic complex and the use of diagnostic systems as a means of automation of information technology is one of the general directions of improving the efficiency of machine-building enterprises. However, in order to make decisions about the scope, stages and feasibility of using a particular diagnostic system for the selected object of study at a particular enterprise, it is necessary to assess its expected benefits. The use of diagnostics during operation of the machine imposes its influence on the means and methods of diagnosis, which should be convenient for use in the factory, to ensure the diagnosis process in the shortest time, to have reliable readings, especially with high requirements for product reliability. and in some cases without disrupting the mechanism, to be economically feasible. The design of the machine is adapted to the needs of diagnostics and must: have built-in devices that evaluate its parameters (pressure in the hydraulic system, temperature of energy-intensive units, accuracy of machining, speed); periodically connect to special equipment that will diagnose the basic parameters of the machine and provide data on its condition. The parameters of the technical condition (diagnostic features), which can be judged on the OD and which are diagnosed during operation of the machine, are: machine parameters that directly characterize its efficiency; damage and defects that occur during operation and lead or may lead to failure; side effects that are functionally or stochastically related to the initial parameters.

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28

Huei-Huang, Chen, and Liu Guang-Sheen. "Response time analysis of using a parallel join algorithm on a multiprocessor backend machine." Information Systems 15, no. 2 (January 1990): 197–206. http://dx.doi.org/10.1016/0306-4379(90)90035-n.

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AZAGURY, ALAIN, ELLIOT K. KOLODNER, and EREZ PETRANK. "A NOTE ON THE IMPLEMENTATION OF REPLICATION-BASED GARBAGE COLLECTION FOR MULTITHREADED APPLICATIONS AND MULTIPROCESSOR ENVIRONMENTS." Parallel Processing Letters 09, no. 03 (September 1999): 391–99. http://dx.doi.org/10.1142/s0129626499000360.

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Replication-based incremental garbage collection is one of the more appealing concurrent garbage collection algorithms known today. It allows continuous operation of the application (the mutator) with very short pauses for garbage collection. There is a growing need for such garbage collectors suitable for a multithreaded environments such as the Java Virtual Machine. Furthermore, it is desirable to construct collectors that also work on multiprocessor computers. We begin by pointing out an important, yet subtle point, which arises when implementing the replication-based garbage collector for a multithreaded environment. We first show that a simple and natural implementation of the algorithm may lead to an incorrect behavior of multithreaded applications. We then show that another simple and natural implementation eliminates the problem completely. Thus, the contribution of this part is in stressing this warning to future implementors. Next, we address the effects of the memory coherence model on this algorithm. We show that even when the algorithm is properly implemented with respect to our first observation, a problem might still arise when a multiprocessor system is used. Adopting a naive solution to this problem results in very frequent (and expensive) synchronization. We offer a slight modification to the algorithm which eliminates the problem and requires little synchronization.

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Bourbakis, N. G., F. Barlos, and J. S. Mertoguno. "Hermes Autonomous Vision System." International Journal of Pattern Recognition and Artificial Intelligence 12, no. 03 (May 1998): 265–91. http://dx.doi.org/10.1142/s0218001498000191.

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This paper deals with the modeling of an extended quartet multiprocessor kernel used for the evaluation of the Hermes system. Hermes is a multiprocessor hybrid system architecture used as a machine vision system. The functionality of Hermes requires an asynchronous information flow upwards and downwards, where "orders"(in a form of code and data) go down and "abstracted" or processed picture information goes up along the system's hierarchy. Moreover, the overall functional behavior of the Hermes system can be considered as an extended quartet kernel in an abstracted manner. The extended quartet kernel studied here presents either a memory-to-memory (M-M) or a bus-to-bus (B-B) connectivity. The evaluation of these two kernel's configurations (M-M, B-B) defines that the structural design of the Hermes system will be based on the M-M scheme. When failures occur on the quartet kernel, however, the M-M scheme will be converted into a B-B one by using a failure recovery procedure. The evaluation of the quartet kernel configurations is based on a probabilistic model. Failures and recovery procedures on the quartet kernel are discussed and the performance evaluation of the kernel (under failures) is also provided.

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Vakhania, Nodari. "Dynamic Restructuring Framework for Scheduling with Release Times and Due-Dates." Mathematics 7, no. 11 (November 14, 2019): 1104. http://dx.doi.org/10.3390/math7111104.

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Scheduling jobs with release and due dates on a single machine is a classical strongly NP-hard combination optimization problem. It has not only immediate real-life applications but also it is effectively used for the solution of more complex multiprocessor and shop scheduling problems. Here, we propose a general method that can be applied to the scheduling problems with job release times and due-dates. Based on this method, we carry out a detailed study of the single-machine scheduling problem, disclosing its useful structural properties. These properties give us more insight into the complex nature of the problem and its bottleneck feature that makes it intractable. This method also helps us to expose explicit conditions when the problem can be solved in polynomial time. In particular, we establish the complexity status of the special case of the problem in which job processing times are mutually divisible by constructing a polynomial-time algorithm that solves this setting. Apparently, this setting is a maximal polynomially solvable special case of the single-machine scheduling problem with non-arbitrary job processing times.

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Niyizamwiyitira, Christine, and Lars Lundberg. "A Utilization-Based Schedulability Test of Real-Time Systems Running on a Multiprocessor Virtual Machine." Computer Journal 62, no. 6 (February 14, 2019): 884–904. http://dx.doi.org/10.1093/comjnl/bxz005.

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33

Wei, Liying, Chao Shang, and Xiaoqiu Chen. "The Use of Knowledge Management-Based Information Collaborative Learning Tool in English Teaching Classroom." Wireless Communications and Mobile Computing 2022 (January 27, 2022): 1–10. http://dx.doi.org/10.1155/2022/6367007.

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In the recent digitization era, knowledge management plays a significant role in the teaching and learning process. Collaborative learning is becoming a trending technology in enhancing the learning process by the concept of “learning through working together.” This learning methodology will make the students learn the courses faster. This research work focuses on applying collaborative learning tools in the learning process of English education in classrooms. Also, knowledge management is focused on in this research work. Multiprocessor learning algorithm (MLA) with support vector machine (SVM) is implemented over the student response. The students’ responses indicate that the students have gained much knowledge with the English education-learning technology from collaborative learning compared to the traditional learning method.

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FORSELL, MARTTI. "ON THE PERFORMANCE AND COST OF SOME PRAM MODELS ON CMP HARDWARE." International Journal of Foundations of Computer Science 21, no. 03 (June 2010): 387–404. http://dx.doi.org/10.1142/s0129054110007325.

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The Parallel Random Access Machine is a very strong model of parallel computing that has resisted cost-efficient implementation attempts for decades. Recently, the development of VLSI technology has provided means for indirect on-chip implementation, but there are different variants of the PRAM model that provide different performance, area and power figures and it is not known how their implementations compare to each others. In this paper we measure the performance and estimate the cost of practical implementations of four PRAM models including EREW, Limited Arbitrary CRCW, Full Arbitrary CRCW, Full Arbitrary Multioperation CRCW on our Eclipse chip multiprocessor framework. Interestingly, the most powerful model shows the lowest simulation cost and highest performance/area and performance/power figures.

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GRIEBEL, MICHAEL. "THE COMBINATION TECHNIQUE FOR THE SPARSE GRID SOLUTION OF PDE'S ON MULTIPROCESSOR MACHINES." Parallel Processing Letters 02, no. 01 (March 1992): 61–70. http://dx.doi.org/10.1142/s0129626492000180.

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We present a new method for the solution of partial differential equations. In contrast to the usual approach which needs in the 2-D case [Formula: see text] grid points, our combination technique works with only [Formula: see text] grid points, where hn denotes the employed grid size. The accuracy of the obtained solution deteriorates only slightly from [Formula: see text] to [Formula: see text] for a sufficiently smooth solution. Additionally, the new method is perfectly suited for parallelization. On a machine with [Formula: see text] processors we get in practice an overall parallel complexity of only [Formula: see text]. The method can be generalized to higher dimensions. Then, the gain is expected to be even more dramatic. For the two-dimensional case, we report the results of numerical experiments obtained on a Transputer system and on the CRAY Y-MP.

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Dackland, Krister, Erik Elmroth, Bo Kålgström, and Charles Van Loan. "Parallel Block Matrix Factorizations on the Shared-Memory Multiprocessor Ibm 3090 VF/600J." International Journal of Supercomputing Applications 6, no. 1 (April 1992): 69–97. http://dx.doi.org/10.1177/109434209200600105.

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Efficient parallel block algorithms for the LU factorization with partial pivoting, the Cholesky factorization, and the QR factorization transportable over a range of parallel MIMD architectures are presented. Parallel implementations of different block algorithms that utilize optimized uniprocessor level-3 BLAS are compared with corresponding routines of LAPACK (under development). Parallelism is mainly invoked implicitly in LAPACK by replacing calls to uniprocessor level-3 kernels by calls to parallel level-3 kernels and thereby maintaining portability. However, by parallelizing at the block level (explicitly) it is possible to overlap and pipeline different matrix-matrix operations and thereby gain some performance. Theoretical models give upper bounds on the best possible speedup of the explicitly and implicitly parallel block algorithms for the target machine.

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Heers, J., C. Schnorr, and H. S. Stiehl. "Globally convergent iterative numerical schemes for nonlinear variational image smoothing and segmentation on a multiprocessor machine." IEEE Transactions on Image Processing 10, no. 6 (June 2001): 852–64. http://dx.doi.org/10.1109/83.923282.

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Papazoglou, M. P., P. I. Georgiadis, D. G. Maritsas, and A. A. Dickie. "Multiprocessor interrupting and synchronizing concepts in the parallel SIMULA machine and their representation by Petri-Nets." Microprocessing and Microprogramming 15, no. 4 (April 1985): 179–90. http://dx.doi.org/10.1016/0165-6074(85)90078-x.

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Khazal, R. R., and M. M. Chawla. "A parallel Cholesky algorithm for the solution of symmetric linear systems." International Journal of Mathematics and Mathematical Sciences 2004, no. 25 (2004): 1315–27. http://dx.doi.org/10.1155/s0161171204202265.

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For the solution of symmetric linear systems, the classical Cholesky method has proved to be difficult to parallelize. In the present paper, we first describe an elimination variant of Cholesky method to produce a lower triangular matrix which reduces the coefficient matrix of the system to an identity matrix. Then, this elimination method is combined with the partitioning method to obtain a parallel Cholesky algorithm. The total serial arithmetical operations count for the parallel algorithm is of the same order as that for the serial Cholesky method. The present parallel algorithm could thus perform withefficiencyclose to 1 if implemented on a multiprocessor machine. We also discuss theexistenceof the parallel algorithm; it is shown that for a symmetric and positive definite system, the presented parallel Cholesky algorithm is well defined and will run to completion.

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CHONG, FREDERIC T., and ANANT AGARWAL. "SHARED MEMORY VERSUS MESSAGE PASSING FOR ITERATIVE SOLUTION OF SPARSE, IRREGULAR PROBLEMS." Parallel Processing Letters 09, no. 01 (March 1999): 159–70. http://dx.doi.org/10.1142/s0129626499000177.

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The benefits of hardware support for shared memory versus those for message passing are difficult to evaluate without an in-depth study of real applications on a common platform. We evaluate the communication mechanisms of the MIT Alewife machine, a multiprocessor which provides integrated cache-coherent shared memory, massage passing, and DMA. We perform this evaluation with "best-effort" implementations which solve several sparse, irregular benchmark problems with a preconditioned conjugate gradient sparse matrix solver (ICCG). We find that machines with fast global memory operations do not need message passing or bulk transfer to suport our irregular problems. This is primarily due to three reasons. First, a 5-to-1 ratio between global and local cache misses makes memory copies in bulk communication expensive relati to communication via shared memory. Second, although message passing has synchronization semantics superior to shared memory for data-driven computation, efficient shared memory can overcome this handicap by using global read-modify-writes to change from the traditional owner-computers model to a producer-computes model. Third, bulk transfers can result in high processor idle times in irregular applications.

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Akay, Mehmet Fatih, Çiğdem İnan Aci, and Fatih Abut. "PREDICTING THE PERFORMANCE MEASURES OF A 2-DIMENSIONAL MESSAGE PASSING MULTIPROCESSOR ARCHITECTURE BY USING MACHINE LEARNING METHODS." Neural Network World 25, no. 3 (2015): 241–65. http://dx.doi.org/10.14311/nnw.2015.25.013.

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42

Bhandarkar, Suchendra M., Salem A. Machaka, Sanjay S. Shete, and Raghuram N. Kota. "Parallel Computation of a Maximum-Likelihood Estimator of a Physical Map." Genetics 157, no. 3 (March 1, 2001): 1021–43. http://dx.doi.org/10.1093/genetics/157.3.1021.

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Abstract Reconstructing a physical map of a chromosome from a genomic library presents a central computational problem in genetics. Physical map reconstruction in the presence of errors is a problem of high computational complexity that provides the motivation for parallel computing. Parallelization strategies for a maximum-likelihood estimation-based approach to physical map reconstruction are presented. The estimation procedure entails a gradient descent search for determining the optimal spacings between probes for a given probe ordering. The optimal probe ordering is determined using a stochastic optimization algorithm such as simulated annealing or microcanonical annealing. A two-level parallelization strategy is proposed wherein the gradient descent search is parallelized at the lower level and the stochastic optimization algorithm is simultaneously parallelized at the higher level. Implementation and experimental results on a distributed-memory multiprocessor cluster running the parallel virtual machine (PVM) environment are presented using simulated and real hybridization data.

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Frustaci, Fabio, Fanny Spagnolo, Stefania Perri, Giuseppe Cocorullo, and Pasquale Corsonello. "Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes." Sensors 22, no. 8 (April 7, 2022): 2839. http://dx.doi.org/10.3390/s22082839.

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This paper addresses the problem of automatic quality inspection in assembly processes by discussing the design of a computer vision system realized by means of a heterogeneous multiprocessor system-on-chip. Such an approach was applied to a real catalytic converter assembly process, to detect planar, translational, and rotational shifts of the flanges welded on the central body. The manufacturing line imposed tight time and room constraints. The image processing method and the features extraction algorithm, based on a specific geometrical model, are described and validated. The algorithm was developed to be highly modular, thus suitable to be implemented by adopting a hardware–software co-design strategy. The most timing consuming computational steps were identified and then implemented by dedicated hardware accelerators. The entire system was implemented on a Xilinx Zynq heterogeneous system-on-chip by using a hardware–software (HW–SW) co-design approach. The system is able to detect planar and rotational shifts of welded flanges, with respect to the ideal positions, with a maximum error lower than one millimeter and one sexagesimal degree, respectively. Remarkably, the proposed HW–SW approach achieves a 23× speed-up compared to the pure software solution running on the Zynq embedded processing system. Therefore, it allows an in-line automatic quality inspection to be performed without affecting the production time of the existing manufacturing process.

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Narayanan, S. Krishna, Dr S. Dhanasekaran, and Dr V. Vasudevan. "Minimizing Overloads of Critical Tasks Using Machine Learning in CPS by Extending Resources." Webology 18, no. 2 (December 23, 2021): 413–24. http://dx.doi.org/10.14704/web/v18i2/web18329.

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With all the growing variety of solutions plus industries as well as nuclear, substance, aerospace, as well as auto sectors to come down with cyber-physical Systems (CPSs), methods remain now actuality seriously loaded. CPSs includes varied dangerous jobs that stand protection dangerous (1) that is high or perhaps non-protection crucial (2) that is low. For conventional job arranging, nearly almost on the current arranging algorithms offer terrible functionality for high criticality jobs, if the method suffers from overburden as well as doesn't present explicit splitting up with various criticality duties to make the most of utilizing cloud online resources. Below, a framework is proposed by us to plan the mixed criticality duties by examining the deadlines of theirs as well as delivery occasions that use the overall presentation of similar handling done by OpenMP (Open Multi-Processing). The suggested agenda presents a piece of ML-based estimate for a job unloading within the area of cloud. Furthermore, it clarifies to perform the nominated variety of low dangerous things within the area of cloud even though the extraordinary serious jobs are operated over the regional CPUs over the method clog. Consequently, the high criticality jobs fulfil almost all the deadlines of theirs and also the method accomplishes a tremendous enhancement within the general delivery period as well as much better throughput. Additionally, the investigational outcomes using OpenMP present the usefulness of utilizing the subdivided arranging during a worldwide arranging technique upon multiprocessor methods to accomplish the works isolation.

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Shahrivari, Saeed, and Saeed Jalili. "Fast Parallel All-Subgraph Enumeration Using Multicore Machines." Scientific Programming 2015 (2015): 1–11. http://dx.doi.org/10.1155/2015/901321.

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Enumerating all subgraphs of an input graph is an important task for analyzing complex networks. Valuable information can be extracted about the characteristics of the input graph using all-subgraph enumeration. Notwithstanding, the number of subgraphs grows exponentially with growth of the input graph or by increasing the size of the subgraphs to be enumerated. Hence, all-subgraph enumeration is very time consuming when the size of the subgraphs or the input graph is big. We propose a parallel solution namedSubenumwhich in contrast to available solutions can perform much faster. Subenum enumerates subgraphs using edges instead of vertices, and this approach leads to a parallel and load-balanced enumeration algorithm that can have efficient execution on current multicore and multiprocessor machines. Also, Subenum uses a fast heuristic which can effectively accelerate non-isomorphism subgraph enumeration. Subenum can efficiently use external memory, and unlike other subgraph enumeration methods, it is not associated with the main memory limits of the used machine. Hence, Subenum can handle large input graphs and subgraph sizes that other solutions cannot handle. Several experiments are done using real-world input graphs. Compared to the available solutions, Subenum can enumerate subgraphs several orders of magnitude faster and the experimental results show that the performance of Subenum scales almost linearly by using additional processor cores.

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Kalapothas, Stavros, Georgios Flamis, and Paris Kitsos. "Efficient Edge-AI Application Deployment for FPGAs." Information 13, no. 6 (May 28, 2022): 279. http://dx.doi.org/10.3390/info13060279.

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Field Programmable Gate Array (FPGA) accelerators have been widely adopted for artificial intelligence (AI) applications on edge devices (Edge-AI) utilizing Deep Neural Networks (DNN) architectures. FPGAs have gained their reputation due to the greater energy efficiency and high parallelism than microcontrollers (MCU) and graphical processing units (GPU), while they are easier to develop and more reconfigurable than the Application Specific Integrated Circuit (ASIC). The development and building of AI applications on resource constraint devices such as FPGAs remains a challenge, however, due to the co-design approach, which requires a valuable expertise in low-level hardware design and in software development. This paper explores the efficacy and the dynamic deployment of hardware accelerated applications on the Kria KV260 development platform based on the Xilinx Kria K26 system-on-module (SoM), which includes a Zynq multiprocessor system-on-chip (MPSoC). The platform supports the Python-based PYNQ framework and maintains a high level of versatility with the support of custom bitstreams (overlays). The demonstration proved the reconfigurabibilty and the overall ease of implementation with low-footprint machine learning (ML) algorithms.

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V, Yashchenko. "Neuron. Molecular supercomputer." Artificial Intelligence 27, AI.2022.27(2) (December 29, 2022): 15–20. http://dx.doi.org/10.15407/jai2022.02.015.

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The article discusses the prospects for the development of intelligent computing systems. It is determined that at present the most promising direction in this area is based on the idea obtained as a result of biological research on the development of biocomputers, special types of molecular microcomputers using the concept of nerve cell DNA as the basis for calculations. In this regard, the structure and functioning of the nerve cell is considered in detail. Based on the consideration and analysis of the works of physiologists on the structure and functions of a biological neuron, it was found that the information perceived by a person is stored in the neurons of the brain at the molecular level, it also suggested that the nucleus and endoplasmic reticulum are elements of processing, transformation and storage of temporary memory. In addition, it was assumed that the nerve cell of the brain is a molecular, analog supercomputer that performs the analysis, synthesis, processing and storage of information. Huge volumes of information perceived by a person from the moment of his birth and throughout his life are stored in a nerve cell. There are about 100 billion neurons in the human brain, with each neuron containing millions of membrane-bound ribosomes. A detailed consideration of the functioning of a biological neuron from the position of a cybernetic system approach led to the understanding that the structure and functions of the ribosomes of a nerve cell almost completely coincide with the structure and functions of a Turing machine. It is shown that, in fact, a Turing machine is a processor consisting of a logical device and external and internal memory. A neuron can be considered as a molecular multiprocessor supercomputer, since in a neuron, an analog of the logical structure of the ribosome, and external and internal memory are transfer RNA and informational RNA. An example of the implementation of the simplest version of the Turing machine is given. In conditions of successful development of this direction, the possibilities of computers of the future are enormous. A brief description of the neuron-like element and the neural-like growing network is given. Their application in the technology of molecular machines will lead to the creation of a machine brain similar to the human brain.

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Allouche, Mohamed, Tarek Frikha, Mihai Mitrea, Gérard Memmi, and Faten Chaabane. "Lightweight Blockchain Processing. Case Study: Scanned Document Tracking on Tezos Blockchain." Applied Sciences 11, no. 15 (August 3, 2021): 7169. http://dx.doi.org/10.3390/app11157169.

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To bridge the current gap between the Blockchain expectancies and their intensive computation constraints, the present paper advances a lightweight processing solution, based on a load-balancing architecture, compatible with the lightweight/embedding processing paradigms. In this way, the execution of complex operations is securely delegated to an off-chain general-purpose computing machine while the intimate Blockchain operations are kept on-chain. The illustrations correspond to an on-chain Tezos configuration and to a multiprocessor ARM embedded platform (integrated into a Raspberry Pi). The performances are assessed in terms of security, execution time, and CPU consumption when achieving a visual document fingerprint task. It is thus demonstrated that the advanced solution makes it possible for a computing intensive application to be deployed under severely constrained computation and memory resources, as set by a Raspberry Pi 3. The experimental results show that up to nine Tezos nodes can be deployed on a single Raspberry Pi 3 and that the limitation is not derived from the memory but from the computation resources. The execution time with a limited number of fingerprints is 40% higher than using a classical PC solution (value computed with 95% relative error lower than 5%).

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Kim, Jeong-Min, Youngsik Kim, Shin-Dug Kim, Tack-Don Han, and Sung-Bong Yang. "An Adaptive Parallel Computer Vision System." International Journal of Pattern Recognition and Artificial Intelligence 12, no. 03 (May 1998): 311–34. http://dx.doi.org/10.1142/s021800149800021x.

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An approach for designing a hybrid parallel system that can perform different levels of parallelism adaptively is presented. An adaptive parallel computer vision system (APVIS) is proposed to attain this goal. The APVIS is constructed by integrating two different types of parallel architectures, i.e. a multiprocessor based system (MBS) and a memory based processor array (MPA), tightly into a single machine. One important feature in the APVIS is that the programming interface to execute data parallel code onto the MPA is the same as the usual subroutine calling mechanism. Thus the existence of the MPA is transparent to the programmers. This research is to design an underlying base architecture that can be optimally executed for a broad range of vision tasks. A performance model is provided to show the effectiveness of the APVIS. It turns out that the proposed APVIS can provide significant performance improvement and cost effectiveness for highly parallel applications having a mixed set of parallelisms. Also an example application composed of a series of vision algorithms, from low-level and medium-level processing steps, is mapped onto the MPA. Consequently, the APVIS with a few or tens of MPA modules can perform the chosen example application in real time when multiple images are incoming successively with a few seconds inter-arrival time.

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Álvarez, Álvaro, Amaia Calleja, Mikel Arizmendi, Haizea González, and Luis Lopez de Lacalle. "Spiral Bevel Gears Face Roughness Prediction Produced by CNC End Milling Centers." Materials 11, no. 8 (July 27, 2018): 1301. http://dx.doi.org/10.3390/ma11081301.

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The emergence of multitasking machines in the machine tool sector presents new opportunities for the machining of large size gears and short production series in these machines. However, the possibility of using standard tools in conventional machines for gears machining represents a technological challenge from the point of view of workpiece quality. Machining conditions in order to achieve both dimensional and surface quality requirements need to be determined. With these considerations in mind, computer numerical control (CNC) methods to provide useful tools for gear processing are studied. Thus, a model for the prediction of surface roughness obtained on the teeth surface of a machined spiral bevel gear in a multiprocess machine is presented. Machining strategies and optimal machining parameters were studied, and the roughness model is validated for 3 + 2 axes and 5 continuous axes machining strategies.

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