Relevant bibliographies by topics / Multiprocessor machine

Contents

  1. Journal articles
  2. Dissertations / Theses
  3. Books
  4. Book chapters
  5. Conference papers

Academic literature on the topic 'Multiprocessor machine'

Author: Grafiati
Published: 25 May 2024

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Journal articles on the topic "Multiprocessor machine"

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Averbuch, A., E. Gabber, S. Itzikowitz, and B. Shoham. "On the Parallel Elliptic Single/Multigrid Solutions about Aligned and Nonaligned Bodies Using the Virtual Machine for Multiprocessors." Scientific Programming 3, no. 1 (1994): 13–32. http://dx.doi.org/10.1155/1994/895737.

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Parallel elliptic single/multigrid solutions around an aligned and nonaligned body are presented and implemented on two multi-user and single-user shared memory multiprocessors (Sequent Symmetry and MOS) and on a distributed memory multiprocessor (a Transputer network). Our parallel implementation uses the Virtual Machine for Muli-Processors (VMMP), a software package that provides a coherent set of services for explicitly parallel application programs running on diverse multiple instruction multiple data (MIMD) multiprocessors, both shared memory and message passing. VMMP is intended to simplify parallel program writing and to promote portable and efficient programming. Furthermore, it ensures high portability of application programs by implementing the same services on all target multiprocessors. The performance of our algorithm is investigated in detail. It is seen to fit well the above architectures when the number of processors is less than the maximal number of grid points along the axes. In general, the efficiency in the nonaligned case is higher than in the aligned case. Alignment overhead is observed to be up to 200% in the shared-memory case and up to 65% in the message-passing case. We have demonstrated that when using VMMP, the portability of the algorithms is straightforward and efficient.
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Staunstrup, Jørgen, Jens Ove Jespersen, and Ole V. Johansen. "Physical datarepresentation in a multiprocessor database machine." Parallel Computing 2, no. 4 (December 1985): 335–43. http://dx.doi.org/10.1016/0167-8191(85)90032-8.

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Miya, E. N. "Multiprocessor/distributed processing bibliography (in machine-readable form)." ACM SIGARCH Computer Architecture News 13, no. 1 (March 1985): 27–29. http://dx.doi.org/10.1145/1296930.1296933.

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Sarkar, Susmit, Peter Sewell, Francesco Zappa Nardelli, Scott Owens, Tom Ridge, Thomas Braibant, Magnus O. Myreen, and Jade Alglave. "The semantics of x86-CC multiprocessor machine code." ACM SIGPLAN Notices 44, no. 1 (January 21, 2009): 379–91. http://dx.doi.org/10.1145/1594834.1480929.

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KELLERER, HANS. "Algorithms for multiprocessor scheduling with machine release times." IIE Transactions 30, no. 11 (November 1998): 991–99. http://dx.doi.org/10.1080/07408179808966555.

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Shachnai and Tamir. "Multiprocessor Scheduling with Machine Allotment and Parallelism Constraints." Algorithmica 32, no. 4 (April 2002): 651–78. http://dx.doi.org/10.1007/s00453-001-0098-3.

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Walter, Rico, and Alexander Lawrinenko. "A characterization of optimal multiprocessor schedules and new dominance rules." Journal of Combinatorial Optimization 40, no. 4 (August 12, 2020): 876–900. http://dx.doi.org/10.1007/s10878-020-00634-9.

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Abstract The paper on hand approaches the classical makespan minimization problem on identical parallel machines from a rather theoretical point of view. Using an approach similar to the idea behind inverse optimization, we identify a general structural pattern of optimal multiprocessor schedules. We also show how to derive new dominance rules from the characteristics of optimal solutions. Results of our computational study attest to the efficacy of the new rules. They are particularly useful in limiting the search space when each machine processes only a few jobs on average.
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Bogdanov, D. R., and O. V. Darintsev. "Multiprocessor systems based on FPGA for receiving and processing data from the position sensors of the manipulator elements with controlled bending." Proceedings of the Mavlyutov Institute of Mechanics 11, no. 1 (2016): 100–106. http://dx.doi.org/10.21662/uim2016.1.015.

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Key moments of technique of reception and processing of information from the MEMS position sensors in the information system of the manipulator built on the basis units with controlled bend is discussed in detail. The differences in the procedure for construction of multiprocessor information systems based on the new programmable logic integrated circuits large capacity which provide the use of soft-core processors is presented too. The results of qualitative comparison of the solutions obtained by use state machine circuits and schemes based on soft-processors is shown. As an example, consider the structure developed multiprocessor information system and variants of its hardware and structural implementation.
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Melikyan, V. SH, H. A. Petrosyan, S. H. Abovyan, L. H. Shakhbazyan, A. H. Stepanyan, and E. O. Musayelyan. "Statistical analysis of time delays multiprocessor systems." Electronics and Communications 15, no. 5 (March 29, 2010): 108–12. http://dx.doi.org/10.20535/2312-1807.2010.58.5.285076.

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In this paper a method of statistical static timing analysis (SSTA) for multicore processors is proposed. An effective method of timing analysis based on simultaneous application of usual static as well as statistical static timing analysis. At the first stage usual static timing analysis (STA) is applied and at the second stage - SSTA. The proposed method of analysis allows reaching of acceptable analysis results from the practical viewpoint of accuracy at considerably small expenses of machine runtime
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Kuruvilla, Abey, and Giuseppe Paletta. "Minimizing Makespan on Identical Parallel Machines." International Journal of Operations Research and Information Systems 6, no. 1 (January 2015): 19–29. http://dx.doi.org/10.4018/ijoris.2015010102.

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A heuristic algorithm that uses iteratively LPT and MF approaches on different job and machine sets constructed by using the current solution is developed to solve a classical multiprocessor scheduling problem with the objective of minimizing the makespan. Computational results indicate that the proposed algorithm is very competitive with respect to well-known constructive algorithms for a large number of benchmark instances.
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Dissertations / Theses on the topic "Multiprocessor machine"

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Monti, Jean-Marc. "Interprocessor communication supports for a multiprocessor dataflow machine." Thesis, McGill University, 1991. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=60009.

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The dataflow model of computation offers a powerful alternative to the von Neumann based model for exploiting the fine-grain parallelism inherent in scientific computations. Under this model, a program is expressed in the form of a graph, where the data values are carried by tokens, moving on the arcs of the graph. A distinctive feature of dataflow computers is the absence of the conventional program counter. Instead, instruction execution is solely determined by the availability of data which provides ample instruction level fine-grain parallelism. A highly pipelined static dataflow architecture has recently been proposed, based on the argument fetching principle, yielding the McGill Dataflow Architecture (MDFA).
In this thesis, an inter-processor communication mechanism is proposed. With this mechanism, a multiprocessor MDFA system can be constructed, based on a distributed memory organization. An efficient inter-processor synchronization and communication support is presented, for sending and receiving data through an interconnection network. An Interprocessor Communication Unit (ICU) has been designed to implement the above mechanism in the MDFA. A simulation testbed has been implemented to study the performance of the multiprocessor. It includes an assembler, with multiprocessor extensions, and a multiprocessor simulator. An analysis based on the simulations results is presented, focusing on the impact of long latency operations on program performance.
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Waters, Andrew Philip. "Program analysis and scheduling for a synchronous multiprocessor machine." Thesis, Royal Holloway, University of London, 1996. http://ethos.bl.uk/OrderDetails.do?uin=uk.bl.ethos.362649.

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Martel, Sylvain. "Design of a multiprocessor DSP-based machine suited for intensive real-time applications." Thesis, McGill University, 1989. http://digitool.Library.McGill.CA:80/R/?func=dbin-jump-full&object_id=61918.

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Mahmoud, Mohamedin Mohamed Ahmed. "ByteSTM: Java Software Transactional Memory at the Virtual Machine Level." Thesis, Virginia Tech, 2012. http://hdl.handle.net/10919/31314.

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As chip vendors are increasingly manufacturing a new generation of multi-processor chips called multicores, improving software performance requires exposing greater concurrency in software. Since code that must be run sequentially is often due to the need for synchronization, the synchronization abstraction has a significant effect on program performance. Lock-based synchronization — the most widely used synchronization method — suffers from programability, scalability, and composability challenges. Transactional memory (TM) is an emerging synchronization abstraction that promises to alleviate the difficulties with lock-based synchronization. With TM, code that read/write shared memory objects is organized as transactions, which speculatively execute. When two transactions conflict (e.g., read/write, write/write), one of them is aborted, while the other commits, yielding (the illusion of) atomicity. Aborted transactions are re-started, after rolling-back changes made to objects. In addition to a simple programming model, TM provides performance comparable to lock-based synchronization. Software transactional memory (STM) implements TM entirely in software, without any special hardware support, and is usually implemented as a library, or supported by a compiler or by a virtual machine. In this thesis, we present ByteSTM, a virtual machine-level Java STM implementation. ByteSTM implements two STM algorithms, TL2 and RingSTM, and transparently supports implicit transactions. Program bytecode is automatically modified to support transactions: memory load/store bytecode instructions automatically switch to transactional mode when a transaction starts, and switch back to normal mode when the transaction successfully commits. Being implemented at the VM-level, it accesses memory directly and uses absolute memory addresses to uniformly handle memory. Moreover, it avoids Java garbage collection (which has a negative impact on STM performance), by manually allocating and recycling memory for transactional metadata. ByteSTM uses field-based granularity, and uses the thread header to store transactional metadata, instead of the slower Java ThreadLocal abstraction. We conducted experimental studies comparing ByteSTM with other state-of-the-art Java STMs including Deuce, ObjectFabric, Multiverse, DSTM2, and JVSTM on a set of micro- benchmarks and macro-benchmarks. Our results reveal that, ByteSTM's transactional throughput improvement over competitors ranges from 20% to 75% on micro-benchmarks and from 36% to 100% on macro-benchmarks.
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Gaildrat, Véronique. "Contribution a l'etude et a la conception d'une machine parallele pour la production rapide d'images de synthese : la machine voxar, conception de l'application synthese d'images realistes." Toulouse 3, 1988. http://www.theses.fr/1988TOU30199.

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L'objectif est de reduire les temps d'obtention d'images de synthese realistes par la technique du lancer de rayon. Un logiciel de synthese d'images, applique a des objets modelises par composition de primitives geometriques, est propose. Afin d'exploiter le parallelisme d'ecran et la coherence spatiale d'une scene, une architecture parallele a ete introduite
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DiTomaso, Dominic F. "Reactive and Proactive Fault-Tolerant Network-on-Chip Architectures using Machine Learning." Ohio University / OhioLINK, 2015. http://rave.ohiolink.edu/etdc/view?acc_num=ohiou1439478822.

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Toch, Lamiel. "Contributions aux techniques d’ordonnancement sur plates-formes parallèles ou distribuées." Electronic Thesis or Diss., Besançon, 2012. http://www.theses.fr/2012BESA2045.

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Les travaux présentés dans ce document portent sur l'ordonnancement d'applications parallèles sur des plates-formes parallèles (cluster) ou distribuées (grilles de calcul). Dans nos travaux de recherche nous nous sommes concentrés sur l'ordonnancement d'applications modélisées par un DAG, graphe orienté sans cycle, pour les grilles de calcul et sur l'ordonnancement pour les (cluster, machines multiprocesseurs) de programmes parallèles (jobs parallèles) représentés sous la forme de surface rectangulaire dont les deux dimensions sont le nombre de processeurs requis et la durée d'exécution. Les recherches s'articulent autour de trois grands axes. Le premier axe concerne l'ordonnancement d'un ensemble d'instances d'une application pour les grilles de calcul. Le deuxième axe est l'ordonnancement de jobs parallèles dans les clusters. Le troisième est l'ordonnancement d'un lot de jobs parallèles pour les machines parallèles. Cette thèse apporte des contributions sur les trois axes. La première contribution associée au premier axeest l'étude expérimentale avancée de trois algorithmes pour l'ordonnancement d'un ensemble d'instances d'une application sur une plate-forme hétérogène où les coûts de communication sont négligeables : un algorithme de liste, un algorithme de régime permanent et un algorithme génétique. D'autre part nous apportons l'intégration des communications dans cet algorithme génétique. La deuxième contribution associée au deuxième axe est la conception d'une nouvelle technique d'ordonnancement de jobs parallèles pour les clusters : le pliage de jobs qui utilise la virtualisation des processeurs. La dernière contribution porte sur la conception d'une nouvelletechnique inspirée du domaine des statistiques et du traitement du signal appliquée à l'ordonnancement de jobs parallèles dans une machine multiprocesseur. Enfin nous donnons quelques travaux de recherches qui on été réalisés mais qui n'ont pas abouti à des résultats significatifs pour l'ordonnancement
Works presented in this document tackle scheduling of parallel applications in either parallel (cluster) or distributed (computing grid) platforms. In our researches we were concentrated on either scheduling of applications modeled by a DAG, directed acyclic graph, for computing grid or scheduling of parallel programs (parallel jobs) represented by a rectangular shape whose the two dimensions are the number of requested processors and the execution time. The researches follow three main topics. The first topic concerns the scheduling of a set of instances of an application for computing grid. The second topic deals with the scheduling of parallel jobs inclusters. The third one tackles the scheduling of parallel jobs in multiprocessor machines. We brought contributions on these three topics. The first contribution under the first topic consists of the advanced experimental study of three algorithms for scheduling a set of instances of an application on a heterogeneous platform without communication costs : a list-based algorithm, a steady-state algorithm and genetic algorithm. Moreover we integrate communications in this genetic algorithm. The second contribution under the second topic is the design of a new technique for scheduling parallel jobs in clusters : job folding which uses virtualization of processors. The third contribution deals with a new technique which comes from statistics and signal cessing applied to scheduling of parallel jobs in a multiprocessor machine. Eventually we givesome works that we carried out but which did not give significant results for scheduling
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Muller, Gilles. "Conception et realisation d'une machine multiprocesseur sure de fonctionnement." Rennes 1, 1988. http://www.theses.fr/1988REN10044.

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Etude de la conception d'une nouvelle architecture de machines sures de fonctionnement. La caracteristique principale de cette architecture est la possibilite de concevoir une machine sure de fonctionnement a partir d'une ou plusieurs machines standards et d'un composant sur de fonctionnement appele memoire stable
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Ben, Ismail Tarek. "Synthèse au niveau système et conception de systèmes mixtes logiciels-matériels." Grenoble INPG, 1996. http://www.theses.fr/1996INPG0003.

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L'objet de ces travaux de these est d'etudier la specification et la synthese de systemes de controle, qui peuvent etre composes a la fois de logiciel et de materiel, sur des architectures multiprocesseurs (asic, fpga, et logiciel). Ce sujet de recherche fait partie a la fois de la synthese de systemes vlsi et de la conception mixte logicielle/materielle. Afin d'atteindre ces objectifs, une methodologie qui permet de concevoir conjointement le logiciel et le materiel a ete developpee. L'originalite de ce travail vient du fait que les specifications a traiter sont decrites a un tres haut niveau d'abstraction, appele niveau systeme, avec le langage sdl. Ceci permet de concevoir des applications de plus en plus complexes. Ces travaux traitent principalement le probleme du decoupage de systemes de controle en sous-systemes de granularite plus fine et donc plus facilement synthetisables. L'approche de decoupage qui a ete developpee se base sur une boite a outils qui offre au concepteur le moyen de transformer, raffiner, decouper un systeme puis d'affecter chaque sous-systeme a une technologie particuliere en logiciel (c) ou en materiel (vhdl). La methode de decoupage suivie est interactive et utilise une forme intermediaire basee sur un modele de machines a etats finis etendues communicantes via des canaux abstraits. Une autre tache tout aussi importante dans cette methodologie de raffinement est de synthetiser la communication entre les differentes partitions resultat d'un decoupage. Cela se traduit par une etape d'allocation de protocoles de communication et une etape de synthese d'interfaces entre les sous-systemes communicants. La premiere etape consiste a selectionner dans une bibliotheque les modeles de communication necessaires entre les sous-systemes. La deuxieme etape consiste a adapter ou generer les interfaces des differents sous-systemes
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Park, Chee-Hang. "Algorithmes de jointure parallele et n-aire : application aux reseaux locaux et aux machines bases de donnees multiprocesseurs." Paris 6, 1987. http://www.theses.fr/1987PA066569.

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Cette these propose une solution concrete pour une requete de jointure (plus precisement, jointure naturelle) dans un reseau local avec diffusion. Les algorithmes proposes sont ceux de jointure n-aire qui permettent un haut degre de parallelisme sans resultats intermediaires
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Books on the topic "Multiprocessor machine"

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K, Naik Vijay, and Institute for Computer Applications in Science and Engineering., eds. Towards developing robust algorithms for solving partial differential equations on MIMD machines. Hampton, Va: Institute for Computer Applications in Science and Engineering, NASA Langley Research Center, 1985.

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Manuel Alejandro Saldana De Fuentes. A parallel programming model for a multi-FPGA multiprocessor machine. 2006.

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Müller, Silvia M., Mikhail Kovalev, and Wolfgang J. Paul. Pipelined Multi-Core MIPS Machine: Hardware Implementation and Correctness Proof. Springer London, Limited, 2014.

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Müller, Silvia M., Mikhail Kovalev, and Wolfgang J. Paul. A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness Proof. Springer, 2014.

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Handbook of Multi and ManyCore Processing Chapman HallCRC Computer Information Science. CRC Press, 2012.

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Solihin, Yan. Fundamentals of Parallel Multicore Architecture. Taylor & Francis Group, 2015.

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Fundamentals of Parallel Multicore Architecture. Taylor & Francis Group, 2020.

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Solihin, Yan. Fundamentals of Parallel Multicore Architecture. Taylor & Francis Group, 2015.

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Solihin, Yan. Fundamentals of Parallel Multicore Architecture. Taylor & Francis Group, 2015.

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Fundamentals of Parallel Multicore Architecture. Chapman and Hall/CRC, 2015.

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Book chapters on the topic "Multiprocessor machine"

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Clocksin, W. F. "The DelPhi Multiprocessor Inference Machine." In Workshops in Computing, 189–98. London: Springer London, 1993. http://dx.doi.org/10.1007/978-1-4471-3421-3_11.

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Austin, John D., and Stephen M. Pizer. "A Multiprocessor Adaptive Histogram Equalization Machine." In Information Processing in Medical Imaging, 375–92. Boston, MA: Springer US, 1988. http://dx.doi.org/10.1007/978-1-4615-7263-3_25.

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Jain, Anamika, Madhu Jain, and Dheeraj Bhardwaj. "Controllable multiprocessor queueing system." In Applications of Mathematical Modeling, Machine Learning, and Intelligent Computing for Industrial Development, 61–76. Boca Raton: CRC Press, 2023. http://dx.doi.org/10.1201/9781003386599-5.

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Agarwal, Anant, David Chaiken, Kirk Johnson, David Kranz, John Kubiatowicz, Kiyoshi Kurihara, Beng-Hong Lim, Gino Maa, and Dan Nussbaum. "The MIT Alewife Machine: A Large-Scale Distributed-Memory Multiprocessor." In Scalable Shared Memory Multiprocessors, 239–61. Boston, MA: Springer US, 1992. http://dx.doi.org/10.1007/978-1-4615-3604-8_13.

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Groesbrink, Stefan. "On the Homogeneous Multiprocessor Virtual Machine Partitioning Problem." In IFIP Advances in Information and Communication Technology, 228–37. Berlin, Heidelberg: Springer Berlin Heidelberg, 2013. http://dx.doi.org/10.1007/978-3-642-38853-8_21.

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Gupta, Gopal. "A Distributed Stack Implementation and an Abstract Machine for And-Or Parallel Execution of Logic Programs on Shared Memory Multiprocessors." In Multiprocessor Execution of Logic Programs, 87–140. Boston, MA: Springer US, 1994. http://dx.doi.org/10.1007/978-1-4615-2778-7_5.

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Machì, A. "SMAE: A Multiprocessor System for Architecture Emulation in Intermediate Level Image Processing Tasks." In Issues on Machine Vision, 209–19. Vienna: Springer Vienna, 1989. http://dx.doi.org/10.1007/978-3-7091-2830-5_14.

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von Bültzingsloewen, Günter, Rolf-Peter Liedtke, and Klaus R. Dittrich. "Set-Oriented Memory Management In A Multiprocessor Database Machine." In The Kluwer International Series in Engineering and Computer Science, 443–57. Boston, MA: Springer US, 1988. http://dx.doi.org/10.1007/978-1-4613-1679-4_32.

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Zeidler, H. Ch. "RDBM — A Relational Database Machine Based on a Dedicated Multiprocessor System." In Database Machines, 15–44. Berlin, Heidelberg: Springer Berlin Heidelberg, 1986. http://dx.doi.org/10.1007/978-3-642-82937-6_2.

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Cesarini, F., F. Pippolini, and G. Soda. "A Technique for Analyzing Query Execution in a Multiprocessor Database Machine." In Database Machines, 68–90. New York, NY: Springer New York, 1985. http://dx.doi.org/10.1007/978-1-4612-5144-6_4.

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Conference papers on the topic "Multiprocessor machine"

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Chow, K. W., and Bruce G. Batchelor. "Multiprocessor architecture for machine vision." In Applications in Optical Science and Engineering, edited by Bruce G. Batchelor, Susan Snell Solomon, and Frederick M. Waltz. SPIE, 1992. http://dx.doi.org/10.1117/12.132063.

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Hamilton, M. L. C. "The application of multiprocessor DSP to machine vision." In IEE Colloquium on `Multiprocessor DSP (Digital Signal Processing) - Applications, Algorithms and Architectures'. IEE, 1995. http://dx.doi.org/10.1049/ic:19950781.

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He, Yong, and Zhiyi Tan. "Multiprocessor scheduling problem with machine constraints." In Multispectral Image Processing and Pattern Recognition, edited by Xubang Shen and Jianguo Liu. SPIE, 2001. http://dx.doi.org/10.1117/12.441674.

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Monro, D. M., J. A. Dallas, J. A. Nicholls, M. D. Cripps, and W. A. Crossland. "An Optically Connected Parallel Machine." In Optical Computing. Washington, D.C.: Optica Publishing Group, 1993. http://dx.doi.org/10.1364/optcomp.1993.othd.5.

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Rygol, M., S. B. Pollard, and C. Brown. "A multiprocessor 3D vision system for pick and place." In British Machine Vision Conference 1990. British Machine Vision Association, 1990. http://dx.doi.org/10.5244/c.4.31.

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Sarkar, Susmit, Peter Sewell, Francesco Zappa Nardelli, Scott Owens, Tom Ridge, Thomas Braibant, Magnus O. Myreen, and Jade Alglave. "The semantics of x86-CC multiprocessor machine code." In the 36th annual ACM SIGPLAN-SIGACT symposium. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1480881.1480929.

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Gupta, Sachi, Vikas Kumar, and Gaurav Agarwal. "Task Scheduling in Multiprocessor System Using Genetic Algorithm." In 2010 Second International Conference on Machine Learning and Computing. IEEE, 2010. http://dx.doi.org/10.1109/icmlc.2010.50.

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Tang, Xin-Liang, Peng Liu, Zhen-Zhou Wang, and Bin Liu. "A load balancing algorithm for homogeneous multiprocessor system." In 2010 International Conference on Machine Learning and Cybernetics (ICMLC). IEEE, 2010. http://dx.doi.org/10.1109/icmlc.2010.5580905.

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Alglave, Jade, Anthony Fox, Samin Ishtiaq, Magnus O. Myreen, Susmit Sarkar, Peter Sewell, and Francesco Zappa Nardelli. "The semantics of power and ARM multiprocessor machine code." In the 4th workshop. New York, New York, USA: ACM Press, 2008. http://dx.doi.org/10.1145/1481839.1481842.

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Kafil, Mohammad, Ishfaq Ahmad, and Ming L. Liou. "Encoding MPEG-2 video batches using a multiprocessor machine." In SPIE's International Symposium on Optical Science, Engineering, and Instrumentation, edited by Hongchi Shi and Patrick C. Coffield. SPIE, 1998. http://dx.doi.org/10.1117/12.323465.

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